Semiconductor device and preparation method thereof

Abstract

The present invention discloses a semiconductor device and a method for manufacturing the same. The method comprises: providing a first substrate; the material of the first substrate comprising silicon; forming a first buffer layer on one side of the first substrate; wherein the first buffer layer comprises multiple intrinsic germanium layers and a dislocation barrier layer located between two adjacent intrinsic germanium layers; each dislocation barrier layer comprises multiple etching openings, and the etching openings of two adjacent dislocation barrier layers are staggered; forming a second buffer layer on a side of the first buffer layer away from the first substrate; forming a semiconductor device layer on a side of the second buffer layer away from the first substrate; providing a second substrate, bonding the semiconductor device layer to one side of the second substrate, and removing the first substrate, the first buffer layer, and the second buffer layer. The technical solution provided by the embodiments of the present invention improves the performance of the semiconductor device while reducing the manufacturing cost of the device.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor technology, and in particular to a semiconductor device and a method for manufacturing the same. Background Art

[0002] With the diversification of semiconductor devices, a combination of multiple semiconductor materials is required to form semiconductor devices. In some scenarios, indium phosphide (InP) materials are needed to prepare optoelectronic devices. However, indium phosphide materials are fragile and the chip size is small, making them unsuitable for directly preparing large-size chips.

[0003] Therefore, in actual operation, there is a demand for forming an indium phosphide thin film on a silicon (Si) substrate. However, the lattice mismatch between silicon and indium phosphide is relatively serious, about 8%, which leads to the generation of a large number of threading dislocations. In addition, indium phosphide and silicon have different polarities and a large difference in thermal expansion coefficient. Therefore, the indium phosphide film layer epitaxially grown on the silicon substrate has serious anti-phase domain defects (APDs), making it difficult to obtain a large area of ​​high-quality indium phosphide film. To ensure device performance, multiple high-quality GaAs buffer layers need to be provided to improve the crystal quality of the epitaxial layer material. However, this will make the GaAs buffer layer too thick, which is not conducive to silicon photonic integration and increases manufacturing costs. In addition, directly growing the GaAs buffer layer epitaxially on the Si substrate will still produce many defects, affecting the performance of the detector. Summary of the Invention

[0004] The embodiments of the present invention provide a semiconductor device and a method for manufacturing the same, so as to improve the performance of the semiconductor device while reducing the manufacturing cost of the device.

[0005] According to one aspect of the present invention, there is provided a method for preparing a semiconductor device, comprising:

[0006] Providing a first substrate; the material of the first substrate includes silicon;

[0007] A first buffer layer is formed on one side of the first substrate; wherein the first buffer layer includes multiple intrinsic germanium layers and a dislocation barrier layer located between two adjacent intrinsic germanium layers; each of the dislocation barrier layers includes multiple etching openings, and the etching openings of the two adjacent dislocation barrier layers are staggered;

[0008] forming a second buffer layer on a side of the first buffer layer away from the first substrate;

[0009] forming a semiconductor device layer on a side of the second buffer layer away from the first substrate;

[0010] A second substrate is provided, the semiconductor device layer is bonded to one side of the second substrate, and the first substrate, the first buffer layer and the second buffer layer are removed.

[0011] Optionally, forming a first buffer layer on one side of the first substrate includes:

[0012] Depositing a germanium material to form a first intrinsic germanium layer, wherein the first intrinsic germanium layer covers the surface of the first substrate;

[0013] forming a first dislocation barrier layer on a side of the first intrinsic germanium layer away from the first substrate;

[0014] etching the first dislocation barrier layer to form an etching opening in the first dislocation barrier layer;

[0015] Depositing germanium material to form a second intrinsic germanium layer to fill the etched opening in the first dislocation barrier layer and cover the first dislocation barrier layer;

[0016] planarizing the second intrinsic germanium layer, and forming a second dislocation barrier layer on a side of the second intrinsic germanium layer away from the first substrate;

[0017] Etching the second dislocation barrier layer to form an etching opening in the second dislocation barrier layer; wherein the etching opening in the second dislocation barrier layer is staggered with the etching opening in the first dislocation barrier layer;

[0018] Depositing germanium material to form a third intrinsic germanium layer to fill the etched opening in the second dislocation barrier layer and cover the second dislocation barrier layer;

[0019] planarizing the third intrinsic germanium layer, and forming a third dislocation barrier layer on a side of the third intrinsic germanium layer away from the first substrate;

[0020] Etching a third dislocation barrier layer to form an etching opening in the third dislocation barrier layer; wherein the etching opening in the third dislocation barrier layer is staggered with the etching opening in the second dislocation barrier layer;

[0021] Depositing a germanium material to form a fourth intrinsic germanium layer to fill the etched opening in the third dislocation barrier layer and cover the third dislocation barrier layer;

[0022] The process is deduced in this way until the preparation of the last intrinsic germanium layer is completed.

[0023] Optionally, forming a dislocation barrier layer on a side of the intrinsic germanium layer away from the first substrate includes:

[0024] forming a first blocking sublayer on a side of the intrinsic germanium layer away from the first substrate; the material of the first blocking sublayer comprises aluminum oxide;

[0025] A second blocking sublayer is formed on a side of the first blocking sublayer away from the first substrate; the material of the second blocking sublayer includes silicon oxide.

[0026] Optionally, depositing a germanium material to form the intrinsic germanium layer includes:

[0027] Growing a first intrinsic germanium sublayer at a low temperature, wherein the low temperature range is 360-460° C.;

[0028] A second intrinsic germanium sub-layer is grown on the first intrinsic germanium sub-layer at a high temperature; the high temperature range is 600-700°C.

[0029] Optionally, before bonding the semiconductor device layer to one side of the second substrate, the method further includes:

[0030] A first dielectric layer and a second dielectric layer are sequentially formed on one side of the second substrate; wherein the material of the first dielectric layer includes silicon oxide, and the material of the second dielectric layer includes aluminum oxide.

[0031] Optionally, forming a semiconductor device layer on a side of the second buffer layer away from the first substrate includes:

[0032] forming a contact layer on a side of the second buffer layer away from the first substrate;

[0033] forming a first doping type semiconductor layer on a side of the contact layer away from the first substrate;

[0034] forming an intrinsic absorption layer on a side of the first doping type semiconductor layer away from the first substrate;

[0035] A second doping type semiconductor layer is formed on a side of the intrinsic absorption layer away from the first substrate.

[0036] Optionally, after bonding the semiconductor device layer to one side of the second substrate and removing the first substrate, the first buffer layer, and the second buffer layer, the method further includes:

[0037] etching the semiconductor device layer to form a detector structure;

[0038] forming a passivation layer on a side of the semiconductor device layer away from the second substrate;

[0039] Etching the passivation layer to form a first electrode hole and a second electrode hole;

[0040] Metal material is deposited in the first electrode hole and the second electrode hole to form a first electrode and a second electrode, respectively.

[0041] Optionally, the detector structure includes a PIN type detector structure, a NIP type detector structure, an MSM type detector structure or an APD type detector structure.

[0042] According to another aspect of the present invention, there is provided a semiconductor device formed by the method for manufacturing a semiconductor device according to any embodiment of the present invention; the semiconductor device comprises:

[0043] a second substrate;

[0044] The semiconductor device layer is located on one side of the second substrate; the semiconductor device layer includes at least one detector structure.

[0045] Optionally, a first dielectric layer and a second dielectric layer are sequentially provided on a side of the second substrate close to the semiconductor device layer; the second substrate, the first dielectric layer and the second dielectric layer are used to constitute a bonding substrate;

[0046] The detector structure includes a PIN type detector structure, a NIP type detector structure, an MSM type detector structure or an APD type detector structure.

[0047] An embodiment of the present invention provides a semiconductor device and a method for fabricating the same, wherein the method comprises: providing a first substrate; the material of the first substrate comprising silicon; forming a first buffer layer on one side of the first substrate; wherein the first buffer layer comprises multiple intrinsic germanium layers and a dislocation barrier layer located between two adjacent intrinsic germanium layers; each dislocation barrier layer comprises multiple etching openings, and the etching openings of the two adjacent dislocation barrier layers are staggered; forming a second buffer layer on a side of the first buffer layer remote from the first substrate; forming a semiconductor device layer on a side of the second buffer layer remote from the first substrate; providing a second substrate, bonding the semiconductor device layer to one side of the second substrate, and removing the first substrate, first buffer layer, and second buffer layer. The technical solution provided by the embodiment of the present invention forms a high-quality first buffer layer through multi-step selective growth of an intrinsic germanium layer, providing favorable conditions for the subsequent epitaxial growth of a second buffer layer and a semiconductor device layer. The purpose is to improve the crystal quality of the subsequent epitaxial layer by optimizing the structure of the Ge buffer layer, thereby enhancing the performance of the semiconductor device. Furthermore, the formation of a multi-layer second buffer layer (GaAs buffer layer) is eliminated, thereby reducing the manufacturing cost of the device.

[0048] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0050] Figure 1 This is a schematic flow chart of a method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0051] Figure 2 1 is a flow chart of step S120 in the method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0052] Figures 3 to 12 is a cross-sectional structural diagram of step S120 in a method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0053] Figure 13 1 is a flow chart of step S130 in the method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0054] Figure 14 is a cross-sectional structural diagram of step S130 in a method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0055] Figure 15 1 is a flow chart of step S140 in the method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0056] Figure 16 is a cross-sectional structural diagram of step S140 in a method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0057] Figures 17 and 18 is a cross-sectional structural diagram of step S150 in a method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0058] Figure 19 is a cross-sectional structural diagram of step S160 in a method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0059] Figure 20 is a cross-sectional structural diagram of step S170 in a method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0060] Figure 21 is a cross-sectional structural diagram of step S180 in a method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0061] Figure 22It is a cross-sectional structural diagram of step S190 in a method for manufacturing a semiconductor device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0062] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0063] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0064] As mentioned in the background technology, with the diversification of semiconductor devices, a combination of multiple semiconductor materials is needed to form semiconductor devices. Short-wave infrared detectors play an important role in many fields. Compared with visible light, infrared detection technology can better adapt to harsh environments such as fog and darkness. In communications, 1310nm and 1550nm are commonly used optical communication wavelengths, both of which are in the infrared detection range; applications in the medical field include infrared thermal imaging technology. The thermal imaging of cancer patients has obvious asymmetry. This is because the metabolism of the tissues in the lesion site is vigorous and the blood supply is rich, which will increase the temperature of the body's epidermis. By scanning the body, the lesion site can be easily found from the infrared imaging; in agriculture, it can monitor crop growth and prevent pests and diseases; in addition, satellite infrared remote sensing imaging and topographic surveying are used to detect earth resources to determine the area and composition of land and forests, which plays a huge role in forest fire prevention, global environmental pollution monitoring, climate change and other aspects.

[0065] The III-V InGaAs material is a direct bandgap semiconductor with high electron mobility, high photoelectric properties, high radiation resistance, and can be lattice-matched with InP through composition adjustment. InGaAs detectors can also perform well at room temperature, do not require refrigeration equipment, reduce the cost of the detector system, and show great potential in miniaturizing the detector system. In addition, InGaAs detectors have high quantum efficiency and strong sensitivity. Considering cost, performance and manufacturing process, infrared detectors made of InP / InGaAs materials have obvious advantages. Especially In 0.53 Ga 0.47 The cutoff wavelength corresponding to As is 1.7 μm, which just includes the two important optical communication bands of 1.33 μm and 1.55 μm, and is in the range of 1.7 μm when the In component in the In1-xGaxAs material is 0.53. 0.53 Ga 0.47 The As lattice is completely matched, so high-quality In can be grown on the InP substrate. 0.53 Ga 0.47 As epitaxial layer, high-performance semiconductor devices are developed.

[0066] Conventional InGaAs / InP heterojunction vertical PIN structure short-wave infrared photodetectors are directly epitaxially grown on 2-inch or 4-inch InP wafers. Some researchers have also used bonding to transfer the epitaxial PIN structure grown on an InP substrate to an insulator substrate. However, the size of the resulting III-VOI (including InPOI or InGaAsOI) wafers is limited by the size of the InP substrate, making large-scale wafer mass production impossible. Currently, Si-based InGaAs heteroepitaxial technology provides an important technical approach for the mass production of large-scale III-VOI wafers. However, Si-based heteroepitaxial InP and InGaAs materials suffer from lattice mismatch and polarity mismatch. Crystal constant mismatch and thermal expansion coefficient mismatch will introduce a large number of dislocations, defects, and even macrocracks during the heteroepitaxial process. Polarity mismatch can lead to antiphase domain problems. These problems can lead to a decrease in device performance. The crystal quality of the InGaAs material needs to be improved by setting up a multi-layer buffer layer (such as a multi-layer GaAs buffer layer), but this increases the device preparation cost and volume.

[0067] In view of this, an embodiment of the present invention provides a method for manufacturing a semiconductor device. Figure 1 is a flow chart of a method for preparing a semiconductor device provided by an embodiment of the present invention, with reference to Figure 1 , a method for preparing a semiconductor device includes:

[0068] S110 , providing a first substrate; the material of the first substrate includes silicon.

[0069] Specifically, in the embodiment of the present application, the material of the first substrate includes silicon, and the first substrate can be a silicon substrate. The surface of the first substrate can be horizontal, that is, the surface of the first substrate is along the (001) direction; the surface of the first substrate can also be at a certain angle to the horizontal direction, for example, the surface of the first substrate is at a 6° angle to the horizontal direction, that is, the first substrate can be a 6° beveled silicon substrate. In this way, diatomic steps can be formed on the surface of the silicon substrate 100, suppressing the reverse crystal domains generated by III-V epitaxy, thereby improving the first substrate and the buffer layer thereon to a certain extent. The material of the first substrate can also be other materials suitable for preparing large-sized wafers (e.g., larger than 8 inches).

[0070] S120. Form a first buffer layer on one side of the first substrate; wherein the first buffer layer includes multiple intrinsic germanium layers, and a dislocation barrier layer located between two adjacent intrinsic germanium layers; each dislocation barrier layer includes multiple etching openings, and the etching openings of two adjacent dislocation barrier layers are staggered.

[0071] Specifically, a first buffer layer is formed epitaxially on the first substrate. The lattice mismatch between the material of the first buffer layer and the first substrate is small, so the film quality is high. The lattice mismatch between the first buffer layer and the second buffer layer is also small, so the film quality of the second buffer layer is also good, thereby ensuring the quality of the semiconductor device layer formed on the second buffer layer.

[0072] The first buffer layer includes multiple intrinsic germanium layers and a dislocation barrier layer located between two adjacent intrinsic germanium layers. The first substrate is in contact with the bottommost intrinsic germanium layer, and the second buffer layer is in contact with the topmost intrinsic germanium layer. Except for the bottommost intrinsic germanium layer, the remaining intrinsic germanium layers can be formed by selective growth, and the intrinsic germanium layer formed by the selective growth method includes at least three layers. The steps of forming the intrinsic germanium layer by the selective growth method include: forming a dislocation barrier layer, etching the dislocation barrier layer to pattern the dislocation barrier layer, and forming multiple etched openings in the etched dislocation barrier layer; depositing germanium material to form an intrinsic germanium layer to fill the etched openings in the dislocation barrier layer and cover the dislocation barrier layer. The pattern of the dislocation barrier layer restricts the epitaxial growth of the intrinsic germanium layer to a predefined area, providing additional control over the strain relaxation process and reducing dislocations through the necking effect and aspect ratio trapping (ART) technology. Furthermore, the staggered etching openings of the two adjacent dislocation barrier layers allow for multiple, staggered selective growth of intrinsic germanium layers, thereby better hindering crack extension and causing self-annihilation at the sidewalls. This significantly reduces the defect density of the epitaxial layer, resulting in a high-quality Ge buffer layer and providing favorable conditions for the subsequent epitaxial growth of the second buffer layer. Deposition methods for the Ge buffer layer include, but are not limited to, LPCVD (Low Pressure Chemical Vapor Deposition) and PECVD (Plasma Enhanced Chemical Vapor Deposition).

[0073] S130 , forming a second buffer layer on a side of the first buffer layer away from the first substrate.

[0074] Specifically, the material of the second buffer layer includes GaAs, forming a GaAs buffer layer. The mismatch between Ge and GaAs is 0.08%, and their thermal expansion coefficients are also relatively close. Therefore, by epitaxially growing a GaAs buffer layer on the Ge buffer layer, and then epitaxially growing an InP film and an InGaAs film layer on this basis to form the semiconductor device layer, the problem of poor epitaxial quality caused by lattice mismatch and polarity mismatch between Si and InP / InGaAs can be further resolved. The deposition method of the GaAs buffer layer is not limited to MOCVD (Metal-organic Chemical Vapor Deposition).

[0075] S140 , forming a semiconductor device layer on a side of the second buffer layer away from the first substrate.

[0076] Specifically, the semiconductor device layer is used to prepare a detector structure. Optionally, the detector structure can be a PIN detector structure, a NIP detector structure, an MSM detector structure, or an APD detector structure.

[0077] S150 , providing a second substrate, bonding the semiconductor device layer to one side of the second substrate, and removing the first substrate, the first buffer layer, and the second buffer layer.

[0078] Specifically, the bonding method for bonding the semiconductor device layer to one side of the second substrate includes, but is not limited to, BCB (benzocyclobutene) bonding. After the semiconductor device layer is bonded to one side of the second substrate, the first substrate, the first buffer layer, and the second buffer layer are removed to expose the semiconductor device layer. Optionally, the first substrate, the first buffer layer, and the second buffer layer can be removed using at least one of grading, wet polishing, dry polishing, and CMP (chemical mechanical polishing).

[0079] The semiconductor device and preparation method provided by the embodiments of the present invention form a high-quality first buffer layer by selectively growing an intrinsic germanium layer in multiple steps (at least three times), providing good conditions for the subsequent epitaxial growth of a second buffer layer and a semiconductor device layer. The purpose is to improve the crystal quality of subsequent epitaxial layers and the performance of semiconductor devices by optimizing the structure of the Ge buffer layer. There is no need to form a multi-layer second buffer layer (GaAs buffer layer), thereby reducing the manufacturing cost of the device.

[0080] For ease of understanding, the specific implementation of each of the above steps will be described in detail below.

[0081] In one embodiment of the present invention, Figure 2 1 is a flow chart of step S120 in the method for manufacturing a semiconductor device provided by an embodiment of the present invention. Figures 3 to 12 is a cross-sectional structural diagram of step S120 in a method for preparing a semiconductor device provided by an embodiment of the present invention, with reference to Figures 2 to 12 Step S120 forms a first buffer layer on one side of the first substrate, comprising:

[0082] S201 , depositing a germanium material to form a first intrinsic germanium layer, where the first intrinsic germanium layer covers a surface of a first substrate.

[0083] Specifically, refer to Figure 3, a germanium material is deposited on the surface of one side of the first substrate 10 to form a first intrinsic germanium layer 211. The process for forming the first intrinsic germanium layer 211 may be a deposition process, such as chemical vapor deposition (CVD), molecular beam epitaxy (MBE), etc. Optionally, the first intrinsic germanium layer 211 may include a multilayer film layer grown under different temperature environments, for example, including a first intrinsic germanium sublayer and a second intrinsic germanium sublayer grown under different temperature environments. The steps of depositing the germanium material to form the first intrinsic germanium layer may specifically include: low-temperature growth of the first intrinsic germanium sublayer; the low temperature range is 360-460°C; high-temperature growth of the second intrinsic germanium sublayer on the first intrinsic germanium sublayer; the high temperature range is 600-700°C. Among them, the role of growing the first intrinsic germanium sublayer at low temperature is to release part of the stress, so that the film layer thereon can be grown under low stress or no stress. Growing the second intrinsic germanium sublayer at high temperature can obtain an ideal second intrinsic germanium sublayer, thereby obtaining an ideal first intrinsic germanium sublayer 211.

[0084] Furthermore, during the process of forming the first intrinsic germanium layer 211, a third intrinsic germanium sublayer can be grown between the first intrinsic germanium sublayer and the second intrinsic germanium sublayer. The role of growing the third intrinsic germanium sublayer at medium temperature is that it can serve as an intermediate temperature buffer zone to promote the two-dimensional planar growth of germanium, improve the lattice defects of the germanium film layer during the growth process, and facilitate the formation of the second intrinsic germanium sublayer thereon, thereby further improving the quality of the first intrinsic germanium layer 211.

[0085] S202 , forming a first dislocation barrier layer on a side of the first intrinsic germanium layer away from the first substrate.

[0086] Specifically, refer to Figure 4The first dislocation barrier layer 221 can be formed using a deposition process, such as chemical vapor deposition (CVD) or atomic layer epitaxy (ALE). The first dislocation barrier layer 221 includes a first barrier sublayer 201 and a second barrier sublayer 202 stacked together. The material of the first barrier sublayer 201 includes aluminum oxide, and the material of the second barrier sublayer 202 includes silicon oxide. The first dislocation barrier layer 221 is formed on the side of the first intrinsic germanium layer 211 away from the first substrate 10, including: depositing Al2O3 material on the side of the first intrinsic germanium layer 211 away from the first substrate 10 to form the first barrier sublayer 201; and depositing SiO2 material on the side of the first barrier sublayer 201 away from the first substrate 10 to form the second barrier sublayer 202. Growing the first barrier sublayer 201 before the second barrier sublayer 202 enhances adhesion between the second barrier sublayer 202 and the intrinsic germanium layer (the first intrinsic germanium layer 211), thereby improving the stability of the second barrier sublayer 202. The thickness of the first blocking sublayer 201 is smaller than the thickness of the second blocking sublayer 202 .

[0087] S203 , etching the first dislocation barrier layer to form an etching opening in the first dislocation barrier layer.

[0088] Specifically, refer to Figure 5 The etching process may be a photolithography process, wherein the first dislocation blocking layer 221 is etched by the photolithography process to form an etching opening 01 in the first dislocation blocking layer 221. The step of etching the first dislocation blocking layer 221 by the photolithography process to form the etching opening 01 in the first dislocation blocking layer 221 may specifically include: forming a photoresist on the first dislocation blocking layer 221; obtaining a patterned photoresist by photolithography and development; etching the first dislocation blocking layer 221 using the photoresist as a mask to form the etching opening 01 in the first dislocation blocking layer 221, wherein the etching opening 01 formed in the first dislocation blocking layer 221 exposes the first dislocation blocking layer 221; and removing the photoresist layer.

[0089] S204 , depositing germanium material to form a second intrinsic germanium layer to fill the etched openings in the first dislocation barrier layer and cover the first dislocation barrier layer.

[0090] Specifically, refer to Figure 6, a germanium material is deposited in the etched opening 01 of the first dislocation barrier layer 221 and on the surface of the first dislocation barrier layer 221 to form a second intrinsic germanium layer 212. The process for forming the second intrinsic germanium layer 212 can be a deposition process, such as chemical vapor deposition, molecular beam epitaxy, etc. Optionally, the second intrinsic germanium layer 212 can include a multilayer film layer grown under different temperature environments, for example, including a first intrinsic germanium sublayer and a second intrinsic germanium sublayer grown under different temperature environments. The steps of depositing the second layer of germanium material to form the intrinsic germanium layer can specifically include: low-temperature growth of the first intrinsic germanium sublayer; the low temperature range is 360-460°C; high-temperature growth of the second intrinsic germanium sublayer on the first intrinsic germanium sublayer; the high temperature range is 600-700°C. The functions can be referred to the above steps and will not be repeated here. The second intrinsic germanium layer 212 is a selectively grown intrinsic germanium layer. If the selectively grown intrinsic germanium layer is grown under different temperature environments, the thickness of the low-temperature grown first intrinsic germanium sublayer can be less than the depth of the etched opening (e.g., etched opening 01), or equal to the depth of the etched opening (e.g., etched opening 01), or greater than the depth of the etched opening (e.g., etched opening 01). This is not limited in the present embodiment. Furthermore, during the formation of the second intrinsic germanium layer 212, a third intrinsic germanium sublayer can be grown at a medium temperature between the first intrinsic germanium sublayer and the second intrinsic germanium sublayer. The function of this third intrinsic germanium sublayer can refer to the above steps and will not be described in detail here.

[0091] S205 , planarizing the second intrinsic germanium layer, and forming a second dislocation barrier layer on a side of the second intrinsic germanium layer away from the first substrate.

[0092] Specifically, the second intrinsic germanium layer 212 is planarized to make the upper surface of the second intrinsic germanium layer 212 relatively flat. Figure 7 A second dislocation barrier layer 222 is formed on the side of the second intrinsic germanium layer 212 away from the first substrate 10 . For specific steps, please refer to the above step S202 and will not be repeated here.

[0093] S206 , etching the second dislocation barrier layer to form an etching opening in the second dislocation barrier layer; wherein the etching opening in the second dislocation barrier layer is staggered with the etching opening in the first dislocation barrier layer.

[0094] Specifically, refer to Figure 8, etching the second dislocation barrier layer 222, forming an etching opening 02 in the second dislocation barrier layer 222. The specific steps can refer to the above-mentioned step S203 and will not be repeated here. It should be noted that the etching opening 02 in the second dislocation barrier layer 222 is staggered with the etching opening 01 in the first dislocation barrier layer 221, that is, the opening positions of the two patterned photoresists are staggered. The staggered etching openings of the two adjacent dislocation barrier layers can stagger the selective growth of the intrinsic germanium layer, thereby better hindering the extension of the cracks, causing them to self-annihilate at the sidewalls, greatly reducing the defect density of the epitaxial layer, and obtaining a high-quality Ge layer, which provides good conditions for the subsequent epitaxial second buffer layer 30.

[0095] S207 , depositing germanium material to form a third intrinsic germanium layer to fill the etched openings in the second dislocation barrier layer and cover the second dislocation barrier layer.

[0096] Specifically, refer to Figure 9 , a germanium material is deposited to form a third intrinsic germanium layer 213 to fill the etched opening 02 in the second dislocation barrier layer 222 and cover the second dislocation barrier layer 222. The specific steps can refer to the above step S204 and will not be repeated here.

[0097] S208 , planarizing the third intrinsic germanium layer, and forming a third dislocation barrier layer on a side of the third intrinsic germanium layer away from the first substrate.

[0098] Specifically, refer to Figure 10 After the third intrinsic germanium layer 213 is planarized, a third dislocation barrier layer 223 is formed on the side of the third intrinsic germanium layer 213 away from the first substrate 10. The specific steps can refer to the above step S202 and will not be repeated here.

[0099] S209 , etching the third dislocation barrier layer to form an etching opening in the third dislocation barrier layer; wherein the etching opening in the third dislocation barrier layer is staggered with the etching opening in the second dislocation barrier layer.

[0100] Specifically, refer to Figure 11 The third dislocation barrier layer 223 is etched to form an etched opening 03 in the third dislocation barrier layer 223. The specific steps can be referred to above step S203 and will not be repeated here. It should be noted that the etched opening 03 in the third dislocation barrier layer 223 is offset from the etched opening 02 in the second dislocation barrier layer 222, that is, the opening positions of the two patterned photoresists are offset. Optionally, the etched opening 03 in the third dislocation barrier layer 223 can be aligned with the etched opening 01 in the first dislocation barrier layer 221.

[0101] S2010 , depositing germanium material to form a fourth intrinsic germanium layer to fill the etched openings in the third dislocation barrier layer and cover the surface of the third dislocation barrier layer.

[0102] Specifically, refer to Figure 12 , depositing germanium material to form a fourth intrinsic germanium layer 214 to fill the etched opening 03 in the third dislocation barrier layer 223 and cover the third dislocation barrier layer 223. The specific steps can refer to the above step S204 and will not be repeated here.

[0103] The above steps S201 to S2010 exemplarily describe the first buffer layer 20 including three selected intrinsic germanium layers (a second intrinsic germanium layer 212, a third intrinsic germanium layer 213, and a fourth intrinsic germanium layer 204). In other embodiments of the present invention, the first buffer layer 20 includes more than three selected intrinsic germanium layers. The above steps are then followed, and so on, until the preparation of the last intrinsic germanium layer is completed. It should be noted that after the last intrinsic germanium layer is deposited, it can be planarized to provide a smooth deposition surface for the preparation of the second buffer layer 30.

[0104] Based on the above embodiments, in one embodiment of the present invention, Figure 13 1 is a flow chart of step S130 in the method for manufacturing a semiconductor device provided by an embodiment of the present invention. Figure 14 is a cross-sectional structural diagram of step S130 in a method for preparing a semiconductor device provided by an embodiment of the present invention, with reference to Figures 13 and 14 Step S130 forms a second buffer layer on a side of the first buffer layer away from the first substrate, comprising:

[0105] S301, growing a first GaAs buffer sublayer at low temperature; the low temperature range is 360-460°C.

[0106] S302 , growing a second GaAs buffer sublayer on the first GaAs buffer sublayer at a high temperature; the high temperature range is 600-700° C.

[0107] Specifically, refer to Figure 14 In the embodiment of the present invention, the second buffer layer 30 includes a first GaAs buffer sublayer grown at low temperature and a second GaAs buffer sublayer grown at high temperature (not shown). The low-temperature growth of the first GaAs buffer sublayer can release some stress, thereby allowing the film layer thereon to be grown under low stress or no stress. The high-temperature growth of the second GaAs buffer sublayer can produce an ideal GaAs layer.

[0108] Based on the above embodiments, in one embodiment of the present invention, Figure 151 is a flow chart of step S140 in the method for manufacturing a semiconductor device provided by an embodiment of the present invention. Figure 16 is a cross-sectional structural diagram of step S140 in a method for preparing a semiconductor device according to an embodiment of the present invention, with reference to Figures 15 and 16 Step S140 forms a semiconductor device layer on a side of the second buffer layer away from the first substrate, including:

[0109] S401 , forming a contact layer on a side of the second buffer layer away from the first substrate.

[0110] S402 , forming a first doping type semiconductor layer on a side of the contact layer away from the first substrate.

[0111] S403 , forming an intrinsic absorption layer on a side of the first doping type semiconductor layer away from the first substrate.

[0112] S404 , forming a second doping type semiconductor layer on a side of the intrinsic absorption layer away from the first substrate.

[0113] Specifically, the material of the contact layer 41 may include InGaAs of the first doping type and being heavily doped, the material of the first doping type semiconductor layer 42 may include InP (indium phosphide), and the material of the intrinsic absorption layer 43 may include In x Ga 1-x The composition range of As and In is 0.53≤x≤1. The material of the second doping type semiconductor layer 44 includes InP. Figure 16 The first doping type is P type, and the second doping type is N type, that is, the material of the contact layer 41 is P type heavily doped InGaAs, the material of the first doping type semiconductor layer 42 is P type InP, and the material of the second doping type semiconductor layer 44 is N type InP.

[0114] Alternatively, the first doping type is N-type and the second doping type is P-type, that is, the material of the first doping type semiconductor layer is N-type InP and the material of the second doping type semiconductor layer is P-type InP. The semiconductor device layer 40 in the embodiment of the present invention is used to prepare a PIN type detector structure or a NIP type detector structure.

[0115] In another embodiment of the present invention (not shown), step S140 forms a semiconductor device layer on a side of the second buffer layer away from the first substrate, comprising:

[0116] S411 , forming a contact layer on a side of the second buffer layer away from the first substrate.

[0117] S412 , forming a first doping type semiconductor layer on a side of the contact layer away from the first substrate.

[0118] S413 , forming an intrinsic absorption layer on a side of the first doping type semiconductor layer away from the first substrate.

[0119] S414 , forming an avalanche multiplication region layer of a first doping type on a side of the intrinsic absorption layer away from the first substrate.

[0120] S415 , forming a second doping type semiconductor layer on a side of the first doping type avalanche region layer away from the first substrate.

[0121] The semiconductor device layer in the embodiment of the present invention is used to prepare an APD type detector structure.

[0122] In another embodiment of the present invention (not shown), step S140 forms a semiconductor device layer on a side of the second buffer layer away from the first substrate, comprising:

[0123] S421 , forming an undoped semiconductor buffer layer on a side of the second buffer layer away from the first substrate.

[0124] S422 , forming a second doping type semiconductor layer on a side of the buffer layer away from the first substrate.

[0125] S423 , forming an undoped semiconductor layer on a side of the second doped type semiconductor layer away from the first substrate.

[0126] The semiconductor device layer in the embodiment of the present invention is used to prepare an MSM type detector structure.

[0127] Figures 17 and 18 is a cross-sectional structural diagram of step S150 in a method for preparing a semiconductor device according to an embodiment of the present invention, with reference to Figures 17 and 18 The semiconductor device layer 40 is bonded to one side of the second substrate 51, and the first substrate 10, the first buffer layer 20 and the second buffer layer 30 are removed by at least one process selected from grading, wet processing, dry processing and CMP.

[0128] Based on the above embodiments, in one embodiment of the present invention, before bonding the semiconductor device layer 40 to one side of the second substrate 51, the process further includes:

[0129] A first dielectric layer 53 and a second dielectric layer 52 are sequentially formed on one side of the second substrate 51 ; the material of the first dielectric layer 52 includes silicon oxide, and the material of the second dielectric layer 53 includes aluminum oxide.

[0130] Specifically, the material of the second substrate 51 includes silicon, which can be a silicon substrate. A silicon oxide layer (first dielectric layer 53) and an aluminum oxide layer (second dielectric layer 52) are sequentially formed on one side of the second substrate 51, and the silicon substrate, the silicon oxide layer and the aluminum oxide layer are used to constitute a silicon-on-insulator (SOI) substrate 50. The material of the first substrate can also be other materials suitable for preparing large-size (for example, greater than 8 inches) wafers. Bonding the semiconductor device layer 40 to one side of the second substrate 51 includes: bonding the semiconductor device layer 40 to the surface of the second dielectric layer 53 away from the second substrate 51. In the embodiment of the present invention, by bonding the semiconductor device layer 40 to the bonding substrate 50, the dark current of the device can be reduced by the insulating layer on the bonding substrate 50, and the second substrate 51 and the first dielectric layer 52 can be used as a resonant cavity to improve the responsiveness of the prepared detector.

[0131] Based on the above embodiments, in one embodiment of the present invention, after step S150, bonding the semiconductor device layer to one side of the second substrate and removing the first substrate, the first buffer layer and the second buffer layer, the process further includes:

[0132] S160, etching the semiconductor device layer 40 to form a detector structure 401 (refer to Figure 19 ).

[0133] S170, forming a passivation layer 60 on the side of the semiconductor device layer 40 away from the second substrate 51 (refer to Figure 20 ).

[0134] S180, etching the passivation layer 60 to form a first electrode hole 61 and a second electrode hole 62 (refer to Figure 21 ).

[0135] S190, depositing metal material in the first electrode hole 61 and the second electrode hole 62 to form the first electrode 71 and the second electrode 72 respectively (refer to Figure 22 ).

[0136] In summary, in the related art, when heteroepitaxial GaAs layer is directly grown on Si substrate as buffer layer, a large number of dislocations will be generated, and the defect density of GaAs layer is about 10 7 In the embodiment of the present invention, after the first selective growth of the intrinsic Ge layer, the order of magnitude is reduced to 10 5After three or more selective growths, the quality of the intrinsic Ge layer becomes increasingly higher, and the defect density of the GaAs layer is significantly reduced. In addition, multiple staggered selective growths of the intrinsic Ge layer can better hinder the extension of dislocations, causing them to self-annihilate at the sidewalls, significantly reducing the defect density of the epitaxial layer and obtaining a high-quality Ge layer, providing good conditions for the subsequent epitaxial GaAs layer. The mismatch between Ge and GaAs is 0.08%, and the thermal expansion coefficients are also relatively close. Therefore, GaAs can be epitaxially grown on Si through a Ge buffer layer, and InP and InGaAs layers can be epitaxially grown on this basis, solving the problem of poor epitaxial quality caused by lattice mismatch and polarity mismatch between Si, InP and InGaAs, and making the dark current, responsivity and other performance of the prepared InGaAs-on-insulator short-wave infrared detection device reach a better level.

[0137] In addition, compared to traditional InP-based InGaAs PDs that can only be prepared on 2-6 inch wafers, the embodiment of the present invention can achieve large-scale preparation of 8-inch and 12-inch wafers based on Si substrates, and the device cost has been greatly reduced. Monolithic heterogeneous integration of InGaAs materials on Si substrates has been achieved, and various new device applications and functions have become possible by utilizing the excellent optoelectronic properties of InGaAs materials and highly mature Si process technology. The technical solution provided by the present invention can continue to prepare 8-inch and 12-inch InGaAs short-wave infrared detectors on insulators, solving the current industry pain points such as high prices of InP substrates, limited wafer size, and fragile wafers, and laying a good technical foundation for the large-scale production of Si-based III-V devices.

[0138] An embodiment of the present invention further provides a semiconductor device, which is formed by the method for preparing the semiconductor device according to any of the above embodiments; Figure 22 , semiconductor devices include:

[0139] Second substrate 51;

[0140] The semiconductor device layer 40 is located on one side of the second substrate 51 ; the semiconductor device layer 40 includes at least one detector structure 401 .

[0141] Optionally, a first dielectric layer 52 and a second dielectric layer 53 are sequentially provided on a side of the second substrate 51 adjacent to the semiconductor device layer 40. The second substrate 51, the first dielectric layer 52, and the second dielectric layer 53 constitute a bonding substrate 50. The detector structure 401 includes a PIN detector structure, a NIP detector structure, an MSM detector structure, or an APD detector structure. The semiconductor device provided in the embodiments of the present invention has the corresponding beneficial effects of the preparation method, which will not be further described here.

[0142] Note that the above are only preferred embodiments of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments, and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments and may include many other equivalent embodiments without departing from the concept of the present invention. The scope of the present invention is determined by the scope of the appended claims.

Claims

1. A method for preparing a semiconductor device, characterized in that: include: Providing a first substrate; the material of the first substrate is silicon; A first buffer layer is formed on one side of the first substrate; wherein the first buffer layer includes multiple intrinsic germanium layers and a dislocation barrier layer located between two adjacent intrinsic germanium layers; each of the dislocation barrier layers is located between two adjacent intrinsic germanium layers; each of the dislocation barrier layers includes multiple etching openings, and the etching openings of the two adjacent dislocation barrier layers are staggered; forming a second buffer layer on a side of the first buffer layer away from the first substrate; the material of the second buffer layer is GaAs; forming a semiconductor device layer on a side of the second buffer layer away from the first substrate; A second substrate is provided, the semiconductor device layer is bonded to one side of the second substrate, and the first substrate, the first buffer layer and the second buffer layer are removed.

2. The method for preparing a semiconductor device according to claim 1, wherein: forming a first buffer layer on one side of the first substrate, comprising: Depositing a germanium material to form a first intrinsic germanium layer, wherein the first intrinsic germanium layer covers the surface of the first substrate; forming a first dislocation barrier layer on a side of the first intrinsic germanium layer away from the first substrate; etching the first dislocation barrier layer to form an etching opening in the first dislocation barrier layer; Depositing germanium material to form a second intrinsic germanium layer to fill the etched opening in the first dislocation barrier layer and cover the first dislocation barrier layer; planarizing the second intrinsic germanium layer, and forming a second dislocation barrier layer on a side of the second intrinsic germanium layer away from the first substrate; Etching the second dislocation barrier layer to form an etching opening in the second dislocation barrier layer; wherein the etching opening in the second dislocation barrier layer is staggered with the etching opening in the first dislocation barrier layer; Depositing germanium material to form a third intrinsic germanium layer to fill the etched opening in the second dislocation barrier layer and cover the second dislocation barrier layer; planarizing the third intrinsic germanium layer, and forming a third dislocation barrier layer on a side of the third intrinsic germanium layer away from the first substrate; Etching a third dislocation barrier layer to form an etching opening in the third dislocation barrier layer; wherein the etching opening in the third dislocation barrier layer is staggered with the etching opening in the second dislocation barrier layer; Depositing a germanium material to form a fourth intrinsic germanium layer to fill the etched opening in the third dislocation barrier layer and cover the third dislocation barrier layer; The process is deduced in this way until the preparation of the last intrinsic germanium layer is completed.

3. The method for preparing a semiconductor device according to claim 2, wherein: Forming a dislocation barrier layer on a side of the intrinsic germanium layer away from the first substrate, comprising: forming a first blocking sublayer on a side of the intrinsic germanium layer away from the first substrate; the material of the first blocking sublayer comprises aluminum oxide; A second blocking sublayer is formed on a side of the first blocking sublayer away from the first substrate; the material of the second blocking sublayer includes silicon oxide.

4. The method for preparing a semiconductor device according to claim 2, wherein: Depositing a germanium material to form the intrinsic germanium layer comprises: Growing a first intrinsic germanium sublayer at a low temperature, wherein the low temperature range is 360-460° C.; A second intrinsic germanium sub-layer is grown on the first intrinsic germanium sub-layer at a high temperature; the high temperature range is 600-700°C.

5. The method for preparing a semiconductor device according to claim 1, wherein: Before bonding the semiconductor device layer to one side of the second substrate, the method further includes: A first dielectric layer and a second dielectric layer are sequentially formed on one side of the second substrate; wherein the material of the first dielectric layer includes silicon oxide, and the material of the second dielectric layer includes aluminum oxide.

6. The method for preparing a semiconductor device according to claim 1, wherein: forming a semiconductor device layer on a side of the second buffer layer away from the first substrate, comprising: forming a contact layer on a side of the second buffer layer away from the first substrate; forming a first doping type semiconductor layer on a side of the contact layer away from the first substrate; forming an intrinsic absorption layer on a side of the first doping type semiconductor layer away from the first substrate; A second doping type semiconductor layer is formed on a side of the intrinsic absorption layer away from the first substrate.

7. The method for preparing a semiconductor device according to claim 1, wherein: After bonding the semiconductor device layer to one side of the second substrate and removing the first substrate, the first buffer layer and the second buffer layer, the method further includes: etching the semiconductor device layer to form a detector structure; forming a passivation layer on a side of the semiconductor device layer away from the second substrate; Etching the passivation layer to form a first electrode hole and a second electrode hole; Metal material is deposited in the first electrode hole and the second electrode hole to form a first electrode and a second electrode, respectively.

8. The method for preparing a semiconductor device according to claim 7, wherein: The detector structure includes a PIN type detector structure, a NIP type detector table structure, an MSM type detector structure or an APD type detector structure.

9. A semiconductor device, characterized in that: The semiconductor device is formed by the method for preparing the semiconductor device according to any one of claims 1 to 8; the semiconductor device comprises: a second substrate; The semiconductor device layer is located on one side of the second substrate; the semiconductor device layer includes at least one detector structure.

10. The semiconductor device according to claim 9, wherein A first dielectric layer and a second dielectric layer are sequentially provided on a side of the second substrate close to the semiconductor device layer; the second substrate, the first dielectric layer and the second dielectric layer are used to constitute a bonding substrate; The detector structure includes a PIN type detector structure, a NIP type detector structure, an MSM type detector structure or an APD type detector structure.

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