A segmented current-steering DAC

Abstract

The application discloses a segmented current steering DAC, comprising: a shunt unit, which comprises shunt subunits corresponding to bit positions, the input end of the shunt subunit is connected with the output end of a first low-bit current source, and the branch current of each shunt subunit is multiplied in turn; the application increases the shunt unit, solves the matching problem of an analog circuit, considers the limitation of a DRC rule, optimizes the performance of the circuit, reduces the chip area and lowers the cost.

Description

Technical Field

[0001] This invention relates to the field of analog integrated circuits, and in particular to a segmented current-steering DAC. Background Technology

[0002] A DAC (Digital-to-Analog Converter) connects the digital and analog worlds, converting digital signals into analog signals. DACs play an indispensable role in daily life. They are crucial in both consumer electronics and automotive electronics. A current-controlled DAC is a widely used circuit primarily used to convert digital signals into analog signals.

[0003] There are many types of current-controlled digital-to-analog converters (DACs), such as binary weighted DACs, thermometer-encoded DACs, and hybrids of binary weighted DACs and thermometer-encoded DACs, namely segmented DACs.

[0004] a) The advantage of a binary-weighted DAC is that it does not require an additional decoder to decode the binary input digital code. The disadvantage is that monotonicity cannot be guaranteed, which is crucial for calibration or tuning because monotonicity is assumed in digital signal processing algorithms.

[0005] b) A thermometer-encoded DAC can guarantee the required monotonicity, but the drawback is that the ratio of unit current source to switch is 2 to the power of N (where N is the DAC's resolution or bit depth). Furthermore, a dedicated decoder is needed to convert the binary input code into thermometer code. If the DAC's resolution exceeds 6, a large number of unit current elements and current switches are required. The decoder area will also increase accordingly.

[0006] c) The common practice is to make a trade-off between design complexity and accuracy, which is the combination of thermometer-encoded DAC and binary weighted DAC, and named segmented DAC.

[0007] However, designing the smallest segmented DAC using traditional methods still presents some challenges. Taking an existing 7-bit segmented DAC as an example... Figure 1As shown, MOS transistors Mswt1n and Mswt1p to Mswt15n and Mswt15p are 15 differential switches, and MOS transistors Mtherm1 to Mtherm15 are 15 current sources, forming a thermometer-encoded DAC for inputting the high bits (bit7, bit6, bit5, and bit4). MOS transistors M3, M2, and M1 are current sources, and MOS transistors Msw1n and Msw1p to Msw3n and Msw3p are differential switches, forming a binary-encoded DAC for inputting the low bits (bit3, bit2, and bit1). If the width-to-length ratio (W / L) of the current sources Mtherm1 to Mtherm15 in the thermometer-encoded DAC is 2, then the width-to-length ratios of the current sources M3, M2, and M1 in the binary-encoded DAC should be 1, 0.5, and 0.25, respectively.

[0008] However, this approach presents a problem: the aspect ratio of the largest and smallest MOS transistors differs by a factor of 8 (2W / L) / (0.25W / L) = 8. In analog circuit design, matching is often necessary. If matching is considered based on the 15 current sources of the thermometer-encoded DAC, the 0.25W / L size of MOS transistor M1 might be unattainable due to DRC rules. If matching is considered based on MOS transistor M1, the area of ​​the 15 thermometer-encoded unary current sources would increase, resulting in wasted area. Summary of the Invention

[0009] To address the shortcomings of existing technologies, this invention proposes a segmented current-controlled DAC. A thermometer decoder is used to decode the high bits of the digital signal to obtain the thermometer code.

[0010] A high-bit-level current source group, the input of which is connected to a current mirror, the high-bit-level current source group including a high-bit-level sub-current source composed of a MOS transistor array;

[0011] The high-bit-level switch unit group has a control terminal that inputs the thermometer code, its input terminal is connected to the output terminal of the high-bit-level current source group, and its output terminal is connected to the output terminal of the current rudder DAC.

[0012] A low-bit current source group, whose input terminal is connected to a current mirror, includes a first low-bit current source and a second low-bit current source composed of MOS transistors.

[0013] The current shunt unit includes a current shunt sub-unit corresponding to a bit. The input terminal of the current shunt sub-unit is connected to the output terminal of the first low bit current source, and the branch current of the current shunt sub-unit increases in size sequentially from the corresponding low bit to the high bit.

[0014] The low-bit switching unit group has its control terminals derived from the low-bit binary signals of the input digital signal. The output terminals are connected to the output terminals of the current-driven DAC. The input terminal of one low-bit switching unit is connected to the output terminal of the second low-bit current source group. Following the bit-by-bit correspondence, the input terminals of the remaining low-bit switching units are connected to the output terminals of the shunt sub-units.

[0015] The segmented current-steering DAC of the present invention includes:

[0016] A thermometer decoder is used to decode the high bits of a digital signal to obtain the thermometer code.

[0017] A high-bit-level current source group, the input of which is connected to a current mirror, the high-bit-level current source group including a high-bit-level sub-current source composed of a MOS transistor array;

[0018] The high-bit-level switch unit group has a control terminal that inputs the thermometer code, its input terminal is connected to the output terminal of the high-bit-level current source group, and its output terminal is connected to the output terminal of the current rudder DAC.

[0019] A low-bit current source group, whose input terminal is connected to a current mirror, includes a first low-bit current source and a second low-bit current source composed of MOS transistors.

[0020] The current shunt unit includes a current shunt sub-unit corresponding to a bit. The input terminal of the current shunt sub-unit is connected to the output terminal of the first low bit current source, and the branch current of the current shunt sub-unit increases sequentially from the corresponding low bit to the high bit.

[0021] The low-bit switch unit group has a control terminal that receives the low-bit binary signal of the digital signal and an output terminal that is connected to the output terminal of the current steering DAC. The input terminal of one of the low-bit switch units is connected to the output terminal of the second low-bit current source group. According to the bit correspondence, the input terminals of the remaining low-bit switch units are respectively connected to the output terminals of the shunt sub-units.

[0022] This invention addresses the analog circuit matching problem by adding a shunt unit, while also taking into account the limitations of the DRC rule. This results in optimized circuit performance, reduced chip area, and lower costs. Attached Figure Description

[0023] The above and other objects, features and advantages of the present invention will become more apparent from the more detailed description of exemplary embodiments of the invention in conjunction with the accompanying drawings, wherein the same reference numerals generally represent the same components in the exemplary embodiments of the invention.

[0024] Figure 1This is a circuit diagram of an existing 7-bit segmented current-controlled DAC;

[0025] Figure 2 This is a schematic diagram of the segmented current steering DAC of the present invention;

[0026] Figure 3 This is a circuit diagram of a 7-bit segmented current steering DAC according to an embodiment of the present invention;

[0027] Figure 4 This is a circuit diagram of an 8-bit segmented current steering DAC according to an embodiment of the present invention. Detailed Implementation

[0028] Preferred embodiments of the invention will now be described in more detail. While preferred embodiments of the invention are described below, it should be understood that the invention can be implemented in various forms and should not be limited to the embodiments set forth herein.

[0029] In this invention, we propose a novel segmented current steering DAC circuit.

[0030] like Figure 2 As shown, a segmented current-controlled DAC includes:

[0031] The thermometer decoder 10 is used to decode the high bits of the digital signal to obtain the thermometer code;

[0032] A high-bit-level current source group 20, the input of which is connected to a current mirror, the high-bit-level current source group including a high-bit-level sub-current source composed of MOS transistors;

[0033] The high-bit-level switch unit group 30 has a control terminal that inputs the thermometer code, its input terminal is connected to the output terminal of the high-bit-level current source group, and its output terminal is connected to the output terminal of the current rudder DAC.

[0034] The low-bit current source group 40 has its input terminal connected to a current mirror and includes a first low-bit current source and a second low-bit current source composed of MOS transistors.

[0035] The current shunt unit 50 includes a current shunt sub-unit corresponding to a bit. The input terminal of the current shunt sub-unit is connected to the output terminal of the first low bit current source, and the branch current of each current shunt sub-unit increases sequentially from the corresponding low bit to the high bit.

[0036] The low-bit switching unit group 60 has its control terminals derived from the low-bit binary signals of the input digital signal, and its output terminals connected to the output terminals of the current steering DAC. The input terminal of one of the low-bit switching units is connected to the output terminal of the second low-bit current source group. According to the bit correspondence, the input terminals of the remaining low-bit switching units are connected to the output terminals of the shunt units.

[0037] The following detailed description is based on a specific embodiment of the present invention, in which the use of MOS transistors as a simple replacement between NMOS and PMOS transistors is within the scope of protection of the present invention. Specifically, as follows... Figure 3 As shown, this is a 7-bit segmented current steering DAC.

[0038] The current mirror Ms provides input current to the high-bit current source group 20. The high-bit current source group 20 includes 15 high-bit sub-current sources Mtherm1 to Mtherm15. Each high-bit sub-current source is a single current source, specifically including a MOS transistor. The MOS transistor has a width-to-length ratio of 2, its gate is connected to the current mirror Ms, its source is connected to the current mirror VDD, and its drain is the output terminal.

[0039] The high-bit-level switch unit group 30 has a control terminal that inputs the thermometer code. Its input terminal is connected to the output terminal of the high-bit-level current source group 20, and its output terminal is connected to the output terminal of the current steering DAC. The high-bit-level switch unit group includes 15 high-bit-level switch units, each connected to a high-bit-level sub-current source. In this embodiment, the high-bit-level switch unit is composed of a pair of MOS transistors Mswt1n and Mswt1p to Mswt15n and Mswt15p forming a differential switch. Its source is connected to the drain of the current source MOS transistor corresponding to the bit of the thermometer code, and its gate is input to the signal T1n to T15n and signal T1p to T15p corresponding to the bit of the thermometer code. The drain of the differential switch is the output terminal Ioutn / Ioutp.

[0040] The low-bit current source group 40 has its input terminal connected to the current mirror and includes a first low-bit current source and a second low-bit current source composed of MOS transistors M1 and M2. The gates of MOS transistors M1 and M2 are connected to the gate of the current mirror MS, the sources are connected to the VDD of the current mirror, and the drains are the output terminals.

[0041] The current shunt unit includes a first current shunt subunit, a second current shunt subunit, and a current shunt transistor. The first current shunt subunit includes a third MOS transistor, the input terminal of which is connected to the output terminal of a first low-bit current source. The second current shunt subunit includes a fourth MOS transistor, and the current shunt transistor is a fifth MOS transistor. The input terminals of the fourth and fifth MOS transistors are connected to the output terminal of the first low-bit current source. The aspect ratio of the third MOS transistor is twice that of the fourth MOS transistor, and the aspect ratios of the fourth and fifth MOS transistors are the same.

[0042] To address the problems existing in the prior art, this invention introduces a third MOS transistor M3, a fourth MOS transistor M4, and a fifth MOS transistor M5. The drain of the first MOS transistor M1 is connected to the source of the third MOS transistor M3, the fourth MOS transistor M4, and the fifth MOS transistor M5. The gates of the third MOS transistor M3, the fourth MOS transistor M4, and the fifth MOS transistor M5 receive a control signal, for example, connected to a voltage source in this embodiment. The third MOS transistor M3, the fourth MOS transistor M4, and the fifth MOS transistor M5 constitute a shunt unit 50. The first MOS transistor M1 is a current source, corresponding to bits 1 and 2 in the binary digital signal. For bits 2 and 1, the third MOS transistor M3 and the fourth MOS transistor M4 are binary weighted current sources. The fifth transistor M5 is a shunt transistor designed to maintain the proportional relationship of the currents, ensuring that the currents of bits 2 and 1 are twice the ratio. In this embodiment, the width-to-length ratio (W / L) of the first MOS transistor M1 is 1, the width-to-length ratio of the second MOS transistor M2 is 1, the width-to-length ratio of the third MOS transistor M3 is 2, the width-to-length ratio of the fourth MOS transistor M4 is 1, and the width-to-length ratio of the fifth MOS transistor M5 is 1. Of course, in other embodiments, the width-to-length ratio of the MOS transistors in the shunt unit only needs to satisfy the correspondence from the low bit to the high bit, with the width-to-length ratio doubling sequentially, and the shunt transistor having the same width-to-length ratio as the MOS transistor of the bit it shunts. For example, the width-to-length ratio of MOS transistor M3 is 2, the width-to-length ratio of MOS transistor M4 is 1, and the width-to-length ratio of MOS transistor M5 is 1.

[0043] In the traditional method, the width-to-length ratios of the current source MOS transistors corresponding to bit2 and bit1 are W / L = 0.5 and W / L = 0.25, respectively.

[0044] In this embodiment, the MOS transistor in the shunt unit is a PMOS transistor, but an NMOS version can also be made using the same principle. Clearly, since all the MOS transistors in the current source have integer multiples of W / L in this invention, the matching or linearity of the DAC should be excellent.

[0045] The low-bit switching unit group 60 includes four low-bit switching units. The input terminal of the first low-bit switching unit 601 is connected to the drain of the second MOS transistor M2, and the output terminal is connected to the output terminal of the current steering DAC. The input terminal of the second low-bit switching unit 602 is connected to the drain of the third MOS transistor M3, and the output terminal is connected to the output terminal Ioutn / Ioutp of the current steering DAC. The input terminal of the third low-bit switching unit 603 is connected to the drain of the fourth MOS transistor M4, and the output terminal is connected to the output terminal Ioutn / Ioutp of the current steering DAC. The input terminal of the fourth low-bit switching unit 604 is connected to the drain of the fourth MOS transistor M4, and the output terminal is grounded.

[0046] In this embodiment, the first low-bit switching unit includes MOS transistor pairs Ms3p and Ms3n; the second low-bit switching unit includes MOS transistor pairs Ms2p and Ms2n; the third low-bit switching unit includes MOS transistors Ms1p and Ms1n; and the fourth low-bit switching unit includes MOS transistors Msp and Msn. The sources of MOS transistors Ms1p and Ms1n are connected to the drain of the fourth MOS transistor M4, and their gates receive the first bit binary signal bit1. The sources of MOS transistor pairs Ms2p and Ms2n are connected to the drain of the third MOS transistor M3, and their gates receive the second bit binary signal bit2. The sources of MOS transistor pairs Ms3p and Ms3n are connected to the drain of the second MOS transistor M2, and their gates receive the third bit binary signal bit3. The drain is the output terminal Ioutn / Ioutp. The sources of MOS transistors Msp and Msn are connected to the drain of the fourth MOS transistor M4, and their gates receive a conduction control signal. The drain is grounded; in other embodiments, if NMOS transistors are used, the drain is connected to a high level.

[0047] The outputs of the high-bit switching unit group 30 and the low-bit switching unit 60 are connected.

[0048] If the number of bits in the binary weighted DAC is increased by 1 bit, a shunt sub-unit can be added. For example, the added shunt sub-unit can use 2 or 4 MOS transistors connected in parallel to achieve proportional shunt, or a new shunt stage consisting of 2 MOS transistors can be added to the next stage of the original shunt unit.

[0049] In this embodiment, as Figure 4The circuit diagram shown is for an 8-bit segmented current-controlled DAC. The shunt units include a first shunt subunit, a second shunt subunit, a third shunt subunit, and shunt transistors. The first shunt subunit includes a third MOS transistor M3, whose input terminal is connected to the output terminal of the first low-bit current source, i.e., the drain of the first MOS transistor M1. The second shunt subunit includes a fourth MOS transistor M4, whose input terminal is connected to the drain of the first MOS transistor M1. The third shunt subunit includes a fifth MOS transistor M5, and the shunt transistor is a sixth MOS transistor M6. The input terminals of the fifth MOS transistor M5 and the sixth MOS transistor M6 are connected to the drain of the first MOS transistor M1. The aspect ratio of the third MOS transistor is twice that of the fourth MOS transistor, the aspect ratio of the fourth MOS transistor is twice that of the fifth MOS transistor, and the aspect ratios of the fifth MOS transistor M5 and the sixth MOS transistor are equal.

[0050] Similarly, if the number of bits increases, the current can be further split into sub-units, and all such schemes are within the protection scope of this invention.

[0051] Continue to refer to Figure 4 The low-bit switching unit group 60 includes 5 low-bit switching units; wherein the input terminal of the first low-bit switching unit 601 is connected to the output terminal of the second low-bit current source group, and the output terminal is connected to the output terminal of the current steering DAC; the input terminal of the second low-bit switching unit 602 is connected to the output terminal of the third MOS transistor, and the output terminal is connected to the output terminal of the current steering DAC; the input terminal of the third low-bit switching unit 603 is connected to the output terminal of the fourth MOS transistor, and the output terminal is connected to the output terminal of the current steering DAC; the input terminal of the fourth low-bit switching unit 604 is connected to the output terminal of the fifth MOS transistor M5, and the output terminal is connected to the output terminal of the current steering DAC; the input terminal of the fifth low-bit switching unit 605 is connected to the output terminal of the sixth MOS transistor M6, and the output terminal is grounded.

[0052] This invention addresses the analog circuit matching problem by adding a shunt unit, while also taking into account the limitations of the DRC rule. This results in optimized circuit performance, reduced chip area, and lower costs.

[0053] The various embodiments of the present invention have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments.

Claims

1. A segmented current-steering DAC, characterized by, The application relates to a thermometer decoder, a high-bit current source group, a high-bit switch unit group, a low-bit current source group, a shunt unit, and a low-bit switch unit group. The thermometer decoder is used for decoding high bits of a digital signal to obtain a thermometer code; the input end of the high-bit current source group is connected with a current mirror; the high-bit current source group comprises high-bit sub-current sources formed by an array of MOS transistors; the control end of the high-bit switch unit group is inputted with the thermometer code; the input end of the high-bit switch unit group is connected with the output end of the high-bit current source group; the output end of the high-bit switch unit group is connected with the output end of a current steering DAC; the input end of the low-bit current source group is connected with the current mirror; the low-bit current source group comprises a first low-bit current source and a second low-bit current source formed by MOS transistors; the shunt unit comprises shunt sub-units corresponding to bits; the input end of the shunt sub-units is connected with the output end of the first low-bit current source; the shunt unit comprises a first shunt sub-unit, a second shunt sub-unit and a shunt transistor; the first shunt sub-unit comprises a third MOS transistor; the input end of the third MOS transistor is connected with the output end of the first low-bit current source; the second shunt sub-unit comprises a fourth MOS transistor; the third shunt sub-unit comprises a fifth MOS transistor; the input end of the fourth MOS transistor and the fifth MOS transistor is connected with the output end of the first low-bit current source; the width-length ratio of the third MOS transistor is twice that of the fourth MOS transistor; the width-length ratio of the fourth MOS transistor is twice that of the fifth MOS transistor; the width-length ratio of the fifth MOS transistor is equal to that of the sixth MOS transistor; the third MOS transistor, the fourth MOS transistor and the fifth MOS transistor are all MOS transistors; the first low-bit current source comprises a first MOS transistor; the control end of the low-bit switch unit group is respectively inputted with low-bit binary signals from the input digital signal; the output end of the low-bit switch unit group is connected with the output end of the current steering DAC; the input end of one of the low-bit switch units is connected with the output end of the second low-bit current source group; according to the bit correspondence, the input end of the remaining low-bit switch units is respectively connected with the output end of the shunt sub-units. The high-bit current source group comprises 15 high-bit sub-current sources; the width-length ratio of the MOS transistors of the high-bit current source group is 2; the width-length ratio of the MOS transistors of the first low-bit sub-current source and the second low-bit sub-current source is 1. The low-bit switch unit group comprises four low-bit switch units; the input end of the first low-bit switch unit is connected with the output end of the second low-bit current source group; the output end of the first low-bit switch unit is connected with the output end of the current steering DAC; the input end of the second low-bit switch unit is connected with the output end of the third MOS transistor; the output end of the second low-bit switch unit is connected with the output end of the current steering DAC; the input end of the third low-bit switch unit is connected with the output end of the fourth MOS transistor; the output end of the third low-bit switch unit is connected with the output end of the current steering DAC. ​ ​ ​ ​ ​ ​ ​ 2. The segmented current-steering DAC of claim 1, wherein, ​ 3. The segmented current-steering DAC of claim 2, wherein, ​ ​ ​ The input end of the fourth low-bit switch unit is connected with the output end of the fifth MOS transistor, and the output end is grounded.

4. The segmented current-steering DAC of claim 3, wherein, The width-length ratio of the third MOS transistor is 2, and the width-length ratio of the fourth MOS transistor and the fifth MOS transistor is 1.

5. The segmented current-steering DAC of claim 4, wherein, The low-bit switch unit group comprises five low-bit switch units; the input end of the first low-bit switch unit is connected with the output end of the second low-bit current source group, and the output end is connected with the output end of the current steering DAC; The input end of the second low-bit switch unit is connected with the output end of the third MOS transistor, and the output end is connected with the output end of the current steering DAC; The input end of the third low-bit switch unit is connected with the output end of the fourth MOS transistor, and the output end is connected with the output end of the current steering DAC; The input end of the fourth low-bit switch unit is connected with the output end of the fifth MOS transistor, and the output end is connected with the output end of the current steering DAC; the input end of the fifth low-bit switch unit is connected with the input end of the sixth MOS transistor, and the output end is grounded.

6. The segmented current-steering DAC of claim 3, wherein, The low-bit sub-current source and the high-bit sub-current source are one-unit current sources, which are composed of one MOS transistor.

7. The segmented current-steering DAC of claim 3, wherein, The high-bit switch unit group comprises multiple high-bit switch units, which are connected with the high-bit sub-current sources one by one.

8. The segmented current-steering DAC of claim 3, wherein, The high-bit switch unit and the low-bit switch unit are composed of a pair of MOS transistors to form a differential switch.

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