Memory cell, memory and method of manufacturing the same

Abstract

The application belongs to the technical field of semiconductor, and particularly relates to a storage unit, a memory and a manufacturing method thereof. The storage unit is arranged in an isolation layer on one side of a substrate. The isolation layer comprises a containing hole. The storage unit comprises a channel layer, an insulating medium layer, a gate electrode layer and a gate medium layer. The channel layer comprises a first channel and a second channel which are arranged in stacks and form intervals. The first channel is located in the containing hole, and the second channel is at least partially located in the containing hole. The insulating medium layer is formed at least between the first channel and the second channel. The gate electrode layer comprises a first gate and a second gate. The first gate is formed in the inner hole of the first channel and directly or indirectly connected with the second channel. The second gate is at least partially formed in the inner hole of the second channel. The gate medium layer is formed between the gate electrode layer and the channel layer. The channel layer, the gate medium layer and the gate electrode layer form reading and writing tubes of a vertical channel arranged in stacks, thereby reducing the area occupied by the storage unit and improving the integration density of the transistor.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor, and particularly relates to a storage unit, a memory and a manufacturing method thereof. BACKGROUND

[0002] A common storage unit of dynamic random access memory (DRAM) is a MOS (Metal Oxide Semiconductor) transistor drain connected to a capacitor. Such a storage unit needs to constantly refresh the charge in the capacitor to ensure that data is not lost, and needs to discharge the charge in the capacitor when reading, and then re-write after reading is completed, which has high power consumption. At the same time, due to the large area occupied by the capacitor, size miniaturization becomes a problem.

[0003] A two-transistor 0-capacitor (2T0C) dynamic random access memory uses two MOS transistors as a storage unit, in which the drain of one transistor is connected to the gate of the other transistor, and the gate capacitance is used to store charge and change the transistor transconductance to store information.

[0004] The existing dynamic random access memory based on the 2T0C storage unit generally uses two horizontal channel thin film transistors (TFT) connected on the same plane, which has a large area and low integration density. SUMMARY

[0005] The present application aims to provide a storage unit, a memory and a manufacturing method thereof, so as to reduce the area occupied by the storage unit and improve the integration density of the dynamic random access memory.

[0006] In order to achieve the above-mentioned purpose, the present application provides a storage unit arranged in an isolation layer on one side of a substrate, the isolation layer comprising a receiving hole, the storage unit comprising:

[0007] a channel layer comprising a first channel and a second channel arranged in a stack and forming a space, the first channel being located in the receiving hole, and the second channel being at least partially located in the receiving hole, the first channel having a first inner hole away from the one side of the substrate, and the second channel having a second inner hole away from the one side of the substrate;

[0008] an insulating medium layer formed at least between the first channel and the second channel;

[0009] a gate electrode layer, comprising a first gate electrode and a second gate electrode, the first gate electrode being formed in the first inner hole and directly or indirectly connected with the second channel, the second gate electrode being at least partially formed in the second inner hole;

[0010] a gate dielectric layer, formed between the gate electrode layer and the channel layer.

[0011] Optionally, the memory cell further comprises a conductor layer, the conductor layer comprising a first conductor portion, the first conductor portion being at least partially located between the first gate electrode and the second channel, the first gate electrode and the second channel being indirectly connected through the first conductor portion, the insulating dielectric layer being arranged around the first conductor portion.

[0012] Optionally, the first conductor portion at least partially extends into the first gate electrode in the first inner hole.

[0013] Optionally, a height of an upper surface of the first conductor portion relative to the substrate is greater than or equal to a height of the insulating dielectric layer relative to the substrate.

[0014] Optionally, the conductor layer further comprises a second conductor portion, the second conductor portion being at least partially arranged in the second inner hole, the second gate electrode being located between the second conductor portion and the gate dielectric layer.

[0015] Optionally, the memory cell further comprises a lead layer, the lead layer comprising a first lead layer, a second lead layer and a third lead layer arranged in intervals, the first lead layer comprising a first drain electrode, the second lead layer comprising a first source electrode, the third lead layer comprising a second source electrode, the first drain electrode and the first source electrode being both located outside the accommodating hole and connected with the first channel, the second source electrode being located outside the accommodating hole and connected with the second channel, the accommodating hole penetrating the second source electrode and the first source electrode to connect with the first drain electrode.

[0016] Optionally, the first channel is partially embedded in the first drain electrode near one end of the substrate.

[0017] The application further provides a memory, comprising:

[0018] a plurality of the memory cells;

[0019] a write word line connected with the second gate electrodes of the plurality of memory cells;

[0020] a write bit line connected with the second source electrodes of the plurality of memory cells;

[0021] a read word line connected with the first drain electrodes of the plurality of memory cells;

[0022] a read bit line connected with the first source electrodes of the plurality of memory cells.

[0023] The application also provides a manufacturing method of a memory, comprising:

[0024] forming an isolation layer and a lead layer on a substrate, the lead layer comprising a first lead layer, a second lead layer and a third lead layer formed in sequence and arranged at intervals, the first lead layer, the second lead layer and the third lead layer are all located in the isolation layer, the first lead layer comprises a first drain and a read word line connected integrally, the second lead layer comprises a first source and a read bit line connected integrally, and the third lead layer comprises a second source and a write bit line connected integrally;

[0025] forming a receiving hole through the second source and the first source and extending to the first drain on the isolation layer;

[0026] forming a first channel, a first gate dielectric part and a first gate in the receiving hole, the first drain and the first source are both connected with the first channel;

[0027] forming an insulating dielectric layer at least on a side of the first channel away from the substrate;

[0028] forming a second channel, a second gate dielectric part, a second gate and a write word line on a side of the insulating dielectric layer away from the substrate, the second channel, the second gate dielectric part and the second gate are all at least partially located in the receiving hole, the first gate is directly or indirectly connected with the second channel, the second source is connected with the second channel, and the write word line is connected with the second gate.

[0029] Optionally, the manufacturing method of the memory comprises:

[0030] forming a first channel layer, a first gate dielectric layer, a first gate electrode layer and a first conductor layer in sequence on a side of the isolation layer away from the substrate, the first channel layer, the first gate dielectric layer, the first gate electrode layer and the first conductor layer are all at least partially located in the receiving hole;

[0031] removing part of the first conductor layer to form a first conductor part in the receiving hole, and then removing part of the first channel layer, the first gate dielectric layer and the first gate electrode layer to form the first channel, the first gate dielectric part and the first gate in the receiving hole, the height of the upper surface of the first conductor part relative to the substrate is greater than the height of the first channel, the first gate dielectric part and the first gate relative to the substrate;

[0032] forming the insulating medium layer surrounding the first conductor portion on a side of the first channel, the first gate medium portion and the first gate away from the substrate, a height of the insulating medium layer relative to the substrate is less than or equal to a height of the first conductor portion relative to the substrate;

[0033] forming a second channel layer, a second gate medium layer, a second gate electrode layer, a second conductor layer and a fourth lead layer on a side of the isolation layer away from the substrate in sequence, the second channel layer, the second gate medium layer, the second gate electrode layer and the second conductor layer are at least partially located in the accommodation hole, and the second channel layer, the second gate medium layer, the second gate electrode layer, the second conductor layer and the fourth lead layer are patterned to form the second channel, the second gate medium portion, the second gate, the second conductor portion and the write word line.

[0034] Optionally, part of the first channel layer, the first gate medium layer, the first gate electrode layer and the first conductor layer are removed by isotropic etching, so that a height of the first conductor portion is greater than a height of the first channel, the first gate medium portion and the first gate.

[0035] Optionally, when the insulating medium layer is formed, an insulating medium base layer covering the first conductor portion, the first channel and the first gate medium portion is formed in the accommodation hole.

[0036] Part of the insulating medium base layer is removed by isotropic etching to form the insulating medium layer.

[0037] Optionally, when the accommodation hole is formed through the second source electrode and the first source electrode and extending to the first drain electrode on the isolation layer, an etching depth is greater than a depth of an upper surface of the first drain electrode.

[0038] Optionally, a normal projection of the accommodation hole on the substrate is located in a normal projection of the first drain electrode, the first source electrode and the second source electrode on the substrate.

[0039] The storage unit, the memory and the manufacturing method thereof disclosed in the application have the following beneficial effects:

[0040] In the application, the storage unit comprises a source-drain electrode, a channel layer, a gate dielectric layer and a gate electrode layer, the channel layer comprises a first channel and a second channel which are arranged in stack and form a space, the first channel is located in the accommodation hole, the second channel is at least partially located in the accommodation hole, the gate electrode layer comprises a first gate and a second gate, the first gate is formed in the first inner hole of the first channel, the second gate is at least partially formed in the second inner hole of the second channel, and the gate dielectric layer is formed between the gate electrode layer and the channel layer. The source-drain electrode, the channel layer, the gate dielectric layer and the gate electrode layer form a reading tube and a writing tube of the vertical channel arranged in stack, and the channels of the reading tube and the writing tube are in the same accommodation hole. Compared with the storage unit connected with the thin film transistor using two horizontal channels in the same plane, the storage unit occupies a smaller area and improves the integration density of the transistor.

[0041] Other features and advantages of the present application will become apparent from the following detailed description, or will be learned by practice of the present application.

[0042] It should be understood that the foregoing general description and the following detailed description are only exemplary and explanatory, and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0043] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and serve to explain the principles of the present application. It is readily apparent to one skilled in the art that the following figures are merely some embodiments of the present application, and other figures can be obtained from these figures without creative labor.

[0044] Figure 1 is a schematic diagram of a storage unit X-direction section in the first embodiment of the present application.

[0045] Figure 2 is a schematic diagram of a storage unit Y-direction section in the first embodiment of the present application.

[0046] Figure 3 is a schematic diagram of a circuit structure of a storage unit in the first embodiment of the present application.

[0047] Figure 4 is a schematic diagram of a circuit structure of a storage unit in the first embodiment of the present application.

[0048] Figure 5 is a flow chart of a manufacturing method of a storage unit in the first embodiment of the present application.

[0049] Figure 6 is a schematic diagram of forming an isolation layer and a lead layer in the first embodiment of the present application.

[0050] Figure 7 is a schematic diagram of opening a hole in the isolation layer in the first embodiment of the present application.

[0051] Figure 8 is a schematic diagram of forming a first conductor layer in an embodiment of the present application.

[0052] Figure 9 is a schematic diagram of forming a first conductor part in an embodiment of the present application.

[0053] Figure 10 is a schematic diagram of forming a read tube in an embodiment of the present application.

[0054] Figure 11 is a schematic diagram of forming an insulating medium base layer in an embodiment of the present application.

[0055] Figure 12 is a schematic diagram of forming an insulating medium layer in an embodiment of the present application.

[0056] Figure 13 is a schematic diagram of forming a fourth lead layer in an embodiment of the present application.

[0057] Figure 14 is a schematic diagram of forming a write tube X-direction cross section in an embodiment of the present application.

[0058] Figure 15 is a schematic diagram of forming a write tube Y-direction cross section in an embodiment of the present application.

[0059] Explanation of reference signs:

[0060] 10, write tube; 20, read tube;

[0061] 100, substrate; 200, isolation layer; 210, accommodating hole;

[0062] 300, lead layer; 310, first lead layer; 311, first drain electrode; 320, second lead layer; 321, first source electrode; 330, third lead layer; 331, second source electrode; 340, fourth lead layer;

[0063] 400, channel layer; 410, first channel layer; 411, first channel; 412, first inner hole; 420, second channel layer; 421, second channel; 422, second inner hole;

[0064] 500, gate medium layer; 510, first gate medium layer; 511, first gate medium part; 520, second gate medium layer; 521, second gate medium part;

[0065] 600, gate electrode layer; 610, first gate electrode layer; 611, first gate electrode; 620, second gate electrode layer; 621, second gate electrode;

[0066] 700, conductor layer; 710, first conductor layer; 711, first conductor portion; 720, second conductor layer; 721, second conductor portion; 800, insulating medium layer; 900, photoresist. DETAILED DESCRIPTION

[0067] Example implementations are now described with reference to the drawings; however, these descriptions are not intended to limit the scope of the application, but are intended to provide example examples, which, while possibly being the best modes of practicing the application at the time, were developed for purposes of illustration. The examples illustrate the principles of the present application and other examples can be used and otherwise specified by those skilled in the art. The examples are not intended to restrict or limit the scope of the present application to the examples described herein.

[0068] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the application. One skilled in the relevant art will recognize, however, that the

[0069] The present application will be further described with reference to the drawings and specific examples. It is to be understood that the specific examples described herein are merely examples and are not intended to limit the scope of the present application. The examples are intended to illustrate the principles of the present application.

[0070] Referring to Figure 1 and Figure 2 In the present embodiment, the storage unit includes a source-drain electrode, a channel layer 400, a gate medium layer 500, a gate electrode layer 600, and an insulating medium layer 800. The storage unit is located in the isolation layer 200 on the substrate 100, and is connected to the extended portion of the lead layer 300.

[0071] The substrate 100 can be any substrate known to those skilled in the art for carrying a semiconductor integrated circuit substrate, such as an insulating substrate, a semiconductor substrate, or a composite substrate, without limitation. It can be understood that the substrate 100 can be removed after the storage unit is manufactured, and the storage unit is bonded to another substrate, such as a peripheral substrate containing peripheral devices, a temporary support substrate, or a substrate provided with other devices, after the substrate 100 is removed. The relationship between the substrate 100 and the storage unit is not specifically limited in the present application.

[0072] The channel layer 400 includes a first channel 411 and a second channel 421, which are stacked and spaced apart. The isolation layer 200 includes a receiving hole 210. The first channel 411 is located in the receiving hole 210, and the second channel 421 is at least partially located in the receiving hole 210. The first channel 411 has a first inner hole 412 on the side away from the substrate 100, and the second channel 421 has a second inner hole 422 on the side away from the substrate 100.

[0073] An insulating dielectric layer 800 is formed at least between the first channel 411 and the second channel 421. The gate electrode layer 600 includes a first gate 611 and a second gate 621. The first gate 611 is formed within a first inner hole 412 and is directly or indirectly connected to the second channel 421. The second gate 621 is at least partially formed within a second inner hole 422. The first gate 611 and the second gate 621 are respectively surrounded by the first channel 411 and the second channel 421, thus the transistor has a larger channel width, improving the transistor's read / write current. A gate dielectric layer 500 is formed between the gate electrode layer 600 and the channel layer 400, serving as insulation between the gate and the channel. The gate dielectric layer 500 may include a first gate dielectric portion 511 and a second gate dielectric portion 521, with the first gate dielectric portion 511 located between the first channel 411 and the first gate 611, and the second gate dielectric portion 521 located between the second channel 421 and the second gate 621.

[0074] like Figure 2 In the illustrated embodiment, the lead layer 300 includes a first lead layer 310, a second lead layer 320, and a third lead layer 330 formed sequentially, all of which are located within the isolation layer 200. The source / drain electrodes include a first drain 311, a first source 321, and a second source 331. Either the source / drain electrode can be distinct from the lead layer, or it can be the portion of the lead layer 300 connected to the channel layer 400, i.e., integrally formed with the lead layer 300; this application does not impose specific limitations. In this embodiment, each of the source / drain electrodes is integral with the lead layer 300; that is, the first lead layer 310 includes the first drain 311, the second lead layer 320 includes the first source 321, and the third lead layer 330 includes the second source 331. The first drain 311 and the first source 321 are both located outside the receiving hole 210 and are both connected to the first channel 411. The second source 331 is located outside the receiving hole 210 and is connected to the second channel 421.

[0075] The storage unit includes two thin film transistors, which are stacked on the substrate 100. The two thin film transistors are a read transistor 20 and a write transistor 10, respectively. The read transistor 20 includes a first gate 611, a first channel 411, a first drain 311 and a first source 321. The write transistor 10 includes a second drain, a second source 331, a second channel 421 and a second gate 621.

[0076] The existing dynamic random memory based on the 2T0C storage unit generally uses the connection of two horizontal channel thin film transistors on the same plane, occupies a large area, and has a low storage density.

[0077] In the embodiment, the storage unit includes a source-drain electrode, a channel layer 400, a gate dielectric layer 500 and a gate electrode layer 600. The channel layer 400 includes a first channel 411 and a second channel 421 which are stacked and spaced. The first channel 411 is located in the accommodation hole 210, and the second channel 421 is at least partially located in the accommodation hole 210. The gate electrode layer 600 includes a first gate 611 and a second gate 621. The first gate 611 is formed in a first inner hole 412 of the first channel 411, and the second gate 621 is at least partially formed in a second inner hole 422 of the second channel 421. The gate dielectric layer 500 is formed between the gate electrode layer 600 and the channel layer 400. The lead layer 300 includes a first drain 311, a first source 321 and a second source 331. The first drain 311 and the first source 321 are both connected to the periphery of the first channel 411, and the second source 331 is connected to the periphery of the second channel 421. The source-drain electrode, the channel layer 400, the gate dielectric layer 500 and the gate electrode layer 600 form a read transistor 20 and a write transistor 10 with vertically stacked channels. The channels of the read transistor 20 and the write transistor 10 are in the same accommodation hole 210. Compared with the storage unit using the connection of two horizontal channel thin film transistors on the same plane, the storage unit reduces the occupied area of the storage unit and improves the integration density of the transistor.

[0078] In addition, the first channel 411 is entirely located in the accommodation hole 210, and the second channel 421 is at least partially located in the accommodation hole 210. The first channel 411 and the second channel 421 are stacked in the same accommodation hole 210, which can simplify the manufacturing process of the memory and reduce the manufacturing cost of the memory during the formation of the vertically stacked write transistor 10 and read transistor 20.

[0079] Referring to FIGS. 1, 2 and 3, Figure 1 and Figure 2 As shown in FIGS. 1, 2 and 3, the storage unit further includes a conductor layer 700. The conductor layer 700 includes a first conductor part 711, which is at least partially located between the first gate 611 and the second channel 421. The first gate 611 and the second channel 421 are indirectly connected through the first conductor part 711.

[0080] The first conductor portion 711 can store or discharge charges when the write tube 10 is open, and the charges stored in the first conductor portion 711 can affect the read current of the read tube 20. Therefore, the first conductor portion 711 can adopt a conductive material with strong charge storage capability, such as doped polysilicon, but the present application is not limited thereto as long as the material of the conductor layer 700 can achieve charge storage.

[0081] Referring to Figure 1 and Figure 2 The insulating medium layer 800 is arranged around the first conductor portion 711. The orthographic projection of the first conductor portion 711 on the substrate 100 is located within the orthographic projection of the first gate 611 on the substrate 100, and the first gate 611 is located between the first conductor portion 711 and the first gate medium portion 511 of the gate medium layer 500. That is, the insulating medium layer 800 separates the first gate 611, the first gate medium portion 511, and the first channel 411 from the second gate 621, the second gate medium portion 521, and the second channel 421.

[0082] The insulating medium layer 800 is arranged around the first conductor portion 711, separates the first conductor portion 711 from the first channel 411, and avoids short circuit between the first conductor portion 711 and the first channel 411, that is, avoids short circuit between the gate and the channel of the read tube 20, thereby affecting the function of the read tube 20. Referring to Figure 1 and Figure 2 The first conductor portion 711 at least partially extends into the first gate 611 in the first inner hole 412.

[0083] The first conductor portion 711 is arranged in the groove formed on the side surface of the first gate 611 away from the first channel 411, and the first conductor portion 711 is connected with the second channel 421. This design can improve the electrical characteristics of the read tube 20 and improve the performance of the storage unit.

[0084] Referring to Figure 1 and Figure 2 The upper surface of the first conductor portion 711 is higher than the upper surface of the end portion of the first gate 611. The first gate 611 and the second channel 421 are arranged in a spaced manner, and the first conductor portion 711 is partially located in the first inner hole 412 and partially located outside the first inner hole 412, and the first gate 611 and the second channel 421 are indirectly connected through the first conductor portion 711.

[0085] The first gate 611 is spaced apart from the second channel 421, the first conductor portion 711 is connected with the second channel 421, and the first gate 611 is not connected with the second channel 421. Thus, the first gate 611 of the read tube 20 can use different materials from the first conductor portion 711, and the material of the first gate 611 of the read tube 20 can be selected according to the electrical characteristics of the read tube 20, and the first conductor portion 711 with strong charge holding capacity can ensure the storage performance of the storage unit.

[0086] Referring to FIGS. 1 and 2, Figure 1 and Figure 2 As shown in FIGS. 1 and 2, the height of the upper surface of the first conductor portion 711 relative to the substrate 100 is greater than or equal to the height of the upper surface of the insulating medium layer 800 relative to the substrate 100.

[0087] The first conductor portion 711 is flush with the insulating medium layer 800 or slightly protrudes from the insulating medium layer 800, which can ensure reliable connection between the first conductor portion 711 and the second channel 421, and the preparation surface of the second channel 421 is relatively flat, thereby reducing the leakage.

[0088] Referring to FIGS. 1 and 2, Figure 1 and Figure 2 As shown in FIGS. 1 and 2, the conductor layer 700 further includes a second conductor portion 721, the second conductor portion 721 is at least partially disposed in the second inner hole 422, and the second gate 621 is located between the second conductor portion 721 and the second gate medium portion 521 of the gate medium layer 500.

[0089] The second conductor portion 721 is disposed in the groove formed on the upper surface of the second gate 621, the stack of the second conductor portion 721 and the second gate 621 is connected with the write word line WWL, which improves the electrical connection between the second gate 621 and the write word line WWL; and when the write word line WWL is prepared at the same time as the second conductor portion 721 and the second gate 621, the process cost, process difficulty, and impedance of the write word line WWL can be reduced, thereby reducing signal delay.

[0090] Referring to FIGS. 1 and 2, Figure 1 and Figure 3 As shown in FIGS. 1 and 2, the second gate 621 of the write tube 10 is connected with the write word line WWL, the second source 331 of the write tube 10 is connected with the write bit line WBL, and the second drain of the write tube 10 is connected with the storage node A. The first gate 611 of the read tube 20 is connected to the storage node A, the first source 321 of the read tube 20 is connected with the read word line RWL, and the first drain 311 of the read tube 20 is connected with the read bit line RBL.

[0091] It can be understood that the connection relationship of the write word line WWL, the write bit line WBL and the write tube 10 can be interchangeable, the connection relationship of the read word line RWL, the read bit line RBL and the read tube 20 can be interchangeable, and the operation method of the write word line WWL, the write bit line WBL, the read word line RWL and the read bit line RBL in the storage operation is also changed correspondingly, and the application is not limited specifically.

[0092] The storage unit changes the charge in the gate capacitor of the read tube 20 through the write tube 10, and then affects the resistance state between the source and the drain of the read tube 20, so as to realize the distinction of "0" and "1". It can be understood that in the embodiment, the gate capacitor of the read tube 20 is the storage node A.

[0093] The specific storage principle of the storage unit is as follows:

[0094] In the process of writing "1", the write word line WWL adds a positive voltage (greater than the threshold voltage Vth) to the gate electrode of the write tube 10 to make the write tube 10 open, and the write bit line WBL adds a positive voltage to the source electrode of the write tube 10 to inject charges into the gate capacitor (i.e. the storage node A) of the read tube 20. After the charge injection, the gate voltage and the source voltage of the write tube 10 are removed, and the "1" state is saved; Figure 3 In the process of reading "1", the read word line RWL adds a read voltage to the source electrode of the read tube 20. Since there is a certain charge in the gate capacitor, the read tube 20 is in a lower resistance state, and the read bit line RBL obtains a larger current. After amplification and identification by the peripheral circuit, the reading "1" process is completed;

[0095] In the process of writing "0", the write word line WWL adds a positive voltage (greater than the threshold voltage Vth) to the gate electrode of the write tube 10 to make the write tube 10 open, and the write bit line WBL adds a negative voltage to the source electrode of the write tube 10 to extract charges from the gate capacitor (i.e. the storage node) of the read tube 20. After the charge extraction, the gate voltage and the source voltage of the write tube 10 are removed, and the "0" state is saved;

[0096] In the process of reading "0", the read word line RWL adds a read voltage to the source electrode of the read tube 20. Since there is no charge in the gate capacitor, the read tube 20 is in a higher resistance state, and the read bit line RBL obtains a smaller current. After amplification and identification by the peripheral circuit, the reading "0" process is completed.

[0097] It can be understood that the connection relationship of the write word line WWL, the write bit line WBL and the write tube 10 can be interchangeable, the connection relationship of the read word line RWL, the read bit line RBL and the read tube 20 can be interchangeable, and the operation method of the write word line WWL, the write bit line WBL, the read word line RWL and the read bit line RBL in the storage operation is also changed correspondingly, and the application is not limited specifically.

[0098] It can be understood that the connection relationship of the write word line WWL, the write bit line WBL and the write tube 10 can be interchangeable, the connection relationship of the read word line RWL, the read bit line RBL and the read tube 20 can be interchangeable, and the operation method of the write word line WWL, the write bit line WBL, the read word line RWL and the read bit line RBL in the storage operation is also changed correspondingly, and the application is not limited specifically. Figure 1 and Figure 2As shown, the first channel 411 is wholly located in the accommodating hole 210, and the second channel 421 is at least partially located in the accommodating hole 210. That is, the second channel 421 can be partially located in the accommodating hole 210 and partially extend out of the orifice of the accommodating hole 210. The orthographic projection of the first channel 411 on the substrate 100 is located in the orthographic projection of the second channel 421 on the substrate 100. That is, the area occupied by the first channel 411 is less than or equal to the area occupied by the second channel 421. It can be understood that the area occupied by the first channel 411 and the area occupied by the second channel 421 do not have a specific relationship, which is not limited in the present application.

[0099] The area occupied by the first channel 411 is less than or equal to the area occupied by the second channel 421, and the read tube 20 and the write tube 10 can be completely overlapped together, so as to reduce the area occupied by the storage unit and improve the storage density. It can be understood that as long as the orthographic projection of the first channel 411 on the substrate 100 and the orthographic projection of the second channel 421 on the substrate 100 have an overlap, the read tube 20 and the write tube 10 can be stacked with each other, so as to reduce the area occupied by the storage unit and improve the storage density.

[0100] Referring to Figure 1 and Figure 2 As shown, in one embodiment, the first channel 411 and the second channel 421 are both cylindrical structures, and the first inner hole 412 and the second inner hole 422 are inner holes of the cylindrical structures. The cylindrical part of the first channel 411 and the cylindrical part of the second channel 421 are coaxially arranged, and the outer diameter of the cylindrical part of the first channel 411 is equal to the outer diameter of the cylindrical part of the second channel 421.

[0101] The cylindrical part of the first channel 411 and the cylindrical part of the second channel 421 are both located in the accommodating hole 210 of the isolation layer 200, which can simplify the manufacturing process of the memory and reduce the manufacturing cost of the memory in the process of forming the vertically stacked write tube 10 and read tube 20. At the same time, the cylindrical part of the first channel 411 and the cylindrical part of the second channel 421 are both located in the accommodating hole 210 of the isolation layer 200, that is, the main body structure of the write tube 10 and the read tube 20 are both located in the accommodating hole 210 of the isolation layer 200, which further reduces the area occupied by the storage unit and improves the integration density of the transistor.

[0102] It should be noted that the second channel 421, the second gate dielectric part 521 and the second gate 621 can all be located in the accommodating hole 210 of the isolation layer 200, but are not limited thereto. The second channel 421, the second gate dielectric part 521 and the second gate 621 can also include a part located outside the accommodating hole 210, which can be determined according to the specific situation.

[0103] Referring to Figure 1 and Figure 2As shown, the lead layer 300 includes a first lead layer 310, a second lead layer 320 and a third lead layer 330 which are arranged in sequence, the first lead layer 310 includes a first drain 311, the second lead layer 320 includes a first source 321, and the third lead layer 330 includes a second source 331. The first drain 311 and the first source 321 are both located outside the accommodating hole 210 and are connected with the first channel 411, and the second source 331 is located outside the accommodating hole 210 and is connected with the second channel 421. The accommodating hole 210 penetrates the second source 331 and the first source 321 and is connected with the first drain 311.

[0104] That is, the orthographic projection of the first channel 411 on the substrate 100 is located within the orthographic projection of the first drain 311 and the first source 321 on the substrate 100, and the orthographic projection of the second channel 421 on the substrate 100 is located within the orthographic projection of the second source 331 on the substrate 100. Specifically, the first channel 411 can be arranged centrally relative to the first drain 311 and the first source 321, and the second channel 421 can be arranged centrally relative to the second source 331.

[0105] The first channel 411 can be arranged centrally relative to the first drain 311 and the first source 321, and the second channel 421 can be arranged centrally relative to the second source 331, which can improve the contact area of the channels of the write tube 10 and the read tube 20 with the corresponding source-drain electrodes, reduce the contact resistance of the source-drain electrodes, improve the performance of the write tube 10 and the read tube 20, and further improve the performance of the storage unit.

[0106] Referring to Figure 1 and Figure 2 As shown, the first lead layer 310 and the second lead layer 320 cross each other, the third lead layer 330 extends in the same direction as the first lead layer 310, and the first channel 411 is formed at the crossing position of the first lead layer 310 and the second lead layer 320. Preferably, the orthographic projection of the first channel 411 on the substrate 100 is located within the orthographic projection of the crossing position of the first lead layer 310 and the second lead layer 320 on the substrate 100.

[0107] Referring to Figure 1 and Figure 2As shown, the portion of the first channel 411 near one end of the substrate 100 is embedded in the first drain 311. That is, the accommodation hole 210 of the isolation layer 200 partially enters the first drain 311. The portion of the first channel 411 near one end of the substrate 100 partially entering the first drain 311 can increase the contact area of the first drain 311 and the first channel 411, reduce the contact resistance, and thus improve the performance of the read tube 20. In other embodiments, the portion of the first channel 411 near one end of the substrate 100 is connected to the first drain 311 in a planar manner, or the portion of the first channel 411 near one end of the substrate 100 is indirectly connected to the first drain 311 through other components.

[0108] In examples, the substrate 100 can be any substrate known to those skilled in the art for carrying a semiconductor integrated circuit substrate, including an insulating substrate, a semiconductor substrate, or a composite substrate, without limitation. In examples, the substrate 100 can be bulk silicon, silicon carbide, germanium, germanium silicon, gallium arsenide, or a semiconductor-on-insulator, etc. In the semiconductor-on-insulator, the corresponding top layer semiconductor material can be silicon, germanium, germanium silicon, or gallium arsenide, etc.

[0109] The isolation layer 200 serves as an interlayer insulating layer and can be a silicon oxide or a low-k (dielectric constant) material layer to reduce crosstalk. The isolation layer 200 can include an air gap. It should be understood that the isolation layer 200 can be any insulating dielectric material known in the art, without limitation.

[0110] The insulating dielectric layer 800 can be made of an insulating material such as nitride or oxynitride, without limitation.

[0111] In some embodiments, the isolation layer 200 and the insulating dielectric layer 800 are made of different materials. The insulating dielectric layer 800 and the isolation layer 200 are made of different materials to have etching selectivity therebetween, facilitating the fabrication of the storage unit. The lead layer 300 and the gate electrode layer 600 can be made of a metal material having good conductivity or a doped semiconductor material. The metal material includes at least one of aluminum (Al), molybdenum (Mo), titanium (Ti), tungsten (W), and an alloy thereof. The doped semiconductor material includes doped polysilicon. The gate electrode layer 600 can be made of a specific material according to the electrical characteristics of the write tube 10 and the read tube 20. The lead layer 300 and the gate electrode layer 600 can be made of the same or different metal material or doped semiconductor material.

[0112] The first conductor portion 711 can be made of a conductive material capable of storing electric charges, such as doped polysilicon, without limitation, as long as the material of the conductor layer 700 can store electric charges.

[0113] In some embodiments, the material for fabricating the conductor layer 700 is different from the material for fabricating the gate electrode layer 600. The material for fabricating the conductor layer 700 is different from the material for fabricating the gate electrode layer 600, so that there is etching selectivity between the two, facilitating fabrication of the storage unit.

[0114] The channel layer 400 can be made of Indium Gallium Zinc Oxide (IGZO). Thin film transistors made of Indium Gallium Zinc Oxide have very small off-state current, and can significantly reduce the leakage speed of dynamic random access memory of 2T0C. It should be understood that the channel layer 400 can be made of Indium Gallium Zinc Oxide material, but is not limited thereto. The channel layer 400 can also be made of other metal oxide or semiconductor materials, as the case can be.

[0115] The gate dielectric layer 500 can be made of high dielectric constant material or other material commonly used in the art for gate dielectric layer, such as hafnium dioxide (HfO2), silicon dioxide (SiO2), and aluminum oxide (Al2O3), etc.

[0116] The application also provides a memory including a plurality of connected storage units.

[0117] Referring to Figures 1 to 4 As shown, the first lead layer 310 includes the first drain 311 and the read word line RWL connected as one, and the first drain 311 of the plurality of storage units is led out by being connected with the read word line RWL. The second lead layer 320 includes the first source 321 and the read bit line RBL connected as one, and the first source 321 of the plurality of storage units is led out by being connected with the read bit line RBL. The third lead layer 330 includes the second source 331 and the write bit line WBL connected as one, and the second source 331 of the plurality of storage units is led out by being connected with the write bit line WBL. The memory further includes the fourth lead layer 340, which is formed on the side of the second conductor portion 721 away from the substrate 100. The write word line WWL includes part of the fourth lead layer 340, and the second gate 621 of the plurality of storage units is led out by being connected with the write word line WWL. The memory can further include an isolation material layer on the fourth lead layer 340, and the isolation layer 200 can be formed by stacking a plurality of isolation material layers.

[0118] In this embodiment, the memory includes multiple interconnected memory cells. Each memory cell includes source / drain electrodes, a channel layer 400, a gate dielectric layer 500, and a gate electrode layer 600. The channel layer 400 is formed on one side of the substrate 100 and includes a first channel 411 and a second channel 421 stacked together. The gate electrode layer 600 includes a first gate 611 and a second gate 621. The first gate 611 is formed in a first inner hole 412 of the first channel 411 and is directly or indirectly connected to the second channel 421 through a first conductor portion 711. The second gate 621 is at least partially formed in a second inner hole 422 of the second channel 421. The gate dielectric layer 500 is formed between the gate electrode layer 600 and the channel layer 400. The source / drain electrodes include a first drain 311, a first source 321, and a second source 331. Both the first drain 311 and the first source 321 are connected to the first channel 411, and the second source 331 is connected to the second channel 421. The read transistor 20 and write transistor 10, which are formed by stacked vertical channels of source and drain electrodes, channel layer 400, gate dielectric layer 500 and gate electrode layer 600, reduce the area occupied by the memory cell and increase the storage density per unit area compared with memory cells formed by connecting two horizontal channels on the same plane.

[0119] This application also provides a method for manufacturing a memory, used to manufacture the memory disclosed above. See also Figures 5 to 15 As shown, the method for manufacturing the memory includes:

[0120] S100: An isolation layer 200 and a lead layer 300 are formed on a substrate 100;

[0121] like Figure 6 In the embodiment shown, the lead layer 300 includes a first lead layer 310, a second lead layer 320, and a third lead layer 330 formed sequentially and spaced apart. The first lead layer 310, the second lead layer 320, and the third lead layer 330 are all located in the isolation layer 200. The first lead layer 310 includes a first drain 311 and a read word line RWL integrally connected. The second lead layer 320 includes a first source 321 and a read bit line RBL integrally connected. The third lead layer 330 includes a second source 331 and a write bit line WBL integrally connected.

[0122] It is understood that the first lead layer 310 and the second lead layer 320 do not extend in the same direction, that is, their orthographic projections on the substrate 100 intersect, while the third lead layer 330 extends in the same direction as either the first lead layer 310 or the second lead layer 320. Preferably, the orthographic projections of the first lead layer 310 and the second lead layer 320 on the substrate 100 are perpendicular to each other, and the third lead layer 330 extends in the same direction as either the first lead layer 310 or the second lead layer 320. The orthographic projection of the third lead layer 330 on the substrate 100 overlaps with the perpendicular intersection point of the orthographic projections of the first lead layer 310 and the second lead layer 320 on the substrate 100.

[0123] S200: A receiving hole 210 is formed on the isolation layer 200, passing through the second source 331 and the first source 321 and extending to the first drain 311;

[0124] like Figure 7 In the illustrated embodiment, the orthographic projection of the accommodating via 210 onto the substrate 100 overlaps with the vertical intersection of the orthographic projections of the first lead layer 310 and the second lead layer 320 onto the substrate 100. The accommodating via 210 preferably has vertical sidewalls, but it is understood that the sidewalls of the accommodating via 210 may have an angle that does not affect the formation of an electrical connection with the source / drain electrodes.

[0125] S300: A first channel 411, a first gate dielectric portion 511, and a first gate 611 are sequentially formed in the accommodating hole 210 on the side away from the substrate 100;

[0126] Both the first drain 311 and the first source 321 are connected to the first channel 411. The height of the bottom surface of the first gate 611 is at least lower than the lower surface of the second lead layer 320, and preferably lower than the upper surface of the first lead layer 310.

[0127] S400: An insulating dielectric layer 800 is formed at least on the side of the first channel 411 away from the substrate 100;

[0128] See Figure 12 As shown, the insulating dielectric layer 800 at least separates the first channel 411 and the second channel 421.

[0129] S500: A second channel 421, a second gate dielectric portion 521, a second gate 621, and a write word line WWL are formed on the side of the first channel 411 away from the substrate 100;

[0130] like Figures 13-15In the shown embodiment, the second channel 421, the second gate dielectric 521 and the second gate 621 are all at least partially located in the accommodation hole 210, the second channel 421 is arranged apart from the first channel 411, the first gate 611 is directly or indirectly connected with the second channel 421, the second source 331 is connected with the second channel 421, and the write word line WWL is connected with the second gate 621.

[0131] The isolation layer 200 can include multiple isolation material layers, and when the isolation layer 200, the first lead layer 310, the second lead layer 320 and the third lead layer 330 are formed, the first isolation material layer, the first lead layer 310, the second isolation material layer, the second lead layer 320, the third isolation material layer, the third lead layer 330 and the fourth isolation material layer can be sequentially formed on the substrate 100, so as to isolate the first lead layer 310, the second lead layer 320 and the third lead layer 330 from each other in the isolation layer 200.

[0132] The memory includes multiple memory cells, and each memory cell includes a read tube 20 and a write tube 10. The read tube 20 includes the first gate 611, the first channel 411, the first drain 311 and the first source 321, and the write tube 10 includes the second drain, the second source 331, the second channel 421 and the second gate 621. The multiple memory cells are connected through the read word line RWL, the read bit line RBL, the write bit line WBL and the write word line WWL.

[0133] The first channel 411 is entirely located in the accommodation hole 210, and the second channel 421 is at least partially located in the accommodation hole 210. The process flow of manufacturing the memory can be simplified, and the manufacturing cost of the memory can be reduced in the process of forming the vertically stacked write tube 10 and read tube 20. Meanwhile, the first channel 411 is entirely located in the accommodation hole 210, and the second channel 421 is at least partially located in the accommodation hole 210. The first channel 411 and the second channel 421 are stacked, so as to reduce the occupied area of the memory cell and improve the storage density.

[0134] Referring to Figures 8 to 15 The manufacturing method of the memory includes:

[0135] The first channel layer 410, the first gate dielectric layer 510, the first gate electrode layer 610 and the first conductor layer 710 are sequentially formed on the side of the isolation layer 200 away from the substrate 100, and the first channel layer 410, the first gate dielectric layer 510, the first gate electrode layer 610 and the first conductor layer 710 are all at least partially located in the accommodation hole 210.

[0136] A portion of the first conductor layer 710 is removed from the top to form a first conductor portion 711 in the accommodation hole 210, the first conductor portion 711 is located between the upper surface of the second lead layer 320 and the lower surface of the third lead layer 330 away from the surface of the substrate 100; then a portion of the first channel layer 410, the first gate dielectric layer 510 and the first gate electrode layer 610 are removed to form a first channel 411, a first gate dielectric portion 511 and a first gate 611 in the accommodation hole 210, the height of the upper surface of the first conductor portion 711 relative to the substrate 100 is greater than the height of the upper surface of the first channel 411, the first gate 611 and the first gate dielectric portion 511 relative to the substrate 100;

[0137] An insulating dielectric layer 800 is formed around the first conductor portion 711 away from the end surface of the substrate 100, the height of the upper surface of the insulating dielectric layer 800 relative to the substrate 100 is less than or equal to the height of the upper surface of the first conductor portion 711 relative to the substrate 100;

[0138] The second channel layer 420, the second gate dielectric layer 520, the second gate electrode layer 620, the second conductor layer 720 and the fourth lead layer 340 are sequentially formed away from the substrate 100 side of the read tube 20 and the insulating dielectric layer 800, the second channel layer 420, the second gate dielectric layer 520, the second gate electrode layer 620 and the second conductor layer 720 are at least partially located in the accommodation hole 210, the second channel layer 420, the second gate dielectric layer 520, the second gate electrode layer 620, the second conductor layer 720 and the fourth lead layer 340 are patterned to form a second channel 421, a second gate dielectric portion 521, a second gate 621, a second conductor portion 721 and a write word line WWL. The second gate 621 and the write word line WWL are connected through the second conductor portion 721.

[0139] When the second channel layer 420, the second gate dielectric layer 520, the second gate electrode layer 620, the second conductor layer 720 and the fourth lead layer 340 are patterned, a photoresist 900 is coated on the fourth lead layer 340, then the second channel layer 420, the second gate dielectric layer 520, the second gate electrode layer 620, the second conductor layer 720 and the fourth lead layer 340 are etched to the isolation layer 200 above the third lead layer 330, then the residual photoresist 900 is removed and a layer of isolation material is coated to form Figure 1 and Figure 2 a memory cell structure.

[0140] It can be understood that the etching can stop on the upper surface of the isolation layer 200; or over-etch to deep into the isolation layer 200 to ensure that the second channel layer 420 is etched completely during the patterning process, reducing the risk of short circuit.

[0141] The first gate 611 and the second channel 421 are spaced apart, the first conductor part 711 is connected with the second channel 421, the first conductor part 711 can store or discharge charges when the write tube 10 is opened, and the charges stored in the first conductor part 711 can affect the read current of the read tube 20.

[0142] It should be noted that the first gate 611 and the second channel 421 are spaced apart, the first gate 611 and the second channel 421 can be indirectly connected through the first conductor part 711, but are not limited thereto, the first gate 611 can also extend to pass through the insulating medium layer 800 and be directly connected with the second channel 421, which can be determined as appropriate.

[0143] Referring to Figures 8 to 15 As shown, etching is performed to remove part of the first channel layer 410, the first gate medium layer 510 and the first gate electrode layer 610, so that the height of the upper surface of the first conductor part 711 is greater than the height of the upper surface of the first channel 411, the first gate 611 and the first gate medium part 511. The etching, for example, can be isotropic etching, which can be dry or wet etching. The gate electrode layer 600 and the conductor layer 700 are formed by different materials, so that when the first gate electrode layer 610 is etched, the first conductor part 711 is not etched.

[0144] It can be understood that in the step of removing part of the first channel layer 410, the first gate medium layer 510 and the first gate electrode layer 610, each layer can be etched simultaneously or separately, which is not limited in the present application.

[0145] Etching is performed to remove the first channel layer 410, the first gate medium layer 510 and the first gate electrode layer 610, so that the height of the upper surface of the first conductor part 711 relative to the substrate 100 is greater than the height of the upper surface of the upper end of the first channel 411, the first gate 611 and the first gate medium part 511. The filling space of the insulating medium layer 800 is generated to avoid the short circuit of the first channel 411, the first gate 611 and the write tube 10, and facilitate the connection of the first conductor part 711 and the second channel 421. The etching, for example, can be isotropic etching, which can be dry or wet etching.

[0146] Referring to Figures 8 to 15 As shown, when the insulating medium layer 800 is formed, at least an insulating medium base layer covering the first conductor part 711, the first channel 411 and the first gate medium part 511 is formed in the accommodation hole 210, part of the insulating medium base layer is located outside the accommodation hole 210, and then isotropic dry or wet etching is used to remove part of the insulating medium base layer to form the insulating medium layer 800. The insulating medium layer 800 and the isolation layer 200 can be made of different materials to produce etching selectivity, so that the hole wall of the accommodation hole 210 is not etched when the insulating medium layer 800 is formed.

[0147] The insulating medium base layer is formed to fill the groove, cover the first conductor part 711, the first channel 411 and the first gate medium part 511, and then the insulating medium layer 800 is formed by isotropic etching the insulating medium base layer, so that the height and shape of the insulating medium layer 800 are more easily controlled.

[0148] Referring to Figures 8 to 15 As shown in the figure, when the accommodation hole 210 is formed through the first source electrode 321 and the second source electrode 331 and extends to the first drain electrode 311 on the isolation layer 200, the etching depth is greater than the depth at which the upper surface of the first drain electrode 311 is located and less than the depth at which the lower surface of the first drain electrode 311 is located. That is, the accommodation hole 210 extends into the first drain electrode 311 but does not penetrate through the first drain electrode 311.

[0149] The accommodation hole 210 formed on the isolation layer 200 extends into the first drain electrode 311, so that the first channel 411 is partially embedded in the first drain electrode 311 close to one end of the substrate 100, thereby improving the connection performance of the first drain electrode 311 and the first channel 411 and improving the performance of the read tube 20.

[0150] Referring to Figures 8 to 15 As shown in the figure, the orthographic projection of the accommodation hole 210 on the substrate 100 is located within the orthographic projection of the first drain electrode 311, the first source electrode 321 and the second source electrode 331 on the substrate 100. Specifically, the first channel 411 can be centrally arranged relative to the first drain electrode 311 and the first source electrode 321, and the second channel 421 can be centrally arranged relative to the second source electrode 331.

[0151] The first channel 411 is centrally arranged relative to the first drain electrode 311 and the first source electrode 321, and the second channel 421 is centrally arranged relative to the second source electrode 331, which can improve the performance of the write tube 10 and the read tube 20 and improve the performance of the storage unit.

[0152] The terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second", etc. can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise explicitly specified and limited.

[0153] In the present application, unless otherwise explicitly specified and limited, the terms "assembly", "connection" and the like should be understood in a broad sense, for example, it can be fixed connection, or detachable connection, or integrated; it can be mechanical connection, or electrical connection; it can be direct connection, or indirect connection through an intermediate medium; it can be the internal communication of two elements or the interaction relationship between two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0154] In the description of the specification, the description of the terms "some embodiments", "exemplarily" and the like means that the specific features, structures, materials or characteristics described in connection with the embodiments or examples are contained in at least one embodiment or example of the present application. In the specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any appropriate manner in any one or more embodiments or examples. In addition, the person skilled in the art can combine and combine the different embodiments or examples described in the specification and the features of the different embodiments or examples without contradiction.

[0155] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limiting the present application, and the person skilled in the art can make changes, modifications, replacements and variations to the above embodiments within the scope of the present application. However, any changes or modifications made in accordance with the claims and specification of the present application shall be within the scope of the present application.

Claims

1. A memory cell, comprising: The storage unit is arranged in an isolation layer on a substrate side, the isolation layer comprises a receiving hole, and the storage unit comprises: a channel layer comprising a first channel and a second channel arranged in a stack and forming a separation, the first channel is located in the receiving hole, and the second channel is at least partially located in the receiving hole, the first channel has a first inner hole away from the substrate side, and the second channel has a second inner hole away from the substrate side; an insulating medium layer formed at least between the first channel and the second channel; a gate electrode layer comprising a first gate and a second gate, the first gate is formed in the first inner hole and directly or indirectly connected with the second channel, and the second gate is at least partially formed in the second inner hole; a gate medium layer formed between the gate electrode layer and the channel layer; the storage unit further comprises a conductor layer, the conductor layer comprises a first conductor part, the first conductor part is at least partially located between the first gate and the second channel, the first gate and the second channel are indirectly connected through the first conductor part, and the insulating medium layer is arranged around the first conductor part.

2. The memory cell of claim 1, wherein, The first conductor part at least partially extends into the first gate in the first inner hole.

3. The memory cell of claim 1, wherein, The height of the upper surface of the first conductor part relative to the substrate is greater than or equal to the height of the upper surface of the insulating medium layer relative to the substrate.

4. The memory cell of claim 1, wherein, The conductor layer further comprises a second conductor part, the second conductor part is at least partially arranged in the second inner hole, and the second gate is located between the second conductor part and the gate medium layer.

5. The memory cell of claim 1, wherein, The storage unit further comprises a lead layer, the lead layer comprises a first lead layer, a second lead layer and a third lead layer arranged in a separation, the first lead layer comprises a first drain, the second lead layer comprises a first source, and the third lead layer comprises a second source, the first drain and the first source are both located outside the receiving hole and connected with the first channel, the second source is located outside the receiving hole and connected with the second channel, and the receiving hole penetrates the second source and the first source to connect with the first drain.

6. The memory cell of claim 5, wherein, The first channel is partially embedded in the first drain near one end of the substrate.

7. A memory, comprising: Comprise: a plurality of storage units as claimed in any one of claims 1-6; a write word line connected with the second gates of a plurality of the storage units; a write bit line connected with the second sources of a plurality of the storage units; a read word line connected with the first drains of a plurality of the storage units; a read bit line connected with the first sources of a plurality of the storage units.

8. A method of fabricating a memory, comprising: Comprise: forming an isolation layer and a lead layer on a substrate, the lead layer comprises a first lead layer, a second lead layer and a third lead layer formed in a sequence and arranged in a separation, the first lead layer, the second lead layer and the third lead layer are all located in the isolation layer, the first lead layer comprises a first drain and a read word line connected integrally, the second lead layer comprises a first source and a read bit line connected integrally, and the third lead layer comprises a second source and a write bit line connected integrally; forming a receiving hole through the second source and the first source and extending to the first drain on the isolation layer; forming a first channel, a first gate dielectric part, a first gate and a first conductor part in the receiving hole, the first drain and the first source are both connected with the first channel; forming an insulating medium layer at least on the side of the first channel away from the substrate; forming a second channel, a second gate dielectric part, a second gate and a write word line on the side of the insulating medium layer away from the substrate, the second channel, the second gate dielectric part and the second gate are all at least partially located in the receiving hole, the first gate is directly or indirectly connected with the second channel, the second source is connected with the second channel, the write word line is connected with the second gate; wherein the method for forming the first channel, the first gate dielectric part, the first gate, the first conductor part and the insulating medium layer comprises: forming a first channel layer, a first gate dielectric layer, a first gate electrode layer and a first conductor layer in sequence on the side of the isolation layer away from the substrate, the first channel layer, the first gate dielectric layer, the first gate electrode layer and the first conductor layer are all at least partially located in the receiving hole; removing part of the first conductor layer to form the first conductor part in the receiving hole, and then removing part of the first channel layer, the first gate dielectric layer and the first gate electrode layer to form the first channel, the first gate dielectric part and the first gate in the receiving hole, the height of the upper surface of the first conductor part relative to the substrate is greater than the height of the upper surface of the first channel, the first gate dielectric part and the first gate relative to the substrate; forming the insulating medium layer surrounding the first conductor part on the side of the first channel, the first gate dielectric part and the first gate away from the substrate, the height of the upper surface of the insulating medium layer relative to the substrate is less than or equal to the height of the upper surface of the first conductor part relative to the substrate.

9. The method of fabricating memory according to claim 8, wherein, the method for manufacturing the memory comprises: forming a second channel layer, a second gate dielectric layer, a second gate electrode layer, a second conductor layer and a fourth lead layer in sequence on the side of the isolation layer away from the substrate, the second channel layer, the second gate dielectric layer, the second gate electrode layer and the second conductor layer are all at least partially located in the receiving hole, and the second channel layer, the second gate dielectric layer, the second gate electrode layer, the second conductor layer and the fourth lead layer are patterned to form the second channel, the second gate dielectric part, the second gate, a second conductor part and the write word line.

10. The method of fabricating memory according to claim 9, wherein, part of the first channel layer, the first gate dielectric layer and the first gate electrode layer is removed by isotropic etching, so that the height of the upper surface of the first conductor part is greater than the height of the upper surface of the first channel, the first gate dielectric part and the first gate.

11. The method of fabricating memory of claim 9, wherein, when the insulating medium layer is formed, an insulating medium base layer covering the first conductor part, the first channel and the first gate dielectric part is formed in the receiving hole; part of the insulating medium base layer is removed by isotropic etching to form the insulating medium layer.

12. The method of claim 8, wherein The etching depth is greater than the depth at which the upper surface of the first drain electrode is located when the accommodation hole is formed through the second source electrode and the first source electrode and extends to the first drain electrode.

13. The method of claim 12, wherein The orthogonal projection of the accommodation hole on the substrate is located within the orthogonal projections of the first drain electrode, the first source electrode and the second source electrode on the substrate.

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