Opportunity store of non-write promoted data in write promoter cache memory

Abstract

The present disclosure relates to opportunistic storage of non-write promoted data in write promoter cache memory. In some implementations, a memory device can receive a write command including data to be written to the memory device. The memory device can receive an indication to deactivate a single level cell data cache for the data. The memory device can determine whether the data is associated with a first data type or a second data type. Based on determining whether the data is associated with the first data type or the second data type and determining whether a single level cell cache memory has available memory not reserved for the single level cell data cache, the memory device can selectively write the data to the single level cell cache memory or a multi-level cell main memory.

Description

[0001] Cross Reference to Related Applications

[0002] This patent application claims priority to U.S. Provisional Patent Application No. 63 / 387,536, filed December 15, 2022, and titled “OPPORTUNISTIC STORAGE OF NON-WRITE-BOOSTED DATA IN WRITE BOOSTER CACHE MEMORY,” and U.S. Non-Provisional Patent Application No. 18 / 505,661, filed November 9, 2023, and titled “OPPORTUNISTIC STORAGE OF NON-WRITE-BOOSTED DATA IN WRITE BOOSTER CACHE MEMORY.” The disclosures of the prior applications are considered part of this patent application and are hereby incorporated by reference into this patent application. TECHNICAL FIELD

[0003] The present disclosure generally relates to memory devices, memory device operations, and, for example, to opportunistic storage of non-write-boosted data in write booster cache memory. BACKGROUND

[0004] Memory devices are widely used to store information in various electronic devices. A memory device includes memory cells. A memory cell is an electronic circuit that can be programmed to a data state of two or more data states. For example, a memory cell can be programmed to a data state representing a single binary value, typically represented by a binary “1” or a binary “0.” As another example, a memory cell can be programmed to a data state representing a fractional value (e.g., 0.5, 1.5, or the like). To store information, an electronic device can write or program a set of memory cells. To access stored information, an electronic device can read or sense the stored state from the set of memory cells.

[0005] There are a variety of types of memory devices, including random access memory (RAM), read only memory (ROM), dynamic RAM (DRAM), static RAM (SRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), holographic RAM (HRAM), flash memory (e.g., NAND and NOR flash memory), and others. Memory devices can be volatile or non-volatile. Non-volatile memory (e.g., flash memory) can store data for long periods of time even in the absence of an external power source. Volatile memory (e.g., DRAM) can lose stored data over time unless it is refreshed by a power source. SUMMARY

[0006] In one aspect, the disclosure relates to a memory device comprising: a non-volatile cache memory; and one or more controllers configured to: receive, from a host device, an indication of a threshold amount of the non-volatile cache memory reserved for first data for which write promotion is activated; receive, from the host device, a write command including second data for which write promotion is deactivated; determine that the second data is hot data; based on determining that the second data is hot data, based on the indication of the threshold amount, and despite write promotion being deactivated for the second data, identify a block of the non-volatile cache memory using a write promotion cursor; and write the second data to the block of the non-volatile cache memory.

[0007] In another aspect, the disclosure relates to a method comprising: receiving, by a memory device, a write command including data to be written to the memory device; receiving, by the memory device, an indication to deactivate a single-level cell data cache for the data; determining, by the memory device, whether the data is associated with a first data type or a second data type; and selectively writing, by the memory device, the data to a single-level cell cache memory or a multi-level cell main memory based on: determining whether the data is associated with the first data type or the second data type, and determining whether the single-level cell cache memory has available memory that is not reserved for the single-level cell data cache.

[0008] In yet another aspect, the disclosure relates to an apparatus comprising: a non-volatile memory array; and a controller configured to execute instructions that cause the apparatus to: process a received command to write data to the non-volatile memory array, wherein the command is received without an indication to write the data in a single level cell (SLC) cache memory of the non-volatile memory array; determine whether the data is associated with a first data type; determine whether the SLC cache memory has sufficient memory unreserved for SLC data caching; and based on determining that the data is associated with the first data type and the SLC cache memory has sufficient memory unreserved for SLC data caching, write the data to the SLC cache memory. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 FIG. 1 is a diagram illustrating an example system that can store non-write promoted data opportunities in a write booster cache memory.

[0010] Figure 2 FIG. 2 is a diagram of example components included in a memory device.

[0011] Figure 3 FIG. 3 is a diagram illustrating an example memory architecture that can be used by a memory device.

[0012] Figure 4 FIG. 4 is a diagram of an example of reserving a portion of a write booster cache memory for write promoted data.

[0013] Figure 5 FIG. 5 is a diagram of an example of opportunity storage of non-write promoted data in a write booster cache memory.

[0014] Figure 6 FIG. 6 is a diagram of an example of performing a garbage collection operation on a write booster cache memory.

[0015] Figures 7 to 9 FIG. 7 is a flow diagram of an example method associated with opportunity storage of non-write promoted data in a write booster cache memory. DETAILED DESCRIPTION

[0016] Some memory devices can use a technique known as "write boosting" (sometimes referred to herein as "single-level cell data cache" or "write boost data cache") to improve the speed of data writes to the memory. Using write boosting, a memory device can write data to a single-level cell (SLC) non-volatile "write booster" cache memory instead of writing the data to a multi-level cell (e.g., dual-level cell, triple-level cell, quad-level cell, or higher) non-volatile main memory. Because data can be written to the SLC cache memory faster than data can be written to the multi-level cell (MLC) main memory, using write boosting improves write speed. A particular write boosting technique is defined by the Joint Electron Device Engineering Council (JEDEC) Universal Flash Storage (UFS) standard JESD220.

[0017] To use write boosting, a host device explicitly instructs a memory device to activate write boosting, for example, by transmitting a message (e.g., in a write command or before transmitting a write command) to the memory device indicating that the memory device is to activate write boosting for one or more write commands. For example, a host device can activate write boosting for a large file that is downloaded by the host device and stored in the memory device. If the host device does not instruct the memory device to activate write boosting, the memory device does not use write boosting.

[0018] However, requiring explicit activation of a memory device to write data to a write booster cache memory (e.g., an SLC cache memory used for write boosting) can result in inefficient utilization of memory resources and poor flexibility in memory block management. For example, if a host device never activates write boosting or occasionally activates write boosting, the write booster cache memory can be used rarely or not at all. On the other hand, if a memory device is permitted to unconditionally write data to the write booster cache memory, the write booster cache memory can not be available for write boost requests from the host device and / or the write booster cache memory can wear out prematurely.

[0019] Some implementations described herein enable a memory device to opportunistically (e.g., conditionally) write non-write boost data to a write booster cache memory, which improves write speed and results in better memory resource utilization. In some implementations, a memory device can reserve a portion of the write booster cache memory for storing data for which write boosting is activated, which increases the likelihood that some write booster cache memory is available when a host device requests write boosting.

[0020] Furthermore, some embodiments described herein limit the types of data that can be stored in the write booster cache memory. As an example, a memory device may store hot data in the write booster cache memory, which has a relatively shorter expected lifetime (e.g., compared to cold data) and / or is accessed, erased, and / or overwritten more frequently (e.g., compared to cold data). This can extend the lifetime of the memory device because the hot data would otherwise be written to MLC main memory and soon marked invalid (e.g., due to its relatively short lifetime as hot data), thus requiring subsequent erases due to shorter program / erase (P / E) cycles and causing faster wear on the MLC main memory. Generally, MLC memory has a shorter lifetime than SLC memory (e.g., becomes unreliable within fewer P / E cycles). Therefore, writing hot data to SLC memory instead of MLC memory has a smaller adverse impact on the lifetime of the memory device compared to writing hot data to MLC memory.

[0021] Therefore, some of the embodiments described herein extend the lifespan of memory devices (e.g., by reducing the write amplification of hot data in MLC memory), improve the resource utilization of memory devices (e.g., by allowing flexible use of SLC memory that would otherwise be used entirely for write boosting), and / or improve the performance of memory devices (e.g., by ensuring that a portion of the write booster memory cache is available for write boosting operations).

[0022] Figure 1 An example system 100 is described that is capable of storing non-write-boosted data opportunities in a write booster cache memory. System 100 may include one or more means, devices, and / or components for performing the operations described herein. For example, system 100 may include a host device 110 and a memory device 120. Memory device 120 may include a controller 130 and memory 140. Host device 110 may communicate with memory device 120 (e.g., the controller 130 of memory device 120) via host interface 150. Controller 130 and memory 140 may communicate via memory interface 160.

[0023] System 100 can be any electronic device configured to store data in memory. For example, system 100 can be a computer, mobile phone, wired or wireless communication device, network device, server, device in a data center, device in a cloud computing environment, vehicle (e.g., car or airplane), and / or Internet of Things (IoT) device. Host device 110 may include one or more processors configured to execute instructions and store data in memory 140. For example, host device 110 may include a central processing unit (CPU), graphics processing unit (GPU), field-programmable gate array (FPGA), application-specific integrated circuit (ASIC), and / or another type of processing component.

[0024] Memory device 120 may be any electronic device or apparatus configured to store data in memory. In some embodiments, memory device 120 may be an electronic device configured to persistently store data in non-volatile memory. For example, memory device 120 may be a hard disk drive, solid-state drive (SSD), flash memory device (e.g., NAND flash memory device or NOR flash memory device), universal serial bus (USB) thumb drive, memory card (e.g., Secure Digital (SD) card), secondary storage device, non-volatile memory fast (NVMe) device, and / or embedded multimedia card (eMMC) device. In this case, memory 140 may include non-volatile memory configured to retain stored data after power loss of memory device 120. For example, memory 140 may include NAND memory or NOR memory. In some implementations, memory 140 may include volatile memory that requires power to maintain stored data and loses stored data after power is turned off from memory device 120, such as one or more latches and / or random access memory (RAM), such as dynamic RAM (DRAM) and / or static RAM (SRAM). For example, the volatile memory may cache data read from non-volatile memory or to be written to non-volatile memory, and / or may cache instructions to be executed by controller 130.

[0025] Controller 130 may be any device configured to communicate with a host device (e.g., via host interface 150) and memory 140 (e.g., via memory interface 160). Alternatively, controller 130 may be configured to control the operation of memory device 120 and / or memory 140. For example, controller 130 may include control logic, a memory controller, a system controller, an ASIC, an FPGA, a processor, a microcontroller, and / or one or more processing components. In some embodiments, controller 130 may be a high-level controller that can communicate directly with host device 110 and instruct one or more low-level controllers to perform memory operations with respect to memory 140. In some embodiments, controller 130 may be a low-level controller that can receive instructions regarding memory operations from a high-level controller that directly interfaces with host device 110. As an example, the high-level controller may be an SSD controller, and the low-level controller may be a non-volatile memory controller (e.g., a NAND controller) or a volatile memory controller (e.g., a DRAM controller). In some implementations, a set of operations described herein as being performed by controller 130 may be performed by a single controller (e.g., the entire set of operations may be performed by a single high-level controller or a single low-level controller). Alternatively, a set of operations described herein as being performed by controller 130 may be performed by more than one controller (e.g., a first subset of the operations may be performed by a high-level controller and a second subset of the operations may be performed by a low-level controller).

[0026] The host interface 150 enables communication between the host device 110 and the storage device 120. The host interface 150 may include, for example, a Small Computer System Interface (SCSI), a Serial Attached SCSI (SAS), a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Fast (PCIe) interface, an NVMe interface, a USB interface, a Universal Flash Storage (UFS) interface, and / or an Embedded Multimedia Card (eMMC) interface.

[0027] Memory interface 160 enables communication between memory device 120 and memory 140. Memory interface 160 may include a non-volatile memory interface (e.g., for communicating with non-volatile memory), such as a NAND interface or a NOR interface. Alternatively, memory interface 160 may include a volatile memory interface (e.g., for communicating with volatile memory), such as a Double Data Rate (DDR) interface.

[0028] In some implementations, memory device 120 and / or controller 130 may be configured to receive from a host device an indication of a threshold amount of non-volatile cache memory reserved for activating write boosting of first data therefor; receive from the host device a write command containing second data for deactivating write boosting of second data; determine that the second data is hot data; based on the determination that the second data is hot data, and based on the indication of the threshold amount and although write boosting is deactivated for the second data, identify a block of the non-volatile cache memory using a write boosting cursor; and write the second data to the block of the non-volatile cache memory.

[0029] In some implementations, memory device 120 and / or controller 130 may be configured to receive a write command containing data to be written to the memory device; receive an indication to deactivate a single-level cell data cache for the data; determine whether the data is associated with a first data type or a second data type; and selectively write the data to a single-level cell cache memory or a multi-level cell main memory based on: determining whether the data is associated with the first data type or the second data type, and determining whether the single-level cell cache memory has available memory that is not reserved for the single-level cell data cache.

[0030] In some implementations, memory device 120 and / or controller 130 may be configured to receive a write command containing data to be written to the memory device; determine that write-elevation data cache is deactivated for the data; determine that the data is associated with a first data type; based on the determination that the data is associated with the first data type and although write-elevation data cache is deactivated for the data, determine that the data should be written to cache memory instead of main memory; and write the data to cache memory based on the determination that the data should be written to cache memory.

[0031] In some embodiments, memory device 120 and / or controller 130 may be configured to process a received command to write data to a non-volatile memory array, wherein the command is received without an indication that the data is to be written to a single-level cell (SLC) cache memory of the non-volatile memory array; determine whether the data is associated with a first data type; determine whether the SLC cache memory has sufficient memory not reserved for SLC data caching; and write the data to the SLC cache memory based on the determination that the data is associated with the first data type and that the SLC cache memory has sufficient memory not reserved for SLC data caching.

[0032] As indicated above, Figure 1 It is provided as an instance. Other instances may differ from those provided. Figure 1 The described instance.

[0033] Figure 2 This is a diagram of an instance component contained in memory device 120. (As described above...) Figure 1 As described, memory device 120 may include controller 130 and memory 140. For example... Figure 2 As shown, memory 140 may include one or more non-volatile memory arrays 205, such as one or more NAND memory arrays and / or one or more NOR memory arrays. Alternatively, memory 140 may include one or more volatile memory arrays 210, such as one or more SRAM arrays and / or one or more DRAM arrays. Controller 130 may use non-volatile memory interface 215 to transmit signals to and receive signals from non-volatile memory array 205. Controller 130 may use volatile memory interface 220 to transmit signals to and receive signals from volatile memory array 210. In some embodiments, a single non-volatile memory array 205 is included together with a local controller in a single corresponding die. Multiple dies, each containing a non-volatile memory array 205 and a local controller, may be stacked and / or incorporated into an integrated circuit together with an external (or global) controller that communicates with the corresponding local controller of each die.

[0034] Controller 130 may control the operation of memory 140, for example, by executing one or more instructions. For instance, memory device 120 may store one or more instructions as firmware in memory 140, and controller 130 may execute those instructions. Alternatively, controller 130 may receive one or more instructions from host device 110 via host interface 150, and may execute those instructions. In some embodiments, non-transitory computer-readable media (e.g., volatile and / or non-volatile memory) may store a set of instructions (e.g., one or more instructions or codes) for execution by controller 130. Controller 130 may execute the set of instructions to perform one or more operations or methods described herein. In some embodiments, execution of the set of instructions by controller 130 causes controller 130 and / or memory device 120 to perform one or more operations or methods described herein. In some embodiments, hard-wired circuitry replaces or combines one or more instructions to perform one or more operations or methods described herein. Alternatively, the controller 130 and / or one or more components of the memory device 120 may be configured to perform one or more operations or methods described herein. Instructions are sometimes referred to as “commands”.

[0035] For example, controller 130 may transmit signals to and / or receive signals from memory 140 based on one or more instructions, such as to transfer (e.g., write or program) data to all or part of memory 140 (e.g., one or more memory cells, pages, sub-blocks, blocks, or planes of memory 140), transfer (e.g., read) data from it, and / or erase it. Alternatively or additionally, controller 130 may be configured to control access to memory 140 and / or provide a translation layer (e.g., for mapping logical addresses to physical addresses of the memory array) between host device 110 and memory 140. In some embodiments, controller 130 may translate host interface commands (e.g., commands received from host device 110) into memory interface commands (e.g., commands for performing operations on the memory array).

[0036] like Figure 2 As shown, memory 140 (e.g., non-volatile memory array 205) may include cache memory 225 (sometimes referred to as non-volatile cache memory) and main memory 230 (sometimes referred to as non-volatile main memory). Both cache memory 225 and main memory 230 may be non-volatile memories. Cache memory 225 may store fewer bits per memory cell than main memory 230, and main memory 230 may store more bits per memory cell than cache memory 225. For example, cache memory 225 may include SLC memory cells that store one bit per cell, while main memory 230 may include MLC memory cells that store more than one bit per cell, such as two-level cell (DLC) memory cells that store two bits per cell, three-level cell (TLC) memory cells that store three bits per cell, four-level cell (QLC) memory cells that store four bits per cell, and / or five-level cell (PLC) memory cells that store five bits per cell. Therefore, cache memory 225 may be referred to as SLC cache memory and main memory 230 may be referred to as MLC main memory. In some embodiments, cache memory 225 (or a portion of cache memory 225) is used for write boosting. For example, cache memory 225 (or a portion of cache memory 225) may be configured to store data for which write boosting is active.

[0037] like Figure 2As shown, controller 130 may include memory management component 235, memory reservation component 240, memory selection component 245, and / or command execution component 250. In some embodiments, one or more of these components are implemented as one or more instructions (e.g., firmware) executed by controller 130. Alternatively, one or more of these components may be implemented as an application-specific integrated circuit (ASIC) different from controller 130.

[0038] Memory management component 235 can be configured to manage the performance of memory device 120. For example, memory management component 235 can perform wear leveling, bad block management, block retirement, read interference management, and / or other memory management operations. In some embodiments, memory device 120 may store one or more memory management tables (e.g., in memory 140). Memory management tables may store information that can be used or updated by memory management component 235, such as information about memory block age, memory block erase counts, and / or error information associated with memory partitions (e.g., memory cells, memory rows, memory blocks, or the like).

[0039] The memory reservation component 240 can be configured to reserve a portion of cache memory 225 for its active write-boosted data (sometimes referred to as "write-boosted data"). For example, the memory reservation component 240 can receive an indication from the host device 110 of the amount of cache memory 225 reserved for write-boosted data, and can reserve that amount of cache memory 225 for write-boosted data.

[0040] Memory selection component 245 may determine and / or select a portion of memory 140 to be written thereto. In some embodiments, memory selection component 245 may determine whether to write data to cache memory 225 or main memory 230 based on the data type (e.g., hot data, cold data, or small fragments of data). Alternatively, memory selection component 245 may determine whether to write data to cache memory 225 or main memory 230 based on whether cache memory 225 has available memory not reserved for write-boosted data (e.g., whether writing data to cache memory 225 reduces the available memory of cache memory 225 to below the amount reserved for write-boosted data in cache memory 225). Alternatively, memory selection component 245 may determine whether to write data to cache memory 225 or main memory 230 based on whether write boosting is activated for the data. In some implementations, the memory selection component 245 may still determine to write data to the cache memory 225 even if write boosting is deactivated for data (e.g., based on data type and / or available memory of cache memory 225).

[0041] Command execution component 250 may be configured to execute one or more memory commands, such as read commands, write commands (sometimes referred to as programming commands), or erase commands. For example, command execution component 250 may receive and / or execute a write command to write data to memory 140. In some embodiments, command execution component 250 may receive an indication from memory selection component 245 whether to write data to cache memory 225 or main memory 230, and command execution component 250 may write data to cache memory 225 or main memory 230 based on the indication. Alternatively or additionally, command execution component 250 may be configured to perform obsolete item collection operations, for example, by copying data from (e.g., cache memory 225) an old block to (e.g., cache memory 225 and / or main memory 230) one or more new blocks.

[0042] Figure 2 One or more devices or components shown herein can be configured to perform the operations described elsewhere herein, such as in combination with Figures 3 to 9 The one or more operations and / or methods described. For example, controller 130, memory management component 235, memory reservation component 240, memory selection component 245 and / or command execution component 250 may be configured to perform one or more operations and / or methods on memory device 120.

[0043] Figure 2 The number and arrangement of components shown are provided as examples. In practice, there may be other... Figure 2 Components other than those shown in the text, compared to Figure 2 The components shown are fewer, and Figure 2 The components shown are different from or related to the components. Figure 2 The components shown are arranged differently. Furthermore, Figure 2 The two or more components shown can be implemented within a single component, or Figure 2 The single component shown can be implemented as multiple distributed components. Alternatively, Figure 2 The set of components shown (e.g., one or more components) can be described as being by Figure 2 The other set of components shown in the diagram performs one or more operations.

[0044] Figure 3This is a diagram illustrating an example memory architecture 300 that can be used by memory device 120. Memory device 120 can use memory architecture 300 to store data. As shown, memory architecture 300 may include a die 310, which may include multiple planes 320. Planes 320 may include multiple blocks 330. Blocks 330 may include multiple pages 340. Although... Figure 3 A specific number of planes 320 per die 310, a specific number of blocks 330 per plane 320, and a specific number of pages 340 per block 330 are shown, but these numbers may differ from those shown. In some implementations, the memory architecture 300 is a NAND memory architecture.

[0045] Die 310 is a structure made of a semiconductor material (e.g., silicon). In some embodiments, die 310 is the smallest memory unit capable of independently executing commands. Memory device 120 may include one or more dies 310. In some embodiments, memory device 120 may include multiple dies 310. In this case, multiple dies 310 may each perform corresponding memory operations (e.g., read operations, write operations, or erase operations) in parallel. For example, controller 130 of memory device 120 may be configured to perform memory operations concurrently on multiple dies 310 for parallel control. In some embodiments, die 310 may include a memory array (e.g., a non-volatile memory array) and a local controller. Multiple dies 310 may be stacked together with and / or otherwise incorporated into memory device 120 along with an external (or global) controller that communicates with a corresponding local controller of each die 310.

[0046] Each die 310 of the memory device 120 includes one or more planes 320. A plane 320 is sometimes referred to as a memory plane. In some embodiments, the same and concurrent operations (sometimes limited) can be performed on multiple planes 320. For example, multi-plane commands (e.g., multi-plane read commands or multi-plane write commands) can be performed concurrently on multiple planes 320, while single-plane commands (e.g., single-plane read commands or single-plane write commands) can be performed on a single plane 320. A logic cell of the memory device 120 may contain one or more planes 320 of the die 310. In some embodiments, a logic cell may contain all planes 320 of the die 310 and may be equivalent to the die 310. Alternatively, a logic cell may contain fewer than all planes 320 of the die 310. A logic cell may be identified by a logic cell number (LUN). Depending on the context, the term "LUN" may refer to a logic cell or an identifier (e.g., a number) of that logic cell.

[0047] Each plane 320 contains multiple blocks 330. Blocks 330 are sometimes referred to as memory blocks. Each block 330 contains multiple pages 340. Pages 340 are sometimes referred to as memory pages. A block 330 is the smallest erasable unit of memory. In other words, an individual page 340 of a block 330 cannot be erased without erasing every other page 340 of the block 330. A page 340 is the smallest unit of memory to which data can be written (i.e., the smallest unit of memory that can be programmed with data). The terms “programmable” memory and “write to” memory are used interchangeably. A page 340 may contain multiple memory cells that can be accessed via the same access line (sometimes referred to as a word line). A “page row” refers to a group of pages 340 located at the same location in multiple planes 320 across a group of planes 320 (e.g., a first page with page index 0 in a first plane, a second page with page index 0 in a second plane, a third page with page index 0 in a third plane, and so on). In some embodiments, a block 330 may be divided into multiple sub-blocks. A sub-block is a part of block 330 and may contain a subset of pages 340 of the block and / or a subset of memory units of block 330.

[0048] In some implementations, read and write operations are performed on a specific page 340, while an erase operation is performed on block 330 (e.g., all pages 340 in block 330). In some implementations, to prevent memory wear, all pages 340 of block 330 may be programmed to enable new programming operations on pages 340 of block 330 before block 330 is erased. After a page 340 is programmed with data (hereinafter referred to as "old data"), that data may be erased, but it cannot be overwritten with new data before it is erased. An erase operation will erase all pages 340 in block 330, and erasing the entire block 330 each time new data replaces old data will rapidly wear down the memory cells of block 330. Therefore, new data may be stored in new pages (e.g., blank pages) (as shown by component symbol 350), and old pages storing old data may be marked as invalid (as shown by component symbol 360) instead of performing an erase operation. The memory device 120 can then direct operations associated with the data to a new page (e.g., in an address table) and can track invalid pages to prevent programming operations from being performed on invalid pages before an erase operation.

[0049] When block 330 meets the erase condition, memory device 120 may choose to erase block 330, copy the valid data of block 330 (e.g., copy to a new block 330 or the same block 330 after erasure), and erase block 330. For example, the erase condition may be that all pages 340 of block 330 or a threshold number or percentage of pages 340 of block 330 are not available for further programming (e.g., invalid or valid data is stored). As another example, the erase condition may be that the number or percentage of free pages 340 of block 330 (e.g., pages 340 available for writing) is less than or equal to a threshold. The process of selecting a block 330 that meets the erase condition, copying the valid pages 340 of that block 330 to a new block 330 (or the same block 330 after erasure), and erasing block 330 is sometimes referred to as scrap collection and is used to free up memory space in memory device 120.

[0050] As indicated above, Figure 3 It is provided as an instance. Other instances may differ from those provided. Figure 3 The described instance.

[0051] Figure 4 This is a diagram of instance 400, which reserves a portion of the write booster cache memory for data that has been written to the booster. Combined with... Figure 4 The described operations may be performed by memory device 120 and / or one or more components of memory device 120 (e.g., controller 130 and / or one or more components of controller 130).

[0052] As illustrated by component symbol 410, memory device 120 (e.g., controller 130) may receive an indication of the amount of cache memory 225 (e.g., non-volatile cache memory) reserved for write boosting. In other words, memory device 120 may receive an indication of the amount of cache memory 225 reserved for data for which it is active write boosting (e.g., write-boosted data). As shown, in some embodiments, memory device 120 may receive the indication from host device 110. The amount of cache memory 225 reserved may be referred to as a threshold amount or a reserved amount. “Write boosting” is sometimes referred to herein as “SLC data cache” or “write-boosted data cache”.

[0053] In some embodiments, host device 110 may determine the amount of cache memory 225 reserved for write boosting based on one or more characteristics of host device 110, such as the device type of host device 110 (e.g., server, personal computer, smartphone, or automotive device), the expected frequency of write boosting requests by host device 110, and / or the expected rate at which host device 110 transmits write commands to memory device 120. In some embodiments, the threshold amount may be indicated as a threshold size of a portion of cache memory 225 to be reserved, such as the number of bytes (e.g., 100 megabytes, 1 gigabyte, 5 gigabytes, or the like). Alternatively, the threshold amount may be indicated as a threshold percentage of cache memory 225 to be reserved, such as 10%, 20%, 30%, or the like. In some embodiments, host device 110 may indicate the amount of cache memory 225 to be reserved by indicating the amount of cache memory 225 available for non-write boosting data, wherein the remaining amount of cache memory 225 is reserved for write boosting data.

[0054] Alternatively, host device 110 may indicate one or more characteristics of host device 110 (as described above) to memory device 120, and memory device 120 may determine the amount of cache memory 225 reserved for write boosting based on one or more characteristics. For example, memory device 120 may reserve a larger amount or percentage of cache memory 225 for host device 110 that is expected to request write boosting more frequently, and memory device 120 may reserve a smaller amount or percentage of cache memory 225 for host device 110 that is expected to request write boosting less frequently.

[0055] As illustrated by component symbol 420, memory device 120 (e.g., controller 130) can configure cache memory 225 based on an indication (e.g., by reserving a threshold amount of cache memory 225 for write boosting). For example, memory device 120 may store an indication in memory 140 of a reserved amount of cache memory 225 reserved for write boosting data. Alternatively, memory device 120 may store an indication in memory 140 of an unreserved amount of cache memory 225 not reserved for write boosting data. Figure 4 In Example 400, memory device 120 reserves 20 percent of cache memory 225 for write-boosted data (represented as "WB data"), and the remaining 80 percent of cache memory 225 is unreserved and available for non-write-boosted data.

[0056] As used herein, "written-promoted data" refers to first data for which write-promoting is activated, and "non-written-promoted data" refers to second data for which write-promoting is deactivated. Write-promoting can be activated or deactivated for data by host device 110. For example, host device 110 can activate write-promoting for first data by transmitting an activation instruction to memory device 120 (e.g., in a write command or before transmitting a write command), the activation instruction instructing memory device 120 to activate write-promoting for a write command containing the first data. In this case, any write command not indicated by the activation instruction is associated with second data for which write-promoting is deactivated. As another example, host device 110 can transmit an activation instruction to activate write-promoting, can transmit one or more write commands for which write-promoting is activated, and can then transmit a deactivation instruction to deactivate write-promoting (e.g., for any subsequent write command until another activation instruction is transmitted).

[0057] As illustrated by component symbol 430, in some embodiments, memory device 120 (e.g., controller 130) may reserve a portion of cache memory 225 for small fragment data. For example, and as shown, memory device 120 may reserve a portion of unreserved cache memory 225 for write-promoted data. Small fragment data is a data type having a size smaller than a threshold size (e.g., in bytes). For example, small fragment data may have a size smaller than the page row size of memory device 120 (e.g., a page row of main memory 230). A page row may contain groups of pages located at the same location and / or across multiple planes and / or dies of memory device 120, identified by the same index value (e.g., in main memory 230). For example, if the page size (e.g., the amount of data stored in individual pages) is 16 kilobytes and there are 16 pages in a page row, then the page row size is 256 kilobytes. In this case, the small data segment can be data to be written to the memory device 120, the data having a size of less than 256 kilobytes.

[0058] In some cases, memory device 120 may be configured to write data to main memory 230 such that each write operation fills an entire page line. If memory device 120 receives a write command indicating that a small piece of data (e.g., less than 256 kilobytes) is to be written to memory device 120, then memory device 120 may need to write non-host data (e.g., dummy data) to the remaining pages of the page line not occupied by the small piece of data. This wastes the memory resources of main memory 230. To improve memory utilization, memory device 120 may store the small piece of data in cache memory 225 until conditions are met (e.g., enough small pieces of data have accumulated in cache memory 225 to fill an entire page line or a threshold portion of the page line).

[0059] By reserving a first portion of cache memory 225 for write-boosted data, while allowing the use of a second portion of cache memory 225 for non-write-boosted data (particularly hot data, as described in more detail below), memory device 120 can extend its lifespan (e.g., by reducing the write amplification of hot data in main memory 230), improve resource utilization of memory device 120 (e.g., by allowing flexible use of cache memory 225 that would otherwise be entirely used for write boosting), and / or improve performance of memory device 120 (e.g., by ensuring that a portion of cache memory 225 is available for write-boosted operations). Furthermore, by reserving a portion of cache memory 225 for small data segments, memory device 120 can ensure that the small data segment operations described above can be performed, thereby improving memory resource utilization of main memory 230.

[0060] As indicated above, Figure 4 It is provided as an instance. Other instances may differ from those provided. Figure 4 The described instance.

[0061] Figure 5 This is a diagram of instance 500 of the opportunity storage of non-write-promoted data in the write-promoter cache memory. Combined with... Figure 5 The described operations may be performed by memory device 120 and / or one or more components of memory device 120 (e.g., controller 130 and / or one or more components of controller 130).

[0062] As illustrated by component symbol 510, memory device 120 (e.g., controller 130) may receive write commands for non-write-promoted data (e.g., data for which write promotion is deactivated). As shown, in some embodiments, memory device 120 may receive write commands from host device 110. In some embodiments, the write command includes data and an indication to deactivate write promotion for the data. In some embodiments, the write command does not include an indication to deactivate write promotion for the data. Instead, host device 110 may transmit a separate instruction indicating whether write promotion is activated for the write command. In some embodiments, write promotion may be deactivated by default, and memory device 120 may determine to deactivate write promotion for a write command unless memory device 120 receives an indication to activate write promotion for the write command.

[0063] As illustrated by component symbol 520, memory device 120 (e.g., controller 130) can determine the data type of non-write-promoted data. The data type can be a first data type (e.g., hot data) or a second data type (e.g., cold data). As used herein, "hot data" can include data with a relatively short expected lifetime (e.g., data that is not overwritten or marked as invalid, as described above). Figure 3 As described above, "cold data" can include data with a relatively long expected lifetime. For example, hot data can have a shorter expected lifetime than the expected lifetime associated with cold data. In other words, hot data is expected to become invalid and / or be overwritten in a shorter amount of time than cold data. In some implementations, hot data has an expected lifetime less than (or equal to) a threshold, and cold data has an expected lifetime greater than (or equal to) a threshold.

[0064] Alternatively, "hot data" may include data that is accessed, erased, and / or overwritten more frequently (e.g., compared to cold data) or relatively more frequently (e.g., compared to cold data), and "cold data" may include data that is accessed, erased, and / or overwritten less frequently (e.g., compared to hot data) or relatively less frequently (e.g., compared to hot data). For example, because hot data is erased more frequently than cold data, hot data may have a shorter lifespan (e.g., in a given memory location) because hot data stored in a given memory location may be erased or marked invalid, and new data replacing the hot data stored in a given memory location may be written to a new memory location. In some implementations, hot data is accessed, erased, and / or overwritten at a frequency greater than (or equal to) a threshold (e.g., the number of examples within a time period), and cold data is accessed, erased, and / or overwritten at a frequency less than (or equal to) a threshold.

[0065] In some implementations, memory device 120 may receive an indication of whether non-write-elevated data included in (or associated with) a write command is hot or cold data. For example, host device 110 may indicate, for example, in a write command or in a separate message, whether the non-write-elevated data included in a write command is hot or cold data. Alternatively or additionally, memory device 120 may determine whether the non-write-elevated data included in a write command is hot or cold data based on one or more characteristics of the non-write-elevated data (e.g., the size of the non-write-elevated data), one or more characteristics of the write command (e.g., other information included in the write command and / or the rate at which the write command is received from host device 110), and / or one or more characteristics associated with host device 110 (as described elsewhere herein).

[0066] In some implementations, memory device 120 may use historical information to determine whether non-write-promoted data in a write command is hot or cold data. For example, memory device 120 may store information about historical data written by memory device 120 based on historical write commands received from host device 110. Memory device 120 may store, for example, an indication of the actual lifetime of historical data previously written to memory device 120 (e.g., the time between writing data and overwriting data or marking data as invalid) along with one or more historical characteristics of the data, one or more historical characteristics of the write command that received the data, and / or one or more historical characteristics of host device 110. Memory device 120 may compare one or more characteristics associated with a new write command (containing non-write-promoted data) with one or more historical characteristics (and corresponding actual lifetimes) to determine whether the non-write-promoted data is hot or cold data.

[0067] Alternatively, the data type can be small fragments of data, as described above. Figure 4 As described. In some embodiments, memory device 120 may determine whether non-write-promoted data is fragmented data based on comparing the size of non-write-promoted data with a threshold size (e.g., page line size). If the size of the non-write-promoted data is less than (or equal to) the threshold size, then the non-write-promoted data is fragmented data. If the size of the non-write-promoted data is greater than (or equal to) the threshold size, then the non-write-promoted data is not fragmented data. While data cannot be both hot and cold, in some embodiments, data can be both hot and fragmented data (e.g., fragmented data with a relatively short expected lifetime), or it can be both cold and fragmented data (e.g., fragmented data with a relatively long expected lifetime).

[0068] As shown by component symbol 530, memory device 120 can determine whether there is sufficient unreserved cache memory 225 available for storing non-write-boosted data. (As described above...) Figure 4 As described, memory device 120 may reserve a threshold amount of cache memory 225 for write-boosted data. If memory device 120 determines that writing non-write-boosted data to cache memory 225 will reduce the available memory of cache memory 225 to below the threshold amount, then memory device 120 may suppress the writing of non-write-boosted data to cache memory 225. In this case, memory device 120 may write the non-write-boosted data to main memory 230. Alternatively, if memory device 120 determines that writing non-write-boosted data to cache memory 225 will leave a remaining amount of available memory in cache memory 225 that meets a threshold (e.g., greater than or equal to the threshold amount), then memory device 120 may write non-write-boosted data to cache memory 225 (e.g., if the non-write-boosted data is hot data and / or small fragments of data, as described elsewhere herein).

[0069] As another example, memory device 120 may determine a threshold amount of unreserved cache memory 225 (e.g., unreserved for write-boosted data). If memory device 120 determines that writing non-write-boosted data to cache memory 225 would cause the amount of cache memory 225 used for non-write-boosted data to exceed this threshold amount, then memory device 120 may suppress writing non-write-boosted data to cache memory 225 (and may write non-write-boosted data to main memory 230). In some embodiments, the threshold amount of unreserved cache memory 225 available for non-write-boosted data is based on a threshold amount of cache memory 225 reserved for write-boosted data (e.g., the remaining amount of unreserved cache memory 225). In some embodiments, the threshold amount of unreserved cache memory 225 available for non-write-boosted data is based on the amount of cache memory 225 reserved for write-boosted data and the amount of cache memory 225 reserved for small data segments (e.g., the remaining amount of unreserved cache memory 225).

[0070] If memory device 120 reserves a portion of cache memory 225 for small data segments and if memory device 120 determines that the non-write-elevated data is small data segments, then memory device 120 may suppress the determination of whether the non-write-elevated data is hot or cold data and may suppress the determination of whether there is sufficient unreserved cache memory 225 available for the non-write-elevated data. This can result in faster write times by eliminating unnecessary operations. However, in some embodiments, memory device 120 may determine whether there is sufficient cache memory 225 available for small data segments (e.g., using cache memory 225 reserved for small data segments and / or unreserved cache memory 225). If not, then memory device 120 may write the small data segments to main memory 230.

[0071] In some embodiments, before determining whether the non-write-promoted data is hot or cold data (as described in conjunction with element symbol 520), the memory device 120 may determine whether there is sufficient unreserved cache memory 225 available for storing the non-write-promoted data (as described in conjunction with element symbol 530). If there is not sufficient unreserved cache memory 225 available for storing the non-write-promoted data, the memory device 120 may suppress the determination of whether the non-write-promoted data is hot or cold data. This can result in faster write times by eliminating unnecessary operations, since the memory device 120 cannot write the non-write-promoted data to the cache memory 225 regardless of whether the non-write-promoted data is hot or cold data. However, in some embodiments, the memory device 120 may still determine whether the non-write-promoted data is a small fragment of data, as described above. Furthermore, if the memory device 120 determines that there is sufficient unreserved cache memory 225 available for storing the non-write-promoted data, then the memory device 120 may then determine whether the non-write-promoted data is hot or cold data (as described in conjunction with element symbol 520).

[0072] Alternatively, before determining whether there is sufficient unreserved cache memory 225 available for storing non-write-boosted data, memory device 120 may determine whether the non-write-boosted data is hot or cold data. If the non-write-boosted data is cold, memory device 120 may suppress the determination of whether there is sufficient unreserved cache memory 225 available for storing the non-write-boosted data. This results in faster write times by eliminating unnecessary operations, as memory device 120 will not write cold non-write-boosted data to cache memory 225. However, if memory device 120 determines that the non-write-boosted data is hot, then memory device 120 may then determine whether there is sufficient unreserved cache memory 225 available for storing hot non-write-boosted data.

[0073] As illustrated by component symbol 540, memory device 120 may selectively write non-write-boosted data to cache memory 225 or main memory 230 based on the data type of the non-write-boosted data and / or based on the availability of sufficient unreserved cache memory 225. As used herein, “selectively” writing non-write-boosted data to cache memory 225 or main memory 230 means writing non-write-boosted data to cache memory 225 or to main memory 230. For example, selectively writing non-write-boosted data to cache memory 225 or main memory 230 based on whether a condition is met (e.g., depending on the data type and / or the availability of sufficient unreserved cache memory 225) means that if the condition is met, then the non-write-boosted data is written to cache memory 225, and if the condition is not met, then the non-write-boosted data is written to main memory 230 (or vice versa). Therefore, selectively writing non-write-boosted data to cache memory 225 or main memory 230 may include determining whether to write non-write-boosted data to cache memory 225 or main memory 230, and then determining whether to write non-write-boosted data to cache memory 225 or main memory 230 based on that determination.

[0074] As an example, and as illustrated by component symbol 550, if memory device 120 determines that the non-write-boosted data is hot data (e.g., associated with a first data type) and cache memory 225 has sufficient memory (e.g., not reserved for write-boosted data and / or not reserved for small fragment data) to store the hot non-write-boosted data, then memory device 120 may write the hot non-write-boosted data to cache memory 225 (e.g., to store the hot non-write-boosted data in cache memory 225). Alternatively, if memory device 120 determines that the non-write-boosted data is small fragment data and cache memory 225 has sufficient memory (e.g., not reserved for write-boosted data and / or reserved for small fragment data) to store small fragments of non-write-boosted data, then memory device 120 may write the small fragments of non-write-boosted data to cache memory 225 (e.g., to store the small fragments of non-write-boosted data in cache memory 225). Although write boosting is deactivated for non-write boosting data, memory device 120 can still write non-write boosting data to cache memory 225 (e.g., write booster cache memory).

[0075] In some implementations, memory device 120 may use a write-promotion cursor to identify the location where non-write-promotion data of cache memory 225 is to be written. The "write-promotion cursor" may contain information stored by memory device 120 (e.g., in non-volatile memory) indicating the location. The location may include, for example, a die, plane, block, sub-block, page line, and / or page. If memory device 120 determines that non-write-promotion data should be stored in cache memory 225, then memory device 120 may use a write-promotion cursor (sometimes referred to as a cache memory cursor) to determine the location where the non-write-promotion data is to be written. Otherwise, memory device 120 may use a different write cursor (e.g., a main memory cursor) to determine the memory location (e.g., in main memory 230) where the non-write-promotion data is to be written.

[0076] As another example, and as illustrated by component symbol 560, if memory device 120 determines that the non-write-promoted data is cold data (e.g., associated with a second data type) or cache memory 225 does not have sufficient memory (e.g., not reserved for write-promoted data and / or not reserved for small fragments of data) to store the non-write-promoted data, then memory device 120 may write the non-write-promoted data to main memory 230 (e.g., to store the non-write-promoted data in main memory 230). As described above, if memory device 120 determines that it needs to store the non-write-promoted data in main memory 230, then memory device 120 may use a main memory cursor to determine the location in main memory 230 where the non-write-promoted data is to be written (e.g., die, plane, block, sub-block, page line, and / or page).

[0077] By writing some non-write-boosted data (e.g., hot data and / or small fragments of data) to cache memory 225 while also reserving a portion of cache memory 225 for write-boosted data, memory device 120 can extend its lifetime (e.g., by reducing the write amplification of hot data in main memory 230), improve resource utilization of memory device 120 (e.g., by allowing flexible use of cache memory 225 that would otherwise be used entirely for write boosting, and by suppressing the writing of large amounts of dummy data along with small fragments of data to main memory 230), and / or improve the performance of memory device 120 (e.g., by ensuring that a portion of cache memory 225 is available for write-boosting operations).

[0078] As indicated above, Figure 5 It is provided as an instance. Other instances may differ from those provided. Figure 5 The described instance.

[0079] Figure 6This is a diagram of instance 600, which involves performing a discard item collection operation on the write-to-booster cache memory. (Combined with...) Figure 6 The described operations may be performed by memory device 120 and / or one or more components of memory device 120 (e.g., controller 130 and / or one or more components of controller 130).

[0080] As shown by component symbol 610, memory device 120 (e.g., controller 130) can perform a discard item collection operation on cache memory 225. (As described above...) Figure 3 As described, the waste item collection operation may include, for example, identifying conditions that meet the erasure criteria (as described above). Figure 3 The cache memory 225 (described herein) blocks (sometimes referred to as old blocks) copy valid pages of the identified blocks to one or more new blocks and erase the identified blocks. The memory device 120 can perform a discard collection to free up memory resources of the cache memory 225.

[0081] In some implementations, as part of performing a discarded item collection operation, the memory device 120 may write data of a first data type (e.g., hot data) from older blocks to a first block 620, and data of a second data type (e.g., cold data) from older blocks to a second block 630. This reduces write amplification and block wear because copying all hot data to a single block instead of multiple blocks reduces the number of blocks that need to be erased later during the short period of data copying.

[0082] For example, as illustrated by component symbol 640, memory device 120 can copy hot data from an older block of cache memory 225 to a first block 620. To identify hot data from the older block, memory device 120 can identify a first set of pages containing the stored hot data (e.g., first data associated with a first data type) within the older block. Memory device 120 can copy the hot data to the first block 620 based on the identification of this first set of pages.

[0083] Similarly, as illustrated by component symbol 650, memory device 120 can copy cold data from an older block of cache memory 225 to a second block 630. To identify cold data from the older block, memory device 120 can identify a second set of pages containing the stored cold data (e.g., second data associated with a second data type) within the older block. Memory device 120 can copy the cold data to the second block 630 based on the identification of this second set of pages.

[0084] In some implementations, memory device 120 may store a data type indicator that indicates, for one or more pages of cache memory 225 (e.g., unreserved portions of cache memory 225), whether data stored in those pages is hot or cold data. For example, the data type indicator may have a first value (e.g., 0) when the corresponding data is hot data, and a second value (e.g., 1) when the corresponding data is cold data. Alternatively, the data type indicator may indicate the time when data was written (e.g., to one or more pages), and memory device 120 may use that time to determine whether the data is hot or cold data. For example, memory device 120 may compare a time (e.g., storage time) with the current time (e.g., associated with performing a discarded item collection operation) to determine whether the data stored in the corresponding page is cold data (e.g., where the difference between the storage time and the current time meets a threshold) or hot data (e.g., where the difference between the storage time and the current time does not meet a threshold). The memory device 120 may use one or more data type indicators to identify a first set of pages storing hot data and / or a second set of pages storing cold data.

[0085] In some implementations, both the first block 620 and the second block 630 are contained in main memory 230, and both hot and cold data are copied to main memory 230. This frees up more memory resources in cache memory 225 compared to storing some data (e.g., hot data) in a new block. Alternatively, in some implementations, the first block 620 may be contained in cache memory 225 and the second block 630 may be contained in main memory 230. This frees up some cache memory 225 (e.g., by copying cold data to main memory 230) while reducing the write amplification of main memory 230 (e.g., by keeping hot data in cache memory 225).

[0086] In some implementations, memory device 120 may determine whether to copy both hot and cold data to main memory 230, or to copy cold data to main memory 230 and hot data to cache memory 225, based on the amount of available unreserved cache memory 225. For example, if the amount of available unreserved cache memory 225 is less than (or equal to) a threshold amount, then memory device 120 may copy both hot and cold data to main memory 230 to free up memory resources in cache memory 225 (e.g., create more available unreserved cache memory 225). If the amount of available unreserved cache memory 225 is greater than (or equal to) a threshold amount, then memory device 120 may copy cold data to main memory 230 and hot data to cache memory 225 to reduce the write amplification of main memory 230 (and because there is less need to free up memory resources in cache memory 225).

[0087] Alternatively, memory device 120 may determine whether to copy both hot and cold data to main memory 230, or to copy cold data to main memory 230 and hot data to cache memory 225, based on one or more block age parameters associated with cache memory 225 (e.g., the number of P / E cycles associated with available blocks of cache memory 225, such as unreserved portions of cache memory 225, and the average number of P / E cycles associated with blocks of cache memory 225, such as unreserved portions of cache memory 225). For example, if the P / E cycle parameter associated with cache memory 225 is greater than (or equal to) a threshold, then memory device 120 may copy both hot and cold data to main memory 230 to reduce wear and tear on cache memory 225. If the P / E cycle parameter associated with cache memory 225 is less than (or equal to) a threshold, then memory device 120 can copy cold data to main memory 230 and hot data to cache memory 225 to reduce the write amplification of main memory 230 (and because there is little need to reduce wear on cache memory 225).

[0088] In some implementations, memory device 120 may use one or more block age parameters to select blocks of cache memory 225 and / or main memory 230 to which hot data is copied. For example, memory device 120 may copy hot data to blocks with a lower P / E cycle count (e.g., less than or equal to a threshold), and / or may suppress the copying of hot data to blocks with a higher P / E cycle count (e.g., greater than or equal to a threshold). This may result in more uniform wear on the blocks of cache memory 225 and / or main memory 230.

[0089] In some implementations, the memory device 120 may be configured to allocate a first set of blocks to cache memory 225 reserved for write-boosted data, a second set of blocks to cache memory 225 reserved for small data segments, and / or a third set of unreserved cache memory 225. For example, if one of the block sets wears out faster than the other block sets (e.g., based on P / E cycle counts), the memory device 120 may modify which blocks are included in each set (e.g., to achieve wear leveling).

[0090] As indicated above, Figure 6 It is provided as an instance. Other instances may differ from those provided. Figure 6 The described instance.

[0091] Figure 7 This is a flowchart of an example method 700 associated with the opportunity storage of non-write-promoted data in a write-promoter cache memory. In some embodiments, a memory device (e.g., memory device 120) is executable or configurable to perform method 700. In some embodiments, another device or group of devices (e.g., system 100) separate from or including the memory device is executable or configurable to perform method 700. Alternatively or additionally, one or more components of the memory device (e.g., controller 130, memory management component 235, memory reservation component 240, memory selection component 245, and / or command execution component 250) are executable or configurable to perform method 700. Thus, the means for performing method 700 may include the memory device and / or one or more components of the memory device. Alternatively or additionally, a non-transitory computer-readable medium may store one or more instructions that, when executed by the memory device (e.g., controller 130 of memory device 120), cause the memory device to perform method 700.

[0092] like Figure 7 As shown, method 700 may include receiving from the host device an indication of a threshold amount of non-volatile cache memory reserved for boosting first data for its activation write (block 710). Figure 7 As further shown, method 700 may include receiving a write command (block 720) from a host device containing second data for deactivating write elevation. Figure 7 As further shown in the diagram, method 700 may include determining that the second data is hot data (box 730). Figure 7 Further illustrating, method 700 may include identifying a block of the non-volatile cache memory (block 740) based on an indication of the threshold amount, determined that the second data is hot data, and despite deactivating write boosting for the second data.Figure 7 As further shown, method 700 may include writing the second data to the block (block 750) of the non-volatile cache memory.

[0093] Method 700 may include additional aspects, such as any single aspect or any combination of aspects described below and / or in conjunction with one or more other methods or operations described elsewhere herein.

[0094] In a first aspect, method 700 includes identifying the block using the write boosting cursor based on determining that writing the second data to the non-volatile cache memory will not reduce the available amount of non-volatile cache memory reserved for the first data to below the threshold amount.

[0095] In the second aspect, either alone or in combination with the first aspect, method 700 includes copying hot data stored in the block to a first new block and copying cold data stored in the block to a second new block during a discarded item collection operation on the block.

[0096] In the third aspect, either alone or in combination with one or more of the first and second aspects, the first new block is a first block of non-volatile main memory and the second new block is a second block of the non-volatile main memory.

[0097] In the fourth aspect, either alone or in combination with one or more of the first to third aspects, the first new block is a new block of the non-volatile cache memory and the second new block is a new block of the non-volatile main memory.

[0098] In the fifth aspect, either alone or in combination with one or more of the first to fourth aspects, method 700 includes copying the hot data to the first new block and the cold data to the second new block during the abandoned item collection operation based on one or more block age parameters associated with the non-volatile cache memory.

[0099] In the sixth aspect, either alone or in combination with one or more of the first to fifth aspects, the indication of the threshold quantity includes a threshold size or a threshold percentage.

[0100] In the seventh aspect, either alone or in combination with one or more of the first to sixth aspects, method 700 includes storing small fragment data in the block of the non-volatile cache memory, the small fragment data having a size smaller than the page line size of the page line of the memory device.

[0101] In the eighth aspect, either alone or in combination with one or more of the first to seventh aspects, a portion of the non-volatile cache memory is reserved for the small data fragments.

[0102] Although Figure 7 The example box for method 700 is shown, but in some implementations, method 700 may include, in addition to, Figure 7 The frame outside the frame depicted in the text, compared to Figure 7 The fewer boxes depicted in the text, and Figure 7 The boxes depicted are different from or similar to those in the text. Figure 8 The boxes depicted herein are arranged differently. Alternatively, two or more of the boxes in method 700 may be performed in parallel. Method 700 is an example of a method that can be performed by one or more means described herein. These one or more means may perform or be configured to perform one or more other methods based on the operations described herein.

[0103] Figure 8 This is a flowchart of an example method 800 associated with the opportunity storage of non-write-promoted data in a write-promoter cache memory. In some embodiments, a memory device (e.g., memory device 120) is executable or configurable to perform method 800. In some embodiments, another device or group of devices (e.g., system 100) separate from or including the memory device is executable or configurable to perform method 800. Alternatively or additionally, one or more components of the memory device (e.g., controller 130, memory management component 235, memory reservation component 240, memory selection component 245, and / or command execution component 250) are executable or configurable to perform method 800. Thus, the components for performing method 800 may include the memory device and / or one or more components of the memory device. Alternatively or additionally, a non-transitory computer-readable medium may store one or more instructions that, when executed by the memory device (e.g., controller 130 of memory device 120), cause the memory device to perform method 800.

[0104] like Figure 8 As shown, method 800 may include receiving a write command (block 810) containing data to be written to the memory device. Figure 8 As further shown, method 800 may include receiving an instruction to deactivate the single-level unit data cache for the data (block 820). Figure 8 Further illustrating this, method 800 may include determining whether the data is associated with a first data type or a second data type (box 830). Figure 8As further shown, method 800 may include selectively writing the data to a single-level cell cache memory or a multi-level cell main memory based on: determining whether the data is associated with the first data type or the second data type, and determining whether the single-level cell cache memory has available memory that is not reserved for caching the single-level cell data (block 840).

[0105] Method 800 may include additional aspects, such as any single aspect or any combination of aspects described below and / or in conjunction with one or more other methods or operations described elsewhere herein.

[0106] In the first aspect, the first data type is associated with a shorter expected lifespan than the expected lifespan associated with the second data type.

[0107] In the second aspect, either alone or in combination with the first aspect, selectively writing the data to the single-level cell cache memory or the multi-level cell main memory includes writing the data to the single-level cell cache memory based on: determining that the data is associated with the first data type, and determining that the single-level cell cache memory has sufficient memory to store the data without being reserved for caching the single-level cell data.

[0108] In the third aspect, selectively writing the data to the single-level cell cache memory or the multi-level cell main memory, either alone or in combination with one or more of the first and second aspects, includes writing the data to the multi-level cell main memory based on determining that the data is associated with a second data type.

[0109] In the fourth aspect, selectively writing the data to the single-level cell cache memory or the multi-level cell main memory, either alone or in combination with one or more of the first to third aspects, includes writing the data to the multi-level cell main memory based on determining that the single-level cell cache memory does not have sufficient memory not reserved for storing the single-level cell data cache.

[0110] In the fifth aspect, either alone or in combination with one or more of the first to fourth aspects, method 800 includes receiving from a host device an indication of the amount of memory in the single-level cell cache memory reserved for the single-level cell data cache, and the determination of whether the single-level cell cache memory has available memory not reserved for the single-level cell data cache is based on the amount of memory in the single-level cell cache memory reserved for the single-level cell data cache.

[0111] In a sixth aspect, either alone or in combination with one or more of the first to fifth aspects, method 800 includes identifying a block of the single-level cell cache memory to which an obsolete item collection operation is to be performed; identifying a first set of pages contained in the block, the first set of pages storing first data associated with the first data type; identifying a second set of pages contained in the block, the second set of pages storing second data associated with the second data type; as part of performing the obsolete item collection operation, copying the first data to a first block; and as part of performing the obsolete item collection operation, copying the second data to a second block.

[0112] In the seventh aspect, one or more of the first to sixth aspects, either individually or in combination, are included in the multilevel unit main memory, with both the first block and the second block contained therein.

[0113] In the eighth aspect, one or more of the first to seventh aspects individually or in combination, wherein the first block is contained in the single-level cell cache memory and the second block is contained in the multi-level cell main memory.

[0114] Although Figure 8 The example box for method 800 is shown, but in some implementations, method 800 may include, in addition to, Figure 8 The frame outside the frame depicted in the text, compared to Figure 8 The fewer boxes depicted in the text, and Figure 8 The boxes depicted are different from or similar to those in the text. Figure 9 The boxes depicted herein are arranged differently. Alternatively, two or more of the boxes in method 800 may be performed in parallel. Method 800 is an example of a method that can be performed by one or more means described herein. These one or more means may perform or be configured to perform one or more other methods based on the operations described herein.

[0115] Figure 9This is a flowchart of an example method 900 associated with the opportunity storage of non-write-promoted data in a write-promoter cache memory. In some embodiments, a memory device (e.g., memory device 120) is executable or configurable to perform method 900. In some embodiments, another device or group of devices (e.g., system 100) separate from or including the memory device is executable or configurable to perform method 900. Alternatively or additionally, one or more components of the memory device (e.g., controller 130, memory management component 235, memory reservation component 240, memory selection component 245, and / or command execution component 250) are executable or configurable to perform method 900. Thus, the components for performing method 900 may include the memory device and / or one or more components of the memory device. Alternatively or additionally, a non-transitory computer-readable medium may store one or more instructions that, when executed by the memory device (e.g., controller 130 of memory device 120), cause the memory device to perform method 900.

[0116] like Figure 9 As shown, method 900 may include receiving a write command (block 910) containing data to be written to a memory device. Figure 9 Further illustrating this, method 900 may include determining to deactivate write-boosting data cache for the data (box 920). Figure 9 As further illustrated, method 900 may include determining that the data is associated with a first data type (box 930). Figure 9 Further illustrating, method 900 may include determining, based on determining that the data is associated with the first data type and although write boosting data cache is deactivated for the data, to write the data to cache memory instead of main memory (block 940). Figure 9 As further shown, method 900 may include writing the data to the cache memory based on determining that the data needs to be written to the cache memory (block 950).

[0117] Method 900 may include additional aspects, such as any single aspect or any combination of aspects described below and / or in conjunction with one or more other methods or operations described elsewhere herein.

[0118] In the first aspect, it is expected that the first data type will become invalid or overwritten in a shorter amount of time than the second data type.

[0119] In the second aspect, either alone or in combination with the first aspect, the main memory stores more bits per memory cell than the cache memory.

[0120] In the third aspect, determining to write the data to the cache memory, either alone or in combination with one or more aspects of the first and second aspects, further includes determining to write the data to the cache memory based on determining that writing the data to the cache memory will leave a remaining amount of available cache memory that meets a threshold.

[0121] In the fourth aspect, either alone or in combination with one or more of the first to third aspects, method 900 includes receiving an indication of the threshold, wherein the threshold indicates an amount of cache memory reserved for the write boosting data cache.

[0122] In a fifth aspect, either alone or in combination with one or more of the first to fourth aspects, method 900 includes writing small fragments of data into the cache memory, the small fragments of data having a size smaller than the page line size of the page line of the memory device.

[0123] In a sixth aspect, either alone or in combination with one or more of the first to fifth aspects, method 900 includes identifying a block of the cache memory for which an obsolete item collection operation is performed; as part of performing the obsolete item collection operation, copying first data associated with the first data type and stored in the block to a first block; and as part of performing the obsolete item collection operation, copying second data associated with the first data type and stored in the block to a second block.

[0124] Although Figure 9 The example box for method 900 is shown, but in some implementations, method 900 may include, in addition to... Figure 9 The frame outside the frame depicted in the text, compared to Figure 9 The fewer boxes depicted in the text, and Figure 9 The boxes depicted are different from or similar to those in the text. ​ The boxes depicted herein are arranged differently. Alternatively, two or more of the boxes in method 900 may be performed in parallel. Method 900 is an example of a method that can be performed by one or more means described herein. These one or more means may perform or be configured to perform one or more other methods based on the operations described herein.

[0125] In some embodiments, a memory device includes one or more components configured to: receive from a host device an indication of a threshold amount of non-volatile cache memory reserved for activating write boosting of first data therefor; receive from the host device a write command containing second data for deactivating write boosting of the second data; determine that the second data is hot data; based on the determination that the second data is hot data, and based on the indication of the threshold amount and although write boosting is deactivated for the second data, identify a block of the non-volatile cache memory using a write boosting cursor; and write the second data into the block of the non-volatile cache memory.

[0126] In some implementations, a method includes: receiving a write command containing data to be written to the memory device; receiving an instruction to deactivate a single-level cell data cache for the data; determining whether the data is associated with a first data type or a second data type; and selectively writing the data to a single-level cell cache memory or a multi-level cell main memory based on: determining whether the data is associated with the first data type or the second data type, and determining whether the single-level cell cache memory has available memory that is not reserved for the single-level cell data cache.

[0127] In some embodiments, a device includes: a non-volatile memory array; and a controller configured to execute instructions that cause the device to: process a received command to write data to the non-volatile memory array, wherein the command is received without an indication to write the data to a single-level cell (SLC) cache memory of the non-volatile memory array; determine whether the data is associated with a first data type; determine whether the SLC cache memory has sufficient memory not reserved for SLC data caching; and write the data to the SLC cache memory based on the determination that the data is associated with the first data type and that the SLC cache memory has sufficient memory not reserved for SLC data caching.

[0128] The foregoing disclosure provides explanations and descriptions, but is not intended to be exhaustive or to limit the implementation to the precise form disclosed. Modifications and variations may be made in light of the foregoing disclosure or may be derived from the practice of the implementations described herein.

[0129] As used herein, depending on the context, "satisfying the threshold" can mean a value greater than the threshold, greater than or equal to the threshold, less than the threshold, less than or equal to the threshold, equal to the threshold, not equal to the threshold, or similar. The phrases "based on" or "in response to" can be used in place of "if," as used herein. For example, an action performed "if" is satisfied can be replaced with an action performed "based on" being satisfied or an action performed "in response to" being satisfied.

[0130] Even though there are specific combinations of features described in the claims and / or disclosed in the specification, these combinations are not intended to limit the disclosure of the embodiments described herein. Many of these features can be combined in ways not specifically described in the claims and / or not disclosed in the specification. For example, this disclosure includes combinations of each dependent claim in a group of claims with each other independent claim in that group of claims and each combination of multiple claims in that group of claims. As used herein, the phrase “at least one” in a list of items refers to any combination of those items containing a single member. As an example, “at least one of the following: a, b, or c” is intended to cover a, b, c, a+b, a+c, b+c, and a+b+c, as well as any combination having multiple identical elements (e.g., a+a, a+a+a, a+a+b, a+a+c, a+b+b, a+c+c, b+b, b+b+b, b+b+c, c+c, and c+c+c, or any other ordering of a, b, and c).

[0131] No element, action, or instruction used herein should be construed as critical or necessary unless explicitly stated otherwise. Furthermore, as used herein, the articles “a” and “an” are intended to include one or more items and are used interchangeably with “one or more.” Additionally, as used herein, the article “described” is intended to include one or more items referenced by the article “described” and is used interchangeably with “described one or more.” Where only one item is anticipated, the phrases “only one,” “single,” or similar language are used. Moreover, as used herein, the terms “has,” “have,” “having,” or similar are intended to be open-ended terms that do not limit the element they modify (e.g., an element “having” A may also have B). Furthermore, the phrase “based on” is intended to mean “at least partially based on,” unless explicitly stated otherwise. As used herein, the term “multiple” can be replaced by “a plurality of” and vice versa. Moreover, as used herein, the term “or” is intended to be inclusive when used in a series and can be used interchangeably with “and / or” unless otherwise expressly stated (e.g., if combined with “either one” or “only one of…”).

Claims

1. A memory device comprising: Non-volatile cache memory; and One or more controllers, configured to: Receive from the host device an indication of the threshold amount of the non-volatile cache memory reserved for the first data to be boosted for its activation write; Receive a write command from the host device containing second data for deactivating write elevation; It has been determined that the second data is hot data; Based on the determination that the second data is hot data, based on the indication of the threshold amount and although write boosting is deactivated for the second data, the block of the non-volatile cache memory is identified using a write boosting cursor; and The second data is written to the block of the non-volatile cache memory.

2. The memory device of claim 1, wherein, in order to identify the block using the write lifting cursor, the one or more controllers are configured to: Based on the determination that writing the second data to the non-volatile cache memory will not reduce the available amount of non-volatile cache memory reserved for the first data to below the threshold amount, the write boosting cursor is used to identify the block.

3. The memory device of claim 1, wherein the one or more controllers are further configured to copy hot data stored in the block to a first new block and cold data stored in the block to a second new block during a discarded item collection operation on the block.

4. The memory device of claim 3, wherein the first new block is a first block of non-volatile main memory and the second new block is a second block of the non-volatile main memory.

5. The memory device of claim 3, wherein the first new block is a new block of the non-volatile cache memory and the second new block is a new block of the non-volatile main memory.

6. The memory device of claim 3, wherein the one or more controllers are configured to copy the hot data to the first new block and the cold data to the second new block during the discarded item collection operation based on one or more block age parameters associated with the non-volatile cache memory.

7. The memory device of claim 1, wherein the indication of the threshold quantity includes a threshold size or a threshold percentage.

8. The memory device of claim 1, further comprising storing small fragment data in the block of the non-volatile cache memory, the small fragment data having a size smaller than the page row size of the page row of the memory device.

9. The memory device of claim 8, wherein a portion of the non-volatile cache memory is reserved for the small data segment.

10. A method comprising: The memory device receives a write command containing data to be written to the memory device; The memory device receives an instruction to deactivate the single-level cell data cache for the data; The memory device determines whether the data is associated with a first data type or a second data type; and The memory device may selectively write the data to a single-level cell cache memory or a multi-level cell main memory based on the following: Determine whether the data is associated with the first data type or the second data type, and Determine whether the single-level unit cache memory has available memory that has not been reserved for the single-level unit data cache.

11. The method of claim 10, wherein the first data type is associated with a shorter expected lifespan than the expected lifespan associated with the second data type.

12. The method of claim 10, wherein selectively writing the data to the single-level cell cache memory or the multi-level cell main memory comprises writing the data to the single-level cell cache memory based on: Determine that the data is associated with the first data type, and It is determined that the single-level unit cache memory has sufficient memory to store the data, without any pre-reserved memory for the single-level unit data cache.

13. The method of claim 10, wherein selectively writing the data to the single-level cell cache memory or the multi-level cell main memory comprises writing the data to the multi-level cell main memory based on determining that the data is associated with the second data type.

14. The method of claim 10, wherein selectively writing the data to the single-level cell cache memory or the multi-level cell main memory comprises writing the data to the multi-level cell main memory based on determining that the single-level cell cache memory does not have sufficient memory not reserved for caching the single-level cell data to store the data.

15. The method of claim 10, further comprising receiving from a host device an indication of the amount of memory in the single-level cell cache memory to be reserved for the single-level cell data cache, and The determination of whether the single-level cell cache memory has available memory that has not been reserved for the single-level cell data cache is based on the amount of memory in the single-level cell cache memory that has not been reserved for the single-level cell data cache.

16. The method of claim 10, further comprising: Identify the blocks in the single-level unit cache memory for which a discard item collection operation is to be performed; Identify a first set of pages contained in the block, the first set of pages storing first data associated with the first data type; Identify a second set of pages contained within the block, the second set of pages storing second data associated with the second data type; As part of performing the abandoned item collection operation, the first data is copied to the first block; and As part of performing the abandoned project collection operation, the second data is copied to the second block.

17. The method of claim 16, wherein both the first block and the second block are contained in the multilevel unit main memory, or The first block is contained in the single-level unit cache memory and the second block is contained in the multi-level unit main memory.

18. An apparatus comprising: Non-volatile memory array; and A controller configured to execute instructions that cause the device to perform the following: Process a received command to write data to the non-volatile memory array, wherein the command is received without an indication that the data is to be written to the single-level cell (SLC) cache memory of the non-volatile memory array. Determine whether the data is associated with a first data type; Determine whether the SLC cache memory has sufficient memory that has not been reserved for SLC data caching; and Based on the determination that the data is associated with the first data type and that the SLC cache memory has sufficient memory not reserved for SLC data caching, the data is written to the SLC cache memory.

19. The device of claim 18, wherein the controller is configured to execute instructions that cause the device to perform the following: Based on the determination that the data is not associated with the first data type or that the SLC cache memory does not have sufficient memory reserved for SLC data caching, the data is written to the multilevel cell memory of the non-volatile memory array.

20. The device of claim 18, wherein the first data type is expected to become invalid or overwritten in a shorter time than the second data type.

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