A microcontroller abnormal reset method

Abstract

The present application provides a method for handling an abnormal reset of a microcontroller, which is used to solve the problem that it is difficult to analyze and accurately locate the cause of the fault after the microcontroller has an abnormal reset. The method includes: after the microcontroller detects an abnormality in itself, determining the abnormality handling mode to be executed according to the source of the abnormality, including: internal action mode and external action mode; if it is the internal action mode, the microcontroller executes the TRAP processing function corresponding to the abnormality, stores the TRAP event error information and the context information of the CSA corresponding to the abnormality in the backup RAM, and then performs a soft reset. It is then determined whether the source of the abnormality is an SMU alarm. If so, the information in the diagnostic register of the SMU is stored in the backup RAM; if it is the external action mode, the microcontroller sends an abnormality signal to the power management module PMIC, and the PMIC triggers the microcontroller to perform a hot power-on reset after a first delay reset preset time length; the time used to execute the internal action mode is no longer than the first delay reset preset time length.

Description

Technical Field

[0001] The present application relates to the technical field of microcontrollers, and in particular to a method for resetting a microcontroller when processing an abnormality. Background Art

[0002] A power management IC (PMIC) is a specialized integrated circuit used to manage power in digital systems. A PMIC monitors power supply, temperature, and microcontroller operating status. Detecting a microcontroller anomaly triggers a reset. A warm power-on reset (Warm POR) caused by an anomaly resets most registers within the microcontroller to their default settings. Furthermore, if the microcontroller's User Configuration Block (UCB) is set to factory defaults, all RAM contents are cleared, making it difficult to locate and document the cause of the fault. Summary of the Invention

[0003] The purpose of the embodiments of the present invention is to provide a method for processing abnormal reset of a microcontroller, which is used to solve the problem that it is difficult to analyze and accurately locate the cause of the fault after the microcontroller is abnormally reset.

[0004] The embodiment of the present application provides a method for resetting a microcontroller for handling an exception, the method comprising: after the microcontroller detects an exception in itself, determining an exception handling mode to be executed according to the source of the exception, the exception handling mode including: an internal action mode and an external action mode; if the determined exception handling mode is the internal action mode, the microcontroller executes a TRAP processing function corresponding to the exception, stores the TRAP event error information and the context information of the context storage area CSA corresponding to the exception in the backup RAM, then performs a soft reset, and then determines whether the source of the exception is an alarm SMU Alarm of the software and hardware safety mechanism. If so, the information in the diagnostic register of the security management unit SMU is stored in the backup RAM. RAM; if the determined exception handling mode is the external action mode, the microcontroller sends an exception signal to the power management module PMIC, and the PMIC is configured to trigger the microcontroller to perform a hot power-on reset after receiving the exception signal at an interval of a first delay reset preset time; if the determined exception handling mode is the internal action mode and the external action mode, the internal action mode and the external action mode are executed simultaneously, and the time used to execute the internal action mode is not greater than the first delay reset preset time.

[0005] In the above solution, after an abnormality occurs in the microcontroller, the PMIC delays the reset for a preset time interval and then triggers the microcontroller to perform a hot power-on reset. Within the time window of the first delay reset preset time interval, the contents of all registers storing fault information are stored in the Backup RAM, providing sufficient information for subsequent fault analysis, thereby solving the problem of difficulty in analyzing and locating the cause of the fault.

[0006] As an optional method, determining the exception handling mode to be executed based on the exception source includes: if the exception source is the SMU alarm, and the SMU alarm supports internal and external actions, and the external action is configured as FSP, then determining the exception handling mode to be executed as the internal action mode or the external action mode. In the above scheme, different exception sources will result in different exception handling modes executed by the microcontroller. Under the general category of exception source, the source of the exception reset can be further subdivided according to the configuration of the fault source, and effective and critical fault information can be captured and stored. This facilitates rapid, accurate, and systematic analysis and location of the fault cause.

[0007] As an optional approach, determining the exception handling mode to be executed based on the exception source includes: if the exception source is the SMU alarm, and the SMU alarm supports both internal and external actions, and the external action is configured as no action, then determining the exception handling mode to be executed is the internal action mode. In this solution, different exception sources result in different exception handling modes executed by the microcontroller. Within the general category of exception sources, the sources of the exception reset can be further subdivided based on the configuration of the fault source, capturing and storing effective and critical fault information. This facilitates rapid, accurate, and systematic analysis and location of the fault cause.

[0008] As an optional approach, determining the exception handling mode to be executed based on the exception source includes: if the exception source is the SMU alarm, and the SMU alarm only supports external actions, then determining the exception handling mode to be executed as the external action mode. In this solution, different exception sources result in different exception handling modes executed by the microcontroller. Within the general category of exception sources, the sources of abnormal resets can be further subdivided based on the configuration of the fault source. This refined classification facilitates rapid, accurate, and systematic analysis and location of the fault cause, effectively locating the specific type of SMU alarm that triggered the reset.

[0009] As an optional method, the exception handling mode to be executed is determined based on the source of the exception, including: if the source of the exception is the exception handling mechanism TRAP, and the TRAP is a non-maskable interrupt NMI type that can be associated with the software and hardware safety mechanism of the microcontroller, then the exception handling mode to be executed is determined to be the internal action mode and the external action mode; otherwise, the exception handling mode to be executed is determined to be the internal action mode. In the above scheme, the exception handling mode executed by the microcontroller is different depending on the source of the exception. Under the general category of the exception source, the source of the abnormal reset can be further subdivided according to the configuration of the fault source, and effective and critical fault information can be captured and saved. This is conducive to quickly, accurately, and systematically analyzing and locating the cause of the fault.

[0010] As an optional feature, the exception handling mode also includes a PMIC failure mode. If the exception handling mode is determined to be the PMIC failure mode, the PMIC directly triggers the microcontroller to perform a warm power-on reset, and then stores the values ​​of the reset-related monitoring registers within the PMIC into backup RAM. In this solution, even if the microcontroller reset is caused by an external factor such as the PMIC, a corresponding exception handling mode is provided. This improves the microcontroller fault handling mechanism and makes subsequent fault analysis more efficient and convenient.

[0011] As an optional approach, determining the exception handling mode to be executed based on the exception source includes: if the exception source is the PMIC, determining the exception handling mode to be executed is the PMIC failure mode. In this solution, a corresponding exception handling mode is also provided for an abnormal reset of the microcontroller caused by an external factor such as the PMIC, thus improving the microcontroller fault handling mechanism and making subsequent fault analysis more efficient and convenient.

[0012] As an optional approach, the method further includes: transferring the information in the Backup RAM to a non-volatile memory (NVRAM), simultaneously storing the timestamp information in the NVRAM; after the transfer is complete, clearing the information in the Backup RAM; reading the information in the NVRAM; and analyzing the fault information resulting from the abnormal reset of the microcontroller. In this solution, the fault information in the Backup RAM is further stored in the NVRAM to ensure that the stored information is persistently preserved after a power outage. This facilitates reading the stored fault information when the faulty component is powered on again for fault analysis, while also reserving sufficient storage space for subsequent fault information.

[0013] As an optional approach, the first reset delay preset duration is within the range of 2ms-20ms. In this solution, the first reset delay preset duration is used as a time window to transfer the contents of the register storing fault information to non-volatile memory, providing sufficient information for subsequent fault analysis, thereby resolving the difficulty in analyzing and locating the cause of the fault.

[0014] As an optional approach, the microcontroller sets the first reset delay preset duration for the PMIC by delaying the operation of the PMIC's ROT pin. In this solution, since the pin is part of the hardware device, transmitting signals through the pin avoids software-level complexity and delays, making data transmission faster and less susceptible to external interference or network failures. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 A schematic diagram of the hardware connection between the PMIC and the microcontroller in some embodiments of the present application is shown;

[0016] Figure 2 A schematic diagram of a process for handling abnormal reset of a microcontroller provided in an embodiment of the present application is shown;

[0017] Figure 3 Context contents in the context storage area in some embodiments of the present application are shown. DETAILED DESCRIPTION

[0018] The following embodiments of the technical solution of the present application will be described in detail with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present application and are therefore only examples and are not intended to limit the scope of protection of the present application.

[0019] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application belongs; the terms used herein are only for the purpose of describing specific embodiments and are not intended to limit this application; the terms "including" and "having" and any variations thereof in the specification and claims of this application and the above-mentioned figure descriptions are intended to cover non-exclusive inclusions.

[0020] In the description of the embodiments of the present application, “multiple” means more than two, unless otherwise clearly and specifically defined.

[0021] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0022] In the description of the embodiments of this application, the term "and / or" is simply a description of the association relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent the following three situations: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " in this document generally indicates that the associated objects are in an "or" relationship.

[0023] In the description of the embodiments of the present application, the term "plurality" refers to more than two (including two).

[0024] In the description of the embodiments of this application, unless otherwise specified or limited, technical terms such as "connection" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be the internal communication between two components or the interaction between two components. For those of ordinary skill in the art, the specific meanings of the above terms in the embodiments of this application can be understood according to the specific circumstances.

[0025] Please refer to Figure 1 , Figure 1 This is a hardware connection diagram between the PMIC and the microcontroller. The PMIC (Power Management IC) is the power management chip of the microcontroller (uC). It monitors power, temperature, and the uC's operating status. If a uC anomaly is detected, it triggers a uC reset. When the PMIC's ROT (Reset Output) pin is connected to the uC's PORST (Power On Reset Input) pin, the PMIC controls the uC to perform a warm power-on reset (Warm Power On Reset, Warm POR). After a warm power-on reset, most registers within the uC are reset to their default states, and all RAM contents are cleared. If a fault triggers a warm power-on reset, all fault traces originally recorded in the uC will be lost, making subsequent analysis and fault cause location difficult.

[0026] For example, the internal Safety Management Unit (SMU) of the Infineon TC3xx series of uCs can generate over 160 different alarms (SMU Alarms). When any of these alarms causes the uC to reset abnormally, and the valid fault information is cleared, it becomes particularly difficult to locate the specific SMU Alarm that triggered the abnormal reset. For another example, the Error Recognition and Reaction (TRAP) of the Infineon TriCore series of uCs can identify and handle a wide variety of error types, including but not limited to Memory Management Unit (MMU) errors, Internal Protection Traps, Instruction Errors, Context Management Errors, System Bus and Peripheral Errors, Assertion Traps, System Calls, and Non-Maskable Interrupts. Each type of TRAP also contains multiple subclasses, making it difficult to analyze and locate the cause of the fault if the valid fault information is cleared.

[0027] The embodiment of the present application provides a method for a microcontroller to handle abnormal reset, such as Figure 2 As shown, the following steps are included:

[0028] S110: After detecting an abnormality in itself, the microcontroller determines an abnormality handling mode to be executed according to the source of the abnormality. The abnormality handling modes include: an internal action mode and an external action mode.

[0029] In step S110, the microcontroller's security mechanism can detect the occurrence of an anomaly, aiming to protect the device from various security threats and attacks. If the program falls into an infinite loop or stops responding, the watchdog timer triggers a reset operation to restore normal operation of the microcontroller.

[0030] Internal operation mode involves the coordinated operation of the microcontroller's modules and the corresponding internal execution. External operation mode involves the microcontroller sending an exception signal to an external device, which then triggers a warm power-on reset of the microcontroller based on the microcontroller's preset delayed reset configuration. In this embodiment, the external device refers to a PMIC. Internal and external operation modes operate independently of each other.

[0031] S120: If the determined exception handling mode is the internal action mode, the microcontroller executes the TRAP processing function corresponding to the exception, stores the TRAP event error information and the context information of the context storage area CSA corresponding to the exception in the Backup RAM, and then performs a soft reset. It is then determined whether the source of the exception is the alarm SMU Alarm of the software and hardware safety mechanism. If so, the information in the diagnostic register of the security management unit SMU is stored in the Backup RAM.

[0032] TRAP generally refers to a strategy that combines the operating system and hardware to handle various exceptions that occur during program execution, including hardware errors, software errors, and other unexpected situations. It plays a key role in error identification and response. Regarding error identification, the TRAP mechanism is triggered when the microcontroller executes a specific instruction or encounters a specific exception condition, such as an illegal instruction, memory protection error, or data memory misalignment. This allows the microcontroller to identify these exceptions and handle them as trap instructions. Regarding error response, when TRAP is triggered, the microcontroller enters a special processing state. Within this state, control transfers to the TRAP handler. This handler can observe and modify program state information, such as variable values ​​and the function call stack, to perform error handling, troubleshooting, or debugging. In this way, the TRAP mechanism allows the microcontroller to respond to errors and take appropriate measures to restore the system state or prevent further errors. TRAP helps ensure microcontroller stability and reliability and provides an effective error handling mechanism.

[0033] The context save area (CSA) described in this application is a specific area or space for storing context information such as program status words, address registers, and data registers so that it can be restored or switched to the previous execution state when needed. In some embodiments, the context save area is as follows: Figure 3 shown.

[0034] The TRAP event error message and the CSA context information corresponding to the exception contain key information about the abnormal reset site, which is crucial for subsequent fault analysis. Because the CSA context is fully recorded, fault analysis can be precisely located to the line code address where the fault occurred or the next line address. This provides greater sensitivity and accuracy in monitoring and diagnosing system faults, enabling earlier detection and resolution of potential issues.

[0035] A soft reset includes an application reset and a system reset. One of these types of resets is performed depending on the configuration of the uC. After a soft reset, the contents of the uC's internal registers are usually not cleared. The uC's internal mechanism can determine the source of the abnormal reset and store fault information related to the abnormal reset.

[0036] The Backup RAM in the embodiment of the present application is a partitioned RAM area that will not be cleared by the initialization code. For some special models of microcontrollers, such as the Infineon series of microcontrollers, it is also necessary to configure the UCB to not clear the Backup RAM content during a warm power-on reset. Otherwise, even if a link definition file is configured to partition a so-called RAM area that will not be cleared after a reset, it is useless.

[0037] S130: If the determined exception handling mode is the external action mode, the microcontroller sends an exception signal to the power management module PMIC. The PMIC is configured to trigger the microcontroller to perform a hot power-on reset after receiving the exception signal at an interval of a first delay reset preset time length.

[0038] In some embodiments, continue to refer to Figure 1 For fault sources that support external actions, when the uC's internal safety mechanism detects an anomaly, it will stop the output of its SMU_FSP0 pin. The SMU_FSP0 pin is connected to the PMIC's ERR (Error Signal Input) pin. When the ERR pin detects a continuous low level exceeding the time specified by the PMIC chip, and then after the first delay reset preset time, the PMIC will trigger the ROT pin to pull low. The PMIC's ROT pin is directly connected to the uC's PORST (Power On Reset Input) pin, so that the PMIC triggers the uC to generate a warm power-on reset through the ROT pin. It should be noted that the first delay reset preset time is set by configuring the PMIC register parameters through the uC software, so that the action time of the PMIC's ROT pin is delayed by the first delay reset preset time after the ERR pin detects an anomaly in the uC. Then, the ROT pin outputs a low level again, causing the uC to delay the first delay reset preset time before performing a warm power-on reset.

[0039] S140: If the determined exception handling mode is the internal action mode and the external action mode, the internal action mode and the external action mode are executed simultaneously, and the duration used to execute the internal action mode is not greater than the first delay reset preset duration.

[0040] The preset duration of the first delayed reset ensures that when both the internal action mode and the external action mode are to be executed, the internal action mode is completed before the external action mode, so that the hot power-on reset triggered in the external action mode is performed after the soft reset in the internal action mode is completed. This ensures that all key fault information is stored in the Backup RAM before being cleared by the hot power-on reset when an abnormal reset occurs.

[0041] In the above solution, after an abnormality occurs in the microcontroller, the PMIC delays the reset for a preset time interval and then triggers the microcontroller to perform a hot power-on reset. The time window of the first delay reset preset time interval is used to store the contents of all registers storing fault information in the backup RAM, providing sufficient information for subsequent fault analysis, thereby solving the problem of difficulty in analyzing and locating the cause of the fault.

[0042] In some embodiments, determining the exception handling mode to be executed according to the exception source in step S110 includes: if the exception source is SMU Alarm, and SMU Alarm can support internal actions and external actions and the external action configuration is FSP, then determining the exception handling mode to be executed as internal action mode and external action mode.

[0043] The microcontroller's SMU is a functional safety hardware module. It primarily collects alarms generated by other modules due to hardware and software functional safety mechanisms. Through user configuration, the SMU can initiate internal or external actions / responses, or choose not to initiate any action at all. As a core component of the safety architecture, the SMU provides a common interface for managing the behavior of microcontrollers with faults. The SMU plays a vital role in microcontroller safety management and fault response. The SMU_Core domain SMU is the main component of the SMU, collecting most alarm signals from hardware monitors and safety mechanisms. These alarms are defined based on safety concepts and cover a wide range of potential security threats and fault conditions. The alarm mapping component plays a key role in the SMU_Core, specifying the alarm interface and categorizing alarm signals into different alarm groups. Each alarm group defines a logical mapping from alarm signals to internal status registers. This mapping mechanism enables the SMU_Core to efficiently process and manage a large number of alarm signals. Through configuration, the SMU_Core can trigger internal actions in response to specific alarm signals or send fault notifications to external systems via the FSP. This enables the SMU_Core to respond quickly when potential security threats are detected, ensuring system safety and stability. SMU_stdby is the SMU's backup domain, primarily collecting alarms from modules that detect clock, power (undervoltage / overvoltage), and temperature faults (under / overtemperature). In addition to collecting these alarm signals, SMU_stdby also monitors the SMU_alive alarm signal. This signal indicates whether the SMU_core is operating normally or is in an active state.

[0044] In the SMU, the Fault Signaling Protocol (FSP) falls under the umbrella of functional safety. Its primary function is to notify external monitoring devices via FSP when a component in a chip or system experiences a failure. This allows the external monitoring device to perform further exception handling based on the received failure status information, such as resetting or resetting the device. When the SMU's core domain, SMU_core, detects an alarm related to hardware monitoring or safety, it can be configured to send a fault signal via FSP, triggering the external device or system to perform the appropriate action.

[0045] In the above embodiment, in addition to recording the TRAP event error information and the CSA context information corresponding to the exception, for an exception reset triggered by an SMU alarm, the fault cause must be analyzed and located in conjunction with information in the SMU diagnostic register. The SMU diagnostic register is used to store the alarm signal flag from the safety mechanism. This combined analysis facilitates fault identification. Furthermore, to ensure immediate data capture and storage, it is essential to ensure that all information in the SMU diagnostic register is fully stored before the first delay reset expires.

[0046] In the above scheme, the exception handling mode executed by the microcontroller is different depending on the source of the exception. Under the general category of the exception source, the source of the abnormal reset can be further subdivided according to the configuration of the fault source, and the effective and critical fault information can be captured and saved. This is conducive to the rapid, accurate and systematic analysis and location of the cause of the fault.

[0047] In some embodiments, determining the exception handling mode to be executed according to the exception source in step S110 includes: if the exception source is the SMU Alarm, and the SMU Alarm can support internal actions and external actions and the external action is configured as no action, then determining the exception handling mode to be executed is the internal action mode.

[0048] Since the external action of the SMU Alarm is configured as no action, no abnormal signal is sent to the external PMIC, and accordingly, the microcontroller is not triggered to perform a warm power-on reset. Therefore, there is no need to configure the first delay reset time interval to perform a warm power-on reset.

[0049] In the above scheme, the exception handling mode executed by the microcontroller is different depending on the source of the exception. Under the general category of the exception source, the source of the abnormal reset can be further subdivided according to the configuration of the fault source, and the effective and critical fault information can be captured and saved. This is conducive to the rapid, accurate and systematic analysis and location of the cause of the fault.

[0050] In some embodiments, determining the exception handling mode to be executed according to the exception source in step S110 includes: if the exception source is the SMU Alarm, and the SMU Alarm only supports external actions, determining the exception handling mode to be executed to be the external action mode.

[0051] In some embodiments, the SMU Alarm can only be configured with external actions and has no corresponding internal actions, except for the aforementioned SMU_alive alarm signal. Therefore, after a hot power-on reset, the wakeup source status register of the power module determines that the reset is caused by the SMU. Combined with the information that there is no internal action mode, the reset can be located as caused by SMU_alive.

[0052] In the above scheme, the microcontroller executes different exception handling modes depending on the source of the exception. Under the general category of exception source, the source of abnormal reset can be further subdivided according to the configuration of the fault source. The refined classification is conducive to the rapid, accurate and systematic analysis and location of the fault cause, and can achieve the effect of locating the specific type of SMU alarm that triggers the reset.

[0053] In some embodiments, in step S110, the exception handling mode to be executed is determined according to the source of the exception, including: if the source of the exception is the exception handling mechanism TRAP, and TRAP is a non-maskable interrupt NMI type that can be associated with the microcontroller's software and hardware security mechanism, then the exception handling mode to be executed is determined to be the internal action mode and the external action mode; otherwise, the exception handling mode to be executed is determined to be the internal action mode.

[0054] The NMI interrupt is a non-maskable emergency interrupt. When an NMI interrupt is triggered, the CPU responds immediately, suspending all current interrupts or tasks and executing the NMI interrupt service routine instead. Because the NMI interrupt has the highest priority, it cannot be blocked by setting the interrupt mask bit. It can be quickly triggered and save critical information when a serious error occurs in the system. Some SMU alarms within the uC are configured as NMI interrupts, such as the SMU alarm of the controller core watchdog. By executing an NMI interrupt, a TRAP is triggered to save the CSA context information, thereby obtaining more fault information, such as locating the specific location of the watchdog overflow.

[0055] For NMI traps that can be associated with the microcontroller's hardware and software safety mechanisms, the microcontroller stores the trap event error information and the CSA context information corresponding to the exception and performs a soft reset. After the first delay reset preset duration expires, a warm power-on reset is performed. For non-NMI traps, the microcontroller only needs to store the trap event error information and the CSA context information corresponding to the exception before performing a soft reset.

[0056] In the above scheme, the exception handling mode executed by the microcontroller is different depending on the source of the exception. Under the general category of the exception source, the source of the abnormal reset can be further subdivided according to the configuration of the fault source, and the effective and critical fault information can be captured and saved. This is conducive to the rapid, accurate and systematic analysis and location of the cause of the fault.

[0057] In some embodiments, the exception handling mode in step S110 also includes a PMIC failure mode. If the determined exception handling mode is the PMIC failure mode, the PMIC directly triggers the microcontroller to perform a hot power-on reset, and then stores the value of the reset-related monitoring register in the PMIC into the Backup RAM.

[0058] The PMIC fault mode handles abnormal resets caused by the PMIC. Since the relevant fault information is stored in the PMIC, there is no need to delay the reset for the preset duration. The microcontroller is directly triggered to perform a warm power-on reset. During the initialization process after the reset, the wake-up source register is first determined. If the abnormal reset is not caused by internal factors within the microcontroller, the contents of the PMIC monitoring register are read. If a flag bit is set, it can be inferred that the abnormal reset was caused by an external factor, the PMIC. The values ​​of the reset-related monitoring registers in the PMIC are stored in the backup RAM. Based on the first-level fault information such as the fault originating from the PMIC, more specific second-level fault information such as the corresponding PMIC fault content can also be obtained.

[0059] In the above solution, the abnormal reset of the microcontroller caused by external factors such as PMIC also has a corresponding exception handling mode, which improves the microcontroller fault handling mechanism and makes subsequent fault analysis more efficient and convenient.

[0060] In some embodiments, determining the exception handling mode to be executed according to the exception source in step S110 includes: if the exception source is a PMIC, determining that the exception handling mode to be executed is the PMIC failure mode.

[0061] Complete TRAP event error information and the CSA context information corresponding to the exception, as well as information about the SMU diagnostic register and the PMIC monitoring register, facilitate subsequent analysis and accurate fault cause location. In addition to obtaining first-level fault information such as TRAP, SMU, and PMIC, precise context information about the specific TRAP type, SMU alarm type, and PMIC fault content, as well as the point where the fault occurred, can also be obtained.

[0062] In some embodiments, the method further includes: transferring information in the Backup RAM to a non-volatile memory NVRAM, storing timestamp information in the NVRAM, clearing information in the Backup RAM after the transfer is complete, reading information in the NVRAM, and analyzing fault information of abnormal reset of the microcontroller.

[0063] Non-Volatile Random Access Memory (NVRAM) does not lose the stored data after the power is turned off. It is a form of static random access memory with non-volatility, which allows data to remain in a stored state even without power supply. Non-volatile memory combines the high-speed read and write performance of traditional RAM with the non-volatility of flash memory to ensure the integrity of data in the event of a sudden power outage or other unexpected situations. Non-volatile memory is configured so that its contents will not be cleared after a warm power-on reset. In some embodiments, non-volatile memory can also be permanent memory, Persistent RAM.

[0064] In the above scheme, the fault information in the Backup RAM is further stored in the NVRAM to achieve sustainable preservation of the stored content after power failure. This is conducive to reading the saved fault information when the faulty component is powered on again to analyze the cause of the fault after power failure, and at the same time, sufficient storage space is reserved for the next fault information.

[0065] In some embodiments, the first reset delay is set to a preset duration of 2ms-20ms. In some embodiments, the first reset delay is set to a preset duration of 10ms. The first reset delay is set to a preset duration that ensures that all critical fault-related information can be transferred and stored in the backup RAM within this time window while also meeting the requirement for a fast response, achieving a balance between the two.

[0066] In the above solution, the first preset time window is used to transfer the contents of the register storing the fault information into the Backup RAM, providing sufficient information for subsequent fault analysis, thereby solving the problem of difficulty in analyzing and locating the cause of the fault.

[0067] In some embodiments, the first reset delay preset duration is set by the microcontroller for the PMIC and is achieved by delaying the action time of the ROT pin of the PMIC.

[0068] By utilizing the PMIC's configurable delayed reset function and configuring the PMIC register through the uC software, the action time of the PMIC's ROT pin can be delayed. After the ERR pin detects an abnormality in the uC, the ROT pin can delay the first delayed reset preset time and then output a low level.

[0069] In the above solution, since the pin is part of the hardware device, transmitting the reset instruction through the pin can avoid the complexity and delay at the software level, making data transmission faster and less susceptible to external interference or network failure.

[0070] The foregoing description is merely an embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention shall be included within the scope of protection of the present invention.

Claims

1. A method for resetting a microcontroller during abnormal processing, the method comprising: After detecting an abnormality in itself, the microcontroller determines the abnormality handling mode to be executed according to the abnormality source. The abnormality handling mode includes: internal action mode and external action mode; If the determined exception handling mode is the internal action mode, the microcontroller executes the TRAP processing function corresponding to the exception, stores the TRAP event error information and the context information of the context storage area CSA corresponding to the exception in the backup RAM, then performs a soft reset, and then determines whether the source of the exception is the alarm SMUAlarm of the software and hardware safety mechanism. If so, the information in the diagnostic register of the security management unit SMU is stored in the backup RAM; If the determined exception handling mode is the external action mode, the microcontroller sends an exception signal to the power management module PMIC, and the PMIC is configured to trigger the microcontroller to perform a hot power-on reset after receiving the exception signal and after a first delay reset preset time period; If the determined exception handling mode is the internal action mode and the external action mode, the internal action mode and the external action mode are executed simultaneously, and the time taken to execute the internal action mode is no longer than the first delay reset preset time.

2. The method according to claim 1, characterized in that Determining the exception handling mode to be executed according to the exception source includes: If the exception source is the SMU Alarm, and the SMU Alarm can support internal actions and external actions, and the external action configuration is FSP, then the exception handling mode to be executed is determined to be the internal action mode and the external action mode.

3. The method according to claim 1, characterized in that Determining the exception handling mode to be executed according to the exception source includes: If the exception source is the SMU Alarm, and the SMU Alarm can support internal actions and external actions, and the external action is configured as no action, then the exception handling mode to be executed is determined to be the internal action mode.

4. The method according to claim 1, wherein Determining the exception handling mode to be executed according to the exception source includes: If the exception source is the SMU Alarm, and the SMU Alarm only supports external actions, the exception handling mode to be executed is determined to be the external action mode.

5. The method according to claim 1, wherein Determining the exception handling mode to be executed according to the exception source includes: If the exception source is the exception handling mechanism TRAP, and the TRAP is a non-maskable interrupt NMI type that can be associated with the software and hardware security mechanism of the microcontroller, then the exception handling mode to be executed is determined to be the internal action mode and the external action mode; otherwise, the exception handling mode to be executed is determined to be the internal action mode.

6. The method according to claim 1, characterized in that The exception handling mode also includes a PMIC failure mode. If the determined exception handling mode is the PMIC failure mode, the PMIC directly triggers the microcontroller to perform a hot power-on reset, and then stores the value of the reset-related monitoring register in the PMIC into the backup RAM.

7. The method according to claim 6, characterized in that Determining the exception handling mode to be executed according to the exception source includes: If the abnormality source is the PMIC, the abnormality handling mode to be executed is determined to be the PMIC failure mode.

8. The method according to any one of claims 1 to 7, characterized in that The method further includes: transferring the information in the backup RAM to a non-volatile memory NVRAM, storing the timestamp information in the NVRAM, clearing the information in the backup RAM after the transfer is completed, reading the information in the NVRAM, and analyzing the fault information of the abnormal reset of the microcontroller.

9. The method according to claim 1, characterized in that The preset duration of the first delayed reset is in the range of 2ms-20ms.

10. The method according to claim 1, characterized in that The first delayed reset preset duration is set by the microcontroller for the PMIC and is achieved by delaying the action time of the reset output pin of the PMIC.

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