DDR topology and PCB board

Abstract

The present invention discloses a DDR topology structure and a PCB board, wherein the DDR topology structure includes a main segment routing connecting a central node and a control signal transmitting end, a first DDR connected to a termination resistor through at least one termination routing, and a second DDR connected to the central node through multiple segment routings. Since the DDR topology structure provided by the present invention is not symmetrically arranged, such a DDR topology structure can realize the layout of an odd number of DDRs and improve signal integrity; at the same time, since the first DDR is terminated with the termination resistor, the termination resistor can reduce the signal reflection of the first DDR and improve the signal quality; and various devices in the DDR topology structure are distributed along multiple directions respectively, which can reduce the wiring area compared with the fly-by topology structure which is only arranged in a chain along one direction.

Description

Technical Field

[0001] The invention belongs to the technical field of circuit boards, and in particular relates to a DDR topology structure and a PCB board. Background Art

[0002] Electronic products are developing at a high speed, and their structures and functions are rapidly iterating. As the performance of various electronic components improves, the speed of each interface module on them is also increasing. Most electronic products are inseparable from the Double Data Rate (DDR) module. Therefore, the development of DDR has been developing from the first generation of DDR to today's mainstream DDR3, DDR4, and its derived Low Power Double Data Rate (LPDDR) series. DDR5 is also being gradually promoted.

[0003] With the iteration and upgrade of DDR and the continuous increase in speed, the topology of DDR has become more complex. When arranging DDR, it is inevitable that there will be an odd number of DDRs in the electronic components. However, the traditional symmetrical T topology cannot achieve the symmetrical layout of an odd number of DDRs, making the signal of the DDR interface incomplete; in the traditional fly-by topology, the signal reflection of the DDR close to the main segment routing is serious and the signal quality is poor. Summary of the invention

[0004] The embodiment of the present invention provides a DDR topology structure and a PCB board, which can solve the problem that the T topology structure cannot realize the symmetrical layout of an odd number of DDRs, and the problem that the signal reflection of DDR particles close to the main segment routing in the fly-by topology structure is serious and the signal quality is poor.

[0005] In a first aspect, an embodiment of the present invention provides a DDR topology structure, the DDR topology structure comprising:

[0006] Main segment routing: The main segment routing connects the central node and the control signal sending end;

[0007] A first DDR, the first DDR is connected to a termination resistor through at least one termination trace, wherein the central node is located between the first DDR and the termination resistor;

[0008] A plurality of second DDRs are connected to the central node through a plurality of segmented routing lines.

[0009] In a possible implementation manner of the first aspect, the lengths of the segmented routings are the same.

[0010] In a possible implementation manner of the first aspect, the central node is located at a pin of a first DDR, and the first DDR is connected to a termination resistor through a termination wiring section.

[0011] In a possible implementation manner of the first aspect, the first DDR is connected to the termination resistor through two sections of termination wiring, and the central node is located between the two sections of termination wiring.

[0012] In a possible implementation manner of the first aspect, the terminated routing, the main segment routing, and the segment routing are all impedance-matched routing.

[0013] In a possible implementation manner of the first aspect, a length of a termination trace connecting the termination resistor and the central node is equal to a package length of the first DDR.

[0014] Since the DDR topology structure provided by the present invention is not symmetrically arranged, such a DDR topology structure can realize the layout of an odd number of DDRs and improve signal integrity; at the same time, since the first DDR is terminated with the termination resistor, the termination resistor can reduce the signal reflection of the first DDR and improve the signal quality; and various devices in the DDR topology structure are distributed along multiple directions respectively, which can reduce the wiring area compared to the fly-by topology structure which is only arranged in a chain along one direction.

[0015] In a second aspect, an embodiment of the present invention provides a PCB board, wherein the front side and / or the back side of the PCB board comprises the DDR topology structure as described in the first aspect.

[0016] In a possible implementation manner of the second aspect, the DDR topology structure described in the first aspect is laid flat on the front side or the back side of the PCB board.

[0017] In a possible implementation manner of the second aspect, the second DDR in the DDR topology structure described in the first aspect is symmetrically arranged on the front and back sides of the PCB board.

[0018] It can be understood that the beneficial effects of the second aspect mentioned above can be found in the relevant description of the first aspect mentioned above, and will not be repeated here.

[0019] Compared with the prior art, the embodiments of the present invention have the following beneficial effects: since the DDR topology structure provided by the present invention is not symmetrically arranged, such a DDR topology structure can realize the layout of an odd number of DDRs and improve signal integrity; at the same time, since the first DDR is terminated with the termination resistor, the termination resistor can reduce the signal reflection of the first DDR and improve the signal quality; and, various devices in the DDR topology structure are distributed along multiple directions respectively, which can reduce the wiring area compared with the fly-by topology structure which is only arranged in a chain along one direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 A schematic diagram of a DDR topology structure provided by an embodiment of the present invention;

[0021] Figure 2 A schematic diagram of another DDR topology structure provided by an embodiment of the present invention;

[0022] Figure 3 A schematic diagram of the structure of a PCB board provided in an embodiment of the present invention;

[0023] Figure 4 A schematic diagram of the structure of another PCB board provided by an embodiment of the present invention;

[0024] Figure 5 A schematic diagram for comparing transient signals of different DDR topologies provided by an embodiment of the present invention;

[0025] Figure 6 A schematic diagram comparing eye diagrams of different DDR topology structures provided by an embodiment of the present invention.

[0026] Reference numerals:

[0027] 110: first DDR; 120: second DDR; : Termination resistor; L: Main segment routing :The first end is connected to the wiring; :The second end is connected to the wiring; to : Segmented routing; Drv: control signal sending end; A: central node. DETAILED DESCRIPTION

[0028] In the following description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present invention. However, it should be clear to those skilled in the art that the present invention may be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present invention.

[0029] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of described features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or combinations thereof.

[0030] It should also be understood that the term "and / or" used in the present description and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.

[0031] As used in the present specification and the appended claims, the term "if" may be interpreted as "when" or "upon" or "in response to determining" or "in response to detecting", depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" may be interpreted as meaning "upon determination" or "in response to determining" or "upon detection of [described condition or event]" or "in response to detecting [described condition or event]", depending on the context.

[0032] In addition, in the description of the present specification and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

[0033] References to "one embodiment" or "some embodiments" etc. described in the present specification mean that one or more embodiments of the present invention include specific features, structures or characteristics described in conjunction with the embodiment. Therefore, the statements "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0034] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0035] Example 1

[0036] Figure 1 The diagram shows a schematic diagram of a DDR topology structure provided by an embodiment of the present invention. As an example but not a limitation, the DDR topology structure may include a first DDR 110, a plurality of second DDRs 120, a termination resistor , Main section routing L, first terminal routing , multiple segment routing to .

[0037] For example, see Figure 1 , the main segment line L can connect the control signal sending end Drv and the central node A; the first DDR110 (ie ) can be terminated by at least one section (only one section is shown here) (i.e., the first termination line ) and terminating resistor Connected; terminating resistor The other end can be connected to the power supply connected, multiple second DDRs (eg to ) can be routed through multiple segments. to Connected to the central node A. The central node A can be located between the first DDR110 and the termination resistor between.

[0038] Since the DDR topology structure provided by the present invention is not symmetrically arranged, such a DDR topology structure can realize the layout of an odd number of DDRs; at the same time, since the first DDR is terminated with the termination resistor, the termination resistor can reduce the signal reflection of the first DDR and improve the signal quality; and various devices in the DDR topology structure are distributed along multiple directions respectively, which can reduce the wiring area compared to the fly-by topology structure which is only arranged in a chain along one direction.

[0039] In one possible implementation, see Figure 1 , when the first DDR110 is only connected through a first termination line and terminating resistors When connected, the central node A may be located at a pin of the first DDR 110 .

[0040] In one example, connect the center node A to the termination resistor The first terminal of the The length of can be equal to the package length of the first DDR110, so that a better termination effect can be achieved.

[0041] In a possible implementation, the length of each segmented routing line may be the same, so as to ensure that the signal reflection of each second DDR120 is the same and the signal quality is balanced.

[0042] In one possible implementation, the first termination trace , main segment routing L and each segment routing to Both can be impedance-matched traces.

[0043] Example 2

[0044] Figure 2 FIG. 1 is a schematic diagram of a DDR topology structure provided by an embodiment of the present invention. Similarly, the DDR topology structure may include a first DDR 110, a plurality of second DDRs 120, a termination resistor , main segment routing L, multiple segment routing to Differently, the DDR topology structure provided in Example 2 may include two sections of termination traces, which are respectively the first termination trace and the second termination trace .

[0045] For example, see Figure 2 The main segment line L can connect the control signal sending end Drv and the central node A; the first DDR110 can be connected through multiple segments (only two segments are shown here) of the termination line (i.e., the first termination line , the second end is connected to the wiring ) and terminating resistor Multiple second DDRs are connected through multiple segmented routings to Connected to the central node A. The central node A can be located between the first DDR110 and the termination resistor between.

[0046] In one possible implementation, see Figure 2 , when the first DDR110 is routed through two terminations, that is, the first termination , the second end is connected to the line , and the terminating resistor When connected, the central node A can be located at the first terminal line and the second termination trace between.

[0047] In one example, connect the center node A to the termination resistor The first terminal of the The length of can be equal to the package length of the first DDR110, so that a better termination effect can be achieved.

[0048] In a possible implementation, the length of each segmented routing line may be the same, so as to ensure that the signal reflection of each second DDR120 is the same and the signal quality is balanced.

[0049] In one possible implementation, the first termination trace , the second end is connected to the line , main segment routing L and each segment routing to Both can be impedance-matched traces.

[0050] Since the DDR topology structure provided by the present invention is not symmetrically arranged, such a DDR topology structure can realize the layout of an odd number of DDRs; at the same time, since the first DDR is terminated with the termination resistor, the termination resistor can reduce the signal reflection of the first DDR and improve the signal quality; and various devices in the DDR topology structure are distributed along multiple directions respectively, which can reduce the wiring area compared to the fly-by topology structure which is only arranged in a chain along one direction.

[0051] Example 3

[0052] On the basis of Example 1 and Example 2, Figure 3 The structure diagram of a PCB board provided by an embodiment of the present invention is shown. As an example but not a limitation, the front or back side of the PCB board may include a DDR topology structure provided by the above-mentioned embodiment 1 or embodiment 2.

[0053] For example, taking the DDR topology in the front and embodiment 1 as an example, see Figure 3 , the DDR topology can be laid flat on the front side of the PCB board.

[0054] Example 4

[0055] On the basis of Example 1 and Example 2, Figure 4 The structure diagram of another PCB board provided by an embodiment of the present invention is shown. As an example but not a limitation, the PCB board may include a DDR topology structure provided by the above-mentioned embodiment 1 or embodiment 2.

[0056] For example, the second DDR 120 in the DDR topology structure provided in the above embodiment 1 or embodiment 2 may be symmetrically distributed on the front and back sides of the PCB board, which can further reduce the wiring area of ​​the DDR topology structure.

[0057] For example, see Figure 4 Taking the DDR topology structure in Example 1 as an example, the second DDR120 includes , , , , , ,in , , Set on the front of the PCB board, , , Set on the back of the PCB board.

[0058] In order to better illustrate the beneficial effects of the present invention, the following simulation experiments were carried out:

[0059] Figure 5 Shown is a schematic diagram of transient signal comparison of different DDR topology structures in an embodiment of the present invention.

[0060] For example, by comparing the transient signals generated by each DDR in the DDR topology structure provided in the above embodiment 1 with the transient signals generated by the DDR at the corresponding position in the fly-by topology structure, it is possible to obtain Figure 5 .

[0061] in, Figure 5(a) is a comparison of transient signals of the first DDR (i.e., the DDR close to the main segment routing) in different DDR topologies. Figure 5 (b)- Figure 5 (e) in the figure are the second DDR in different DDR topologies (i.e. , , , The solid line represents the transient signal of DDR in the DDR topology structure provided by the present invention, the dotted line represents the transient signal of DDR in the fly-by topology structure, and Y1 represents the amplitude of the signal.

[0062] See also Figure 5 (a)- Figure 5 As can be seen from (e) in the figure, the signal quality of the first DDR and the second DDR in the DDR topology structure provided by the present invention is almost the same, while the DDR signal reflection problem close to the main segment routing in the fly-by topology structure is serious; therefore, the DDR topology structure provided by the present invention can reduce the signal reflection of the first DDR and improve the signal quality by terminating the first DDR with a termination resistor.

[0063] Figure 6 Provided is a comparison diagram of eye diagrams of different DDR topologies.

[0064] Figure 6 (a) is the eye diagram of the DDR topology structure provided by the present invention, Figure 6 (b) in the figure is the eye diagram of the fly-by topology structure, and Y1 represents the amplitude of the signal.

[0065] See also Figure 6 It can be seen that the eye diagram effect of the DDR topology structure provided by the present invention is better, which indicates that the signal integrity quality of the DDR topology structure provided by the present invention is higher.

[0066] Since the DDR topology structure provided by the present invention is not symmetrically arranged, such a DDR topology structure can realize the layout of an odd number of DDRs and improve signal integrity; at the same time, since the first DDR is terminated with the termination resistor, the termination resistor can reduce the signal reflection of the first DDR and improve the signal quality; and various devices in the DDR topology structure are distributed along multiple directions respectively, which can reduce the wiring area compared to the fly-by topology structure which is only arranged in a chain along one direction.

[0067] In the description of the present invention, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0068] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification.

[0069] Although the present invention is described herein in conjunction with various embodiments, in the process of implementing the claimed invention, those skilled in the art may understand and implement other variations of the disclosed embodiments by viewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "one" or "an" does not exclude multiple situations. A single processor or other unit may implement several functions listed in the claims. Certain measures are recorded in different dependent claims, but this does not mean that these measures cannot be combined to produce good results.

[0070] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, any modifications made without departing from the concept of the present invention should be deemed to belong to the protection scope of the present invention.

Claims

1. A DDR topology structure, characterized in that: include: A main section wiring, wherein the main section wiring connects the central node and the control signal sending end; A first DDR, wherein the first DDR is connected to a termination resistor through at least one termination trace, wherein the central node is located between the first DDR and the termination resistor; A plurality of second DDRs are connected to the central node through a plurality of segmented routings to realize a layout of an odd number of DDRs, wherein the segmented routings have the same length, and the termination routings, the main segment routings and the segmented routings are all impedance-matched routings.

2. The DDR topology structure according to claim 1, characterized in that: The central node is located at a pin of the first DDR, and the first DDR is connected to the termination resistor via a termination wiring.

3. The DDR topology structure according to claim 1, characterized in that: The first DDR is connected to the termination resistor via two sections of termination wiring, and the central node is located between the two sections of termination wiring.

4. The DDR topology structure according to claim 1, characterized in that: The length of the termination trace connecting the termination resistor and the central node is equal to the package length of the first DDR.

5. A PCB board, characterized in that: The front side and / or the back side of the PCB board comprises the DDR topology structure as claimed in any one of claims 1 to 4.

6. The PCB board according to claim 5, characterized in that: The DDR topology structure is laid flat on the front side or the back side of the PCB board.

7. The PCB board according to claim 5, characterized in that: The second DDR in the DDR topology structure is symmetrically arranged on the front and back sides of the PCB board.

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