Chip packaging structure with integrated cooling and manufacturing method thereof

Abstract

The present application relates to a cooling-integrated chip packaging structure and a manufacturing method thereof. The method for manufacturing a cooling-integrated chip packaging structure includes: forming a plurality of microchannels recessed from the second side of the substrate into the substrate according to the chip mounting position on the first side of the substrate; forming a flow channel layer, the flow channel layer having a plurality of parallel flow channels; forming a manifold layer stacked on the flow channel layer, wherein the first group of manifolds and the second group of manifolds are staggered among the multiple manifolds of the manifold layer, and each group of manifolds is connected to different flow channels; fixing the flow channel layer to the substrate so that the flow channels are connected to the microchannels, and the extension direction of the flow channels intersects with the extension direction of the microchannels; forming a distribution layer, the distribution layer having an inlet groove and an outlet groove; and installing the distribution layer on the side of the manifold layer facing away from the flow channel layer, so that the inlet groove is connected to the manifold of the first group, and the outlet groove is connected to the manifold of the second group. This method can form microchannels in a targeted manner to achieve more balanced heat dissipation at the chip mounting position.

Description

Technical Field

[0001] The present disclosure relates to the field of heat dissipation of semiconductor devices, and in particular to a cooling-integrated chip packaging structure and a manufacturing method thereof. Background Art

[0002] Power electronic devices are mainly used in power electronic systems, including power converters, inverters, DC-DC converters, etc., for the conversion and regulation of electric energy. Power electronic devices play an important role in energy conversion and energy conservation. Power electronic devices generate heat during operation, and high temperature will affect the operation of power electronic devices, so it is necessary to dissipate heat from power electronic devices. Moreover, many fields require efficient heat dissipation, such as computers, automobiles, electronic equipment, etc.

[0003] Conventional power electronic devices include a channel heat sink, a substrate and a chip. The chip is mounted on the substrate, and the channel heat sink is also mounted on the substrate. The channel heat sink is usually provided with fins or S-shaped flow channels, and the medium flowing therein is used to dissipate heat from the chip.

[0004] However, current flow channel heat sinks have poor heat dissipation capabilities. Summary of the invention

[0005] Based on this, it is necessary to address the problem of poor heat dissipation capacity of the channel heat sink and provide a cooling integrated chip packaging structure and a manufacturing method thereof.

[0006] On the one hand, an embodiment of the present disclosure provides a method for manufacturing a cooling-integrated chip packaging structure, the method comprising: forming a plurality of microchannels recessed from a second side of a substrate into the substrate according to a chip mounting position on a first side of a substrate; forming a flow channel layer having a plurality of parallel flow channels; forming a manifold layer stacked on the flow channel layer, wherein the manifold layer has a plurality of manifolds, a first group of manifolds and a second group of manifolds are alternately arranged, and each group of manifolds is connected to different flow channels; fixing the flow channel layer to the substrate so that the flow channels are connected to the microchannels, and an extension direction of the flow channels intersects with an extension direction of the microchannels; forming a distribution layer having an inlet groove and an outlet groove; and installing the distribution layer on a side of the manifold layer facing away from the flow channel layer so that the inlet groove is connected to the manifolds of the first group, and the outlet groove is connected to the manifolds of the second group.

[0007] The method for manufacturing a cooling-integrated chip packaging structure provided in the embodiments of the present disclosure can form microchannels in a targeted manner, and form flow channels and manifold layers that relatively evenly control the cooling medium in the microchannels, thereby achieving relatively even heat dissipation at the chip mounting position. The method can flexibly manufacture a cooling-integrated chip packaging structure with a personalized heat dissipation design for different chips.

[0008] In some embodiments, a method for manufacturing a cooling-integrated chip packaging structure, which further includes: mounting a chip on a chip mounting position of a substrate; packaging the chip, substrate, flow channel layer, and manifold layer; forming an inlet pipe connected to an inlet groove, and forming an outlet pipe connected to an outlet groove; wherein the step of installing a distribution layer includes: sealing the distribution layer and the manifold layer with a sealing material.

[0009] Such an arrangement can form a packaging structure for protecting the chip. This method achieves efficient heat dissipation through the integrated design of chip arrangement and heat dissipation structure; helps prevent leakage of the distribution layer and the manifold layer; and alleviates the impact of moisture or external vibration on the chip.

[0010] In some embodiments, the chip is connected to the substrate through a silver sintering process; the chip is electrically connected to the substrate through aluminum wire bonding and ultrasonic welding; the packaging step is plastic packaging; the step of installing the distribution layer includes: crimping the distribution layer to the manifold layer through bolts.

[0011] Such arrangement helps to avoid chip fragmentation caused by multiple pressure sintering. In addition, while facilitating overall assembly, it ensures the reliable use of the electrical structure.

[0012] In some embodiments, microchannels are formed by laser etching; the manifold flow channel plate is polished, pickled, and ultrasonically cleaned, the manifold flow channel plate is an integrated copper-containing structure, and the manifold flow channel plate includes a manifold layer and a flow channel layer; the flow channel layer is fixed to the substrate by silver sintering, copper sintering, diffusion welding or reflow welding process.

[0013] Such a setting can ensure a good sealing state and help dissipate heat.

[0014] On the other hand, an embodiment of the present disclosure provides a cooling-integrated chip packaging structure, which includes: a substrate, a first side of the substrate having a chip mounting position, and the substrate having a plurality of microchannels corresponding to the chip mounting position and recessed into the substrate from a second side; a flow channel layer, stacked on the substrate, the flow channel layer having a plurality of parallel flow channels, the flow channels are connected to the microchannels, and an extension direction of the flow channels intersects with an extension direction of the microchannels; a manifold layer, stacked on the flow channel layer, the manifold layer having a plurality of manifolds, a first group of manifolds and a second group of manifolds are alternately arranged, and each group of manifolds is connected to different flow channels; and a distribution layer, stacked on the manifold layer, the distribution layer having an inlet slot and an outlet slot, the inlet slot being connected to the manifold of the first group, and the outlet slot being connected to the manifold of the second group.

[0015] The cooling-integrated chip packaging structure provided in the embodiments of the present disclosure has high heat dissipation efficiency and a compact structure. The cooling structure designed in the cooling-integrated chip packaging structure is directly integrated into the substrate, which can effectively dissipate the heat generated by the high-power density chip; it has low overall thermal resistance, high performance, and good reliability. The cooling-integrated chip packaging structure can be configured with multiple chips, and the cooling medium can flow evenly between the multiple chips, thereby ensuring that each chip can obtain sufficient and balanced cooling, which helps to reduce the junction temperature difference between the chips, thereby ensuring the uniform distribution of current. The cooling-integrated chip packaging structure can well meet the heat dissipation requirements of high-power chips and facilitates the optimization design of the chip and the cooling structure. The cooling structure is configured as a multi-layer manifold shunt structure, which can effectively shorten the process in the microchannel, improve the uniformity of fluid distribution between each microchannel, and reduce the overall flow pressure drop.

[0016] In some embodiments, the cooling integrated chip packaging structure also includes a chip, an inlet pipe and an outlet pipe, the chip is located at the chip mounting position, the inlet pipe is connected to the inlet groove, and the outlet pipe is connected to the outlet groove; the chip, substrate, flow channel layer and manifold layer constitute a packaging structure; the distribution layer is sealingly connected to the manifold layer.

[0017] Such an arrangement can effectively protect the chip, facilitate the delivery of the cooling medium and avoid leakage at the distribution layer.

[0018] In some embodiments, the inlet pipe and the outlet pipe are spaced apart from each other along the arrangement direction of the manifolds of the first group.

[0019] With this arrangement, the inlet pipe and the outlet pipe are relatively separated, which helps to plan the layout of the inlet slot and the outlet slot and ensure the effective transportation of the cooling medium.

[0020] In some embodiments, the manifold layer and the flow channel layer form an integrated copper-containing manifold flow channel plate; the parallelism deviation of the two sides of the manifold flow channel plate along the stacking direction is less than 20 μm; and the aspect ratio of the microchannel is 7 to 10.

[0021] With such arrangement, the manifold channel plate is assembled precisely and reliably, and has a good heat dissipation effect; the channel layer can effectively cooperate with the microchannel to achieve efficient heat dissipation of the chip at the chip mounting position.

[0022] In some embodiments, the plurality of manifolds are arranged along the arrangement direction of the plurality of flow channels, and the manifolds of the second group are located on both sides of the manifolds of the first group along the extension direction of the flow channels.

[0023] In this arrangement, liquid enters from the manifold located in the middle and exits from the manifolds on both sides. Liquid entry through the middle helps the low-temperature cooling medium to flow evenly to each microchannel; it also helps the cooling medium to be quickly discharged after heating.

[0024] In some embodiments, the extension direction of the flow channel is perpendicular to the extension direction of the microchannel; the plurality of microchannels are divided into two regions along the extension direction of the flow channel relative to the manifold of the first group, and the two regions correspond to the manifolds of the second group respectively; each region corresponds to at least one chip mounting position.

[0025] With such an arrangement, at least two chips can be configured, and each chip can be cooled sufficiently and evenly. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 A schematic flowchart of a method for manufacturing a cooling-integrated chip packaging structure according to an embodiment of the present disclosure;

[0027] Figure 2 A schematic exploded view of a cooling-integrated chip packaging structure according to an embodiment of the present disclosure;

[0028] Figure 3 A schematic exploded view of a cooling-integrated chip packaging structure from another perspective according to an embodiment of the present disclosure;

[0029] Figure 4 It is a schematic structural diagram of a substrate in an embodiment of the present disclosure;

[0030] Figure 5 is a schematic bottom view of a substrate in an embodiment of the present disclosure;

[0031] Figure 6 for Figure 5 The enlarged view of point A in the middle;

[0032] Figure 7 is a schematic top view of a manifold channel plate in an embodiment of the present disclosure;

[0033] Figure 8 for Figure 7 Schematic diagram of the cross section at AA in the middle;

[0034] Fig. 9 for Figure 7 Schematic diagram of the cross section at BB;

[0035] Fig.10 for Figure 7 Schematic diagram of the cross section at CC;

[0036] Fig.11 is a schematic bottom view of a manifold channel plate in an embodiment of the present disclosure;

[0037] Fig.12 is a schematic top view of a flow distribution structure in an embodiment of the present disclosure;

[0038] Fig.13 is a schematic bottom view of the flow distribution structure in an embodiment of the present disclosure;

[0039] Fig.14 It is a schematic structural diagram of a cooling-integrated chip packaging structure according to an embodiment of the present disclosure;

[0040] Fig.15 It is a schematic diagram of the structure of a chip module of a comparative example of the present disclosure;

[0041] Fig.16 It is a schematic diagram of the structure of the fin plate in the comparative example of the present disclosure;

[0042] Fig.17 This is a comparison chart of the cooling performance of the cooling-integrated chip packaging structure of the embodiment of the present disclosure and the chip module of the comparative example of the present disclosure.

[0043] Description of reference numerals: 100, chip packaging structure; 1, substrate; 2, insulating plate; 201, microchannel; 210, first cooling zone; 220, second cooling zone; 3, circuit pattern; 310, chip mounting position; 4, chip;

[0044] 5. Manifold channel plate; 6. Channel layer; 610. Channel; 611. First channel; 612. Second channel; 7. Manifold layer; 710. Manifold; 711. First manifold; 712. Second manifold; 8. Flow distribution structure; 9. Flow distribution layer; 901. Inlet slot; 902. Outlet slot; 10. Inlet pipe; 101. Inlet; 11. Outlet pipe; 111. Outlet;

[0045] 200, chip module; 300, fin plate; 400, comparison substrate; 500, comparison chip; 600, fin rib. DETAILED DESCRIPTION

[0046] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present disclosure more obvious and understandable, the specific implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. In the following description, many specific details are set forth to facilitate a full understanding of the embodiments of the present disclosure. However, the embodiments of the present disclosure can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without violating the connotation of the embodiments of the present disclosure, so the embodiments of the present disclosure are not limited by the specific examples of the embodiments disclosed below.

[0047] In the description of the embodiments of the present disclosure, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "perpendicular", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the embodiments of the present disclosure and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the embodiments of the present disclosure.

[0048] In the embodiments of the present disclosure, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0049] In addition, the terms "first", "second", "third", etc. are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. Exemplarily, the first flow channel may also be referred to as the second flow channel, and the second flow channel may also be referred to as the first flow channel. In the description of the embodiments of the present disclosure, the meaning of "multiple" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0050] In the embodiments of the present disclosure, unless otherwise clearly specified and limited, the terms "connected", "connected", etc. should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integrated connection; it can be a flexible connection, or a rigid connection along at least one direction; it can be a mechanical connection or an electrical connection; it can be directly connected, or indirectly connected through an intermediate medium, or directly connected with the presence of an intermediate medium, or it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly limited. The terms "installed", "set", "fixed", etc. can be broadly understood as connection. For ordinary technicians in this field, the specific meanings of the above terms in the embodiments of the present disclosure can be understood according to specific circumstances.

[0051] As used herein, the terms "layer" and "region" refer to a portion of a material that includes an area with a certain thickness. A layer can extend horizontally, vertically and / or along a tapered surface. A layer can be an area of ​​a uniform or non-uniform continuous structure, and its thickness perpendicular to the extension direction may not be greater than the thickness of the continuous structure. A layer can include multiple layers, which can be stacked layers or multiple layers extending discretely. The shapes of various regions and layers in the drawings and their relative sizes and positional relationships are only exemplary, and may actually deviate due to manufacturing tolerances or technical limitations, and the design can be adjusted according to actual needs.

[0052] Some flow channel heat sinks include a heat sink with an S-shaped flow channel and heat dissipation fins. The heat sink is directly attached to the copper-clad ceramic substrate on which the chip is provided. This will cause the liquid temperature to gradually rise along the flow direction; when there are multiple chips, the junction temperature difference between the chips is large, which leads to uneven current distribution between the chips. Furthermore, this uneven current distribution may cause thermal differences between chips, thereby affecting the performance and reliability of the system. In particular, high-power chips have high heat dissipation requirements, and this uneven current distribution problem caused by traditional heat dissipation methods is particularly serious in high-power chips.

[0053] refer to Figure 1 , Figure 1 The process of the method for manufacturing a cooling-integrated chip packaging structure in an embodiment of the present disclosure is shown. Figure 2 As shown, Figure 2 The schematic exploded view of the cooling integrated chip package structure of the embodiment of the present disclosure is shown in FIG. The cooling integrated chip package structure 100 can be obtained by the method 1000 of the present disclosure.

[0054] In some embodiments, the method 1000 for manufacturing a cooling-integrated chip package structure includes the following steps.

[0055] Step S110, forming a plurality of microchannels. Figures 3 to 6 Specifically, a plurality of microchannels 201 are formed to be recessed from the second side of the substrate 1 into the substrate 1 according to the chip mounting position 310 on the first side of the substrate 1. Figure 2 The first side and the second side of the substrate 1 are opposite to each other along the Z-axis direction.

[0056] Step S121, forming a flow channel layer. Specifically, a flow channel layer 6 is formed on another plate different from the substrate 1. The flow channel layer 6 has a plurality of parallel flow channels 610. Figure 2 As shown, the flow channel 610 may extend along the Y-axis direction; and a plurality of flow channels 610 may be arranged along the X-axis direction.

[0057] Step S122, forming a manifold layer stacked on the flow channel layer. Figures 7 to 11Among the multiple manifolds 710 of the manifold layer 7, the first group of manifolds 710 and the second group of manifolds 710 are arranged alternately, and each group of manifolds 710 is connected to different flow channels 610. The manifolds 710 in each group can be arranged along the X-axis direction, and the first group and the second group are arranged along the Y-axis direction.

[0058] Step S130, fix the flow channel layer to the substrate. Specifically, the flow channel layer 6 is disposed on the second side of the substrate 1, and the flow channel layer 6 is fixed to the substrate 1, so that the flow channel 610 is connected to the microchannel 201. Figure 1 and Figure 2 , the extension direction of the flow channel 610 intersects with the extension direction of the microchannel 201. Exemplarily, each flow channel 610 passes through all the microchannels 201, and each microchannel 201 is passed by all the flow channels 610.

[0059] In some embodiments, the method 1000 further includes step S140 of forming a packaging structure. The packaging structure (not shown) includes a substrate 1 , a flow channel layer 6 , and a manifold layer 7 .

[0060] Step S151 , forming a flow distribution layer. The flow distribution layer 9 has an inlet groove 901 and an outlet groove 902 .

[0061] Step S160, install the distribution layer on the side of the manifold layer facing away from the flow channel layer. Specifically, install the distribution layer 9 to the manifold layer 7, and the distribution layer 9 is located on the side of the manifold layer 7 facing away from the flow channel layer 6. After installation, the inlet slot 901 is connected to the manifold 710 of the first group, and the outlet slot 902 is connected to the manifold 702 of the second group.

[0062] The method 1000 for manufacturing a cooling-integrated chip packaging structure provided in the embodiment of the present disclosure forms a microchannel 201 on the substrate 1, which can directly and specifically dissipate heat from the chip mounting position 310 according to needs while ensuring the normal use of the substrate 1. Through layered manufacturing and installation, a cooling structure of a cross-laminated three-dimensional manifold channel can be simply and conveniently realized, thereby achieving uniform and effective heat dissipation of the chip 4.

[0063] Exemplarily, the substrate 1 is a copper-clad ceramic circuit board. Figures 4 to 6 , the substrate 1 includes an insulating plate 2 and a circuit pattern 3. The material of the insulating plate 2 may include aluminum nitride or other ceramic materials. The circuit pattern 3 is fixed to one side of the insulating plate 2 along the Z-axis direction; the material of the circuit pattern 3 includes copper or other metals. The circuit pattern 3 defines chip mounting positions 310, for example, six chip mounting positions 310. Along the X-axis direction, three chip mounting positions 310 are arranged in a row; along the Y-axis direction, two rows of chip mounting positions 310 are arranged.

[0064] In some embodiments, the microchannel 201 is formed by laser etching. Exemplarily, the aspect ratio of the microchannel 201 is 7 to 10, for example, the ratio of the depth to the width is 8:1. The microchannel 201 can extend along the X-axis direction through three chip mounting positions 310. A continuous whole microchannel 201 is relatively easy to process and ensures heat dissipation performance. The laser etching process can ensure processing accuracy, and the microchannel 201 is sufficiently spaced from the circuit pattern 3 to achieve electrical insulation.

[0065] Exemplarily, the method 1000 includes step S120, forming a manifold flow channel plate 5. Step S120 includes step S121 and step S122. Exemplarily, the manifold flow channel plate 5 is an integrated structure, for example, a copper frame structure with a hollow pattern. The manifold flow channel plate 5 includes a manifold layer 7 and a flow channel layer 6; the manifold layer 7 and the flow channel layer 6 constitute an integrated copper-containing manifold flow channel plate 5.

[0066] refer to Figures 7 to 11 , the flow channels 610 are arranged along the X-axis direction, and the plurality of flow channels 610 include a first flow channel 611 and a second flow channel 612 arranged at intervals. The plurality of manifolds 710 include a first manifold 711 and a second manifold 712. The manifold 710 corresponds to and communicates with the flow channels 610 along the Z-axis direction. The first manifold 711 corresponds to and communicates with the first flow channel 611, and the second manifold 712 corresponds to and communicates with the second flow channel 612.

[0067] For example, in the manifold channel plate 5, the first manifold 711 and the second manifold 712 are respectively connected to different channels 610. The first manifold 711 may be located in the middle of the first channel 611 along the Y-axis direction. The two second manifolds 712 may correspond to the same second channel 612, and the two second manifolds 712 may be located away from the middle and close to the two ends of the second channel 612 along the Y-axis direction.

[0068] Exemplarily, the first manifold 711 and the second manifold 712 are spaced apart from each other along the Y-axis direction.

[0069] In some embodiments, the manifold flow channel plate 5 is polished, pickled, or ultrasonically cleaned. Polishing the manifold flow channel plate 5 can remove the oxide layer on the surface of the manifold flow channel plate 5; it is also beneficial to improve the surface smoothness, thereby enabling the manifold flow channel plate 5 to be used for tight fitting. Pickling and ultrasonic cleaning can be performed multiple times to reliably remove surface impurities. Exemplarily, ultrasonic cleaning can be deionized water ultrasonic cleaning or alcohol ultrasonic cleaning.

[0070] For example, the parallelism deviation of the two side surfaces of the manifold channel plate 5 along the stacking direction, ie, the Z-axis direction, is less than 20 μm, for example, 10 μm or 15 μm, which is conducive to the connection and sealing of the manifold channel plate 5 with other plates.

[0071] Optionally, the flow channel layer 60 is fixed to the substrate 1 by silver sintering, copper sintering, diffusion welding or reflow welding. The flow channel layer 60 is reliably connected to the substrate 1. For example, by using the silver sintering process, nano silver paste can be firstly applied to the manifold layer 7, and then the flow channel layer 60 and the substrate 1 are sintered into one by using a pressure silver sintering device. Specifically, the flow channel layer 6 is sintered to the insulating plate 2.

[0072] refer to Figure 1 The method 1000 for manufacturing a cooling integrated chip package structure further includes step S140, forming a package structure. Step S140 includes: step S141, mounting a chip on a chip mounting position of a substrate; and step S142, packaging the chip, substrate, flow channel layer and manifold layer.

[0073] In step S141 , a plurality of chips 4 may be mounted to corresponding chip mounting positions 310 . Exemplarily, the chips 4 are connected to the substrate 1 by a silver sintering process. The chips 4 may be connected to the circuit pattern 3 .

[0074] Step S140 also includes: electrically connecting the chip 4 to the substrate 1 by aluminum wire bonding or ultrasonic welding. Specifically, the terminals of the chip 4 are electrically connected to the corresponding terminals of the circuit pattern 3. In other embodiments, the chip 4 can be electrically connected to the substrate 1 by copper wire bonding or reflow soldering.

[0075] Exemplarily, the encapsulation step is plastic encapsulation, which can reliably encapsulate the circuit structure. The obtained encapsulation structure can be installed together with the current distribution structure 8. The encapsulation structure can protect the chip 4 and the electrical and thermal interconnection structure, and alleviate the influence of moisture and external vibration.

[0076] For example, reference Figure 1 The method 1000 for manufacturing a cooling integrated chip package structure further includes step S150, forming a package structure. Step S150 may include step S151 and step S152, forming an inlet pipe and forming an outlet pipe. Specifically, forming an inlet pipe 10 connected to the inlet groove 901, and forming an outlet pipe 11 connected to the outlet groove 902.

[0077] refer to Figure 3 , Fig.12 and Fig.13 The inlet pipe 10 has an inlet 101; the outlet pipe 11 has an outlet 111. The inlet 101 may correspond to the inlet groove 901 along the Z-axis direction and be connected to the inlet groove 901. The outlet 111 may correspond to the outlet groove 902 along the Z-axis direction and be connected to the outlet groove 902.

[0078] Combination Figure 2 , Figure 3 and Fig.11The first group of manifolds 710, i.e., a plurality of first manifolds 711, are arranged along the X-axis direction, and the inlet pipes 10 and the outlet pipes 11 are arranged at intervals along the X-axis direction. Fig.12 As shown, the inlet 101 is located at the left end of the inlet slot 901, and the outlet 111 is located at the right end of the outlet slot 902. The inlet slot 901 can be linear, and the outlet slot 902 can be U-shaped. This helps to ensure that the cooling medium is fed in evenly and stably, and discharged quickly.

[0079] Exemplarily, the step of installing the distribution layer 9 includes: sealing the distribution layer 9 and the manifold layer 7 with a sealing material. A silicone pad may be provided between the distribution layer 9 and the manifold layer 7. Exemplarily, the step of installing the distribution layer 9 includes: crimping the distribution layer 9 to the manifold layer 7 by bolts (not shown). The distribution structure 8 and the manifold flow channel plate 5 respectively have bolt holes (not shown), which may be threaded holes, for example. The distribution structure 8 can be simply and reliably sealed and crimped to the manifold flow channel plate 5.

[0080] refer to Figure 2 , Figure 3 and Fig.14 The present disclosure provides a chip packaging structure 100, which is a cooling integrated chip packaging structure. In some embodiments, the cooling integrated chip packaging structure 100 includes: a substrate 1, a flow channel layer 6, a manifold layer 7, and a distribution layer 9.

[0081] refer to Fig.14 The upper side of the substrate 1 along the Z-axis direction is the first side, and the lower side is the second side. The first side of the substrate 1 has a chip mounting position 310. The chip mounting position 310 is used to set the chip 4. The substrate 1 has a plurality of microchannels 201 corresponding to the chip mounting position 310 and recessed from the second side of the substrate 1. The microchannels 201 extend along the X-axis direction; and the plurality of microchannels 201 are arranged along the Y-axis direction.

[0082] The flow channel layer 6 is stacked on the substrate 1; the flow channel layer 6 is located on the lower side of the substrate 1, i.e., the second side. The flow channel layer 6 has a plurality of parallel flow channels 610. The flow channels 610 are connected to the microchannel 201. The extension direction of the flow channel 610 intersects with the extension direction of the microchannel 201, for example, the flow channel 610 extends along the Y-axis direction and then perpendicular to the extension direction of the microchannel 201.

[0083] The manifold layer 7 is stacked on the flow channel layer 6 and is located at the lower side of the flow channel layer, that is, the side facing away from the substrate 1. Among the multiple manifolds 710 of the manifold layer 7, the first group of manifolds 710 and the second group of manifolds 710 are alternately arranged, and each group of manifolds 710 is connected to different flow channels 610. Fig.14In the second group of manifolds 710, two second manifolds 712 are connected to the same second flow channel 612, and the second flow channel 612 is not directly connected to the first manifold 711 along the Z-axis direction, but the second flow channel 612 can be connected to other flow channels 610 through the microchannel 201. The manifold layer 7 and the flow channel layer 6 are an integrated structure, in which the channel for conveying the cooling medium is cleverly constructed, and the manifold flow channel plate 5 has a compact structure.

[0084] The distribution layer 9 is stacked on the manifold layer 7; the distribution layer 9 is located below the manifold layer 7. The distribution layer 9 has an inlet groove 901 and an outlet groove 902. The inlet groove 901 is connected to the first group of manifolds 710, and the outlet groove 902 is connected to the second group of manifolds 710. The inlet groove 901 and the outlet groove 902 can extend along the X-axis direction respectively.

[0085] The inlet slot 901 is connected to the first flow channel 611 through the first manifold 711, the first flow channel 611 is connected to the second flow channel 612 through the microchannel 201, and the second flow channel 612 is connected to the outlet slot 902 through the second manifold 712. During operation, the heat of the chip 4 is continuously absorbed through the microchannel 201, and then the heat is taken away through the manifold layer 7. Since the microchannel 201 has a large surface area, it can effectively absorb the heat released by the chip 4 to make the chip 4 run stably and at a constant temperature; the multi-layer manifold diversion structure can effectively shorten the process in the channel structure, and improve the uniformity of fluid distribution between each microchannel 201, and reduce the overall flow pressure drop.

[0086] The chip packaging structure provided in the embodiments of the present disclosure is a cooling integrated structure, which improves the traditional heat dissipation structure and improves the heat dissipation efficiency and stability. The embodiments of the present disclosure achieve improvements in the design and preparation process of module packaging and heat dissipation structure through innovations such as the collaborative design of the "microchannel-chip" arrangement, fluid guidance of the multi-layer shunt structure, and packaging of the overall module, thereby overcoming the heat dissipation problems of traditional power modules, including low heat dissipation efficiency of traditional cooling structures, large junction temperature differences between chips, and poor flexibility of heat sink structures. The application of the innovative points in the embodiments of the present disclosure has significantly improved the heat dissipation efficiency of the chip packaging structure of the power chip, and greatly reduced the junction current thermal resistance; the chip packaging structure of the embodiments of the present disclosure has good flexibility and can be applied to power modules of different packaging types.

[0087] In an exemplary embodiment, the cooling integrated chip package structure 100 further includes a chip 4, an inlet pipe 10 and an outlet pipe 11. The chip 4 is located at the chip mounting position 310, the inlet pipe 10 is connected to the inlet groove 901, and the outlet pipe 11 is connected to the outlet groove 902.

[0088] The chip packaging structure 100 provided in the embodiment of the present disclosure can make the cooling medium, such as cooling water, flow evenly between multiple chips 4, and can keep the water temperature stable. The heat dissipation method achieved by adopting a special channel design can make the water flow along different paths, thereby ensuring that each chip 4 can obtain the same cooling water temperature and flow, reducing the junction temperature difference between the chips 4, and ensuring the uniform distribution of current. In addition, since the chip packaging structure 100 can better meet the heat dissipation requirements of high-power chips, this uniform current distribution problem is also effectively solved in high-power chips. The chip packaging structure 100 provided in the embodiment of the present disclosure has higher performance and reliability, and can better meet the needs of various application scenarios.

[0089] The chip 4, substrate 1, channel layer 6 and manifold layer 7 constitute a packaging structure. Fig.14 The packaging material is not shown. The distribution layer 9 is sealedly connected to the manifold layer 7.

[0090] The chip packaging structure provided by the embodiment of the present disclosure adopts an advanced integrated design of chip arrangement and heat dissipation structure, which organically combines the chip and the heat dissipation structure, thereby giving full play to the advantages of both and achieving more efficient heat dissipation. This integrated design can optimize factors such as the distance, angle, and size between the chip and the heat sink to meet the heat dissipation requirements of different chips, and can achieve a more flexible and accurate heat dissipation design, thereby improving the efficiency and performance of the entire chip packaging structure.

[0091] Exemplarily, the plurality of manifolds 710 are arranged along the arrangement direction of the plurality of channels 610, and the second group of manifolds 710 are located on both sides of the first group of manifolds 710 along the extension direction of the channels 610. The plurality of second manifolds 712 are located on both sides of the first manifold 711 along the Y axis direction.

[0092] In some embodiments, the extension direction of the flow channel 610 is perpendicular to the extension direction of the microchannel 201. The plurality of microchannels 201 are divided into two regions along the extension direction of the flow channel 610 relative to the first group of manifolds 710, and the two regions correspond to the second group of manifolds 710 respectively. Figure 3 In the two regions, the first cooling region 210 corresponds to a row of second manifolds 712 on the right along the Y-axis direction, and the second cooling region 220 corresponds to a row of second manifolds 712 on the left. Each region corresponds to at least one chip mounting position 310, for example, the first cooling region 210 corresponds to three chip mounting positions 310, and the second cooling region 220 corresponds to three chip mounting positions 310.

[0093] refer to Fig.15 and Fig.16 , Fig.15The chip module of the comparative example of the present disclosure is shown. Exemplarily, the chip module 200 comprises a fin plate 300, a comparative substrate 400 and a comparative chip 500 stacked in sequence, the fin plate 300 has fin ribs 600, and the cooling medium can be bent and diverted under the action of the fin ribs 600 to dissipate heat for the comparative chip 500.

[0094] refer to Fig.17 , the data set of the chip module 200 of the comparative example is Pin-fin; in the chip package structure 100 of the embodiment of the present disclosure, the model and layout of the chip 4 are the same as the model and layout of the comparative chip 500. One embodiment of the present disclosure sets the width of the microchannel 201 to 50 microns, and its data set is 50μm-MMC. Another embodiment sets the width of the microchannel 201 to 80 microns, and its data set is 80μm-MMC.

[0095] At ambient temperature T in =294.15K, flow rate m=12g / s, cooling medium is water, the comparative example and two embodiments are measured at different power densities q die (Unit: W / cm 2 ) under the temperature rise ΔT j,ave (Unit: K).

[0096] like Fig.17 As shown, as the power density of the test increases, the temperature rise of the comparative chip module 200 increases rapidly, while the temperature rise of the two embodiments of the present disclosure increases slowly. The chip packaging structure 100 of the embodiment of the present disclosure can effectively dissipate heat for the chip 4.

[0097] The disclosed embodiment adopts an innovative heat dissipation structure, which greatly improves the heat dissipation efficiency. Compared with the traditional pin-fin type or S-type shunt channel, this new heat dissipation structure can directly embed the cooling structure into, for example, a copper-clad ceramic substrate, which can more effectively dissipate the heat generated by high-power density chips, reduce the thermal resistance of the overall structure, and thus improve the performance and reliability of the overall structure.

[0098] The technical features of the embodiments disclosed above can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0099] In the embodiments disclosed above, unless otherwise clearly specified and limited, the execution order of each step is not limited, for example, it can be executed in parallel, or it can be executed successively in different orders. The sub-steps of each step can also be executed alternately. The above-mentioned various forms of processes can be used, and steps can be reordered, added or deleted, as long as the desired results of the technical solution provided in the embodiment of the present disclosure can be achieved, and this document does not limit it here.

[0100] The embodiments disclosed above only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of patent protection of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the scope of patent protection required by the present application. Therefore, the scope of patent protection of the present application shall be subject to the attached claims.

Claims

1. A method for manufacturing a cooling-integrated chip package structure, characterized in that: include: According to the chip mounting position on the first side of the substrate, a plurality of microchannels are formed which are recessed into the substrate from the second side of the substrate; forming a flow channel layer, wherein the flow channel layer has a plurality of parallel flow channels; forming a manifold layer stacked on the flow channel layer, wherein the manifold layer has a plurality of manifolds, a first group of manifolds and a second group of manifolds are alternately arranged, and each group of manifolds is connected to a different flow channel; Fixing the flow channel layer to the substrate so that the flow channel is connected to the microchannel and the extension direction of the flow channel intersects with the extension direction of the microchannel; forming a flow distribution layer, the flow distribution layer having an inlet slot and an outlet slot; as well as The distribution layer is installed on a side of the manifold layer facing away from the flow channel layer, so that the inlet groove is connected to the manifold of the first group, and the outlet groove is connected to the manifold of the second group.

2. The method for manufacturing a cooling-integrated chip package structure according to claim 1, wherein: It also includes: mounting a chip on the chip mounting position of the substrate; Encapsulating the chip, the substrate, the flow channel layer and the manifold layer; forming an inlet pipe connected to the inlet groove, and forming an outlet pipe connected to the outlet groove; Wherein, the step of installing the distribution layer includes: sealing the distribution layer and the manifold layer by using a sealing material.

3. The method for manufacturing a cooling-integrated chip packaging structure according to claim 2, wherein: Connecting the chip to the substrate through a silver sintering process; The chip is electrically connected to the substrate by aluminum wire bonding and ultrasonic welding; The packaging step is plastic packaging; The step of installing the distribution layer includes: crimping the distribution layer to the manifold layer by bolts.

4. The method for manufacturing a cooling-integrated chip package structure according to claim 1, wherein: forming the microchannel by laser etching; Grinding, pickling, and ultrasonic cleaning the manifold channel plate, wherein the manifold channel plate is an integrated copper-containing structure, and the manifold channel plate includes the manifold layer and the channel layer; The flow channel layer is fixed to the substrate through silver sintering, copper sintering, diffusion welding or reflow welding process.

5. A cooling integrated chip packaging structure, characterized in that: include: A substrate, wherein a first side of the substrate has a chip mounting position, and the substrate has a plurality of microchannels corresponding to the chip mounting position and recessed into the substrate from a second side; A flow channel layer, stacked on the substrate, the flow channel layer having a plurality of parallel flow channels, the flow channels are connected to the microchannels, and the extension direction of the flow channels intersects with the extension direction of the microchannels; A manifold layer, stacked on the flow channel layer, wherein the manifolds of the manifold layer are arranged in a staggered manner with the manifolds of the first group and the manifolds of the second group, and each group of manifolds is connected to different flow channels; as well as The flow distribution layer is stacked on the manifold layer, and has an inlet groove and an outlet groove. The inlet groove is communicated with the manifold of the first group, and the outlet groove is communicated with the manifold of the second group.

6. The cooling integrated chip packaging structure according to claim 5, wherein: It also includes a chip, an inlet pipe and an outlet pipe, wherein the chip is located at the chip mounting position, the inlet pipe is connected to the inlet slot, and the outlet pipe is connected to the outlet slot; The chip, the substrate, the flow channel layer and the manifold layer constitute a packaging structure; The flow distribution layer is sealingly connected to the manifold layer.

7. The cooling integrated chip packaging structure according to claim 6, wherein: The inlet pipe and the outlet pipe are arranged at intervals along the arrangement direction of the manifolds of the first group.

8. The cooling integrated chip packaging structure according to claim 5, wherein: The manifold layer and the flow channel layer form an integrated copper-containing manifold flow channel plate; The parallelism deviation of the two sides of the manifold channel plate along the stacking direction is less than 20 μm; The aspect ratio of the microchannel is 7 to 10.

9. The cooling integrated chip packaging structure according to claim 5, wherein: The plurality of manifolds are arranged along an arrangement direction of the plurality of flow channels, and the manifolds of the second group are located on both sides of the manifolds of the first group along an extension direction of the flow channels.

10. The cooling integrated chip packaging structure according to claim 9, wherein: The extension direction of the flow channel is perpendicular to the extension direction of the microchannel; The plurality of microchannels are divided into two regions along the extension direction of the flow channel relative to the manifold of the first group, and the two regions correspond to the manifold of the second group respectively; each of the regions corresponds to at least one chip mounting position.

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