Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a method for forming the same, wherein the method comprises: providing a substrate, the substrate comprising an insulating layer and a substrate layer on the insulating layer; forming a gate on a part of the substrate surface; forming a main sidewall on the gate sidewall; forming a first epitaxial layer on the substrate surface after forming the main sidewall; implanting first doping ions into the surface of the first epitaxial layer with the main sidewall and the gate as masks, and forming source-drain doping regions in the first epitaxial layer and the substrate, which is conducive to reducing the series resistance of the source and the drain, improving the carrier rate, reducing the junction capacitance and enhancing the current density, which is conducive to suppressing the short channel effect and improving the performance of the MOSFET device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] Metal-oxide-semiconductor field-effect transistors (MOSFETs) are among the most widely used device structures. A MOSFET is a four-terminal device with a source, gate, drain, and body terminal. Its function is mainly determined by the flow of charge carriers in the channel width; charge carriers enter the channel through the source and leave through the drain.

[0003] With the continuous development of semiconductor technology, semiconductor technology nodes are constantly shrinking and transistors are becoming smaller. Parasitic capacitance, short-channel effect and device subthreshold current have become the main factors hindering the further development of semiconductor technology. In process technology, increasing the doping concentration at the channel position can control the short-channel effect, but highly doped channels will introduce Coulomb scattering problem, which will reduce carrier mobility and reduce device speed.

[0004] In summary, the performance of MOSFET devices produced by existing technologies urgently needs to be improved. Summary of the Invention

[0005] The technical problem solved by this invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of the formed semiconductor structure.

[0006] To address the aforementioned technical problems, the present invention provides a semiconductor structure comprising: a substrate, the substrate including an insulating layer and a substrate layer located on the insulating layer; a gate located on a portion of the substrate surface; a main sidewall located on the gate sidewall and the substrate surface; a first epitaxial layer located on both sides of the gate and the main sidewall on the substrate; and source / drain doped regions located on both sides of the gate and the main sidewall and within the substrate.

[0007] Optionally, it further includes: an offset sidewall located between the gate sidewall and the main sidewall; a lightly doped region located within the substrates on both sides of the offset sidewall and the gate, and surrounding the source / drain doped region; the source / drain doped region and the lightly doped region have the same conductivity type.

[0008] Optionally, the lightly doped region portion further extends to the bottom of the offset sidewall; the lightly doped region portion further extends to the bottom of the gate.

[0009] Optionally, it further includes: a second epitaxial layer located on the substrate surface on both sides of the gate and the offset sidewall, wherein the main sidewall and the first epitaxial layer are located on the surface of the second epitaxial layer; the lightly doped region is also located within the second epitaxial layer on both sides of the offset sidewall and the gate; the source / drain doped region is also located within the second epitaxial layer on both sides of the gate and the main sidewall.

[0010] Optionally, the source / drain doped regions also extend to the bottom of the main sidewall.

[0011] Optionally, it further includes: a halo region located within the substrates on both sides of the offset sidewall and the gate, and surrounding the source / drain doped region; the depth of the halo region is greater than the depth of the lightly doped region; the source / drain doped region and the halo region have different conductivity types.

[0012] Optionally, the depth of the source / drain doped region is greater than the depth of the lightly doped region.

[0013] Optionally, the insulating layer is made of silicon oxide; the substrate layer is made of silicon.

[0014] Optionally, the bottom of the source / drain doped region does not contact the surface of the insulating layer.

[0015] Optionally, the bottom of the source / drain doped region is in contact with the surface of the insulating layer.

[0016] Optionally, it may also include: a contact layer located on the surface of a portion of the source / drain doped region; the material of the contact layer includes metal silicide.

[0017] Accordingly, the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including an insulating layer and a substrate layer located on the insulating layer; forming a gate on a portion of the substrate surface; forming a main sidewall on the gate sidewall; forming a first epitaxial layer on the substrate surface after forming the main sidewall; and implanting a first dopant ion into the surface of the first epitaxial layer using the main sidewall and the gate as a mask, thereby forming source / drain doped regions in the first epitaxial layer and the substrate.

[0018] Optionally, after forming the gate and before forming the main sidewall, the process includes: forming an offset sidewall on the gate sidewall; using the offset sidewall and the gate as a mask, implanting second doped ions into the substrate surface to form an initial lightly doped region in the substrate, wherein the source / drain doped region and the initial lightly doped region have the same conductivity type; and using the initial lightly doped region outside the source / drain doped region as the lightly doped region.

[0019] Optionally, the initial lightly doped region further extends to the bottom of the offset sidewall; the method for forming the initial lightly doped region further includes: a second annealing process after the second doped ion implantation process, so that the second doped ions diffuse to the bottom of the offset sidewall.

[0020] Optionally, the initial lightly doped region further extends to the bottom of the gate; the method for forming the initial lightly doped region further includes a second annealing process after the second doped ion implantation process, so that the second doped ions diffuse to the bottom of the gate.

[0021] Optionally, after forming the offset sidewall and before forming the initial lightly doped region, a second epitaxial layer is also formed on the substrate surfaces on both sides of the gate and the offset sidewall; the method for forming the initial lightly doped region further includes: implanting the second dopant ions into the second epitaxial layer; after forming the initial lightly doped region, forming the main sidewall, which is also located on the surface of the second epitaxial layer; forming the first epitaxial layer on the surface of the second epitaxial layer; and the first dopant ions are further implanted into the second epitaxial layer to form the source / drain doped region.

[0022] Optionally, the source / drain doped region further extends to the bottom of the main sidewall; the method for forming the source / drain doped region further includes: a first annealing process after the first doped ion implantation process, so that the first doped ions diffuse to the bottom of the main sidewall.

[0023] Optionally, after forming the offset sidewall and before forming the main sidewall, the method further includes: using the offset sidewall and the gate as a mask, implanting a third doped ion into the second epitaxial layer, wherein the implantation depth of the third doped ion is greater than the implantation depth of the second doped ion, to form an initial halo region; and using the initial halo region outside the source / drain doped region as the halo region.

[0024] Optionally, the initial halo region is formed after the initial lightly doped region is formed.

[0025] Optionally, the formation process of the second epitaxial layer includes a selective epitaxial growth process.

[0026] Optionally, the method for forming the gate includes: forming a gate material layer on the surface of the substrate; forming a hard mask layer on a portion of the surface of the gate material layer; and etching the gate material layer using the hard mask layer as a mask to form the gate.

[0027] Optionally, the formation process of the first epitaxial layer includes a selective epitaxial growth process.

[0028] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0029] In the semiconductor structure formation method provided by the present invention, the substrate includes an insulating layer and a substrate layer located on the insulating layer. A first epitaxial layer is formed on the surface of the substrate, and a first dopant ion is implanted onto the surface of the first epitaxial layer. Source and drain doped regions are formed in the first epitaxial layer and the substrate. The insulating layer restricts the channel depth, and the source and drain doped regions protrude from the channel structure, which is beneficial for reducing the source and drain series resistance, increasing the carrier velocity, reducing the junction capacitance, and enhancing the current density. It is also beneficial for suppressing the short-channel effect and improving the performance of the MOSFET device.

[0030] Furthermore, the second epitaxial layer is used to precisely position the implantation accuracy of the second doped ions, which helps to improve the stability of the formed device.

[0031] Furthermore, the lightly doped region helps to suppress the hot carrier injection (HCI) effect.

[0032] Furthermore, the halo region is used to reduce the occurrence of source-drain punch-through anomalies.

[0033] In the semiconductor structure provided by the present invention, the substrate includes an insulating layer and a substrate layer located on the insulating layer. The insulating layer limits the channel depth, and the source and drain doped regions protrude from the channel structure, which helps to reduce the source and drain series resistance, increase the carrier velocity, reduce the junction capacitance and enhance the current density, and help to suppress the short-channel effect and improve the performance of MOSFET devices.

[0034] Furthermore, the lightly doped region helps to suppress the hot carrier injection (HCI) effect.

[0035] Furthermore, the halo region is used to reduce the occurrence of source-drain punch-through anomalies. Attached Figure Description

[0036] Figures 1 to 7 This is a schematic diagram of the steps in the method for forming a semiconductor structure according to an embodiment of the present invention. Detailed Implementation

[0037] It should be noted that the terms "surface" and "on" in this specification are used to describe the relative spatial position and are not limited to whether there is direct contact.

[0038] As described in the background section, the performance of MOSFET devices produced by existing technologies urgently needs to be improved.

[0039] To address the aforementioned problems, the present invention provides a semiconductor structure and its formation method, wherein the substrate includes an insulating layer and a substrate layer located on the insulating layer, a first epitaxial layer is formed on the substrate surface, a first dopant ion is implanted onto the surface of the first epitaxial layer, and source / drain doped regions are formed in the first epitaxial layer and the substrate. The insulating layer restricts the channel depth, and the source / drain doped regions protrude from the channel structure, which is beneficial for reducing the source and drain series resistance, increasing the carrier velocity, reducing the junction capacitance, and enhancing the current density, thereby suppressing the short-channel effect and improving the performance of the MOSFET device.

[0040] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0041] Figures 1 to 7 This is a schematic diagram of the steps in the method for forming a semiconductor structure according to an embodiment of the present invention.

[0042] Please refer to Figure 1 A substrate 100 is provided, the substrate 100 including an insulating layer 101 and a substrate layer 102 located on the insulating layer 101.

[0043] The insulating layer 101 is used to limit the channel depth of the formed MOS device.

[0044] In this embodiment, the thickness of the substrate layer 102 is 17 nm. In other embodiments, the thickness of the substrate layer can be adjusted according to actual needs. It should be noted that the thickness mentioned herein refers to the dimension perpendicular to the surface of the substrate 100.

[0045] In this embodiment, the insulating layer 101 is made of silicon oxide.

[0046] In this embodiment, the substrate layer 102 is made of silicon. In other embodiments, the substrate layer may also be made of materials such as germanium-silicon or germanium.

[0047] Please refer to Figure 2 A gate 103 is formed on a portion of the surface of the substrate 100.

[0048] In this embodiment, the method for forming the gate 103 includes: forming a gate material layer (not shown in the figure) on the surface of the substrate 100; forming a hard mask layer 104 on a portion of the surface of the gate material layer; using the hard mask layer 104 as a mask, etching the gate material layer until the surface of the substrate 100 is exposed, thereby forming the gate 103.

[0049] In this embodiment, the gate 103 is made of polycrystalline silicon.

[0050] In this embodiment, a gate oxide layer 105 is further provided between the substrate 100 and the gate 103. The method for forming the gate oxide layer 105 includes: forming a gate oxide material layer (not shown in the figure) on the surface of the substrate 100 before forming the gate material layer; and forming the gate oxide layer 105 with the gate oxide material layer.

[0051] Subsequently, a main sidewall is formed on the sidewall of the gate 103. In this embodiment, after the gate 103 is formed and before the main sidewall is formed, please refer to... Figures 3 to 4 .

[0052] Please refer to Figure 3 An offset sidewall 106 is formed on the sidewall of the gate 103.

[0053] The offset sidewall 106 is made of a dielectric material, which includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon carbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon carbide nitride. In this embodiment, the offset sidewall 106 is made of aluminum oxide (Al2O3).

[0054] In this embodiment, the method for forming the offset sidewall 106 includes: forming a first dielectric material layer (not shown in the figure) on the surface of the gate 103 and the substrate 100; etching back the first dielectric material layer until the surface of the substrate 100 and the top surface of the gate 103 are exposed.

[0055] In this embodiment, the formation process of the first dielectric material layer includes atomic layer deposition (ALD). ALD is beneficial for improving the thickness uniformity of the formed material film.

[0056] Please refer to Figure 4 Using the offset sidewall 106 and the gate 103 as masks, second doped ions are implanted into the surface of the substrate 100 to form an initial lightly doped region 107 in the substrate 100.

[0057] The source / drain doped regions and the initial lightly doped region 107 have the same conductivity type. In this embodiment, for forming an NMOS device, both the source / drain doped regions and the initial lightly doped region 107 have an N-type conductivity type. In another embodiment, for forming a PMOS device, both the source / drain doped regions and the initial lightly doped region have a P-type conductivity type.

[0058] In this embodiment, after the offset sidewall 106 is formed and before the initial lightly doped region 107 is formed, a second epitaxial layer 108 is also formed on the surface of the substrate 100 on both sides of the gate 103 and the offset sidewall 106.

[0059] In this embodiment, the formation process of the second epitaxial layer 108 includes a selective epitaxial growth process.

[0060] In this embodiment, the method for forming the initial lightly doped region 107 further includes: implanting the second dopant ions into the second epitaxial layer 108. The second epitaxial layer 108 is used to precisely position the implantation accuracy of the second dopant ions, which helps to improve the stability of the formed device.

[0061] In this embodiment, the initial lightly doped region 107 extends to the bottom of the gate 103; the method for forming the initial lightly doped region 107 further includes a second annealing process after the second doped ion implantation process, so that the second doped ions diffuse to the bottom of the gate 103.

[0062] In another embodiment, the initial lightly doped region extends to the bottom of the offset sidewall; the method of forming the initial lightly doped region further includes a second annealing process following the second doped ion implantation process, so that the second doped ions diffuse to the bottom of the offset sidewall.

[0063] In this embodiment, after the offset sidewall 106 is formed and before the main sidewall is formed, a third doped ion is implanted into the second epitaxial layer 108 using the offset sidewall 106 and the gate 103 as a mask. The implantation depth of the third doped ion is greater than the implantation depth of the second doped ion, forming an initial halo region (not shown in the figure).

[0064] The source / drain doped regions and the initial halo region have different conductivity types. In this embodiment, the initial halo region has a P-type conductivity. In another embodiment, the initial halo region has an N-type conductivity. In yet another embodiment, the initial halo region may not be formed.

[0065] In this embodiment, after the initial lightly doped region 107 is formed, the initial halo region (not shown in the figure) is formed.

[0066] Please refer to Figure 5 A main sidewall 109 is formed on the sidewall of the gate 103.

[0067] Specifically, after the initial lightly doped region 107 is formed, the main sidewall 109 is formed, and the main sidewall 109 is also located on the surface of the second epitaxial layer 108.

[0068] The material of the main sidewall 109 includes a dielectric material, which includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon carbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon carbide nitride. In this embodiment, the material of the main sidewall 109 is silicon nitride.

[0069] Please refer to Figure 6 After the main sidewall 109 is formed, a first epitaxial layer 110 is formed on the surface of the substrate 100.

[0070] Specifically, the first epitaxial layer 110 is formed on the surface of the second epitaxial layer 108.

[0071] Please refer to Figure 7 Using the main sidewall 109 and the gate 103 as masks, first doped ions are implanted into the surface of the first epitaxial layer 110 to form source / drain doped regions 111 in the first epitaxial layer 110 and the substrate 100.

[0072] Thus, the insulating layer 101 restricts the channel depth, and the source and drain doped regions 111 protrude from the channel structure, which helps to reduce the source and drain series resistance, increase the carrier velocity, reduce the junction capacitance and enhance the current density, which helps to suppress the short-channel effect and improve the performance of the MOSFET device.

[0073] In this embodiment, the bottom of the source / drain doped region 111 is in contact with the surface of the insulating layer 101. This contact between the bottom of the source / drain doped region 111 and the surface of the insulating layer 101 forms a fully depleted (FD) structure. In another embodiment, the bottom of the source / drain doped region may not be in contact with the surface of the insulating layer, forming a partially depleted (PD) structure.

[0074] In this embodiment, the formation process of the first epitaxial layer 110 includes a selective epitaxial growth process.

[0075] In this embodiment, the first doped ions are also implanted into the second epitaxial layer 108 to form the source / drain doped region 111.

[0076] In this embodiment, the initial lightly doped region 107 (e.g., outside the source / drain doped region 111) is also used. Figure 6 The region shown is the lightly doped region 112. The lightly doped region 112 is beneficial for suppressing the hot carrier injection (HCI) effect.

[0077] In this embodiment, the initial halo region outside the source / drain doped region 111 is also considered as the halo region (not shown in the figure). The halo region is used to reduce the occurrence of source / drain punch-through anomalies.

[0078] In this embodiment, the source / drain doped region 111 further extends to the bottom of the main sidewall 109; the method for forming the source / drain doped region 111 further includes: a first annealing process after the first doped ion implantation process, so that the first doped ions diffuse to the bottom of the main sidewall 109.

[0079] In this embodiment, after forming the source / drain doped region 111, a contact layer 113 is also formed on a portion of the surface of the source / drain doped region 111.

[0080] In this embodiment, the contact layer 113 is made of metal silicide. The contact layer 113 is used to reduce the contact resistance between the subsequently formed conductive layer and the source / drain doped region 111.

[0081] Accordingly, this invention also provides a semiconductor structure formed using the above method. Please refer to [link / reference needed]. Figure 7 The substrate 100 includes an insulating layer 101 and a substrate layer 102 located on the insulating layer 101; a gate 103 located on a portion of the surface of the substrate 100; a main sidewall 109 located on the sidewall of the gate 103 and the surface of the substrate 100; a first epitaxial layer 110 located on both sides of the gate 103 and the main sidewall 109 on the substrate 100; and source / drain doped regions 111 located on both sides of the gate 103 and the main sidewall 109 and within the substrate 100.

[0082] Thus, the insulating layer 101 restricts the channel depth, and the source and drain doped regions 111 protrude from the channel structure, which helps to reduce the source and drain series resistance, increase the carrier velocity, reduce the junction capacitance and enhance the current density, which helps to suppress the short-channel effect and improve the performance of the MOSFET device.

[0083] In this embodiment, the semiconductor structure further includes: an offset sidewall 106 located between the sidewall of the gate 103 and the main sidewall 109; and a lightly doped region 112 located within the substrates 100 on both sides of the offset sidewall 106 and the gate 103, surrounding the source / drain doped region 111; the source / drain doped region 111 and the lightly doped region 112 have the same conductivity type. The lightly doped region 112 is beneficial for suppressing hot carrier injection (HCI).

[0084] In this embodiment, the lightly doped region 112 extends to the bottom of the offset sidewall 106; the lightly doped region 112 also extends to the bottom of the gate 103.

[0085] In this embodiment, the semiconductor structure further includes: a second epitaxial layer 108 located on the surface of the substrate 100 on both sides of the gate 103 and the offset sidewall 106, the main sidewall 109 and the first epitaxial layer 110 located on the surface of the second epitaxial layer 108; the lightly doped region 112 is also located within the second epitaxial layer 108 on both sides of the offset sidewall 106 and the gate 103; the source / drain doped region 111 is also located within the second epitaxial layer 108 on both sides of the gate 103 and the main sidewall 109.

[0086] In this embodiment, the source / drain doped region 111 also extends to the bottom of the main sidewall 109.

[0087] In this embodiment, the semiconductor structure further includes: a halo region (not shown in the figure) located within the substrate 100 on both sides of the offset sidewall 106 and the gate 103, and surrounding the source / drain doped region 111; the depth of the halo region is greater than the depth of the lightly doped region 112; the source / drain doped region 111 and the halo region have different conductivity types. The halo region is used to reduce the occurrence of source / drain punch-through anomalies.

[0088] In this embodiment, the depth of the source / drain doped region 111 is greater than the depth of the lightly doped region 112.

[0089] In this embodiment, the insulating layer 101 is made of silicon oxide; the substrate layer 102 is made of silicon.

[0090] In this embodiment, the bottom of the source / drain doped region 111 is in contact with the surface of the insulating layer 101. In another embodiment, the bottom of the source / drain doped region is not in contact with the surface of the insulating layer.

[0091] In this embodiment, the semiconductor structure further includes a contact layer 113 located on a portion of the surface of the source / drain doped region 111; the material of the contact layer 113 includes metal silicide. The contact layer 113 is used to reduce the contact resistance between the conductive layer (not shown) and the source / drain doped region 111.

[0092] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: The substrate includes an insulating layer and a substrate layer located on the insulating layer; A gate located on a portion of the substrate surface; Main sidewalls located on the gate sidewall and substrate surface; A first epitaxial layer located on the substrates on both sides of the gate and the main sidewall; The source / drain doped regions are located in the first epitaxial layer and the substrate on both sides of the gate and the main sidewall; An offset sidewall located between the gate sidewall and the main sidewall; A lightly doped region located within the substrates on both sides of the offset sidewall and the gate, and surrounding the source / drain doped region, wherein the source / drain doped region and the lightly doped region have the same conductivity type; A second epitaxial layer is located on the substrate surfaces on both sides of the gate and the offset sidewall, wherein the main sidewall and the first epitaxial layer are located on the surface of the second epitaxial layer; The lightly doped region is also located within the second epitaxial layer on both sides of the offset sidewall and the gate; The source and drain doped regions are also located within the second epitaxial layer on both sides of the gate and the main sidewall.

2. The semiconductor structure as described in claim 1, characterized in that, The lightly doped region also extends to the bottom of the offset sidewall; the lightly doped region also extends to the bottom of the gate.

3. The semiconductor structure as described in claim 1, characterized in that, The source / drain doped regions also extend to the bottom of the main sidewall.

4. The semiconductor structure as described in claim 1, characterized in that, It also includes: a halo region located within the substrates on both sides of the offset sidewall and the gate, and surrounding the source / drain doped region; the depth of the halo region is greater than the depth of the lightly doped region; the source / drain doped region and the halo region have different conductivity types.

5. The semiconductor structure as described in claim 1, characterized in that, The depth of the source / drain doped region is greater than the depth of the lightly doped region.

6. The semiconductor structure as described in claim 1, characterized in that, The insulating layer is made of silicon oxide; the substrate layer is made of silicon.

7. The semiconductor structure as described in claim 1, characterized in that, The bottom of the source / drain doped region is not in contact with the surface of the insulating layer.

8. The semiconductor structure as described in claim 1, characterized in that, The bottom of the source / drain doped region is in contact with the surface of the insulating layer.

9. The semiconductor structure as described in claim 1, characterized in that, Also includes: A contact layer located on the surface of a portion of the source / drain doped region; The material of the contact layer includes metal silicides.

10. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate comprising an insulating layer and a substrate layer located on the insulating layer; A gate is formed on a portion of the substrate surface; An offset sidewall is formed on the gate sidewall; A second epitaxial layer is formed on the substrate surfaces on both sides of the gate and the offset sidewall; Using the offset sidewall and the gate as a mask, second doped ions are implanted into the surface of the substrate to form an initial lightly doped region in the substrate and the second epitaxial layer; After the initial lightly doped region is formed, a main sidewall is formed on the gate sidewall, and the main sidewall is also located on the surface of the second epitaxial layer. After the main sidewall is formed, a first epitaxial layer is formed on the surface of the second epitaxial layer; Using the main sidewall and the gate as masks, first doped ions are implanted into the surface of the first epitaxial layer to form source / drain doped regions in the first epitaxial layer, the second epitaxial layer and the substrate. The initial lightly doped region outside the source / drain doped region is the lightly doped region, and the source / drain doped region and the initial lightly doped region have the same conductivity type.

11. The method for forming a semiconductor structure as described in claim 10, characterized in that, The initial lightly doped region also extends to the bottom of the offset sidewall; the method for forming the initial lightly doped region further includes: a second annealing process after the second doped ion implantation process, so that the second doped ions diffuse to the bottom of the offset sidewall.

12. The method for forming a semiconductor structure as described in claim 10, characterized in that, The initial lightly doped region also extends to the bottom of the gate; the method for forming the initial lightly doped region further includes: a second annealing process after the second doped ion implantation process, so that the second doped ions diffuse to the bottom of the gate.

13. The method for forming a semiconductor structure as described in claim 10, characterized in that, The source / drain doped region also extends to the bottom of the main sidewall; the method for forming the source / drain doped region further includes: a first annealing process after the first doped ion implantation process, so that the first doped ions diffuse to the bottom of the main sidewall.

14. The method for forming a semiconductor structure as described in claim 10, characterized in that, After forming the offset sidewall and before forming the main sidewall, the method further includes: using the offset sidewall and the gate as a mask, implanting a third doped ion into the second epitaxial layer, wherein the implantation depth of the third doped ion is greater than the implantation depth of the second doped ion, to form an initial halo region; and using the initial halo region outside the source / drain doped region as the halo region.

15. The method for forming a semiconductor structure as described in claim 14, characterized in that, After the initial lightly doped region is formed, the initial halo region is formed.

16. The method for forming a semiconductor structure as described in claim 10, characterized in that, The formation process of the second epitaxial layer includes a selective epitaxial growth process.

17. The method for forming a semiconductor structure as described in claim 10, characterized in that, The method for forming the gate includes: forming a gate material layer on the surface of the substrate; forming a hard mask layer on a portion of the surface of the gate material layer; and etching the gate material layer using the hard mask layer as a mask to form the gate.

18. The method for forming a semiconductor structure as described in claim 10, characterized in that, The formation process of the first epitaxial layer includes a selective epitaxial growth process.

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