Semiconductor device

Abstract

A semiconductor device includes a substrate, gate structures, a plurality of insulating spacers, a plurality of first pads, an insulating layer, and a high dielectric constant material layer. The insulating spacers are disposed on the substrate alternately with the gate structures. The first pads are disposed on the insulating spacers. The insulating layer covers the insulating spacers and the gate structures, wherein the insulating layer covering the gate structures has a recess. The high dielectric constant material layer is disposed in the recess, and a bottommost surface of the high dielectric constant material layer is lower than a topmost surface of the first pads. In this way, the structural defects at the top of the gate structures are improved by the disposition of the high dielectric constant material layer and / or the insulating layer, and the possible short circuit problem between the gate structures and the metal interconnection lines disposed above is avoided.

Description

TECHNICAL FIELD

[0001] The present invention relates to a semiconductor device, and more particularly to a semiconductor device with a gate structure. BACKGROUND

[0002] With the trend of miniaturization of various electronic products, the design of semiconductor devices must also meet the requirements of high integration and high density. For dynamic random access memory (DRAM) with a recessed gate structure, because it can obtain a longer carrier channel length in the same semiconductor substrate to reduce the leakage of the capacitor structure, it has gradually replaced dynamic random access memory with only a planar gate structure under the current mainstream development trend. Generally, dynamic random access memory with a recessed gate structure is formed by a large number of memory cells gathered to form an array region for storing information, and each memory cell can be composed of a transistor component and a capacitor component in series to receive voltage information from a word line (WL) and a bit line (BL). In response to product demand, the density of memory cells in the array region must continue to be improved, resulting in increasing difficulty and complexity of related manufacturing processes and designs. Therefore, the existing technology or structure still needs to be further improved to effectively improve the performance and reliability of related memory devices. SUMMARY

[0003] One object of the present invention is to provide a semiconductor device, which additionally provides a high dielectric constant material layer with a recess or a bottom surface lower pad spacer on a gate structure to effectively cover and protect the gate structure. In this way, the structural defects at the top of the gate structure are improved, and possible short circuit problems between the gate structure and the metal interconnection line arranged above are avoided.

[0004] To achieve the above object, one embodiment of the present invention provides a semiconductor device, which includes a substrate, a gate structure, a plurality of insulating spacers, a plurality of first pads, an insulating layer, and a high dielectric constant material layer. The gate structure is arranged on the substrate. The insulating spacers are arranged on the substrate alternately with the gate structure. The first pads are arranged on the insulating spacers. The insulating layer covers each of the insulating spacers and the gate structure, wherein the insulating layer covering the gate structure has a recess. The high dielectric constant material layer is arranged in the recess, and the bottom surface of the high dielectric constant material layer is lower than the top surface of the first pad.

[0005] To achieve the above object, one embodiment of the present application provides a semiconductor device including a substrate, a gate structure, a first spacer structure, a plurality of insulating spacers, a plurality of first pads, and a plurality of pad spacers. The substrate includes a first region and a second region. The gate structure is disposed on the substrate and located in the first region. The first spacer structure is disposed on a sidewall of the gate structure. The insulating spacers are alternately disposed on the substrate with the gate structure and located in the first region. The first pads are respectively disposed on each of the insulating spacers in the first region. The pad spacers are respectively disposed on sidewalls of each of the first pads in the first region, wherein a bottom surface of the pad spacers is lower than a top surface of the first spacer structure. BRIEF DESCRIPTION OF DRAWINGS

[0006] The accompanying drawings are included to provide a further understanding of embodiments of the application and are incorporated in and constitute a part of this specification. The drawings

[0007] Figure 1 FIG. 1 illustrates a cross-sectional view of a semiconductor device according to a first embodiment of the present application.

[0008] Figures 2 to 7 FIG. 2 illustrates a structure obtained by a manufacturing method of a semiconductor device according to a preferred embodiment of the present application.

[0009] Figure 2 FIG. 3 illustrates a cross-sectional view of the semiconductor device after forming a plug hole.

[0010] Figure 3 FIG. 4 illustrates a cross-sectional view of the semiconductor device after forming a metal material layer.

[0011] Figure 4 FIG. 5 illustrates a cross-sectional view of the semiconductor device after forming a pad.

[0012] Figure 5 FIG. 6 illustrates a cross-sectional view of the semiconductor device after forming a first dielectric material layer.

[0013] Figure 6 FIG. 7 illustrates a cross-sectional view of the semiconductor device after forming a second dielectric material layer.

[0014] Figure 7 FIG. 8 illustrates a cross-sectional view of the semiconductor device after forming a capacitor dielectric layer.

[0015] Figure 8 FIG. 9 illustrates a cross-sectional view of a semiconductor device according to a second embodiment of the present application.

[0016] Figure 9 A cross-sectional view of a semiconductor device according to a third embodiment of the present application is shown. Reference numerals are explained as follows:

[0017] 10, 30, 50 semiconductor device

[0018] 100 substrate

[0019] 101 first region

[0020] 102 second region

[0021] 110 shallow trench isolation

[0022] 120 dielectric layer

[0023] 130, 530 gate structure

[0024] 130a gate stack structure

[0025] 132 semiconductor layer

[0026] 134 barrier layer

[0027] 136 metal layer

[0028] 138 cap layer

[0029] 140 first spacer structure

[0030] 140t top surface

[0031] 142 first spacer

[0032] 144 second spacer

[0033] 146 third spacer

[0034] 150 insulating spacer

[0035] 160 first pad

[0036] 160t topmost surface

[0037] 162 barrier layer

[0038] 162a barrier material layer

[0039] 164 metal layer

[0040] 164a metal material layer

[0041] 170, 370, 570 insulating layer

[0042] 172 pad spacer

[0043] 172a first dielectric material layer

[0044] 172b bottom surface

[0045] 174, 374, 574 cap layer

[0046] 174a second dielectric material layer

[0047] 184, 384 high-k material layer

[0048] 184b bottommost surface

[0049] 190 contact structure

[0050] 210 shallow trench isolation

[0051] 220 dielectric layer

[0052] 222 silicon oxide layer

[0053] 224 silicon nitride layer

[0054] 226 silicon oxide layer

[0055] 230 bit line

[0056] 230a bit line plug

[0057] 240 second spacer structure

[0058] 250 plug

[0059] 250a plug hole

[0060] 252 metal silicide layer

[0061] 260 second pad

[0062] 270 insulating layer

[0063] 272 first dielectric layer

[0064] 274 second dielectric layer

[0065] 280 capacitor structure

[0066] 282 bottom electrode layer

[0067] 284 capacitor dielectric layer

[0068] 286 top electrode layer

[0069] 376 void

[0070] 530a recess

[0071] H height

[0072] R1 Depression Detailed Implementation

[0073] To enable those skilled in the art to further understand the present invention, preferred embodiments are described below in conjunction with the accompanying drawings to explain in detail the composition and desired effects of the invention. It should be understood that the features described below can be substituted, rearranged, or mixed to achieve other embodiments without departing from the spirit of the invention.

[0074] Please refer to Figure 1 As shown, Figure 1 This is a cross-sectional schematic diagram of the semiconductor device 10 according to the first embodiment of the present invention. Figure 1 As shown, the semiconductor device 10 includes a substrate 100, a gate structure 130, a plurality of insulating spacers 150, a plurality of first pads 160, an insulating layer 170, and a high-dielectric-constant material layer 184. The substrate 100 may include, for example, a silicon substrate, a silicon-containing substrate, an epitaxial silicon substrate, a silicon-on-insulator substrate, or a substrate made of other suitable materials, but is not limited thereto. In one embodiment, the substrate 100 further includes a first region 101 with relatively low component density, for example, serving as a peripheral region of the semiconductor device 10, and a second region 102 with relatively high component density, for example, serving as a cell region of the semiconductor device 10. The first region 101 and the second region 102 may be arranged adjacent to each other, but are not limited thereto. Furthermore, multiple shallow trench isolation (STI) 110 and 210 are provided in the first region 101 and the second region 102 of the substrate 100, and multiple active areas (AA, not shown) are defined in the substrate 100.

[0075] The gate structure 130 and the insulating spacer 150 are disposed on the substrate 100 and are both located in the first region 101, wherein the insulating spacer 150 is located on both sides of the gate structure 130. The first pad 160 is disposed on the insulating spacer 150, which is covered by the insulating layer 170, and the insulating layer 170 also covers the gate structure 130. The high dielectric constant material layer 184 is further disposed on the insulating layer 170. It should be noted that the insulating layer 170 covering the gate structure 130 has a recess R1, so that the high dielectric constant material layer 184 is partially disposed in the recess R1, wherein the bottom surface 184b of the high dielectric constant material layer 184 is lower than the top surface 160t of the first pad 160. In this way, the top structure of the gate structure 130 with relatively large line width is protected by the sequential covering of the insulating layer 170 and the high dielectric constant material layer 184, so as to effectively isolate the first pad 160 from physically contacting the gate structure 130, thereby avoiding the possible short circuit problem of the metal interconnection line (such as the contact structure 190) disposed above the first pad 160.

[0076] In one embodiment, the first pad 160 has a height H in a direction perpendicular to the substrate 100 (not shown), and the bottom surface 184b of the high-k material layer 184 is preferably located below a position of half the height (i.e., ½H) of the first pad 160, ensuring that the high-k material layer 184 is completely and effectively covered on the first pad 160 and the gate structure 130, avoiding mutual contact therebetween. The semiconductor device 10 further includes a dielectric layer 120 disposed at the bottom of the gate structure 130, and a first spacer structure 140 disposed on the sidewall of the gate structure 130. The dielectric layer 120 includes an insulating material such as silicon oxide, for example, as a gate dielectric layer of the gate structure 130, and the first spacer structure 140 is located between the gate structure 130 and the insulating spacer 150 as a gate sidewall structure of the gate structure 130. Preferably, the top surface 140t of the first spacer structure 140 is higher than the top surface of the gate structure 130, effectively isolating the gate structure 130 and the first pad 160. In one embodiment, the insulating layer 170 further includes a plurality of pad spacers 172 and a cover layer 174. The pad spacers 172 are disposed on the sidewalls of both sides of the first pad 160 and simultaneously cover the upper half of the sidewall of the first spacer structure 140, for example, and the cover layer 174 is conformally covered on the pad spacers 172 and the first pad 160, such that the insulating layer 170 presents a recess R1 between two adjacent pad spacers 172, but not limited thereto. In addition, a plurality of contact structures 190 are further disposed on the first pad 160, respectively, including a low-resistivity metal material such as aluminum (Al), copper (Cu), or tungsten (W), for example, as a first layer of metal interconnection of the semiconductor device 10, electrically connected to other conductive structures subsequently disposed above the semiconductor device 10.

[0077] On the other hand, the semiconductor device 10 further includes a plurality of bit lines 230, a plurality of plugs 250, a plurality of second pads 260, and a capacitor structure 280 disposed in the second region 102. The bit lines 230 and the plugs 250 are alternately disposed on the substrate 100 with the second spacer structures 240 disposed therebetween. In an embodiment, the fabrication process of the bit lines 230 is integrated with the fabrication process of the gate structures 130 disposed in the first region 101, such that the bit lines 230 and the gate structures 130 respectively include a semiconductor layer 132, a barrier layer 134, and a metal layer 136 sequentially stacked from bottom to top, with an additional cap layer 138 disposed on the metal layer 136 of the bit lines 230. The semiconductor layer 132 includes, for example, doped polysilicon, doped amorphous silicon, or other semiconductor materials, the barrier layer 134 includes, for example, titanium and / or titanium nitride (TiN), tantalum (Ta) and / or tantalum oxide (TaN), or other conductive barrier materials, the metal layer 136 includes, for example, copper, aluminum, tungsten, or other suitable low-resistivity conductive materials, and the cap layer 138 includes, for example, silicon oxide, silicon nitride, or silicon oxynitride, or other insulating materials, but not limited thereto. The bit lines 230 are disposed on the dielectric layer 220 in principle, and extend into the substrate 100 through the corresponding bit line contacts (BLCs) 230a formed thereunder to electrically connect to the corresponding active regions. In an embodiment, the dielectric layer 220 includes, for example, a silicon oxide layer 222, a silicon nitride layer 224, and a silicon oxide layer 226 sequentially stacked to have an oxide-nitride-oxide (ONO) structure, but not limited thereto. In another embodiment, the fabrication process of the second spacer structures 240 can also be integrated with the fabrication process of the first spacer structures 140 disposed in the first region 101, such that the first spacer structures 140 and the second spacer structures 240 respectively include a first spacer 142, a second spacer 144, and a third spacer 146 sequentially disposed on the sidewalls of the gate structures 130 and the sidewalls of the bit lines 230 in the horizontal direction. The top surface of the second spacer structures 240 is coplanar with the top surface of the bit lines 230, and is higher than the top surface 140t of the first spacer structures 140 located in the first region 101. The first spacer 142 and the third spacer 146 include, for example, the same insulating material, such as silicon nitride, silicon carbon nitride, or the like, and the second spacer 144 includes, for example, a different insulating material from the first spacer 142 and the third spacer 146, such as silicon oxide, silicon oxynitride, or the like, but not limited thereto.

[0078] The plug 250, for example, includes an epitaxial material such as silicon (Si), silicon phosphorus (SiP), silicon germanium (SiGe), or germanium (Ge), and the like, to physically contact the active region as a storage node contact (SN contact) of the semiconductor device 10. The second pads 260 are disposed above the plug 250 as storage node pads (SN pads) of the semiconductor device 10, and the capacitor structure 280 is disposed on the second pads 260. In detail, the adjacent second pads 260 are isolated from each other by the insulating layer 270, and a metal silicide layer 252, for example, including a metal silicide material such as cobalt disilicide (CoSi2), titanium silicide (TiSi2), or nickel silicide (Ni2Si), but not limited thereto, is further disposed between the second pads 260 and the plug 250. In an embodiment, the fabrication process of the second pads 260 is integrated with the fabrication process of the first pads 160 disposed in the first region 101, such that the second pads 260 and the first pads 160 respectively include a barrier layer 162 and a metal layer 164 stacked in sequence. The barrier layer 162, for example, includes a conductive barrier material such as titanium and / or titanium nitride (TiN), tantalum (Ta) and / or tantalum nitride (TaN), and the like, and the metal layer 164, for example, includes copper, aluminum, tungsten, or other suitable low resistivity conductive material, but not limited thereto.

[0079] In one embodiment, the insulating layer 270 includes a first dielectric layer 272 and a second dielectric layer 274 stacked in sequence, wherein the first dielectric layer 272 and the second dielectric layer 274 can have the same or different insulating materials, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, or the like, preferably both including silicon nitride, but not limited thereto. Also, the fabrication process of the insulating layer 270 can be integrated with the fabrication process of the insulating layer 170 disposed in the first region 101, such that the pad spacer 172 of the insulating layer 170 includes the same material as the first dielectric layer 272, and the cap layer 174 of the insulating layer 170 includes the same material as the second dielectric layer 274, but not limited thereto. The capacitor structure 280 includes a plurality of bottom electrode layers 282, a capacitor dielectric layer 284, and a top electrode layer 286 disposed in sequence, constituting a plurality of vertically-extended capacitors as storage nodes (SN) of the semiconductor device 10 and physically contacting the underlying storage node pads (i.e., the second pads 260), respectively. For example, the bottom electrode layer 282 includes titanium nitride, the top electrode layer 286 includes a composite structure of titanium nitride and silicon germanium, and the capacitor dielectric layer 284 includes a high dielectric constant dielectric material selected from a group consisting of hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), zirconium oxide (ZrO2), titanium oxide (TiO2), and zirconium-aluminum-zirconium oxide (ZAZ), preferably including zirconium-aluminum-zirconium oxide, but not limited thereto. In a preferred embodiment, the fabrication process of the capacitor dielectric layer 284 can be integrated with the high dielectric constant material layer 184 disposed in the first region 101, for example, by simultaneously forming the capacitor dielectric layer 284 and the high dielectric constant material layer 184 in the first region 101, such that the capacitor dielectric layer 284 and the high dielectric constant material layer 184 include the same material.

[0080] Under this arrangement, the capacitor and a transistor assembly (not shown) disposed in the second region 102 of the substrate 100 can constitute a minimum-constituent memory cell to receive voltage information from the bit line 230 and a word line (not shown), so that the semiconductor device 10 of the present embodiment constitutes a dynamic random access memory (DRAM) device and achieves more optimal operational performance. According to the semiconductor device 10 of the present embodiment, the high-dielectric-constant material layer 184 disposed on the gate structure 130 and the insulating layer 170 thereunder are additionally arranged to cover and protect the top structure of the gate structure 130, so as to ensure that the metal interconnection line subsequently disposed in the first region 101 is electrically connected to the first pad 160 only and does not contact the gate structure 130, thereby avoiding possible short-circuit problems. Moreover, the high-dielectric-constant material layer 184 and the insulating layer 170 disposed in the first region 101 can be formed together with the assembly disposed in the second region 102 in the same manufacturing process, without the need to perform additional operations or processes, so that the semiconductor device 10 of the present embodiment can have more reliable structure and performance under the premise of simplified manufacturing.

[0081] Those of ordinary skill in the art of the present application should easily understand that, in order to meet the requirements of actual products, the semiconductor device of the present application can also have other forms and is not limited to the foregoing. Further embodiments or variations of the semiconductor device of the present application will be described below. For simplicity, the following description mainly focuses on the differences between the embodiments and does not repeat the same parts. In addition, the same components in the embodiments of the present application are denoted by the same reference numerals for the purpose of mutual comparison between the embodiments.

[0082] For example Figure 1As shown, in another embodiment, the semiconductor device 10 may also include a substrate 100, a gate structure 130, a plurality of insulating spacers 150, a first spacer wall structure 140, a plurality of first pads 160, and a plurality of pad spacer walls 172. The gate structure 130 and the insulating spacers 150 are respectively disposed on the substrate 100, both located within the first region 101, such that the insulating spacers 150 are located on both sides of the gate structure 130. The first spacer wall structure 140 is disposed on the sidewall of the gate structure 130 and is located between the gate structure 130 and the insulating spacers 150. The first pads 160 are disposed on the insulating spacers 150. It should be particularly noted that the plurality of pad spacer walls 172 are respectively disposed on the sidewall of the first pads 160, and simultaneously cover the upper half of the sidewall of the first spacer wall structure 140, such that the bottom surface 172b of the pad spacer wall 172 is lower than the top surface 140t of the first spacer wall structure 140. Therefore, the pad gap wall 172 can effectively isolate the physical contact between the first pad 160 and the gate structure 130, ensuring that the subsequent metal interconnects (such as the contact structure 190) are only electrically connected to the first pad 160 and do not contact the gate structure 130, thus avoiding possible short circuit problems.

[0083] To enable those skilled in the art to easily understand the semiconductor device 10 of the present invention, the manufacturing method of the semiconductor device 10 of the present invention will be further described below.

[0084] Please see Figures 2 to 7 The diagram shown illustrates a method for fabricating the semiconductor device 10 according to a preferred embodiment of the present invention. First, as... Figure 2 As shown, a substrate 100 is provided, and shallow trench isolations 110 and 210 are formed in a first region 101 and a second region 102 of the substrate 100, respectively, while the active regions are defined simultaneously in the first region 101 and the second region 102. In one embodiment, the shallow trench isolations 110 and 210 are formed, for example, by first forming a plurality of trenches (not shown) in the substrate 100 using an etching process, and then filling the trenches with at least one insulating material (such as silicon oxide, silicon nitride, etc.) to form shallow trench isolations 110 and 210 with surfaces flush with the top surface of the substrate 100, but this is not a limitation.

[0085] Next, a plurality of buried word lines (not shown) are formed on the first region 101 and the second region 102 of the substrate 100. In one embodiment, the buried word lines are formed by a process including, but not limited to, the following steps, for example, forming a plurality of trenches (not shown) that can simultaneously pass through a plurality of the active regions and the shallow trench isolation 210, forming a dielectric layer (not shown) covering the entire surface of the trenches, forming a gate dielectric layer (not shown) covering the lower half of the surface of the trenches, forming a gate (not shown) filling the lower half of the trenches, and forming a cap layer (not shown) filling the upper half of the trenches, but not limited thereto. Also, a dielectric layer 120 and a dielectric layer 220 are formed on the first region 101 and the second region 102 of the substrate 100, respectively. In one embodiment, the dielectric layer 120 and the dielectric layer 220 are formed by a process including, but not limited to, the following steps, for example, forming a dielectric material layer including a first silicon oxide material layer (not shown), a silicon nitride material layer (not shown), and a second silicon oxide material layer (not shown) stacked in sequence on the first region 101 and the second region 102 of the substrate 100, and removing at least the second silicon oxide material layer and the silicon nitride material layer formed on the first region 101 of the substrate 100, so that the first silicon oxide material layer on the first region 101 of the substrate 100 forms the dielectric layer 120, and the dielectric material layer on the second region 102 of the substrate 100 forms the dielectric layer 220. Alternatively, in another embodiment, the dielectric material layer on the first region 101 of the substrate 100 can also be completely removed, and then the dielectric layer 120 is formed again.

[0086] Then, a plurality of gate stack structures 130a and a plurality of bit lines 230 are formed on the first region 101 and the second region 102 of the substrate 100, respectively, by a similar process. The gate stack structures 130a have a relatively larger line width than the bit lines 230, but are not limited thereto. In one embodiment, the gate stack structures 130a and the bit lines 230 are formed by a process including, but not limited to, the following steps. First, a plurality of openings (not shown) are formed in the second region 102 to pass through the dielectric layer 220 and partially expose the substrate 100, a semiconductor material layer (not shown, for example, including a plurality of semiconductor materials such as polysilicon, doped amorphous silicon, etc.) is formed in the first region 101 and the second region 102 to fill the openings, a barrier material layer (not shown, for example, including a plurality of conductive barrier materials such as titanium and / or titanium nitride, tantalum and / or tantalum oxide, etc.), a metal material layer (not shown, for example, including a plurality of low-resistance metal materials such as tungsten, aluminum, or copper, etc.), and a cap material layer (not shown, for example, including a plurality of insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride, etc.) are formed on the semiconductor material layer, and finally, the gate stack structures 130a and the bit lines 230 are formed simultaneously by a patterning process. Figure 2The gate stack structure 130a and bit line 230 shown have an integrally formed bit line plug 230a below part of the bit line 230. The gate stack structure 130a and bit line 230 respectively include a semiconductor layer 132, a barrier layer 134, a metal layer 136 and a capping layer 138 stacked sequentially from bottom to top.

[0087] For example Figure 2 As shown, a first spacer structure 140 and a second spacer structure 240 are formed on the sidewalls of the gate stack structure 130a and the bit line 230 using the same process, including a first spacer 142 (e.g., including silicon nitride and silicon carbonitride), a second spacer 144 (e.g., including silicon oxide and silicon oxynitride), and a third spacer 146 (e.g., including silicon nitride and silicon carbonitride) stacked sequentially in the horizontal direction, but not limited thereto.

[0088] Then, a deposition and etch-back fabrication process is performed to form an insulating material between adjacent gate stack structures 130a and adjacent bit lines 230, such that the insulating material formed in the first region 101 forms an insulating space 150. Next, the insulating material between the adjacent bit lines 230 is removed through a mask layer (not shown), forming a plurality of plug vias 250a partially exposing the substrate 100 in the second region 102, as shown. Figure 2 As shown, the mask layer is then completely removed.

[0089] like Figure 3 As shown, an epitaxial fabrication process is performed to form a plug 250 within a plug hole 250a in the second region 102, and a metal silicide fabrication process is performed on the plug 250 to form a metal silicide layer 252. In one embodiment, the plug 250 may include epitaxial materials such as silicon, silicon-phosphorus, silicon-germanium, or germanium, while the metal silicide layer 252 may include metal silicide materials such as cobalt disilicide, titanium silicide, or nickel silicide, but is not limited thereto. Thus, the formed plug 250 can serve as a memory node plug for the semiconductor device 10. Then, at least one deposition fabrication process is performed to simultaneously form a barrier material layer 162a (e.g., including titanium and / or titanium nitride, tantalum and / or tantalum oxide, etc., conductive barrier materials) and a metal material layer 164a (e.g., including copper, aluminum, tungsten, or other suitable low resistivity metal materials) on the first region 101 and the second region 102 of the substrate 100. A portion of the barrier material layer 162a is conformally formed on a surface such as... Figure 2 The plug hole 250a shown is inside another part of the barrier material layer 162a outside the plug hole 250a, and the remaining space of the plug hole 250a is filled by a part of the metal material layer 164a.

[0090] like Figure 4As shown, a first pad 160 and a second pad 260 are formed on the first region 101 and the second region 102 of the substrate 100, respectively, by another mask layer (not shown) and then the another mask layer is completely removed. The first pad 160 has a height H in the direction perpendicular to the substrate 100, for example, but not limited to. It is noted that the first pad 160 is formed on the insulating spacer 150 and the first spacer structure 140, and at the same time, the cap layer 138 of the gate stack structure 130a is removed by adjusting the etching parameters to form the gate structure 130 when the first pad 160 is formed. On the other hand, the second pad 260 is partially formed on the bit line 230 and the second spacer structure 240, and partially formed in the plug hole 250a as shown, and physically contacts the metal silicide layer 252 to electrically connect the plug 250. Thus, the second pad 260 formed can be used as a storage node pad of the semiconductor device 10. Figure 2 As shown, a first pad 160 and a second pad 260 are formed on the first region 101 and the second region 102 of the substrate 100, respectively, by another mask layer (not shown) and then the another mask layer is completely removed. The first pad 160 has a height H in the direction perpendicular to the substrate 100, for example, but not limited to. It is noted that the first pad 160 is formed on the insulating spacer 150 and the first spacer structure 140, and at the same time, the cap layer 138 of the gate stack structure 130a is removed by adjusting the etching parameters to form the gate structure 130 when the first pad 160 is formed. On the other hand, the second pad 260 is partially formed on the bit line 230 and the second spacer structure 240, and partially formed in the plug hole 250a as shown, and physically contacts the metal silicide layer 252 to electrically connect the plug 250. Thus, the second pad 260 formed can be used as a storage node pad of the semiconductor device 10.

[0091] As shown, a first pad 160 and a second pad 260 are formed on the first region 101 and the second region 102 of the substrate 100, respectively, by another mask layer (not shown) and then the another mask layer is completely removed. The first pad 160 has a height H in the direction perpendicular to the substrate 100, for example, but not limited to. It is noted that the first pad 160 is formed on the insulating spacer 150 and the first spacer structure 140, and at the same time, the cap layer 138 of the gate stack structure 130a is removed by adjusting the etching parameters to form the gate structure 130 when the first pad 160 is formed. On the other hand, the second pad 260 is partially formed on the bit line 230 and the second spacer structure 240, and partially formed in the plug hole 250a as shown, and physically contacts the metal silicide layer 252 to electrically connect the plug 250. Thus, the second pad 260 formed can be used as a storage node pad of the semiconductor device 10. Figure 5 As shown, a first pad 160 and a second pad 260 are formed on the first region 101 and the second region 102 of the substrate 100, respectively, by another mask layer (not shown) and then the another mask layer is completely removed. The first pad 160 has a height H in the direction perpendicular to the substrate 100, for example, but not limited to. It is noted that the first pad 160 is formed on the insulating spacer 150 and the first spacer structure 140, and at the same time, the cap layer 138 of the gate stack structure 130a is removed by adjusting the etching parameters to form the gate structure 130 when the first pad 160 is formed. On the other hand, the second pad 260 is partially formed on the bit line 230 and the second spacer structure 240, and partially formed in the plug hole 250a as shown, and physically contacts the metal silicide layer 252 to electrically connect the plug 250. Thus, the second pad 260 formed can be used as a storage node pad of the semiconductor device 10.

[0092] Figure 6 As shown, a first pad 160 and a second pad 260 are formed on the first region 101 and the second region 102 of the substrate 100, respectively, by another mask layer (not shown) and then the another mask layer is completely removed. The first pad 160 has a height H in the direction perpendicular to the substrate 100, for example, but not limited to. It is noted that the first pad 160 is formed on the insulating spacer 150 and the first spacer structure 140, and at the same time, the cap layer 138 of the gate stack structure 130a is removed by adjusting the etching parameters to form the gate structure 130 when the first pad 160 is formed. On the other hand, the second pad 260 is partially formed on the bit line 230 and the second spacer structure 240, and partially formed in the plug hole 250a as shown, and physically contacts the metal silicide layer 252 to electrically connect the plug 250. Thus, the second pad 260 formed can be used as a storage node pad of the semiconductor device 10.

[0093] ​Next, another deposition process is performed to simultaneously form a second dielectric material layer 174a on the first region 101 and the second region 102 of the substrate 100. This layer may contain insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, or silicon carbonitride. The second dielectric material layer 174a formed in the first region 101 conformally covers the gate structure 130 with a relatively large linewidth and the pad spacer 172, creating a recess R1 between adjacent pad spacers 172. The bottom of the recess R1 may be lower than the bottom surface of the first pad 160, but is not limited to this. Thus, the fabrication of the second dielectric material layer 174a protects and covers the top structure of the gate structure 130, further isolating the physical contact between the first pad 160 and the gate structure 130. On the other hand, the second dielectric material layer 174a formed in the second region 102 just fills the remaining space between adjacent second pads 260, resulting in an overall flat top surface. In one embodiment, the first dielectric material layer 172a and the second dielectric material layer 174a preferably have different insulating materials. For example, the first dielectric material layer 172a may include silicon oxide or silicon oxynitride, and the second dielectric material layer 174a may include silicon nitride or silicon carbonitride, but this is not a limitation.

[0094] like Figure 7 As shown, a planarization process is performed on the second region 102 of the substrate 100, partially removing the second dielectric material layer 174a and the first dielectric material layer 172a. This results in the second dielectric material layer 174a formed in the first region 101 forming a capping layer 174. The capping layer 174 and the pad spacer 172 in the first region 101 together form an insulating layer 170 with a recess R1. On the other hand, the second dielectric material layer 174a and the first dielectric layer 172a formed in the second region 102 form a second dielectric layer 274 and a first dielectric layer 272 with a U-shaped cross-section after the planarization process. The first dielectric layer 272 and the second dielectric layer 274 in the second region 102 together form an insulating layer 270, wherein the top surface of the insulating layer 270 is flush with the top surface of the second pad 260.

[0095] Then, a bottom electrode layer 282 is formed on the insulating layer 270 and the second pad 260, physically contacting the top surface of the second pad 260. The bottom electrode layer 282 includes, for example, but not limited to, titanium nitride. Next, a capacitor dielectric layer 284 is formed on the bottom electrode layer 282, including, for example, a high dielectric constant dielectric material selected from the group consisting of hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, zinc oxide, titanium oxide, and zirconium-aluminum-zirconium oxide, and preferably including zirconium-aluminum-zirconium oxide. It is noted that the capacitor dielectric layer 284 can also be formed to further extend into the first region 101 and cover the insulating layer 170 at the same time. Thus, the capacitor dielectric layer 284 formed in the first region 101 is a high dielectric constant material layer 184 as shown in Figure 1 , partially formed in the recess Rl such that the bottommost surface 184b is lower than the topmost surface 160t of the first pad 160. That is, the high dielectric constant material layer 184 in the first region 101 is a part of the capacitor dielectric layer 284 in the second region 102, and the fabrication process of the high dielectric constant material layer 184 can be integrated with the fabrication process of the capacitor dielectric layer 284 in the second region 102, including the same material.

[0096] Then, a top electrode layer 286 is formed on the capacitor dielectric layer 284, such that the top electrode layer 286, the capacitor dielectric layer 284, and the bottom electrode layer 282 in the second region 102 collectively form a capacitor structure 280 as shown in Figure 1 , and the contact structure 190 as shown in Figure 1 is formed in the first region 101, completing the fabrication of the semiconductor device 10 in this embodiment. The vertical capacitance of the capacitor structure 280 and the transistor components (not shown) formed in the second region 102 of the substrate 100 can constitute a minimum-constituent memory cell to receive voltage information from the bit line 230 and the word line, such that the semiconductor device 10 in this embodiment forms the dynamic random access memory device and achieves more optimized operational performance.

[0097] According to the manufacturing method of the present embodiment, the manufacturing processes of the components on the first region 101 and the second region 102 of the substrate 100 are integrated, and the gate structure 130 with relatively large line width and the bit line 230 are formed in the first region 101 and the second region 102 respectively by similar processes. Moreover, the manufacturing processes of the insulating layer 170 and the insulating layer 270 on the first region 101 and the second region 102 are integrated, and / or the manufacturing processes of the high dielectric constant material layer 184 and the capacitor dielectric layer 284 on the first region 101 and the second region 102 are integrated, so as to protect the top structure of the gate structure 130 by the high dielectric constant material layer 184 and / or the insulating layer 170 formed in the first region 101, and avoid the contact between the first pad 160 and the gate structure 130 caused by the removal of the cap layer 138 formed in the first region 101. In this way, the manufacturing method of the semiconductor device in the present embodiment can simplify the manufacturing process, and form the semiconductor device 10 with reliable structure and performance.

[0098] Please refer to Figure 8 , which is a schematic cross-sectional view of a semiconductor device 30 in a second embodiment of the present application. The semiconductor device 30 in the present embodiment has substantially the same structure as the semiconductor device 10 in the first embodiment, and the same parts are not described again. The main difference between the semiconductor device 30 in the present embodiment and the semiconductor device 10 in the first embodiment is that the cover layer 374 in the present embodiment has an aperture 376 located below the recess R1. Figure 1

[0099] In detail, as shown in Figure 8 , the insulating layer 370 in the present embodiment includes the pad spacer 172 and the cover layer 374. The cover layer 374 is conformally formed on the pad spacer 172, the first pad 160, and the gate structure 130 with relatively large line width, so that the cover layer 374 presents a recess (not shown) between two adjacent pad spacers 172. It should be noted that the high dielectric constant material layer 384 formed later further covers and partially seals the recess, forming the recess R1 and the aperture 376 as shown in Figure 8 . In addition to the above, part of the high dielectric constant material layer 384 is also formed in the aperture 376 and directly contacts the aperture 376.

[0100] ​Under this arrangement, the semiconductor device 30 of the present embodiment can effectively protect the top structure of the gate structure 130 by the covering of the insulating layer 370 and / or the high dielectric constant material layer 384, so as to ensure that the metal interconnection lines (e.g. the contact structure 190) subsequently arranged in the first region 101 only electrically connect the first pad 160 without contacting the gate structure 130, thereby avoiding the possible short circuit problem. Thus, the dynamic random access memory device composed of the semiconductor device 30 of the present embodiment can also have reliable structure and performance, and achieve more optimized operation performance.

[0101] Please refer to Figure 9 , which is a schematic cross-sectional view of a semiconductor device 50 in a third embodiment of the present application. The semiconductor device 50 of the present embodiment has substantially the same structure as the semiconductor device 10 in the first embodiment, as shown in Figure 1 . The same parts are not described again here. The main difference between the semiconductor device 50 of the present embodiment and the semiconductor device 10 of the first embodiment is that the gate structure 530 of the present embodiment has a top surface recess 530a, and the covering layer 574 fills the recess 530a.

[0102] In detail, as shown in Figure 9 , the insulating layer 570 of the present embodiment includes the pad spacer 172 and the covering layer 574. The covering layer 574 also covers the pad spacer 172, the first pad 160, and the gate structure 530 with a relatively large line width in a common type, so that the covering layer 574 presents a recess R1 between two adjacent pad spacers 172. It should be noted that in the present embodiment, the etching conditions of the etching-back manufacturing process are adjusted to partially remove the metal layer 136 of the gate structure 530 when the first dielectric material layer 172a in the first region 101 is partially removed, as shown in Figure 5 , so as to form the recess 530a on the top surface of the gate structure 530. In this way, the recess 530a can be formed between two adjacent pad spacers 172, and the sidewall of the recess 530a can also be optionally cut vertically to the sidewall of the pad spacer 172, but it is not limited thereto. Then, the covering layer 574 subsequently formed fills the recess 530a to cover and protect the top structure of the gate structure 530.

[0103] Under this arrangement, the semiconductor device 50 of the present embodiment can effectively protect the top structure of the gate structure 530 by the covering of the insulating layer 570 and / or the high dielectric constant material layer 184, so as to ensure that the metal interconnection lines (e.g. the contact structure 190) subsequently arranged in the first region 101 only electrically connect the first pad 160 without contacting the gate structure 530, thereby avoiding the possible short circuit problem. Thus, the dynamic random access memory device composed of the semiconductor device 50 of the present embodiment can also have reliable structure and performance, and achieve more optimized operation performance.

[0104] In summary, the semiconductor device of the present application integrates the fabrication processes of components in different regions, and additionally provides a high dielectric constant material layer with a recess or a bottom lower pad spacer on the gate structure in the peripheral region under the premise of process simplification, effectively covering and protecting the gate structure, and isolating the gate structure from the possible physical contact between the gate structure and the pad. In this way, the structural defects at the top of the gate structure are improved, and the possible short circuit problem between the gate structure and the metal interconnection line arranged above is avoided.

[0105] The above only describes the preferred embodiments of the present application and is not intended to limit the present application. For those skilled in the art, the present application can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A semiconductor device, characterized by, The method comprises: providing a substrate; forming a gate structure on the substrate; forming a plurality of insulating spacers on the substrate and on both sides of the gate structure; forming a plurality of first pads on the insulating spacers; forming an insulating layer on the insulating spacers and the gate structure, wherein the insulating layer on the gate structure has a recess; and forming a high dielectric constant material layer in the recess, and a bottom surface of the high dielectric constant material layer is lower than a top surface of the first pads.

2. The semiconductor device according to claim 1, wherein The insulating layer further comprises a plurality of pad spacer walls formed on sidewalls of the first pads, wherein the recess is between two adjacent pad spacer walls; and a cover layer is formed on the pad spacer walls.

3. The semiconductor device according to claim 2, wherein The cover layer has an aperture below the recess.

4. The semiconductor device according to claim 2, wherein A top surface of the gate structure has a recessed portion between the two adjacent pad spacer walls, and the cover layer fills the recessed portion.

5. The semiconductor device according to claim 3, wherein The high dielectric constant material layer contacts the aperture.

6. The semiconductor device according to claim 1, wherein The method further comprises: forming a plurality of contact structures on the first pads; and forming a first spacer structure between the insulating spacers and the gate structure, wherein a top surface of the first spacer structure is higher than a top surface of the gate structure. Each of the first pads has a height in a direction perpendicular to the substrate, and the bottom surface of the high dielectric constant material layer is lower than half of the height.

7. The semiconductor device according to claim 1, wherein The method further comprises:

8. The semiconductor device according to claim 1, wherein forming a plurality of bit lines on the substrate; forming a plurality of plugs on the substrate alternately with the bit lines; forming a plurality of second pads on the plugs; and forming a capacitor structure on the second pads, wherein the capacitor structure comprises a bottom electrode layer, a capacitor dielectric layer, and a top electrode layer formed in sequence, and the capacitor dielectric layer and the high dielectric constant material layer comprise the same material. The method comprises: providing a substrate comprising a first region and a second region; 9. A semiconductor device, characterized by comprising: forming a gate structure on the substrate and in the first region; forming a plurality of insulating spacers on the substrate and on both sides of the gate structure; forming a first spacer structure on sidewalls of the gate structure and between the gate structure and the insulating spacers; forming a plurality of first pads on the insulating spacers, respectively; and forming a plurality of pad spacer walls on sidewalls of the first pads, respectively, wherein a bottom surface of the pad spacer walls is lower than a top surface of the first spacer structure. The method further comprises: forming a cover layer on the pad spacer walls, the gate structure, and the first pads, wherein the cover layer has a recess, and the recess is between two adjacent pad spacer walls and on the gate structure. The method further comprises:

10. The semiconductor device according to claim 9, wherein forming a plurality of bit lines on the substrate and in the second region; forming a plurality of plugs on the substrate alternately with the bit lines; 11. The semiconductor device according to claim 10, wherein forming a plurality of second pads on the plugs; and forming a capacitor structure on the second pads in the second region, wherein the capacitor structure comprises a bottom electrode layer, a capacitor dielectric layer, and a top electrode layer formed in sequence, and at least part of the capacitor dielectric layer is in the recess. ​ ​ ​ ​ 12. The semiconductor device according to claim 11, wherein A bottommost surface of the capacitive dielectric layer of the portion is lower than a topmost surface of the first pad within the first region.

13. The semiconductor device according to claim 11, wherein The cap layer has an aperture located below the recess.

14. The semiconductor device according to claim 13, wherein The capacitive dielectric layer of the portion contacts the aperture.

15. The semiconductor device of claim 10, wherein Further comprising: A plurality of contact structures disposed on the first pad.

16. The semiconductor device according to claim 10, wherein A top surface of the gate structure has a recess located between the two adjacent pad spacers, and the cap layer fills the recess.

17. The semiconductor device of claim 11, wherein The top surface of the first spacer structure is higher than a top surface of the gate structure.

18. The semiconductor device according to claim 17, wherein Further comprising: A second spacer structure disposed between each of the bit lines and each of the plugs, a top surface of the second spacer structure is coplanar with a top surface of the bit lines and higher than the top surface of the first spacer structure.

19. The semiconductor device of claim 11, wherein Further comprising: An insulating layer covering the bit lines and comprising a first dielectric layer and a second dielectric layer stacked in sequence, wherein the first dielectric layer and the pad spacers comprise a same material.

20. The semiconductor device according to claim 19, wherein A top surface of the insulating layer is coplanar with a top surface of the second pad.

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