Display panel and display device

Abstract

The application provides a display panel and a display device. The display panel comprises: a driving chip, a driving mode of which is column inversion driving; a plurality of data lines, which are arranged at intervals along a first direction and extend along a second direction, and first ends of the plurality of data lines are electrically connected to output ends of the driving chip; a plurality of sub-pixels, which are arranged in an array along the first direction and the second direction, and sub-pixels located in the same column along the second direction constitute a sub-pixel column, one sub-pixel column corresponds to at least one data line, and second ends of the data line are electrically connected to at least part of the sub-pixels in the corresponding sub-pixel column; a logic gate circuit, a target data line is electrically connected to a target structure through the logic gate circuit, and the logic gate circuit is used for changing the voltage polarity of the target sub-pixel, so that each sub-pixel is flipped in a row inversion mode or a frame inversion mode, and the target structure comprises the driving chip and / or the target sub-pixel. The application solves the problem of low display screen transmittance.

Description

Technical Field

[0001] This application relates to the field of display technology, and more specifically, to a display panel and a display device. Background Technology

[0002] Liquid crystal displays (LCDs) have advantages such as good image quality, small size, light weight, low driving voltage, low power consumption, no radiation, and relatively low manufacturing cost, and they dominate the flat panel display field.

[0003] VR (Virtual Reality) headsets use LCDs called FAST LCDs (Fast Liquid Crystal Displays), which require high PPI. However, when the PPI (pixels per inch) is high, the pixel pitch becomes smaller, and the electric fields of adjacent sub-pixels in the row direction will affect each other, which will affect transmittance and color shift. Summary of the Invention

[0004] The main objective of this application is to provide a display panel and display device to at least solve the problem in the prior art where the electric fields between adjacent sub-pixels in the row direction affect each other, resulting in low transmittance of the display screen.

[0005] To achieve the above objectives, according to one aspect of this application, a display panel is provided, the display panel comprising:

[0006] The driving chip is driven by column flipping;

[0007] Multiple data lines are arranged at intervals along a first direction and extend along a second direction, the first direction intersects the second direction, and the first end of the multiple data lines is electrically connected to the output end of the driver chip;

[0008] Multiple sub-pixels are arranged in an array along the first direction and the second direction. Sub-pixels located in the same column along the second direction constitute a sub-pixel column. A sub-pixel column corresponds to at least one data line. The second end of the data line is electrically connected to at least a portion of the sub-pixels in the corresponding sub-pixel column.

[0009] A logic gate circuit is provided, through which the target data line is electrically connected to the target structure. The logic gate circuit is used to change the polarity of the voltage transmitted to the target sub-pixel, so that each sub-pixel is flipped in a row-flipping mode or a frame-flipping mode. The target structure includes at least one of the following: the driving chip and the target sub-pixel. The target data line is at least one of a plurality of data lines, and the plurality of sub-pixels include the target sub-pixel.

[0010] According to another aspect of this application, a display device is provided, the display device comprising any of the aforementioned display panels.

[0011] By applying the technical solution of this application, a logic gate circuit is set between the data line and the driver chip, or between the data line and the sub-pixel. The voltage polarity of some sub-pixels in the sub-pixel array is changed by the logic gate circuit, so that the driver chip with column flip driving as the driving method can realize row flip or frame flip of the display panel. This eliminates the voltage difference between adjacent sub-pixels in the row direction, solves the influence of the voltage difference between adjacent sub-pixels on the transmittance in the column flip mode, and ensures that the transmittance of the display panel is high. Attached Figure Description

[0012] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:

[0013] Figure 1 A schematic diagram of the voltage polarity of a sub-pixel under column flipping conditions provided in an embodiment of this application is shown;

[0014] Figures 2(a) to 2(d) Cross-sectional structural schematic diagrams of display panels provided according to embodiments of this application are shown respectively;

[0015] Figure 3 A schematic diagram of the structure of a display panel according to an embodiment of this application is shown;

[0016] Figure 4 A schematic diagram of the specific structure of a display panel according to an embodiment of this application is shown;

[0017] Figure 5 A schematic diagram of the specific structure of another display panel provided according to an embodiment of this application is shown;

[0018] Figure 6 A schematic diagram of the specific structure of another display panel provided according to an embodiment of this application is shown;

[0019] Figure 7A schematic diagram of the specific structure of another display panel provided according to an embodiment of this application is shown;

[0020] Figure 8 A schematic diagram of the specific structure of another display panel provided according to an embodiment of this application is shown;

[0021] Figure 9 A schematic diagram of the structure of a display device provided according to an embodiment of this application is shown.

[0022] The above figures include the following reference numerals:

[0023] 10. Data line; 11. Sub-pixel; 12. Logic gate circuit; 13. Target data line; 14. Target sub-pixel; 15. First inverter; 16. NAND gate; 17. NOR gate; 18. Second inverter; 19. First data line; 20. Second data line; 21. Third inverter; 100. TFT substrate; 101. CF substrate; 102. Insulating layer; 103. Pixel electrode; 104. Common electrode; 105. Light-shielding layer. Detailed Implementation

[0024] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0025] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0026] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this application described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0027] As described in the background section, in existing high-pixel-density displays, the electric fields between adjacent sub-pixels in the row direction influence each other, resulting in low transmittance of the display. Specifically, when the aforementioned sub-pixels are flipped in a column-flip manner, the corresponding sub-pixel voltage polarity diagram is as follows: Figure 1 As shown, "+" indicates that the voltage polarity of the sub-pixel is positive, and "-" indicates that the voltage polarity of the sub-pixel is negative. Figure 1 As can be seen, during column flipping, the voltage polarities between adjacent sub-pixel columns are different, resulting in a voltage difference between adjacent sub-pixels in the row direction. This creates an electric field between them, as shown by the horizontal arrows in Figures 2(a) and 2(c). This causes the liquid crystal molecules in this area to become disordered. As shown in Figure 2(a), when the display panel is in normal black mode and a white image is displayed, this area will form a dark area, causing a decrease in transmittance. As shown in Figure 2(c), when the display panel is in normal white mode and a black image is displayed, this area will form a bright area, causing light leakage. However, as shown in Figures 2(b) and 2(d), when the voltages of adjacent sub-pixels are the same, neither dark nor bright areas will be formed. Figures 2(a) to (d) are schematic cross-sectional views of the display panel. Figures 2(a) to (d) show the TFT (Thin Film Transistor) substrate 100, CF (Color Filter) substrate 101, sub-pixels 11, insulating layer 102, pixel electrodes 103 and common electrodes 104 located between the TFT substrate 100 and the CF substrate 101. The display panel also includes a light-shielding layer 105 located on the side of the CF substrate 101 near the TFT substrate 100.

[0028] To address the above-mentioned technical problems, embodiments of this application provide a display panel and a display device.

[0029] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0030] This embodiment provides a display panel. Figure 3 This is a schematic diagram of the structure of a display panel according to an embodiment of this application. Figure 3 As shown, the above display panel includes:

[0031] The driving chip (not shown in the figure) is driven by column inversion. Under the drive of the driving chip, the sub-pixels in the display panel are flipped in column order. The voltage polarities of the sub-pixels in adjacent columns are opposite, and there is a voltage difference.

[0032] Multiple data lines 10 are arranged at intervals along a first direction and extend along a second direction, wherein the first direction is the row direction of the display panel, the second direction is the column direction of the display panel, the first direction and the second direction intersect, and the first end of the multiple data lines 10 is electrically connected to the output end of the driver chip.

[0033] Specifically, the first direction and the second direction are perpendicular to each other.

[0034] Multiple sub-pixels 11 are arranged in an array along the first direction and the second direction. Sub-pixels located in the same column along the second direction constitute a sub-pixel column. A sub-pixel column corresponds to at least one data line 10. The second end of the data line 10 is electrically connected to at least a portion of the sub-pixels 11 in the corresponding sub-pixel column.

[0035] The logic gate circuit 12 and the target data line 13 are electrically connected to the target structure through the logic gate circuit 12. The logic gate circuit 12 is used to change the voltage polarity transmitted to the target sub-pixel, so that each sub-pixel is flipped in either row inversion mode or frame inversion mode. When each sub-pixel is flipped in row inversion mode, the voltage of the sub-pixels located in the same row is the same. When each sub-pixel is flipped in frame inversion mode, the voltage of any two adjacent sub-pixels is the same. The target structure includes at least one of the following: the driving chip and the target sub-pixel (not shown in the figure). The target data line 13 is at least one of the plurality of data lines 10. The plurality of sub-pixels 11 include the target sub-pixel.

[0036] Through the above embodiments, logic gate circuits are set between the data line and the driver chip, or between the data line and the sub-pixel. The voltage polarity of some sub-pixels in the sub-pixel array is changed by the logic gate circuits, so that the driver chip with column flip driving as the driving method can realize row flip or frame flip of the display panel. This eliminates the voltage difference between adjacent sub-pixels in the row direction, solves the influence of the voltage difference between adjacent sub-pixels on the transmittance in the column flip mode, and ensures that the transmittance of the display panel is high.

[0037] The display panel described in this application can specifically be an LTPS (Low Temperature Poly-Silicon) LCD. Currently, the driving method of LTPS LCD driver chips does not support line flipping and frame flipping. Therefore, the embodiments described in this application do not require the development of a new LTPS LCD driver chip; high transmittance of the display panel can be achieved using existing driver chips.

[0038] It should be noted that each sub-pixel in the sub-pixel column is electrically connected to the second end of the data line. Specifically, if there is only one data line corresponding to the sub-pixel column, all sub-pixels in the sub-pixel column are electrically connected to the corresponding data line. If there are multiple data lines corresponding to the sub-pixel column, taking two data lines as an example, some sub-pixels in the sub-pixel column are electrically connected to one of the corresponding data lines, and the remaining sub-pixels are electrically connected to the other corresponding data line.

[0039] Furthermore, the aforementioned display panel also includes multiple multiplexers. The driver chip is electrically connected to the data lines via the multiplexers. Specifically, when a logic gate circuit is provided between the driver chip and the data lines, the driver chip is electrically connected to the first end of the data lines sequentially via the multiplexers and the logic gate circuit. When no logic gate circuit is provided between the driver chip and the data lines, the driver chip is electrically connected to the first end of the data lines via the multiplexers. One multiplexer corresponds to at least two data lines. Figures 4 to 8 An exemplary diagram illustrates the sub-pixel voltage polarity when the multiplexer is 1:2Demux, where one of the aforementioned multiplexers is connected to two of the aforementioned data lines, with the connection terminals being S1 and S2, respectively. The implementation principle of 1:3Demux or other multiplexers is the same as that of 1:2Demux, and will not be elaborated upon in this application.

[0040] In one alternative, such as Figure 4 As shown, the target structure includes the driver chip, and the target data line 13 is the data line 10 corresponding to the sub-pixel column located in an even-numbered column or an odd-numbered column. The odd-numbered column and the even-numbered column are the sub-pixel columns located in odd-numbered positions and the sub-pixel columns located in even-numbered positions along the first direction. Figure 4 This illustrates the arrangement of the data lines in a horizontal direction. Specifically, the first direction can be from horizontal left to horizontal right, or from horizontal right to horizontal left. Figure 4 An example is shown where the target data line 13 is the data line 10 corresponding to the sub-pixel column located in the odd-numbered column. The logic gate circuit includes: a first inverter 15, the input terminal of the first inverter 15 is electrically connected to the output terminal of the driver chip, and the output terminal of the first inverter 15 is electrically connected to the first terminal of the target data line 13. When the driver chip outputs a driving signal to each sub-pixel 11 through each of the data lines 10, each sub-pixel 11 is flipped in the frame flipping mode.

[0041] In the above embodiment, the data line corresponding to the sub-pixel column located in one of the even-numbered and odd-numbered columns along the first direction is electrically connected to the driving chip through the first inverter. Through the first inverter, the voltage polarity of the sub-pixel column located in one of the even-numbered and odd-numbered columns can be changed so that it is the same as the voltage polarity of the other sub-pixel column located in the even-numbered and odd-numbered columns. That is to say, during the process of the driving chip driving each sub-pixel to flip in the column flip driving mode, the voltage polarity of any two adjacent sub-pixel columns is the same. This is equivalent to realizing the display panel to flip in the frame flip mode. There is no voltage difference between adjacent sub-pixel columns, which further solves the problem of the influence of the electric field formed by the voltage difference on the transmittance and further improves the transmittance of the display panel.

[0042] It is understood that, in the above embodiments, as Figure 4 As shown, each sub-pixel column corresponds to one of the aforementioned data lines 10, and each sub-pixel 11 in the sub-pixel column is electrically connected to the second end of the corresponding data line 10. Except for the target data line 13, the other data lines 10 are not electrically connected to the driver chip through the aforementioned first inverter 15, but are directly electrically connected to the driver chip.

[0043] Among them, such as Figure 4 As shown, when the logic gate circuit includes the first inverter, when the input signal at the S1 terminal is high, the output at the B terminal is low, and when the input signal at the S1 terminal is low, the output at the B terminal is high. The input inversion method of the driver chip is column flipping, and the flipping method of the display panel is frame flipping, thereby achieving the function of improving transmittance.

[0044] Specifically, the aforementioned display panel further includes a display area and a non-display area surrounding the display area, with the first inverter located in the non-display area of ​​the display panel. This avoids the first inverter occupying the layout and wiring space of the display area, ensuring a high aperture ratio for the display panel.

[0045] like Figure 4 As shown, in the above logic gate circuit, there are multiple first inverters, and their specific number can be the same as the number of multiplexers.

[0046] In another alternative, such as Figure 5 As shown, the target structure includes the driver chip, and the target data line 13 is the data line 10 corresponding to the sub-pixel column located in an even-numbered column or an odd-numbered column. The odd-numbered column and the even-numbered column are the sub-pixel columns located in odd-numbered positions and the sub-pixel columns located in even-numbered positions along the first direction. Figure 5 This illustrates the arrangement of the data lines in a horizontal direction. Specifically, the first direction can be from horizontal left to horizontal right, or from horizontal right to horizontal left. Figure 5An exemplary illustration shows that the target data line 13 is the data line 10 corresponding to the sub-pixel column located in the odd-numbered column. The logic gate circuit includes a NAND gate 16, which has two input terminals and one output terminal. The first input terminal of the NAND gate 16 is electrically connected to the output terminal of the driver chip. The second input terminal of the NAND gate 16 is used to receive a first level signal. The output terminal of the NAND gate 16 is electrically connected to the first terminal of the target data line 13. When the driver chip outputs a driving signal to each sub-pixel 11 through each of the data lines 10, each of the sub-pixels 11 is flipped in the frame flipping mode.

[0047] In the above embodiments, the data lines corresponding to the sub-pixel columns located in one of the even-numbered and odd-numbered columns along the first direction are electrically connected to the driver chip through a NAND gate. By controlling the first level signal through the NAND gate, the voltage polarity of the sub-pixel column located in one of the even-numbered and odd-numbered columns can be changed so that it is the same as the voltage polarity of the other sub-pixel column located in the even-numbered and odd-numbered columns. That is to say, during the process of the driver chip driving each sub-pixel to flip in the column-flipping driving mode, the voltage polarity of any two adjacent sub-pixel columns is the same. This is equivalent to realizing the display panel to flip in the frame-flipping mode, with no voltage difference between adjacent sub-pixel columns. This further solves the problem of the influence of the electric field formed by the voltage difference on the transmittance and further improves the transmittance of the display panel.

[0048] Furthermore, in the above embodiments, by adjusting the first level signal, the flipping mode of the display panel can be changed from column flipping to frame flipping when the driver chip is driven in column driving mode, and the flipping mode of the display panel can be changed from frame flipping to column flipping when the driver chip is driven in column driving mode. This can satisfy both the high transmittance requirement and the high image quality requirement of the display panel.

[0049] It is understood that, in the above embodiments, as Figure 5 As shown, each sub-pixel column corresponds to one of the aforementioned data lines 10, and each sub-pixel 11 in the sub-pixel column is electrically connected to the second end of the corresponding data line 10. Except for the target data line 13, the other data lines 10 are not electrically connected to the driver chip through the aforementioned NAND gate 16, but are directly electrically connected to the driver chip.

[0050] Among them, such as Figure 5 As shown, when the logic gate circuit includes a NAND gate, when the input signal at the S1 terminal is high, the output terminal B can be high or low by controlling the input level of the second input terminal A of the NAND gate. This allows for switching between flipping modes, i.e., switching between column flipping and frame flipping. When high transmittance is required, the frame flipping mode can be selected, and when high image quality is required, the column flipping mode can be selected.

[0051] Furthermore, when the display panel needs to perform frame flipping, the first level signal includes a high level signal. When the first level signal is a high level signal, the level of the first input terminal of the NAND gate is opposite to the level of the output terminal, thereby further realizing that while the driver chip drives each sub-pixel to flip in a column-flipping driving mode, the display panel flips in a frame-flipping mode, thereby further avoiding the problem of poor transmittance of the display panel caused by high PPI.

[0052] Specifically, the aforementioned display panel also includes a display area and a non-display area surrounding the display area, with the NAND gate located in the non-display area of ​​the display panel. This avoids the NAND gate occupying the layout and wiring space of the display area, ensuring a high aperture ratio for the display panel.

[0053] like Figure 5 As shown, in the above logic gate circuit, there are multiple NAND gates, and their specific number can be the same as the number of multiplexers.

[0054] In another alternative, such as Figure 6 As shown, the target structure includes the driver chip, and the target data line 13 is the data line 10 corresponding to the sub-pixel column located in an even-numbered column or an odd-numbered column. The odd-numbered column and the even-numbered column are the sub-pixel columns located in odd-numbered positions and the sub-pixel columns located in even-numbered positions along the first direction. Figure 6 This illustrates the arrangement of the data lines in a horizontal direction. Specifically, the first direction can be from horizontal left to horizontal right, or from horizontal right to horizontal left. Figure 6 The target data line 13 is exemplarily shown as the data line 10 corresponding to the sub-pixel column located in the even-numbered column. The logic gate circuit includes a NOR gate 17, which has two input terminals and one output terminal. The first input terminal of the NOR gate 17 is electrically connected to the output terminal of the driver chip. The second input terminal of the NOR gate 17 is used to receive a second level signal. The output terminal of the NOR gate 17 is electrically connected to the first terminal of the target data line 13. When the driver chip outputs a driving signal to each sub-pixel 11 through each of the data lines 10, each sub-pixel 11 is flipped in the frame flipping mode.

[0055] In the above embodiments, the data lines corresponding to the sub-pixel columns located in one of the even-numbered and odd-numbered columns along the first direction are electrically connected to the driver chip through a NOR gate. Through the NOR gate, the voltage polarity of the sub-pixel column located in one of the even-numbered and odd-numbered columns can be changed so that it is the same as the voltage polarity of the other sub-pixel column located in the even-numbered and odd-numbered columns. That is, during the process of the driver chip driving each sub-pixel to flip in a column-flipping driving mode, the voltage polarity of any two adjacent sub-pixel columns is the same. This is equivalent to realizing the display panel flipping in a frame-flipping mode, with no voltage difference between adjacent sub-pixel columns. This further solves the problem of the influence of the electric field formed by the voltage difference on the transmittance and further improves the transmittance of the display panel.

[0056] Furthermore, in the above embodiments, by adjusting the second level signal, the flipping mode of the display panel can be changed from column flipping to frame flipping when the driver chip is driven in column driving mode, and the flipping mode of the display panel can be changed from frame flipping to column flipping when the driver chip is driven in column driving mode. This can satisfy both the high transmittance requirement and the high image quality requirement of the display panel.

[0057] It is understood that, in the above embodiments, as Figure 6 As shown, each sub-pixel column corresponds to one of the aforementioned data lines 10, and each sub-pixel 11 in the sub-pixel column is electrically connected to the second end of the corresponding data line 10. Except for the target data line 13, the other data lines 10 are not electrically connected to the driver chip through the aforementioned NOR gate 17, but are directly electrically connected to the driver chip.

[0058] Among them, such as Figure 6 As shown, when the logic gate circuit includes a NOR gate, when the S2 input signal is low, the output D of the NOR gate can be controlled by controlling the input level of the second input terminal C of the NOR gate. This allows for switching between flipping modes, i.e., switching between column flipping and frame flipping. When high transmittance is required, the frame flipping mode can be selected, and when high image quality is required, the column flipping mode can be selected.

[0059] Furthermore, when the display panel needs to perform frame flipping, the second level signal includes a low level signal. When the second level signal is a low level signal, the level of the first input terminal of the NOR gate is opposite to the level of the output terminal, thereby further realizing that while the driver chip drives each sub-pixel to flip in a column-flipping driving mode, the display panel flips in a frame-flipping mode, thereby further avoiding the problem of poor transmittance of the display panel caused by high PPI.

[0060] Specifically, the aforementioned display panel also includes a display area and a non-display area surrounding the display area, with the aforementioned NOR gate located in the non-display area of ​​the display panel. This avoids the NOR gate occupying the layout wiring space of the display area, ensuring a high aperture ratio for the display panel.

[0061] like Figure 6 As shown, in the above logic gate circuit, there are multiple NOR gates, and their specific number can be the same as the number of multiplexers.

[0062] In another alternative, such as Figure 7 As shown, the multiple data lines 10 are all target data lines 13. The target structure includes the target sub-pixel 14. The other sub-pixels 11 besides the target sub-pixel 14 are arranged alternately with the target sub-pixel 14 in the first direction and the second direction, respectively. That is, the target sub-pixel 14 and the other sub-pixels 11 are arranged in a checkerboard pattern. The logic gate circuit includes a second inverter 18. The output terminal of the second inverter 18 is electrically connected to the target sub-pixel 14. The input terminal of the second inverter 18 is electrically connected to the second end of the target data line 13 corresponding to the target sub-pixel 14. When the driver chip outputs a drive signal to each sub-pixel 11 through each data line 10, each sub-pixel 11 is flipped in the row flipping mode.

[0063] In the above embodiment, the target sub-pixel in the display panel is arranged in a checkerboard pattern with other sub-pixels. By setting a second inverter between the data line and the corresponding target sub-pixel, the voltage polarity of the target sub-pixel can be changed, so that the voltage polarity of the target sub-pixel is the same as that of the adjacent sub-pixels along the row direction. That is, when the driving chip drives each sub-pixel to flip in a column-flip driving mode, the voltage polarity of any two adjacent sub-pixel columns in the row direction is the same. This is equivalent to realizing the display panel to flip in a row-flip mode, and there is no voltage difference between adjacent sub-pixel columns in the row direction. This further solves the problem of the influence of the electric field formed by the voltage difference on the transmittance, and further improves the transmittance of the display panel.

[0064] It is understood that, in the above embodiments, as Figure 7 As shown, each sub-pixel column corresponds to one of the aforementioned data lines 10, and each sub-pixel 11 in the sub-pixel column is electrically connected to the second end of the corresponding data line 10. Except for the target sub-pixel 14, the other sub-pixels 11 are not electrically connected to the corresponding data line 10 through the aforementioned second inverter 18, but are directly electrically connected to the aforementioned data line 10.

[0065] like Figure 7As shown, in the above logic gate circuit, there are multiple second inverters, and their specific number is the same as the number of target sub-pixels.

[0066] Furthermore, the aforementioned display panel also includes a display area and a non-display area surrounding the display area. The aperture ratio requirement of the aforementioned display panel is not high, and the aforementioned second inverter is located in the display area of ​​the aforementioned display panel.

[0067] According to some other exemplary embodiments of this application, such as Figure 8 As shown, the target structure includes the driver chip, with one sub-pixel column corresponding to two data lines, namely a first data line 19 and a second data line 20. Along the first direction, each pair of adjacent sub-pixel columns forms a pixel group, and in the pixel group located in the odd-numbered columns along the first direction, the first data line 19 is electrically connected to the sub-pixel 11 located in the odd-numbered position along the second direction in the corresponding sub-pixel column, and the second data line 20 is electrically connected to the sub-pixel 11 located in the even-numbered position along the second direction in the corresponding sub-pixel column. In the pixel group located in the even-numbered columns along the first direction, the... The first data line 19 is electrically connected to the sub-pixel 11 located at the even position in the corresponding sub-pixel column, and the second data line 20 is electrically connected to the sub-pixel 11 located at the odd position in the corresponding sub-pixel column. The target data line 13 is the first data line 19. The logic gate circuit includes a third inverter 21. The output terminal of the third inverter 21 is electrically connected to the first terminal of the target data line 13, and the input terminal of the third inverter 21 is electrically connected to the output terminal of the driver chip. When the driver chip outputs a driving signal to each sub-pixel 11 through each of the data lines, each sub-pixel 11 is flipped in the row flipping mode.

[0068] in, Figure 8 The diagram illustrates a configuration where the data lines are arranged horizontally and extend vertically. Specifically, the first direction can be from horizontal left to horizontal right, or from horizontal right to horizontal left. The second direction can be from the data lines to the driver chip, or from the driver chip to the data lines.

[0069] In the above embodiment, along the first direction, adjacent sub-pixel columns are divided into two pixel column groups. By setting the odd-numbered sub-pixels in the sub-pixel columns corresponding to the first data line in the odd-numbered pixel column groups to be connected to the first data line, and setting the even-numbered sub-pixels in the sub-pixel columns corresponding to the first data line in the even-numbered pixel column groups to be connected to the first data line, these sub-pixels are electrically connected to the driving chip through the first data line and the third inverter in sequence. This changes the voltage polarity of the sub-pixels electrically connected to the first data line, so that the voltage polarity of any two adjacent sub-pixels along the row direction is the same. That is, during the process of the driving chip driving each sub-pixel to flip in the column flip driving mode, the voltage polarity of any two adjacent sub-pixel columns in the row direction is the same. This is equivalent to realizing the display panel to flip in the row flip mode. There is no voltage difference between adjacent sub-pixel columns in the row direction, which further solves the problem of the influence of the electric field formed by the voltage difference on the transmittance, and further improves the transmittance of the display panel.

[0070] In one specific embodiment, the target data line is the first data line, and the target sub-pixel is a sub-pixel electrically connected to the first data line. The first ends of the other data lines besides the target data line are directly electrically connected to the driver chip, while the target data line is electrically connected to the driver chip through the logic gate circuit, namely the third inverter. Each sub-pixel is directly electrically connected to the second end of its corresponding data line.

[0071] It is understood that, in the above embodiments, as Figure 8 As shown, each sub-pixel column corresponds to two data lines, namely a first data line 19 and a second data line 20. When the sub-pixel column corresponding to the first data line 19 is located in an odd-numbered column group along the first direction, the second end of the first data line 19 is electrically connected to the sub-pixel 11 located in an odd-numbered column along the second direction in the corresponding sub-pixel column; when the sub-pixel column corresponding to the first data line 19 is located in an even-numbered column group along the first direction, the second end of the first data line 19 is electrically connected to the sub-pixel 11 located in an even-numbered column along the second direction in the corresponding sub-pixel column, while the first end of each first data line 19 is connected to the driver chip via a third inverter 21; in the case of the second data line... When the sub-pixel column corresponding to 20 is located in an odd-numbered column group along the first direction, the second end of the second data line 20 is electrically connected to the sub-pixel 11 located in an even-numbered column along the second direction in the corresponding sub-pixel column; when the sub-pixel column corresponding to the second data line 20 is located in an even-numbered column group along the first direction, the second end of the second data line 20 is electrically connected to the sub-pixel 11 located in an odd-numbered column along the second direction in the corresponding sub-pixel column, and the first end of each second data line 20 is not electrically connected to the driver chip through the third inverter 21, but is directly electrically connected to the driver chip.

[0072] like Figure 8 As shown, when the logic gate circuit includes a third inverter, when the input signal at the S1 terminal is high, the output of the third inverter is low, causing the voltage polarity of the sub-pixel electrically connected to the first data line to be low, and the voltage polarity of the sub-pixel electrically connected to the second data line to be high; when the input signal at the S1 terminal is low, the output of the third inverter is high, causing the voltage polarity of the sub-pixel electrically connected to the first data line to be high, and the voltage polarity of the sub-pixel electrically connected to the second data line to be low. After passing through the third inverter, the voltage polarity of the sub-pixels in the same row is the same. Thus, the inversion method of the driver chip's input is column flipping, and the flipping method of the display panel is row flipping, achieving the function of improving transmittance.

[0073] In the embodiments of this application, the display panel further includes a display area and a non-display area surrounding the display area, with the third inverter located in the non-display area. While placing a second inverter between the data lines and sub-pixels in the display area helps improve the overall transmittance of the display panel, its placement in the display area may affect the aperture ratio of high-PPI display panels. In this embodiment, the third inverter is located in the non-display area, further ensuring high transmittance of the display panel while avoiding any impact on its aperture ratio, thus further ensuring better overall display performance.

[0074] like Figure 8 As shown, in the above logic gate circuit, there are multiple third inverters, and their specific number can be the same as the number of multiplexers.

[0075] In practical applications, the aforementioned first data line can be configured in a one-to-one correspondence with the aforementioned third inverter, or in a one-to-many configuration. To improve the transmittance of the display panel while ensuring the narrow bezel design requirements, some other exemplary solutions in this application, such as... Figure 8As shown, each pixel column group corresponds to two first data lines 19 and two second data lines 20. The first ends of all the second data lines 20 in a pixel column group are electrically connected. The first ends of the multiple electrically connected second data lines serve as a common terminal, that is, the first ends of the two second data lines 20 in each pixel column group are electrically connected and serve as a common terminal, which is connected to the driver chip. The output terminal of the third inverter is connected to the first ends of all the first data lines 19 in a pixel column group. That is, the third inverter 21 corresponds one-to-one with the pixel column group. The first ends of the two first data lines 19 in each pixel column group are electrically connected and electrically connected to the output terminal of the corresponding third inverter 21. The input terminal of the third inverter 21 is electrically connected to the output terminal of the driver chip through the corresponding common terminal. That is, the input terminal of the third inverter 21 is electrically connected to the common terminal and then electrically connected to the output terminal of the driver chip. Compared to the one-to-one connection between the first data line and the third inverter, in this embodiment, one pixel column corresponds to one third inverter, which reduces the number of third inverters and thus reduces the space occupied by the third inverter in the non-display area, thereby facilitating narrow bezel design.

[0076] In practical applications, the subpixels in the aforementioned display panel are arranged in an array. To facilitate wiring, the data lines can be correspondingly positioned on one side of the corresponding subpixel column. Specifically, the data lines can be positioned on the same side of the corresponding subpixel column, or they can be positioned on different sides of the corresponding subpixel column. Figures 4 to 8 The example shown illustrates the case where all the data lines are located to the left of the corresponding sub-pixel column. Of course, the data lines can also be located to the right of the corresponding sub-pixel column, or some of the data lines can be located on one side of the corresponding sub-pixel column, while the remaining data lines can be located on the other side, etc.

[0077] It should be noted that the features of the above embodiments can be combined with each other. For example, in some embodiments, the logic gate circuit includes a first inverter and a second inverter, with a portion of the target data lines electrically connected to the driver chip through the first inverter, and the remaining portion of the target data lines electrically connected to the target sub-pixel through the second inverter. In other embodiments, the logic gate circuit may also include at least two of a first inverter, a NAND gate, and a NOR gate, etc.

[0078] Embodiments of this application also provide a method such as Figure 9 The display device shown includes any of the above-described display panels.

[0079] Through the above embodiments, the display device includes any of the above-mentioned display panels. A logic gate circuit is provided between the data lines and the driving chip in the display panel, or between the data lines and the sub-pixels. The voltage polarity of some sub-pixels in the sub-pixel array is changed by the logic gate circuit, so that the driving chip with column flip driving as the driving method can realize row flipping or frame flipping of the display panel. This eliminates the voltage difference between adjacent sub-pixels in the row direction, solves the influence of the voltage difference between adjacent sub-pixels on the transmittance in the column flip mode, ensures that the transmittance of the display panel is high, and thus ensures that the display performance of the display device is good.

[0080] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0081] As can be seen from the above description, the embodiments of this application achieve the following technical effects:

[0082] 1) The display panel of this application sets a logic gate circuit between the data line and the driver chip, or sets a logic gate circuit between the data line and the sub-pixel. The logic gate circuit changes the voltage polarity of some sub-pixels in the sub-pixel array, so that the driver chip with column flip driving as the driving method can realize row flip or frame flip of the display panel, eliminate the voltage difference between adjacent sub-pixels in the row direction, solve the influence of the voltage difference between adjacent sub-pixels on the transmittance in the column flip mode, and ensure that the transmittance of the display panel is high.

[0083] 2) The display device of this application includes any of the above-mentioned display panels. A logic gate circuit is provided between the data line and the driving chip in the display panel, or a logic gate circuit is provided between the data line and the sub-pixel. The voltage polarity of some sub-pixels in the sub-pixel array is changed by the logic gate circuit, so that the driving chip with column flip driving as the driving mode can realize row flip or frame flip of the display panel. This eliminates the voltage difference between adjacent sub-pixels in the row direction, solves the influence of the voltage difference between adjacent sub-pixels on the transmittance in the column flip mode, ensures that the transmittance of the display panel is high, and thus ensures that the display device has good display performance.

[0084] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A display panel, characterized in that, include: The driving chip is driven by column flipping; Multiple data lines are arranged at intervals along a first direction and extend along a second direction, the first direction intersects the second direction, and the first end of the multiple data lines is electrically connected to the output end of the driver chip; Multiple sub-pixels are arranged in an array along the first direction and the second direction. Sub-pixels located in the same column along the second direction constitute a sub-pixel column. A sub-pixel column corresponds to at least one data line. The second end of the data line is electrically connected to at least a portion of the sub-pixels in the corresponding sub-pixel column. A logic gate circuit is provided, through which the target data line is electrically connected to the target structure. The logic gate circuit is used to change the polarity of the voltage transmitted to the target sub-pixel, so that each sub-pixel is flipped in a row-flipping mode or a frame-flipping mode. The target structure includes the driver chip or the target sub-pixel. The target data line is at least one of a plurality of data lines, and the plurality of sub-pixels include the target sub-pixel.

2. The display panel according to claim 1, characterized in that, The target structure includes the driving chip, the target data line is the data line corresponding to the sub-pixel column located in an even column or an odd column along the first direction, and the logic gate circuit includes: A first inverter, the input of which is electrically connected to the output of the driver chip, and the output of which is electrically connected to the first end of the target data line, wherein when the driver chip outputs a driving signal to each sub-pixel through each of the data lines, each sub-pixel is flipped in the frame flipping mode.

3. The display panel according to claim 1, characterized in that, The target structure includes the driving chip, the target data line is the data line corresponding to the sub-pixel column located in an even column or an odd column along the first direction, and the logic gate circuit includes: The NAND gate has its first input terminal electrically connected to the output terminal of the driver chip, its second input terminal used to receive a first level signal, and its output terminal electrically connected to the first terminal of the target data line. When the driver chip outputs a driving signal to each sub-pixel through each of the data lines, each sub-pixel is flipped in the frame flipping mode.

4. The display panel according to claim 3, characterized in that, The first level signal includes a high level signal.

5. The display panel according to claim 1, characterized in that, The target structure includes the driving chip, the target data line is the data line corresponding to the sub-pixel column located in an even column or an odd column along the first direction, and the logic gate circuit includes: The NOR gate has its first input terminal electrically connected to the output terminal of the driver chip, its second input terminal used to receive a second level signal, and its output terminal electrically connected to the first terminal of the target data line. When the driver chip outputs a driving signal to each sub-pixel through each of the data lines, each sub-pixel is flipped in the frame flipping mode.

6. The display panel according to claim 5, characterized in that, The second level signal includes a low level signal.

7. The display panel according to claim 1, characterized in that, Multiple data lines are all target data lines. The target structure includes the target sub-pixel. Other sub-pixels besides the target sub-pixel are alternately arranged with the target sub-pixel in the first direction and the second direction, respectively. The logic gate circuit includes: The second inverter has its output terminal electrically connected to the target sub-pixel and its input terminal electrically connected to the second end of the target data line corresponding to the target sub-pixel. When the driving chip outputs driving signals to each sub-pixel through each of the data lines, each sub-pixel is flipped in the row flipping mode.

8. The display panel according to claim 7, characterized in that, The second inverter is located in the display area of ​​the display panel.

9. The display panel according to claim 1, characterized in that, The target structure includes the driving chip, where each sub-pixel column corresponds to two data lines, namely a first data line and a second data line. Along the first direction, every two adjacent sub-pixel columns form a pixel column group. In the pixel column group located in the odd-numbered columns along the first direction, the first data line is electrically connected to the sub-pixel in the corresponding sub-pixel column located in the odd-numbered position along the second direction, and the second data line is electrically connected to the sub-pixel in the corresponding sub-pixel column located in the even-numbered position along the second direction. In the pixel column group located in the even-numbered columns along the first direction, the first data line is electrically connected to the sub-pixel in the corresponding sub-pixel column located in the even-numbered position, and the second data line is electrically connected to the sub-pixel in the corresponding sub-pixel column located in the odd-numbered position. The target data line is the first data line. The logic gate circuit includes: The third inverter has its output terminal electrically connected to the first terminal of the target data line and its input terminal electrically connected to the output terminal of the driver chip. When the driver chip outputs a driving signal to each sub-pixel through each of the data lines, each sub-pixel is flipped in the row flipping mode.

10. The display panel according to claim 9, characterized in that, The first ends of all the second data lines in a pixel column are electrically connected, and the first ends of the multiple electrically connected second data lines serve as a common terminal. The output terminal of a third inverter is correspondingly connected to the first ends of all the first data lines in a pixel column, and the input terminal of a third inverter is electrically connected to the output terminal of the driver chip through the corresponding common terminal.

11. The display panel according to claim 9, characterized in that, The third inverter is located in the non-display area of ​​the display panel.

12. The display panel according to any one of claims 1 to 11, characterized in that, The first end of all data lines other than the target data line is directly electrically connected to the driver chip.

13. The display panel according to any one of claims 1 to 11, characterized in that, The display panel also includes: Multiple multiplexers are provided, and the driver chip is electrically connected to the data lines through the multiplexers. Each multiplexer corresponds to at least two data lines.

14. A display device, characterized in that, include: The display panel according to any one of claims 1 to 13.

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