Vertical channel reconfigurable transistor and method of manufacturing the same

Abstract

The application discloses a vertical channel type reconfigurable transistor and a preparation method thereof. The transistor mainly comprises a drain electrode, a vertical channel layer, a gate dielectric layer, a programming electrode, a control electrode, a source electrode and a silicon substrate. The vertical channel layer is directly arranged on the silicon substrate. The upper end of the vertical channel layer extends along the horizontal direction to form an upper end extension. The programming electrode and the control electrode are arranged between the upper end extension of the vertical channel layer and the silicon substrate, and are isolated from each other and connected with the vertical part of the vertical channel layer through the gate dielectric layer. The source electrode and the drain electrode are in Schottky contact to realize the reconfigurable function. The structure of the vertical channel layer and the gate dielectric layer realizes the integration of the device in a smaller area. The programming electrode is used for regulating the carrier type in the vertical channel layer, the working mode of the device can be regulated, and the control electrode is used for regulating the concentration of the conduction charge in the vertical channel.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor technology, and particularly relates to a vertical channel reconfigurable transistor and a preparation method thereof. BACKGROUND

[0002] Reconfigurable transistors are considered as one of the most potential solutions for integrated circuit device to solve this problem due to their dynamic reconfigurable characteristics. However, the scaling of integrated circuits in the post-Moore era has faced physical limits, and traditional transistors usually need a larger size to achieve the required function. Due to the limitation of gate length, the limited space limits the integration of integrated circuits and the miniaturization and integration of transistors, and further improves the operating speed. SUMMARY

[0003] In order to overcome the above-mentioned shortcomings of the prior art, in view of the large amount of information storage and processing demand generated by the development of integrated circuits, the purpose of the present application is to provide a vertical channel reconfigurable transistor and a preparation method thereof. By adopting a vertical channel structure, a plurality of gates are used to control the channel carriers, and the bipolarity of the Schottky barrier is utilized to realize the dynamic switching of N-type and P-type under the structure device, thereby improving the integration and performance of the transistor.

[0004] The present application adopts a vertical channel structure and introduces a reconfigurable function. The vertical channel structure is an effective design method to release the space limitation of the device in the horizontal direction, and is suitable for field effect tubes with a node technology of 5nm or more. By combining the reconfigurable transistor with the vertical channel structure design, the vertical channel reconfigurable transistor formed has better scalability, can further reduce the circuit area of the device, thereby realizing higher integration and better performance, and is expected to become an ideal device that breaks through the limitations of traditional technology, and provides a new technical route for future high-density and high-performance circuit applications.

[0005] In order to achieve the above-mentioned purpose, the technical scheme adopted by the present application is:

[0006] A vertical channel reconfigurable transistor, comprising a drain electrode, a vertical channel layer, an isolation oxide layer, a gate dielectric layer, a programming electrode, a control electrode, a source electrode and a silicon substrate;

[0007] The vertical channel layer is arranged on the silicon substrate, and the upper end thereof extends in the horizontal direction. The programming electrode and the control electrode are isolated from each other by the isolation oxide layer, and are arranged between the upper end extension of the vertical channel layer and the silicon substrate, and between the vertical part of the vertical channel layer with the gate dielectric layer.

[0008] The programming electrode is used to control the type of carriers in the vertical channel layer, thereby controlling the working mode of the device. The control electrode is used to control the concentration of the conduction charge in the vertical channel.

[0009] In one embodiment, the upper and lower ends of the vertical channel layer extend along the same side in the horizontal direction, the programming end electrode and the control end electrode are arranged between the upper and lower end extensions of the vertical channel layer, the drain end electrode is arranged at the upper end extension of the vertical channel layer, and the source end electrode is arranged at the lower end extension of the vertical channel layer or on the silicon substrate.

[0010] In one embodiment, the programming end electrode, the control end electrode, and the upper and lower end extensions are each isolated by an isolation oxide layer.

[0011] In one embodiment, a stack-shaped accumulation structure formed by a plurality of isolation oxide layers and a plurality of metal layers is arranged between the upper and lower end extensions of the vertical channel layer, a part of the metal layers serving as the programming end electrode or leading out the programming end electrode, and another part of the metal layers serving as the control end electrode or leading out the control end electrode.

[0012] In one embodiment, a passivation layer is arranged between the upper end extension of the vertical channel layer and the uppermost isolation oxide layer of the stack-shaped accumulation structure.

[0013] In one embodiment, the source end electrode and the drain end electrode are in Schottky contact, providing an electron and hole tunneling barrier with a difference within 0.2 eV, and realizing reconfigurable functions.

[0014] In one embodiment, the vertical channel layer is made of a lightly doped or intrinsic semiconductor.

[0015] When the source end electrode is grounded and the drain end electrode is connected to a forward voltage, the device is adjusted to an N-type: a forward voltage is applied to the programming end electrode, the control end electrode is grounded, a positive electric field generated near the surface of the vertical channel layer attracts free electrons nearby, so that the accumulation of electrons in the vertical channel layer increases, thereby making the device realize N-type doping; a forward voltage is applied to the control end electrode, corresponding to the accumulation of electrons in the vertical channel layer, and under the joint action of the programming end voltage, the channel presents a low resistance state, and the device is turned on as an N-FET.

[0016] When the source end electrode is grounded and the drain end electrode is connected to a reverse voltage, the device is adjusted to a P-type: a reverse voltage is applied to the programming end electrode, the control end electrode is grounded, a negative electric field generated near the surface of the vertical channel layer attracts free holes nearby, so that the accumulation of holes in the vertical channel layer increases, thereby making the device realize P-type doping; a reverse voltage is applied to the control end electrode, corresponding to the accumulation of holes in the vertical channel layer, and under the joint action of the programming end voltage, the channel presents a low resistance state, and the device is turned on as a P-FET.

[0017] In one embodiment, the material of the drain electrode, the programming electrode, the control electrode, and the source electrode is any one of tungsten, titanium, copper, aluminum, platinum, iridium, ruthenium, molybdenum, tungsten nitride, titanium nitride, tungsten silicide, titanium silicide, and tantalum silicide;

[0018] The vertical channel layer is any one of Si, SiGe, GaN, GaO, GaAs, In2O3, ZnO, SnO, IGZO, and SiC;

[0019] The material of the gate dielectric layer is any one of SiO2, Si3N4, TiO2, Nb2O5, HZO, HSO, HAO, HLO, ZnSnO3, HZO, AlScN, HfO2, HYO, BFO, PZT, BST, ZrO2.

[0020] The application also provides a preparation method of the vertical channel reconfigurable transistor, comprising the following steps:

[0021] Step 1, using etching and deposition processes to form a source contact region on a silicon substrate;

[0022] Step 2, using deposition and sputtering processes to form mutually isolated programming electrodes and control electrodes above the source contact region;

[0023] Step 3, using etching to etch a vertical columnar hole in the structure above the source contact region;

[0024] Step 4, using deposition to deposit a dielectric material in the vertical columnar hole to form a gate dielectric layer, and then depositing a channel material to form a vertical channel layer;

[0025] Step 5, using sputtering to form a source electrode and a drain electrode.

[0026] In one embodiment, the step 2 is to first deposit an isolation oxide layer above the source contact region, and then sputter a metal layer, and the isolation oxide layer and the metal layer are alternately stacked to form a stack structure, or first deposit a lower end extension of the vertical channel layer above the source contact region, and then deposit an isolation oxide layer and a metal layer, and the isolation oxide layer and the metal layer are alternately stacked to form a stack structure; the step 3 is to etch the vertical columnar hole in the stack structure; the step 4 is to deposit a passivation layer above the stack structure, and then deposit an isolation oxide layer to fill the columnar hole after forming the vertical channel layer; and the step 5 is to use etching to remove the excess source-drain contact and gate stack.

[0027] Compared with existing technologies, this invention fully utilizes the advantages of vertically stacked transistors, resulting in a more compact device structure and enabling higher integration within a given area. By changing the electrical signal applied to the programming electrode, the carrier type within the vertical channel layer is controlled, thereby regulating the device's operating mode. Furthermore, this invention features lower operating voltage and better current characteristics, facilitating the development of higher-performance reconfigurable devices. It represents an ideal device for overcoming traditional technological limitations, providing a new technical route for future high-density, high-computing-power circuit applications. Attached Figure Description

[0028] Figure 1 This is a schematic diagram of the structure of the vertical channel reconfigurable transistor of the present invention.

[0029] Figure 2 This is a schematic diagram of the fabrication process for a vertical channel reconfigurable transistor.

[0030] In the figure: 1. Drain electrode, 2. Vertical channel layer, 3. Isolation oxide layer, 4. Gate dielectric layer, 5. Passivation layer, 6. Programming electrode, 7. Control electrode, 8. Source electrode, 9. Silicon substrate. Detailed Implementation

[0031] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention are within the scope of protection of the present invention.

[0032] like Figure 1 As shown, the vertical channel reconfigurable transistor of the present invention mainly includes a drain electrode 1, a vertical channel layer 2, an isolation oxide layer 3, a gate dielectric layer 4, a programming electrode 6, a control electrode 7, a source electrode 8, and a silicon substrate 9.

[0033] The vertical channel layer 2 is directly disposed on the silicon substrate 9. To accommodate the drain electrode 1, the upper end of the vertical channel layer 2 extends horizontally, forming an upper extension. The programming electrode 6 and the control electrode 7 are disposed between the upper extension of the vertical channel layer 2 and the silicon substrate 9, isolated from each other, and connected to the vertical portion of the vertical channel layer 2 by a gate dielectric layer 4.

[0034] The drain electrode 1 is disposed at the upper extension of the vertical channel layer 2. The source electrode 8 and the drain electrode 1 are in Schottky contact, which can provide an electron and hole tunneling barrier with a difference of less than 0.2 eV, thereby realizing the reconfigurable function.

[0035] The structure of the vertical channel layer 2 and the gate dielectric layer 4 realizes the integration of the device in a smaller area, wherein the vertical channel layer 2 can be selected from intrinsic semiconductor, P-type lightly doped semiconductor or N-type lightly doped semiconductor, and specifically, the material of the vertical channel layer 2 can be any one of Si, SiGe, GaN, GaAs, GaO, In2O3, ZnO, SnO, IGZO and SiC.

[0036] The application can control the working mode of the device by regulating the carrier type in the vertical channel layer 2 through the programming end electrode 6, and can control the concentration of the conduction charge in the vertical channel 2 by controlling the control end electrode 7.

[0037] Specifically, referring to Figure 2 The principle of the vertical channel type reconfigurable transistor under the regulation of different electrical signals is as follows:

[0038] When the source end electrode 8 is grounded and the drain end electrode 1 is connected to a forward voltage, the working state of the device is adjusted to N-type: a forward voltage is applied to the programming end electrode 6, the control end electrode 7 is grounded, and the positive electric field generated near the surface of the vertical channel layer 2 attracts the free electrons nearby, so that the accumulation of electrons in the vertical channel layer 2 increases, thereby realizing N-type doping of the device; a forward voltage is applied to the control end electrode 7 (at this time, when the gate dielectric layer 4 is a non-ferroelectric material, the programming end electrode 6 applies a forward voltage; when the gate dielectric layer 4 is a ferroelectric material, the programming end electrode 6 can not apply a voltage), which corresponds to the accumulation of electrons in the vertical channel layer 2, and under the joint action of the programming end electrode 6, the channel presents a low resistance state, and the device is turned on as an N-FET.

[0039] When the source end electrode 8 is grounded and the drain end electrode 1 is connected to a reverse voltage, the working state of the device is adjusted to P-type: a reverse voltage is applied to the programming end electrode 6, the control end electrode 7 is grounded, and the negative electric field generated near the surface of the vertical channel layer 2 attracts the free holes nearby, so that the accumulation of holes in the vertical channel layer 2 increases, thereby realizing P-type doping of the device; a reverse voltage is applied to the control end electrode 7 (at this time, when the gate dielectric layer 4 is a non-ferroelectric material, the programming end electrode 6 applies a reverse voltage; when the gate dielectric layer 4 is a ferroelectric material, the programming end electrode 6 can not apply a voltage), which corresponds to the accumulation of holes in the vertical channel layer 2, and under the joint action of the programming end electrode 6, the channel presents a low resistance state, and the device is turned on as a P-FET.

[0040] The gate dielectric layer 4 plays a role of isolation between the gate and the channel, prevents direct contact between the gate and the channel, and can ensure that the gate stably controls the channel current. The material of the gate dielectric layer 4 can be any one of SiO2, Si3N4, TiO2, Nb2O5, HZO, HSO, HAO, HLO, ZnSnO3, HYO, BFO, PZT, BST and ZrO2.

[0041] According to the above structure and working mechanism, the vertical channel reconfigurable transistor has the advantages of good current characteristics and low working voltage.

[0042] In summary, the small area of the vertical channel can realize higher integration of the device; by applying an electrical signal to the programming electrode, the type of carriers in the vertical channel layer can be controlled, thereby controlling the working mode of the device, and by applying a direct current signal to the control electrode, the concentration of the conduction charge in the vertical channel layer can be controlled; and a single device can realize good current characteristics, low working voltage, etc., and has the significant advantage of reconfiguration.

[0043] The present application takes advantage of the vertical channel, breaks through the traditional device process node, and realizes the integration of the device in a small area; by applying an electrical signal to the programming electrode, the type of carriers in the vertical channel layer can be controlled, thereby controlling the working mode of the device, and by applying a direct current signal to the control electrode, the concentration of the conduction charge in the vertical channel layer can be controlled; by using the bipolarity of the source-drain contact Schottky barrier, dynamic switching of N-type and P-type on the same device can be realized, and the reconfigurable characteristic is possessed. Secondly, the present application has low working voltage and good current characteristics, which is helpful for developing higher performance reconfigurable devices, and becomes an ideal device that breaks through the limitation of traditional technology, and provides a new technical route for future high-density and high-performance circuit applications.

[0044] In an embodiment of the present application, the upper and lower ends of the vertical channel layer 2 extend along the same side in the horizontal direction, respectively forming an upper end extension and a lower end extension, the programming electrode 6 and the control electrode 7 are arranged between the upper and lower end extensions of the vertical channel layer 2, and the source electrode 8 can be arranged on the lower end extension of the vertical channel layer 2 or on the silicon substrate 9.

[0045] The upper and lower end extensions can increase the control area of the source-drain electrode, which is more conducive to controlling the movement of channel carriers.

[0046] In an embodiment of the present application, the programming electrode 6 and the control electrode 7 are isolated by the isolation oxide layer 3, and the programming electrode 6 or the control electrode 7 is also isolated from the upper end extension or the lower end extension by the isolation oxide layer 3.

[0047] In an embodiment of the present application, a stack structure is arranged between the upper and lower end extensions of the vertical channel layer 2 or between the upper end extension of the vertical channel layer 2 and the silicon substrate 9. The stack structure is formed by a plurality of isolation oxide layers 3 and a plurality of metal layers stacked in sequence, wherein a part of the metal layers are used as the programming electrode 6 or lead out the programming electrode 6, and another part of the metal layers are used as the control electrode 7 or lead out the control electrode 7.

[0048] The embodiment adopts a stack structure, which comprises a plurality of layers of gate metal and gate isolation oxide layer stacked from top to bottom in sequence, and is located beside the vertical channel layer, thereby facilitating the control of the gate metal.

[0049] In the embodiment, the number of the programming end electrode 6 and the control end electrode 7 is not limited, and the relative position relationship between the two is not limited, as long as the two are isolated from each other and connected to the vertical channel layer 2 through the gate dielectric layer 4.

[0050] In an embodiment of the present application, a passivation layer 5 is arranged between the upper end extension of the vertical channel layer 2 and the isolation oxide layer 3 of the uppermost layer of the stack structure. The material of the passivation layer 5 is any one of Al2O3, SiO2, SiON, HfON, TiON and ZrON, and the passivation layer 5 functions to inhibit the irregular growth of the oxide layer during the deposition process and reduce defects and interface trap charges.

[0051] In an embodiment of the present application, the smaller area of the vertical channel can achieve higher integration of the device, and the present application can process a plurality of devices on the same silicon substrate 9, i.e., a plurality of vertical channel layers 2 are arranged on the same silicon substrate 9, and the adjacent vertical channel layers 2 and even the adjacent devices are isolated by the isolation oxide layer 3.

[0052] In the present application, the drain end electrode 1, the programming end electrode 6, the control end electrode 7 and the source end electrode 8 are all made of metal materials. Specifically, the materials of the drain end electrode 1, the programming end electrode 6, the control end electrode 7 and the source end electrode 8 are any one of tungsten, titanium, copper, aluminum, platinum, iridium, ruthenium, molybdenum, tungsten nitride, titanium nitride, tantalum nitride, iridium oxide, ruthenium oxide, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide and tantalum silicide.

[0053] Referring to Figure 2 The present application also includes a preparation method of the vertical channel type reconfigurable transistor, which comprises the following specific steps:

[0054] Step 1: using etching and deposition processes to form a source contact region on the silicon substrate 9.

[0055] Step 2: using deposition and sputtering processes to form the programming end electrode 6 and the control end electrode 7 which are isolated from each other above the source contact region.

[0056] Specifically, a layer of isolation oxide layer 3 can be first deposited and then a layer of metal can be sputtered to form the stack structure by alternately stacking the two in sequence. Alternatively, a lower end extension of the vertical channel layer 2 can be first deposited, and then a layer of isolation oxide layer 3 and a layer of metal can be deposited to form the stack structure by alternately stacking the two in sequence.

[0057] Step 3, etching vertical columnar holes in the structure above the source contact area by etching process.

[0058] Specifically, when the stack structure is prepared in Step 2, the vertical columnar holes are etched in the stack structure.

[0059] Step 4, depositing dielectric material in the vertical columnar holes to form gate dielectric layer 4, and then depositing channel material to form vertical channel layer 2 by deposition process.

[0060] Specifically, after forming the gate dielectric layer 4, a passivation layer 5 is deposited on the stack structure, and then the channel material is deposited to form the vertical channel layer 2; and after forming the vertical channel layer 2, the columnar holes are filled with the isolation oxide layer 3, and finally the excess isolation oxide layer is etched away.

[0061] The vertical channel layer 2 formed in the vertical columnar holes in this step connects the metal electrode to the vertical channel layer 2, reduces the area of the device in the horizontal direction, and the vertical structure has higher integration in unit area.

[0062] Step 5, forming source electrode 8 and drain electrode 1 by sputtering process.

[0063] Specifically, the excess source and drain contact and gate stack can be removed by etching process first; then thin layer of electrode material is deposited on the gate and source and drain contact area by sputtering process to form control electrode 7, programming electrode 6, source electrode 8 and drain electrode 1.

[0064] The following gives three specific embodiments of the preparation methods of vertical channel type reconfigurable transistors based on different materials.

[0065] The gate dielectric layer 4 is made of TiO2, the vertical channel layer 2 is made of polysilicon, and the materials of the programming electrode 6, control electrode 7, source electrode 8 and drain electrode 1 are made of metal tungsten, and the specific preparation method is as follows:

[0066] Step 1: depositing and forming a source contact area on the substrate by etching process and deposition process.

[0067] Step 2: depositing SiO2 on the channel layer 2 to form an oxide layer 3, and sputtering an electrode material on the oxide layer 3 to form a stack structure alternately.

[0068] In this step, a molecular pump or a cold pump is used to vacuum the reaction chamber until the vacuum pressure in the reaction chamber reaches 0.02 Torr, and then a layer of metal W is deposited on the surface of the oxide layer 3 by uniform sputtering of metal W as target material under the condition of sputtering power of 350 W and argon pressure of 5 mTorr, forming a stack structure.

[0069] Step three: etching vertical columnar hole by etching process;

[0070] In this step, the center part of the stack accumulation layer is etched to the substrate surface by dry etching process to form a vertical columnar hole.

[0071] Step four: depositing dielectric material to form gate dielectric layer 4, and depositing a layer of passivation layer 5 above the stack accumulation, depositing polysilicon to form vertical channel layer 2, and then depositing isolation oxide layer to fill the columnar hole;

[0072] In this step, atomic layer deposition process is used, with ion water as oxygen source and tetraethyl methyl amino titanium (TEMATi) as titanium precursor source, the temperature is raised to 573K; TiO2 material thin film with Zr component of 0.5 is grown on the surface of the vertical columnar hole to form gate dielectric layer 4.

[0073] In this step, atomic layer deposition process is used, with Si2H6 as silicon precursor source, and the reaction temperature is 573K; vertical channel layer 2 is deposited on the surface of gate dielectric layer 4.

[0074] Step five: thin layer electrode material is deposited on the gate and source-drain contact area by sputtering process, and control electrode 7, programming electrode 6, source electrode 8 and drain electrode 1 are formed by stripping process;

[0075] In this step, photolithography process and etching process are used, SiCl4 is introduced for etching metal W, then CF4 is used for etching SiO2, after the first layer etching is completed, the photoresist is trimmed to adjust the width of the photoresist, and then cleaned to remove the residues generated during etching. Repeat the above steps to form a stack accumulation step.

[0076] In this step, reaction sputtering process is used, a molecular pump or a cold pump is used to vacuum the reaction chamber until the vacuum pressure in the reaction chamber reaches 0.02 Torr, then under the condition of sputtering power of 350W and argon pressure of 5mTorr, metal W is used as target material to uniformly sputter the channel surface 2, a layer of metal W is deposited on the surface to form control electrode 7, programming electrode 6, source electrode 8 and drain electrode 1, and the preparation of vertical channel type reconfigurable transistor is completed.

[0077] Example 2:

[0078] HYO material is used to make gate dielectric layer 4, ZnO is used as vertical channel layer 2, and metal titanium is used as the material of programming electrode 6, control electrode 7, source electrode 8 and drain electrode 1, and the specific manufacturing method is as follows:

[0079] Step one: etching process and deposition process are used to deposit source contact area on the substrate.

[0080] Step two: deposit SiO2 above the channel layer 2 to form an oxide layer 3, and sputter a layer of electrode material above the oxide layer 3 to form a stack alternately;

[0081] In this step, a reaction sputtering process is used. First, a molecular pump or a cold pump is used to pump the reaction cavity to a vacuum pressure of 0.02 Torr. Then, under the conditions of a sputtering power of 350 W and an argon pressure of 5 mTorr, a metal Ti is used as a target material to uniformly sputter the surface of the oxide layer 3 to deposit a layer of metal Ti on the surface, thereby forming a stack.

[0082] Step three: etching a vertical columnar hole by using an etching process;

[0083] In this step, a dry etching process is used to etch the center part of the stack layer to the substrate surface to form a vertical columnar hole.

[0084] Step four: depositing a dielectric material to generate a gate dielectric layer 4, and depositing a passivation layer 5 above the stack, depositing ZnO to generate a vertical channel layer 2, and then depositing an isolation oxide layer to fill the columnar hole;

[0085] A pulsed laser sputtering deposition process is used to alternately sputter and deposit a HYO material thin film on the surface of the passivation layer 5 by using a double target (HfO2 ceramic target 99.99%, Y2O3 ceramic target 99.99%), and then an annealing process is used to crystallize the HYO material to form a gate dielectric layer 4.

[0086] In this step, an atomic layer deposition process is used. First, ionized water is used as an oxygen source, and tetraethylmethylammonium zinc (TEMAZn) is used as a zinc precursor source. The temperature is raised to 573 K to deposit a vertical channel layer 2 on the surface of the gate dielectric layer 4.

[0087] Step five: depositing a thin layer of electrode material above the gate and source-drain ZnO by using a sputtering process, and forming a control electrode 7, a programming electrode 6, a source electrode 8, and a drain electrode 1 by using a stripping process;

[0088] In this step, a photolithography process and an etching process are used. SiCl4 is introduced to etch the metal Ti, and then CF4 is selected to etch the SiO2. After the first layer is etched, the photoresist is trimmed to adjust the width of the photoresist, and then cleaned to remove the residues generated during etching. The above steps are repeated to form a stack step.

[0089] In this step, the reaction sputtering process is used. First, the reaction cavity is vacuumed by a molecular pump or a cold pump until the vacuum pressure in the reaction cavity reaches 0.02 Torr. Then, a layer of metal Ti is deposited on the surface of the channel layer 2 by using the metal Ti as the target material and performing uniform sputtering under the conditions of a sputtering power of 350 W and an argon pressure of 5 mTorr, so as to form the control electrode 7, the programming electrode 6, the source electrode 8 and the drain electrode 1 and complete the preparation of the vertical channel type reconfigurable transistor.

[0090] Embodiment 3

[0091] The gate dielectric layer 4 is made of PZT material, the vertical channel layer 2 is made of intrinsic Si substrate, and the metal copper is used as the material of the programming electrode 6, the control electrode 7, the source electrode 8 and the drain electrode 1. The specific manufacturing method is as follows:

[0092] Step one: the source contact area is formed on the substrate by using the etching process and the deposition process.

[0093] Step two: the SiO2 is deposited on the channel layer 2 to form the oxide layer 3, and a layer of electrode material is sputtered on the oxide layer 3 to form the stack alternately.

[0094] In this step, the reaction sputtering process is used. First, the reaction cavity is vacuumed by a molecular pump or a cold pump until the vacuum pressure in the reaction cavity reaches 0.02 Torr. Then, a layer of metal Ti is deposited on the surface of the channel layer 2 by using the metal Ti as the target material and performing uniform sputtering under the conditions of a sputtering power of 350 W and an argon pressure of 5 mTorr, so as to form the control electrode 7, the programming electrode 6, the source electrode 8 and the drain electrode 1 and complete the preparation of the vertical channel type reconfigurable transistor.

[0095] Step three: the vertical columnar hole is etched by using the etching process.

[0096] In this step, the center part of the stack is etched to the surface of the substrate by using the dry etching process, so as to form the vertical columnar hole.

[0097] Step four: the gate dielectric layer 4 is formed by depositing the dielectric material, a layer of passivation layer 5 is deposited on the stack, the vertical channel layer 2 is formed by depositing the intrinsic Si, and the columnar hole is filled by depositing the isolation oxide layer.

[0098] In this step, the atomic layer deposition process is used. First, the ion water is used as the oxygen source, PbH4

[0099] is used as the lead precursor source, tetraethyl methylimino zirconium (TEMAZr) is used as the zirconium precursor source, and tetraethyl methylimino titanium (TEMATi) is used as the titanium precursor source. The temperature is increased to 573 K. Then, the PZT material thin film is deposited on the surface of the vertical columnar hole by adjusting the pulse ratio of the titanium precursor source and the zirconium precursor source, so as to form the gate dielectric layer 4.

[0100] In this step, the atomic layer deposition process is used to deposit a vertical channel layer 2 on the surface of the gate dielectric layer 4 by using Si2H6 as the precursor source of silicon at a reaction temperature of 573K.

[0101] In step five, the thin electrode material is deposited on the gate and source-drain intrinsic Si by using the sputtering process, and the control terminal electrode 7, the programming terminal electrode 6, the source terminal electrode 8 and the drain terminal electrode 1 are formed by using the stripping process.

[0102] In this step, the photolithography process and the etching process are used to etch the metal Cu by using SiCl4, and then the SiO2 is etched by using CF4. After the first layer etching is completed, the photoresist is trimmed to adjust the width of the photoresist, and then the photoresist is cleaned to remove the residues generated in the etching. The above steps are repeatedly cycled to form the stack-shaped accumulation steps.

[0103] In this step, the reaction sputtering process is used. First, the reaction chamber is vacuumized by using a molecular pump or a cold pump until the vacuum pressure in the reaction chamber reaches 0.02 Torr. Then, the surface 2 of the channel is uniformly sputtered by using the metal Cu as the target material at a sputtering power of 350W and an argon pressure of 5mTorr. A layer of metal Cu is deposited on the surface of the channel to form the control terminal electrode 7, the programming terminal electrode 6, the source terminal electrode 8 and the drain terminal electrode 1, and the preparation of the vertical channel type reconfigurable transistor is completed.

[0104] The present application is not limited to the above-mentioned best mode of implementation, and anyone can derive other various forms of products under the inspiration of the present application, but regardless of any changes in shape or structure, any technical solution with the same or similar technical solutions as the present application falls within the protection scope of the present application.

Claims

1. A vertical channel reconfigurable transistor, characterized by, It comprises a drain electrode (1), a vertical channel layer (2), an isolation oxide layer (3), a gate dielectric layer (4), a programming electrode (6), a control electrode (7), a source electrode (8) and a silicon substrate (9). The vertical channel layer (2) is arranged on the silicon substrate (9) and extends along the horizontal direction at the upper end, the programming electrode (6) and the control electrode (7) are isolated from each other by the isolation oxide layer (3) and arranged between the upper end extension of the vertical channel layer (2) and the silicon substrate (9) and between the vertical part of the vertical channel layer (2) and the gate dielectric layer (4). The type of carrier in the vertical channel layer (2) is regulated by the programming electrode (6), thereby regulating the working mode of the device, and the concentration of the conduction charge in the vertical channel layer (2) is regulated by the control electrode (7).

2. The vertically-channeled reconfigurable transistor of claim 1, wherein, The upper and lower ends of the vertical channel layer (2) extend along the horizontal direction on the same side, the programming electrode (6) and the control electrode (7) are arranged between the upper and lower end extensions of the vertical channel layer (2), the drain electrode (1) is arranged on the upper end extension of the vertical channel layer (2), and the source electrode (8) is arranged on the lower end extension of the vertical channel layer (2) or the silicon substrate (9).

3. The vertically channelled reconfigurable transistor according to claim 2, wherein The programming electrode (6), the control electrode (7) and the upper and lower end extensions are all isolated from each other by the isolation oxide layer (3).

4. The vertically-channeled reconfigurable transistor of claim 3, wherein, A stack-shaped stacking structure formed by stacking a plurality of isolation oxide layers (3) and a plurality of metal layers is arranged between the upper and lower end extensions of the vertical channel layer (2), a part of the metal layers are used as the programming electrode (6) or lead out the programming electrode (6), and another part of the metal layers are used as the control electrode (7) or lead out the control electrode (7).

5. The vertically channel reconfigurable transistor of claim 3, wherein, A passivation layer (5) is arranged between the upper end extension of the vertical channel layer (2) and the uppermost isolation oxide layer (3) of the stack-shaped stacking structure.

6. The vertically-channeled reconfigurable transistor of claim 1, wherein, The source electrode (8) and the drain electrode (1) are Schottky contacts, which provide an electron and hole tunneling barrier with a difference of less than 0.2eV, and realize a reconfigurable function.

7. The vertical channel reconfigurable transistor according to any one of claims 1 to 6, wherein The vertical channel layer (2) is made of lightly doped or intrinsic semiconductor; When the source electrode (8) is grounded and the drain electrode (1) is connected to a forward voltage, the device working state is adjusted to N type: a forward voltage is applied to the programming electrode (6), the control electrode (7) is grounded, and the positive electric field generated near the surface of the vertical channel layer (2) attracts free electrons nearby, so that the accumulation of electrons in the vertical channel layer (2) increases, thereby making the device realize N type doping; a forward voltage is applied to the control electrode (7), which corresponds to the accumulation of electrons in the vertical channel layer (2), and under the joint action of the programming voltage, the channel presents a low resistance state, and the device works as an N-FET. When the source electrode (8) is grounded and the drain electrode (1) is connected to the reverse voltage, the device is adjusted to P-type: a reverse voltage is applied to the programming electrode (6), the control electrode (7) is grounded, and the negative electric field generated near the surface of the vertical channel layer (2) attracts the free holes nearby, so that the accumulation of holes in the vertical channel layer (2) increases, thereby making the device realize P-type doping; a reverse voltage is applied to the control electrode (7), which corresponds to the accumulation of holes in the vertical channel layer (2), and under the joint action of the programming voltage, the channel presents a low resistance state, and the device is turned on as a P-FET.

8. The vertically-channeled reconfigurable transistor of claim 1, wherein, The materials of the drain electrode (1), the programming electrode (6), the control electrode (7), and the source electrode (8) are any one of tungsten, titanium, copper, aluminum, platinum, iridium, ruthenium, molybdenum, tungsten nitride, titanium nitride, tungsten silicide, titanium silicide, and tantalum silicide; The vertical channel layer (2) is any one of Si, SiGe, GaN, GaO, GaAs, In2O3, ZnO, SnO, IGZO, and SiC; The material of the gate dielectric layer (4) is any one of SiO2, Si3N4, TiO2, Nb2O5, HZO, HSO, HAO, HLO, ZnSnO3, AlScN, HfO2, HYO, BFO, PZT, BST, and ZrO2.

9. A method for manufacturing the vertically-channeled reconfigurable transistor of claim 1, characterized by, The method comprises the following steps: Step 1: forming a source contact area on a silicon substrate (9) by using etching and deposition processes; Step 2: forming mutually isolated programming electrodes (6) and control electrodes (7) above the source contact area by using deposition and sputtering processes; Step 3: etching a vertical columnar hole in the structure above the source contact area by using an etching process; Step 4: depositing a dielectric material to form a gate dielectric layer (4) in the vertical columnar hole, and then depositing a channel material to form a vertical channel layer (2); Step 5: forming a source electrode (8) and a drain electrode (1) by using a sputtering process.

10. The method of claim 9, wherein the vertical channel reconfigurable transistor is formed by the steps of: In step 2, a stack structure is formed by alternately stacking an isolation oxide layer (3) and a metal layer on the source contact area, or an extension of the vertical channel layer (2) is first deposited, and then the isolation oxide layer (3) and the metal layer are alternately stacked to form a stack structure; in step 3, the vertical columnar hole is etched in the stack structure; in step 4, a passivation layer (5) is deposited on the stack structure, and the isolation oxide layer (3) is deposited again to fill the columnar hole after the vertical channel layer (2) is formed; in step 5, the excess source and drain contacts and the gate stack are removed by using an etching process. ​

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