A gate drive circuit, hybrid power device and control method thereof

Abstract

The present invention relates to a gate drive circuit, a hybrid power device and a control method thereof. The gate drive circuit of the present invention includes an isolation unit, a first drive circuit and a second drive circuit; the first drive circuit includes a first current limiting resistor, a first push-pull circuit, a first delay line circuit and a first load switch circuit, and the first load switch circuit is used to delay the opening of the first power semiconductor device; the second drive circuit includes a second current limiting resistor, a second push-pull circuit, a second delay line circuit and a second load switch circuit, and the second load switch circuit is used to delay the closing of the second power semiconductor device. When in use, the control method helps to dynamically adjust the switching timing of the hybrid power device, significantly reduce the switching loss of the hybrid power semiconductor device, give full play to the respective advantages of the first power semiconductor device and the second power semiconductor device, improve the efficiency and power density of the hybrid power device, and reduce the overall cost of the power device.

Description

Technical Field

[0001] The present invention relates to the technical field of power electronic systems, and in particular to a gate drive circuit, a hybrid power device and a control method thereof. Background Art

[0002] Currently, most power electronic devices use power devices based on traditional silicon (Si) materials. Although these devices are widely used in various applications, traditional Si materials face many challenges due to their inherent physical limitations (such as narrow bandgap, low thermal conductivity and low critical electric field), such as high loss, low switching frequency, and difficulty in meeting higher blocking voltage and power factor requirements.

[0003] As the requirements for semiconductor performance increase, silicon carbide (SiC), as a third-generation semiconductor material, has attracted widespread attention due to its excellent performance characteristics. Compared with traditional Si materials, SiC shows significant advantages in breakdown field strength, bandgap width, carrier saturation drift velocity, and thermal conductivity. These characteristics make SiC materials particularly suitable for high-power applications with high temperature and high pressure, greatly improving the efficiency and power density of power electronic converters, while helping to achieve lightweight and miniaturization of equipment. However, since the current manufacturing process of SiC semiconductor devices is not yet mature, chip yield and tolerance issues have led to high costs and technical difficulties, especially in high-power multi-chip parallel applications. These challenges have prompted engineers to seek more economical and efficient solutions.

[0004] Therefore, SiC MOSFET and Si IGBT are used in parallel to form hybrid power devices in order to overcome the limitations of their respective materials while taking advantage of their respective advantages. Hybrid power devices combine the low cost and wide current range advantages of Si IGBTs with the high efficiency and high frequency characteristics of SiC MOSFETs. Through careful design, these hybrid devices are able to achieve optimized conduction and switching characteristics under various load conditions, effectively improving the limitations of Si materials in terms of loss and switching frequency, while maintaining the advantages of SiC materials in high temperature and high voltage applications. However, the losses of such hybrid power devices are still relatively high. Summary of the invention

[0005] An object of the present invention is to provide a gate drive circuit, a hybrid power device and a control method thereof, so as to reduce the loss of the hybrid power device.

[0006] In order to solve the above technical problems, the present invention provides a gate driving circuit, including an isolation unit, a first driving circuit and a second driving circuit;

[0007] The first driving circuit includes a first current limiting resistor, a first push-pull circuit, a first delay line circuit and a first load switch circuit, the first current limiting resistor is connected in series with the first push-pull circuit for current limiting, the first push-pull circuit and the first delay line circuit are both connected to the first load switch circuit, and the first load switch circuit is used to delay the turning on of the first power semiconductor device;

[0008] The second driving circuit comprises a second current limiting resistor, a second push-pull circuit, a second delay line circuit and a second load switch circuit, the second current limiting resistor is connected in series with the second push-pull circuit for current limiting, the second push-pull circuit and the second delay line circuit are both connected to the second load switch circuit, and the second load switch circuit is used to delay the shutdown of the second power semiconductor device;

[0009] The isolation unit is arranged at input ends of the first push-pull circuit and the second push-pull circuit.

[0010] Further, the first load switch circuit is driven by a first logic enable signal, and includes a cascaded first transistor and a second transistor, wherein the first transistor is cascaded with the first delay line circuit; when the first logic enable signal is at a high level, the first transistor is turned on, the second transistor is also turned on, and the first load switch circuit is turned on to delay the opening of the first power semiconductor device; the first push-pull circuit is located before the first load switch circuit, and the second transistor is also connected to the first push-pull circuit and the first power semiconductor device at the same time; or, the first load switch circuit is located before the first push-pull circuit, the second transistor is connected to the first push-pull circuit, and the first push-pull circuit is connected to the first power semiconductor device.

[0011] Further, the first transistor is an N-channel MOSFET, the second transistor is a P-channel MOSFET, the gate of the first transistor is connected to the first delay line circuit, the source of the first transistor is grounded, and the drain of the first transistor is connected to the gate of the second transistor; when the first push-pull circuit is located before the first load switch circuit, the source of the second transistor is connected to the output end of the first push-pull circuit, and the drain of the second transistor is connected to the gate of the first power semiconductor device; when the first load switch circuit is located before the first push-pull circuit, the source of the second transistor is connected to the input end of the first push-pull circuit, and the drain of the second transistor is connected to the isolation unit.

[0012] Further, the second load switch circuit is driven by a second logic enable signal, and includes a cascaded third transistor and a fourth transistor, wherein the third transistor is cascaded with the second delay line circuit; when the second logic enable signal is at a low level, the third transistor is turned on, the fourth transistor is also turned on, and the second load switch circuit is turned on to delay the shutdown of the second power semiconductor device; the second push-pull circuit is located before the second load switch circuit, and the fourth transistor is also connected to the second push-pull circuit and the second power semiconductor device at the same time; or, the second load switch circuit is located before the second push-pull circuit, the fourth transistor is connected to the second push-pull circuit, and the second push-pull circuit is connected to the second power semiconductor device.

[0013] Further, the third transistor is a P-channel MOSFET, the fourth transistor is an N-channel MOSFET, the gate of the third transistor is connected to the second delay line circuit, the source of the third transistor is connected to the bias voltage, and the drain of the third transistor is connected to the gate of the fourth transistor; when the second push-pull circuit is located before the second load switch circuit, the source of the fourth transistor is connected to the output end of the second push-pull circuit, and the drain of the fourth transistor is connected to the gate of the second power semiconductor device; when the second load switch circuit is located before the second push-pull circuit, the source of the fourth transistor is connected to the input end of the second push-pull circuit, and the drain of the fourth transistor is connected to the isolation unit.

[0014] Further, the isolation unit is provided with one, and the first driving circuit and the second driving circuit are simultaneously connected to the isolation unit;

[0015] Alternatively, there are two isolation units, namely a first isolation unit and a second isolation unit. The first isolation unit is arranged between the first load switch circuit and the first push-pull circuit and is located at the input end of the first push-pull circuit. The second isolation unit is arranged between the second load switch circuit and the second push-pull circuit and is located at the input end of the second push-pull circuit.

[0016] Furthermore, a pull-down resistor and / or a Zener diode are provided in both the first load switch circuit and the second load switch circuit.

[0017] The present invention also provides a hybrid power device, comprising a first power semiconductor device, a second power semiconductor device and a gate drive circuit as described in any one of the above technical solutions, wherein a startup speed of the first power semiconductor device is lower than a startup speed of the second power semiconductor device.

[0018] Further, the first power semiconductor device is an IGBT, and the second power semiconductor device is a SiCMOSFET; or, the first power semiconductor device is an IGBT, and the second power semiconductor device is a Cascode SiCJFET; or, the first power semiconductor device is an IGBT, and the second power semiconductor device is a Cascode GaNFET; or, the first power semiconductor device is a SiC MOSFET, and the second power semiconductor device is a Cascode SiC JFET; or, the first power semiconductor device is a SiC MOSFET, and the second power semiconductor device is a Cascode GaN FET.

[0019] The present invention further provides a control method for a hybrid power device, which is used to control the hybrid power device according to any one of the above technical solutions, comprising:

[0020] When the load current is not greater than the first boundary load current, the second power semiconductor device is turned on and the first power semiconductor device is turned off;

[0021] When the load current is higher than the first boundary load current and lower than the second boundary load current, before the first power semiconductor device is turned on, the second power semiconductor device is fully turned on, and before the second power semiconductor device is turned off, the first power semiconductor device is fully turned off;

[0022] When the load current is not less than the second boundary load current, the first power semiconductor device is fully turned on before the second power semiconductor device is turned on, and the second power semiconductor device is fully turned off before the first power semiconductor device is turned off.

[0023] Compared with the prior art, the present invention has at least the following beneficial effects:

[0024] In actual use, the second power semiconductor device has a faster startup speed and lower power consumption. When used in parallel with the first power semiconductor device, the second semiconductor device is turned on before the first power semiconductor device and turned off later than the first power semiconductor device, which helps to dynamically adjust the switching timing of the hybrid power device, thereby significantly reducing the switching loss of the first power semiconductor device, giving full play to the respective advantages of the first power semiconductor device and the second power semiconductor device, reducing the switching loss of the hybrid power device, and not needing to reserve a large heat dissipation area, which is conducive to setting up more hybrid power devices per unit area, improving the efficiency and power density of the hybrid power device, and reducing the overall cost of the power device.

[0025] In addition, the present invention also provides a control method for a hybrid power device. Using this control method, the working modes of the first power semiconductor device and the second power semiconductor device can be reasonably configured according to load currents of different sizes, thereby reducing switching losses during hybrid power operation. When the load current is large, the first power semiconductor device with a stronger carrying capacity is turned on first and turned off last, so that the hybrid power device has a higher overcurrent capacity while ensuring safe operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 The switching loss comparison chart of SiC MOSFET and Si IGBT;

[0027] Figure 2 The electrical connection diagram of the hybrid power device of the first embodiment of the present application, which is composed of SiC MOSFET and Si IGBT connected in parallel;

[0028] Figure 3 An electrical connection diagram of a hybrid power device of a second embodiment of the present application composed of a Cascode SiC JFET and a Si IGBT;

[0029] Figure 4 An electrical connection diagram of a hybrid power device of a second embodiment of the present application composed of a Cascode GaN FET and a Si IGBT;

[0030] Figure 5 is a schematic diagram of electrical connections of a hybrid power device and a gate drive circuit thereof according to one embodiment of the present application;

[0031] Figure 6 yes Figure 5 A circuit diagram of an embodiment of the first driving circuit in;

[0032] Figure 7 yes Figure 5 A circuit diagram of an embodiment of the second driving circuit in;

[0033] Figure 8 yes Figure 6 A circuit diagram of another embodiment of the first driving circuit in;

[0034] Fig. 9 yes Figure 7 A circuit diagram of another embodiment of the second driving circuit in;

[0035] Fig.10 is a schematic diagram of electrical connections of a hybrid power device and a gate drive circuit thereof according to another embodiment of the present application;

[0036] Fig.11is an electrical schematic diagram of the overall structure of a dual-level voltage source inverter-based motor control system using the hybrid power device of the present application;

[0037] Fig.12 yes Fig.11 Circuit configuration diagram of half-bridge topology captured by the dual-level inverter in FIG.

[0038] Fig.13 is a circuit configuration diagram of a half-bridge topology of an NPC three-level inverter using the hybrid power device of the present application;

[0039] Fig.14 is a circuit configuration diagram of a half-bridge topology of an ANPC three-level inverter using the hybrid power device of the present application;

[0040] Fig.15 is a circuit configuration diagram of a half-bridge topology of a T-type NPC three-level inverter using the hybrid power device of the present application;

[0041] Fig.16 It is a schematic diagram of the current-voltage curve of SiC MOSFET and Si IGBT;

[0042] Fig.17 is an application curve diagram of three control modes of the control method of the hybrid power device of the present application;

[0043] Fig.18 is a timing diagram of a driving signal of a first mode I of a control method for a hybrid power device of the present application;

[0044] Fig.19 It is a timing diagram of the driving signal and the voltage and current changes of the power circuit in the second mode II of the control method of the hybrid power device of the present application;

[0045] Fig. 20 yes Fig.19 A simulation result of a delayed turn-on process of the gate drive circuit of the present application in the second mode;

[0046] Fig.21 yes Fig.19 Simulation results of the delayed turn-off process of the gate drive circuit of the present application in the second mode;

[0047] Fig. 22 It is a timing diagram of the driving signal of the third mode III of the control method of the hybrid power device of the present application.

[0048] Reference numerals:

[0049] 1. First drive circuit; 2. Second drive circuit; 3. First resistor; 4. First push-pull circuit; 4a. First P-channel MOSFET; 4b. First N-channel MOSFET; 5. First positive power supply; 6. First negative power supply; 7. Second resistor; 8. First load switch circuit; 8a. Second transistor; 8b. First transistor; 8c. First Zener diode; 8d. First pull-down resistor; 8f. Second pull-down resistor; 9. First delay line circuit;

[0050] 11. a first power semiconductor device; 12. a second load switch circuit; 12a. a fourth transistor; 12b. a third transistor; 12c. a second Zener diode; 12d. a third pull-down resistor; 12f. a fourth pull-down resistor; 13. a second power semiconductor device; 14. a second push-pull circuit; 14a. a second P-channel MOSFET; 14b. a second N-channel MOSFET; 15. a second positive power supply; 16. a second negative power supply; 17. a third resistor; 18. a fourth resistor; 19. a bias voltage; 20. a second delay line circuit;

[0051] 21. DC power supply; 22. Inverter; 22u. First bridge arm; 22v. Second bridge arm; 22w. Third bridge arm; 23. Motor; 24. Control circuit. DETAILED DESCRIPTION

[0052] A gate drive circuit, a hybrid power device and a control method thereof of the present invention will be described below in conjunction with a schematic diagram, wherein preferred embodiments of the present invention are shown, and it should be understood that those skilled in the art can modify the present invention described herein while still achieving the advantageous effects of the present invention. Therefore, the following description should be understood as being widely known to those skilled in the art, and not as a limitation of the present invention.

[0053] The present invention is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. The advantages and features of the present invention will become more apparent from the following description and claims. It should be noted that the drawings are in very simplified form and in non-precise proportions, and are only used to facilitate and clearly assist in illustrating the purpose of the embodiments of the present invention.

[0054] The inventors have found that in hybrid power devices, the faster the switching speed of the semiconductor device, the lower the switching loss. For example, Si IGBT (silicon insulated gate bipolar transistor) and SiC MOSFET (silicon carbide metal oxide semiconductor field effect transistor), Figure 1As shown in the figure, the larger triangle area on the left represents the turn-on loss of the IGBT; the smaller triangle area on the left represents the turn-on loss of the SiC MOSFET. Similarly, the larger triangle area on the right represents the turn-off loss of the IGBT; the smaller triangle area on the left represents the turn-off loss of the SiC MOSFET. Taking the turn-on loss of the SiC MOSFET as an example for detailed explanation, when the SiC MOSFET starts to conduct, the current i D Starts to rise from zero, at which point the voltage V across the SiC MOSFET DS is the DC bus voltage, so the loss is 0. D The voltage V across the SiCMOSFET increases to the highest point and the turn-on loss also reaches its peak value. DS starts to decrease, and the current i D remains unchanged, so the loss begins to decrease. Figure 1 It can be seen that SiC MOSFET has a faster switching speed, which makes SiC MOSFET produce lower switching loss than Si IGBT. Therefore, the switching loss of the hybrid power device is mainly determined by the switching loss of Si IGBT. If SiC MOSFET in the hybrid power device takes on all the turn-on and turn-off actions, the switching loss of Si IGBT can be significantly reduced, thereby reducing the switching loss of the hybrid power device.

[0055] Based on the above research findings, the present application provides a hybrid power device. The following describes a hybrid power device according to an embodiment of the first aspect of the present invention in conjunction with the accompanying drawings.

[0056] In one embodiment, if Figure 5 As shown, the hybrid power device includes a first power semiconductor device 11 , a second power semiconductor device 13 and a gate drive circuit, and a startup speed of the first power semiconductor device 11 is lower than a startup speed of the second power semiconductor device 13 .

[0057] Preferably, the first power semiconductor device is an IGBT (insulated gate bipolar transistor), for example, a SiIGBT. The second power semiconductor device is a SiC MOSFET (silicon carbide metal oxide semiconductor field effect transistor). The corresponding structural schematic diagram of the hybrid power device is as shown in FIG. Figure 2 As shown, Figure 2 and below Figure 3 and Figure 4The driving IC in the gate driving circuit is the gate driving circuit. In the second embodiment, the first power semiconductor device is an IGBT, and the second power semiconductor device can also be a Cascode SiC JFET (a cascade amplifier configuration composed of silicon carbide junction field effect transistors). The corresponding structural schematic diagram of the hybrid power device is as follows: Figure 3 shown.

[0058] In the third embodiment, the first power semiconductor device is an IGBT, and the second semiconductor device may also be a Cascode GaN FET (a two-stage amplifier configuration composed of gallium nitride field effect transistors). The corresponding structural schematic diagram of the hybrid power device is as follows: Figure 4 shown.

[0059] Of course, in other embodiments, the first power semiconductor device may also be a SiC MOSFET, and the second power semiconductor device may be a Cascode GaN FET; or, the first power semiconductor device may be a SiC MOSFET, and the second power semiconductor device may be a Cascode SiC JFET; or, the first power semiconductor device may be a SiC MOSFET, and the second power semiconductor device may be a Cascode GaN FET. It is only necessary to ensure that the startup speed of the first power semiconductor device is greater than the startup speed of the second power semiconductor device, and examples are not given here one by one.

[0060] like Figure 5 As shown, the gate driving circuit includes an isolation unit, a first driving circuit 1 and a second driving circuit 2.

[0061] Among them, Figure 6 As shown, the first driving circuit 1 includes a first current limiting resistor, a first push-pull circuit 4, a first delay line circuit 9 and a first load switch circuit 8. The first current limiting resistor is connected in series with the first push-pull circuit 4 for current limiting. The first push-pull circuit 4 and the first delay line circuit 9 are both connected to the first load switch circuit 8. The first load switch circuit 8 is used to delay the opening of the first power semiconductor device 11.

[0062] Specifically, in one embodiment, taking the first power semiconductor device 11 as a Si IGBT and the second power semiconductor device 13 as a SiC MOSFET as an example, the first drive circuit 1 is as follows: Figure 6As shown, the first push-pull circuit 4 includes a first P-channel MOSFET 4a, a first N-channel MOSFET 4b, a first positive power supply 5 and a first negative power supply 6, wherein the first positive power supply 5 is used as a forward bias power supply of the first power semiconductor device 11, and the first negative power supply 6 is used as a reverse bias power supply of the first power semiconductor device. When in use, a gate drive signal S as a PWM signal (pulse width modulation signal) is input into the first push-pull circuit 4, and the voltage of the first positive power supply 5 or the voltage of the first negative power supply 6 is output according to the gate drive signal S. In order to limit the current in the first push-pull circuit 4, the first current limiting resistor includes a first resistor 3 and a second resistor 7, which are respectively arranged on both sides of the first push-pull circuit 4.

[0063] Preferably, the first delay line circuit 9 is a programmable delay line circuit, which is programmed using a serial interface or a parallel interface. When the gate drive signal S is applied to the input port of the device, it reappears at the output as a first logic enable (EN) signal after the delay time programmed by the device, and the leading and trailing edges of the output waveform are delayed by the same time.

[0064] Furthermore, the first load switch circuit 8 is driven by a first logic enable signal, and includes a cascaded first transistor 8b and a second transistor 8a, the first transistor 8b is cascaded with the first delay line circuit 9, and the second transistor 8a is also connected to the first push-pull circuit 4 and the first power semiconductor device 11 at the same time; when the first logic enable signal is at a high level, the first transistor 8b is turned on, the second transistor 8a is also turned on, and the first load switch circuit 8 is opened.

[0065] Specifically, in one embodiment, the first transistor 8b is an N-channel MOSFET, the second transistor 8a is a P-channel MOSFET, the gate of the first transistor 8b is connected to the first delay line circuit 9, the source of the first transistor 8b is grounded, the drain of the first transistor 8b is connected to the gate of the second transistor 8a, the source of the second transistor 8a is connected to the output end of the first push-pull circuit, and the drain of the second transistor 8a is connected to the gate of the first power semiconductor device 11.

[0066] In other embodiments, the first transistor may also be a PNP-type BJT (PNP-type bipolar transistor), and the second transistor may be an NPN-type BJT (NPN-type bipolar transistor).

[0067] When the first logic enable signal is at a low level, the N-channel MOSFET as the first transistor 8b is turned off, and the P-channel MOSFET as the second transistor 8a is also in an off state. When the first logic enable signal is at a high level, the N-channel MOSFET as the first transistor 8b is turned on, and then the gate of the P-channel MOSFET as the second transistor 8a is grounded, and then the second transistor 8a is turned on, and the first positive power supply 5 outputs a positive voltage and passes through the second transistor 8a, so that the first load switch circuit 11 is turned on to delay the opening of the first power semiconductor device 11.

[0068] Furthermore, in order to protect the circuit, a first pull-down resistor 8d and a second pull-down resistor 8f are provided in the first load switch circuit, and a first Zener diode 8c is also provided.

[0069] Among them, Figure 7 As shown, the second driving circuit 2 includes a second current limiting resistor, a second push-pull circuit 14, a second delay line circuit 20 and a second load switch circuit 12, the second current limiting resistor is connected in series with the second push-pull circuit 14 for current limiting, the second push-pull circuit 14 and the second delay line circuit 20 are both connected to the second load switch circuit 12, and the second load switch circuit 12 is used to delay the shutdown of the second power semiconductor device 13.

[0070] Specifically, the second driving circuit 2 is as follows Figure 7 As shown, in one embodiment, the second push-pull circuit 14 includes a second P-channel MOSFET 14a, a second N-channel MOSFET 14b, a second positive power supply 15 and a second negative power supply 16, wherein the second positive power supply 15 is used as a forward bias power supply of the second power semiconductor device 13, and the second negative power supply 16 is used as a negative bias power supply of the second power semiconductor device 13. When in use, a gate drive signal S as a PWM signal (pulse width modulation signal) is input into the second push-pull circuit 14, and a positive voltage of the second positive power supply 15 or a negative voltage of the second negative power supply 16 is output according to the gate drive signal S. In order to limit the current in the second push-pull circuit 14, the second current limiting resistor includes a third resistor 17 and a fourth resistor 18, which are respectively arranged on both sides of the second push-pull circuit 14.

[0071] Preferably, the second delay line circuit 20 is also a programmable delay line circuit, which is programmed using a serial interface or a parallel interface. When the gate drive signal S is applied to the input port of the device, it reappears at the output as a second logic enable (EN) signal after the delay time programmed by the device, and the leading and trailing edges of the output waveform are delayed by the same time. Furthermore, the second load switch circuit 12 is driven by a second logic enable signal, and includes a cascaded third transistor 12b and a fourth transistor 12a, wherein the third transistor 12b is cascaded with the second delay line circuit 20, and the fourth transistor 12a is also connected to the second push-pull circuit 14 and the second power semiconductor device 13 at the same time; when the second logic enable signal is at a low level, the third transistor 12b is turned on, the fourth transistor 12a is also turned on, and the second load switch circuit 12 is turned on.

[0072] Specifically, in one embodiment, the third transistor 12b is a P-channel MOSFET, the fourth transistor 12a is an N-channel MOSFET, the gate of the third transistor 12b is connected to the second delay line circuit 20, the source of the third transistor 12b is connected to the bias voltage 19, the drain of the third transistor 12b is connected to the gate of the fourth transistor 12a, the source of the fourth transistor 12a is connected to the output end of the second push-pull circuit, and the drain of the fourth transistor 12a is connected to the gate of the second power semiconductor device 13.

[0073] In other embodiments, the third transistor may also be an NPN-type BJT (NPN-type bipolar transistor), and the fourth transistor may be a PNP-type BJT (PNP-type bipolar transistor).

[0074] When the second logic enable signal is at a high level, the gate voltage of the P-channel MOSFET as the third transistor 12b is higher than the threshold voltage, so the third transistor 12b is in the off state, the fourth transistor 12a is also in the off state, and the output current of the second push-pull circuit 14 is passed through the internal diode of the N-channel MOSFET as the fourth transistor 12a to the gate-source capacitance C of the SiC MOSFET. GS The SiC MOSFET is charged to realize the conduction of the SiC MOSFET. Therefore, the turn-on of the SiC MOSFET is only controlled by the output signal of the driver. When the second logic enable signal is at a low level, the gate voltage of the P-type MOSFET as the third transistor 12b is lower than the threshold voltage, so that the third transistor 12b is turned on. Since the bias voltage is higher than the source voltage of the N-type MOSFET as the fourth transistor 12a, the fourth transistor 12a is turned on, and the negative voltage of the second negative power supply 16 turns off the SiC MOSFET through the fourth transistor 12a.

[0075] Furthermore, in order to protect the circuit, a third pull-down resistor 12d and a fourth pull-down resistor 12f are provided in the second load switch circuit 12, and a second Zener diode 12c is also provided.

[0076] Among them, the isolation unit is arranged at the input end of the first push-pull circuit and the second push-pull circuit. On the one hand, the isolation unit is used to prevent direct electrical connection between the high-voltage part and the low-voltage part, thereby protecting the control circuit from the influence of high-voltage fault; on the other hand, the isolation unit can provide a signal conversion function, such as level conversion, so that signals of different levels can be effectively transmitted and matched.

[0077] In one embodiment, if Figure 5 As shown, only one isolation unit is provided, and the first driving circuit 1 and the second driving circuit 2 are simultaneously connected to the isolation unit.

[0078] In actual use, the second power semiconductor device 13 has a faster startup speed and lower power consumption. When used in parallel with the first power semiconductor device 11, the second semiconductor device 13 is turned on before the first power semiconductor device 11 and turned off later than the first power semiconductor device 11, which helps to dynamically adjust the switching timing of the hybrid power device, thereby significantly reducing the switching loss of the first power semiconductor device 11, giving full play to the respective advantages of the first power semiconductor device and the second power semiconductor device, reducing the switching loss of the hybrid power device, and not needing to reserve a large heat dissipation area, which is conducive to setting up more hybrid power devices per unit area, improving the efficiency and power density of the hybrid power device, and reducing the overall cost of the power device.

[0079] In the above embodiment, the first push-pull circuit is located before the first load switch circuit, and the second push-pull circuit is located before the second load switch circuit.

[0080] In another embodiment, if Figure 8 As shown, the first load switch circuit 8 is located before the first push-pull circuit 4, the second transistor 8a is connected to the first push-pull circuit 4, a first resistor 3 is arranged between the two, the first push-pull circuit 4 is connected to the first power semiconductor device, specifically, the source of the second transistor 8a is connected to the input end of the first push-pull circuit 4, and the drain of the second transistor 8a is connected to the Figure 5 The isolation unit is connected. Fig. 9As shown, the second load switch circuit 12 is located before the second push-pull circuit 14, the fourth transistor 12a is connected to the second push-pull circuit 14, a third resistor 17 is provided between the second push-pull circuit 14 and the second power semiconductor device. Specifically, the source of the fourth transistor 12a is connected to the input end of the second push-pull circuit 14, and the drain of the fourth transistor 12a is connected to the Figure 5 The isolation unit is connected.

[0081] In another embodiment, if Fig.10 As shown, in this embodiment, two isolation units are provided, namely a first isolation unit and a second isolation unit. The first isolation unit is provided between the first load switch circuit and the first push-pull circuit and is located at the input end of the first push-pull circuit. The second isolation unit is provided between the second load switch circuit and the second push-pull circuit and is located at the input end of the second push-pull circuit. The source of the P-channel MOSFET as the second transistor and the source of the N-channel MOSFET as the fourth transistor are respectively connected to the two isolation units. The drain of the P-channel MOSFET as the second transistor and the drain of the N-channel MOSFET as the fourth transistor both directly receive the PWM signal S.

[0082] The hybrid power device of the embodiment of this aspect has a wide range of applications. In one embodiment, for example Fig.11 As shown, a motor control system based on a dual-level voltage source inverter is shown, including a DC power supply 21, an inverter 22, a motor 23 and a control circuit 24, wherein the inverter 22 is a three-phase inverter that converts the DC power supplied by the DC power supply into AC power and supplies three-phase AC power to the motor; the motor 23 is driven to rotate by the three-phase AC power supplied by the inverter. The control circuit 24 controls the inverter 22 to make the motor 23 move.

[0083] The inverter 22 has the same number of bridge arms as the number of AC power output. In this embodiment, the inverter 22 is composed of a first bridge arm 22u, a second bridge arm 22v, and a third bridge arm 22w. Fig.12 is from Fig.11 A circuit configuration diagram of a half-bridge topology captured by a dual-level inverter in FIG. 1 , wherein each half-bridge topology has two hybrid power devices according to an embodiment of the present invention, wherein: Figures 12 to 15 Hs x D stands for hybrid switch. “Gate drive” refers to the gate drive circuit of the hybrid switch. X Represents the diode, Q X Represents transistor.

[0084] In another embodiment, the hybrid power device of the embodiment of this aspect can also be applied to an NPC (Neutral Point Clamped) three-level inverter, and the circuit configuration diagram of the half-bridge topology is as shown in FIG. Fig.13 As shown, each half-bridge topology has four hybrid power devices according to the embodiment of the present invention.

[0085] In another embodiment, the hybrid power device of the embodiment of this aspect can also be applied to an ANPC (Active Neutral Point Clamped) three-level inverter, and the circuit configuration diagram of the half-bridge topology is as shown in FIG. Fig.14 As shown, each half-bridge topology has four hybrid power devices according to the embodiment of the present invention.

[0086] In another embodiment, the hybrid power device of the embodiment of this aspect can also be applied to a T-type NPC (T-type neutral point clamped) three-level inverter, and the circuit configuration diagram of the half-bridge topology is as shown in FIG. Fig.15 As shown, each half-bridge topology has two hybrid power devices according to the embodiment of the present invention.

[0087] The second aspect of the present application provides a gate drive circuit, the structure of which is the same as that of the gate drive circuit in the first aspect of the present application, and will not be described in detail here.

[0088] The inventors further found that when comparing the voltage-current characteristics in the saturation region of the IGBT and the SiC MOSFET, it becomes as follows Fig.16 As shown in the relationship, in the first region of the figure, when the on-current value is the same, the on-voltage of SiC MOSFET is lower than that of IGBT, so SiC MOSFET has lower switching loss. On the contrary, in the second region of the figure, when the on-current value is the same, the on-voltage of IGBT is lower than that of SiC MOSFET, so IGBT has lower switching loss.

[0089] In order to make full use of the characteristics of a hybrid power device composed of SiC MOSFET and Si IGBT in parallel and reduce the loss of the hybrid power device, the present application proposes a control method for a hybrid power device. The following describes a control method for a hybrid power device in accordance with an embodiment of the third aspect of the present application in conjunction with the accompanying drawings of the specification.

[0090] The control method of the hybrid power device in the embodiment of this aspect is used to control the hybrid power device in the embodiment of the first aspect, and includes the following contents:

[0091] When the load current is not greater than the first boundary load current, the second power semiconductor device is turned on and the first power semiconductor device is turned off;

[0092] When the load current is higher than the first boundary load current and lower than the second boundary load current, before the first power semiconductor device is turned on, the second power semiconductor device is fully turned on, and before the second power semiconductor device is turned off, the first power semiconductor device is fully turned off;

[0093] When the load current is not less than the second boundary load current, the first power semiconductor device is fully turned on before the second power semiconductor device is turned on, and the second power semiconductor device is fully turned off before the first power semiconductor device is turned off.

[0094] In the control method of the hybrid power device, there are three control modes for controlling the hybrid power device. The following is an example in which the first power semiconductor device is a Si IGBT and the second power semiconductor device is a SiC MOSFET.

[0095] The first mode I is when the load current is not greater than Fig.17 The first boundary load current I1 shown in FIG is used, and the shaded portion I represents the working range of the first mode I, wherein the first boundary load current I1 is determined by the corresponding current at the Si IGBT threshold voltage of the current-voltage curve of the SiC MOSFET. The driving signals of the SiC MOSFET and the Si IGBT are shown in FIG. Fig.18 As shown, when the load current in the hybrid power device is lower than this first boundary load current I1, the voltage drop across the SiC MOSFET is not high enough to achieve conduction in the Si IGBT, and only the SiC MOSFET is turned on / off while the Si IGBT remains inactive and does not contribute to forward conduction in the hybrid power device. This first mode I ensures safe operation of the hybrid power device and minimizes turn-on / off energy loss under relatively light load conditions. This first mode I can be often used in UPS (uninterruptible power supply) because most three-phase UPS devices usually operate in the range of 20-40% of the maximum load.

[0096] The second mode II is used when the load current is higher than the first boundary load current I1 and lower than the second boundary load current I2. The shaded portion II represents the working range of the second mode II, where the second boundary load current I2 is the maximum SOA (safe operating area) current of the SiC MOSFET. The driving signals of the SiC MOSFET and the Si IGBT are as follows: Fig.19As shown, the SiC MOSFET is turned on first and turned off last relative to the Si IGBT, which means that the duty cycle of the periodic control signal (e.g., gate signal) applied to the SiC MOSFET is greater than the duty cycle of the periodic control signal (e.g., gate signal) applied to the Si IGBT.

[0097] Since the turn-on and turn-off switching are performed first and last by the SiC MOSFET respectively, there is a very low on-state voltage when turning on / off the Si IGBT, and this method of turning on / off the Si IGBT is generally referred to as zero voltage turn-on (ZVS) and zero current turn-off (ZCS) of the Si IGBT. Fig.19 In the figure, the shaded part on the left represents the time range of zero current shutdown (ZCS) and the voltage and current characteristics that can characterize zero current shutdown (ZCS), and the shaded part on the right represents the time range of zero voltage switch-on (ZVS) and the voltage and current characteristics that can characterize zero voltage switch-on (ZVS). In addition, the symbols on the horizontal axis function similarly to ellipsis, indicating that this is only a schematic diagram, and the switch-on and switch-off waveforms shown in the figure may not appear in the same cycle, or even if the two appear in the same cycle, the time interval between the two may be longer than that shown in the figure.

[0098] In order to enable zero voltage turn-on of the IGBT, and because of the generally much faster switching speed and lower switching losses of the SiC MOSFET in hybrid modules, such as Fig.19 As shown, the first time delay t on is imposed on the turn-on of the Si IGBT relative to the SiC MOSFET, by Figure 6 The first load switch circuit is realized in the second time delay t off is imposed on the turn-off of the SiC MOSFET relative to the Si IGBT, by Figure 7 The second load switch circuit in is implemented. Fig.19 The first time delay t on and the second time delay t off The specific value of can be determined by the relative switching speeds of the Si IGBT and SiC MOSFET and the length of the dead time between the two complementary hybrid modules.

[0099] The turn-on and turn-off delays between the SiC MOSFET and the Si IGBT may be large enough to ensure that during turn-on, the SiC MOSFET is fully turned on before the Si IGBT is turned on (e.g., the SiC MOSFET current reaches above about 90% of the steady-state SiC MOSFET current), but during turn-off, the Si IGBT is fully turned off before the SiC MOSFET is turned off (e.g., the Si IGBT current reaches below about 10% of the Si IGBT steady-state current).

[0100] The simulation results are as follows Fig. 20 and Fig.21 As shown, Fig. 20 The simulation results of the delayed connection process are shown. Fig.21 The simulation results of the delayed turn-off process are shown, which realizes that SiC MOSFET is fully turned on before Si IGBT is turned on, and Si IGBT is fully turned off before SiC MOSFET is turned off. Among them, VGS_MOSFET is the gate-source voltage of SiC MOSFET, VGE_IGBT is the gate-emitter voltage of IGBT; VDS is the drain-source voltage of SiC MOSFET, VCE is the collector-emitter voltage of IGBT, and since SiC MOSFET and IGBT are connected in parallel, the drain-source voltage (VDS) and the collector-emitter voltage (VCE) are equal; ID is the leakage current of SiC MOSFET, IC is the collector current of IGBT; Eon_SiC MOSFET is the turn-on loss of SiC MOSFET, Eon_IGBT is the turn-on loss of IGBT, Eoff_SiC MOSFET is the turn-off loss of SiC MOSFET, and Eoff_IGBT is the turn-off loss of IGBT.

[0101] The third mode III is used when the load current is not less than the second boundary load current I2. The shaded portion III represents the working range of the third mode III. The driving signals of SiC MOSFET and Si IGBT are as follows: Fig. 22 As shown, the Si IGBT is turned on first and turned off last relative to the SiC MOSFET, which means that the duty cycle of the periodic control signal applied to the Si IGBT is greater than the duty cycle of the periodic control signal applied to the SiC MOSFET. One goal of using the third mode III is to ensure that whenever the load current exceeds the maximum SOA (safe operating area) current of the SiC MOSFET, the load current can be safely interrupted by the Si IGBT. In order to achieve this goal of safe current interruption, whenever the load current is outside the maximum SOA of the SiC MOSFET, the Si IGBT is preferably turned on first and turned off last.

[0102] By using the control method of the hybrid power device of the present invention, the working modes of the first power semiconductor device and the second power semiconductor device can be reasonably configured according to load currents of different sizes, thereby reducing the switching loss of the hybrid power device. When the load current is large, the first power semiconductor device with a stronger carrying capacity is turned on first and turned off last, so that the hybrid power device has a higher overcurrent capacity while ensuring safe operation.

[0103] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A gate drive circuit, characterized in that: It includes an isolation unit, a first drive circuit and a second drive circuit; the input ends of the first drive circuit and the second drive circuit are simultaneously excited by the same gate drive signal; The first driving circuit includes a first current limiting resistor, a first push-pull circuit, a first delay line circuit and a first load switch circuit, the first current limiting resistor is connected in series with the first push-pull circuit for current limiting, the first push-pull circuit and the first delay line circuit are both connected to the first load switch circuit, and the first load switch circuit is used to delay the turning on of the first power semiconductor device; The second driving circuit comprises a second current limiting resistor, a second push-pull circuit, a second delay line circuit and a second load switch circuit, the second current limiting resistor is connected in series with the second push-pull circuit for current limiting, the second push-pull circuit and the second delay line circuit are both connected to the second load switch circuit, and the second load switch circuit is used to delay the shutdown of the second power semiconductor device; The first delay line circuit and the second delay line circuit are both programmable delay line circuits; The isolation unit is arranged at the input ends of the first push-pull circuit and the second push-pull circuit; The first load switch circuit is driven by a first logic enable signal, and includes a cascaded first transistor and a second transistor, wherein the first transistor is cascaded with the first delay line circuit; when the first logic enable signal is at a high level, the first transistor is turned on, the second transistor is also turned on, and the first load switch circuit is turned on to delay the turning on of the first power semiconductor device; the first push-pull circuit is located before the first load switch circuit, and the second transistor is also connected to the first push-pull circuit and the first power semiconductor device at the same time; or, the first load switch circuit is located before the first push-pull circuit, the second transistor is connected to the first push-pull circuit, and the first push-pull circuit is connected to the first power semiconductor device; The first transistor is an N-channel MOSFET, the second transistor is a P-channel MOSFET, the gate of the first transistor is connected to the first delay line circuit, the source of the first transistor is grounded, and the drain of the first transistor is connected to the gate of the second transistor; when the first push-pull circuit is located before the first load switch circuit, the source of the second transistor is connected to the output end of the first push-pull circuit, and the drain of the second transistor is connected to the gate of the first power semiconductor device; when the first load switch circuit is located before the first push-pull circuit, the source of the second transistor is connected to the input end of the first push-pull circuit, and the drain of the second transistor is connected to the isolation unit; The first push-pull circuit includes a first P-channel MOSFET, a first N-channel MOSFET, a first positive power supply and a first negative power supply, the first positive power supply is used as a forward bias power supply of the first power semiconductor device, and the first negative power supply is used as a reverse bias power supply of the first power semiconductor device; The second load switch circuit is driven by a second logic enable signal, and includes a cascaded third transistor and a fourth transistor, wherein the third transistor is cascaded with the second delay line circuit; when the second logic enable signal is at a low level, the third transistor is turned on, the fourth transistor is also turned on, and the second load switch circuit is turned on to delay the shutdown of the second power semiconductor device; the second push-pull circuit is located before the second load switch circuit, and the fourth transistor is also connected to the second push-pull circuit and the second power semiconductor device at the same time; or, the second load switch circuit is located before the second push-pull circuit, the fourth transistor is connected to the second push-pull circuit, and the second push-pull circuit is connected to the second power semiconductor device; The third transistor is a P-channel MOSFET, the fourth transistor is an N-channel MOSFET, the gate of the third transistor is connected to the second delay line circuit, the source of the third transistor is connected to the bias voltage, and the drain of the third transistor is connected to the gate of the fourth transistor; when the second push-pull circuit is located before the second load switch circuit, the source of the fourth transistor is connected to the output end of the second push-pull circuit, and the drain of the fourth transistor is connected to the gate of the second power semiconductor device; when the second load switch circuit is located before the second push-pull circuit, the source of the fourth transistor is connected to the input end of the second push-pull circuit, and the drain of the fourth transistor is connected to the isolation unit; The second push-pull circuit includes a second P-channel MOSFET, a second N-channel MOSFET, a second positive power supply and a second negative power supply, wherein the second positive power supply is used as a forward bias power supply for the second power semiconductor device, and the second negative power supply is used as a negative bias power supply for the second power semiconductor device.

2. The gate driving circuit according to claim 1, characterized in that: The isolation unit is provided with one, and the first driving circuit and the second driving circuit are simultaneously connected to the isolation unit; Alternatively, there are two isolation units, namely a first isolation unit and a second isolation unit. The first isolation unit is arranged between the first load switch circuit and the first push-pull circuit and is located at the input end of the first push-pull circuit. The second isolation unit is arranged between the second load switch circuit and the second push-pull circuit and is located at the input end of the second push-pull circuit.

3. The gate driving circuit according to claim 1, characterized in that: The first load switch circuit and the second load switch circuit are both provided with a pull-down resistor and / or a Zener diode.

4. A hybrid power device, characterized in that: The invention comprises a first power semiconductor device, a second power semiconductor device and a gate driving circuit as claimed in any one of claims 1 to 3, wherein a startup speed of the first power semiconductor device is lower than a startup speed of the second power semiconductor device.

5. The hybrid power device according to claim 4, characterized in that: The first power semiconductor device is an IGBT, and the second power semiconductor device is a SiC MOSFET; or, the first power semiconductor device is an IGBT, and the second power semiconductor device is a Cascode SiC JFET; Alternatively, the first power semiconductor device is an IGBT, and the second power semiconductor device is a Cascode GaN FET; Alternatively, the first power semiconductor device is a SiC MOSFET, and the second power semiconductor device is a Cascode SiC JFET; or, the first power semiconductor device is a SiC MOSFET, and the second power semiconductor device is a Cascode GaN FET.

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