A wide bandgap and ultra-wide bandgap trench-gate MOSFET device

Abstract

The present invention belongs to the field of power semiconductor technology and specifically provides a heterojunction-type wide-bandgap and ultra-wide-bandgap trench-gate MOSFET device with an integrated heterojunction diode. The device is used to address the technical bottleneck of the ultra-wide-bandgap semiconductor Ga2O3, which is unable to produce high-power normally-off inversion-layer trench MOSFET devices due to the lack of P-type doping. The device also addresses the low channel mobility and high process requirements of existing Ga2O3 Fin-gate technology, as well as the low channel mobility of existing 4H-SiC MOSFET devices and MOSFETs composed of GaN, AlGaN, and even AlN. Furthermore, the device addresses the technical difficulty of the high reverse conduction voltage drop of the aforementioned MOSFETs. By utilizing easily fabricated, low-cost, wide-bandgap semiconductors such as heavily doped heterogeneous P-type NiO or SnO2, or P-type semiconductor materials of the same material as the voltage-suppressing layer, to form electric field protection for the inversion layer channel region and gate oxide layer composed of the heterogeneous semiconductor material with a lower breakdown electric field, this ensures that breakdown occurs in the voltage-suppressing layer rather than the P-type channel region of the heterogeneous semiconductor material. This allows for the realization of various normally-off inversion layer MOSFET devices with low channel resistance without compromising the high breakdown characteristics of the material. Furthermore, the heterojunction diode formed by the heavily doped heterogeneous P-type NiO or SnO2 material and the voltage-suppressing layer, or the heterojunction diode formed by the heterogeneous P-type channel region and the voltage-suppressing layer, exhibits low reverse voltage drop and unipolar conduction characteristics, contributing to reduced static and dynamic losses.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor power devices, and relates to a vertical semiconductor power device composed of wide bandgap and ultra-wide bandgap materials, specifically a heterogeneous heterostructured wide bandgap and ultra-wide bandgap trench gate MOSFET device. Background Art

[0002] Silicon carbide (SiC) material has the characteristics of large bandgap, high breakdown field strength, high thermal conductivity, and high saturated electron drift rate, making it more suitable for high-frequency, high-voltage, and high-temperature applications. SiC trench-gate MOSFET has the advantages of high-temperature operation, low conduction loss, high switching frequency, high voltage capability, high anti-interference ability, small size, and lightweight, and has broad application prospects. SiC materials have different crystal structures, among which the most common ones are 3C-SiC, 4H-SiC, and 6H-SiC. Based on the characteristics of the material, 4H-SiC is more suitable for making high-voltage MOSFET devices, but the effective mobility of the inversion layer channel electrons of the trench-gate MOSFET made of 4H-SiC material is low, usually about 40-90cm 2 / Vs, resulting in a high total specific on-resistance of the device. Furthermore, the reverse voltage drop of the SiC MOSFET body diode is very high, typically reaching 4-5V. Furthermore, since the reverse body diode conducts as a PN junction diode when conducting, its conductivity modulation effect increases significantly with increasing temperature. This leads to a sharp increase in the diode's reverse recovery charge and losses, as well as the turn-on current stress and losses of the adjacent switch, making it unsuitable for high-temperature and high-power density applications.

[0003] Gallium nitride (GaN), aluminum gallium nitride (AlGaN), and AlN have wider band gaps and much higher figures of merit than SiC. However, due to the difficulty in controlling the activation rate of their P-type doping, they are not conducive to the production of normally-off inversion-layer channel MOSFETs, making their widespread application in power electronics systems difficult. Furthermore, the mobility of the inversion-layer channel produced by them is lower than that of SiC, resulting in an increase in specific on-resistance, making it difficult to fully utilize their material properties. Furthermore, their body diode reverse voltage drop suffers from the same drawbacks as SiC MOSFETs: a very high reverse voltage drop and high losses.

[0004] Ga2O3 materials have an ultra-wide bandgap, a high critical breakdown electric field, and a larger Baliga figure of merit. Power devices made from them can significantly reduce system volume and weight, significantly reduce system losses, and improve system efficiency. They can be widely used in high-power, high-voltage, and high-frequency environments. However, Ga2O3 materials cannot achieve effective P-type doping, making it impossible to produce normally-off MOSFET devices with inversion layer channels. Its application in power electronics systems will not be promoted. Current normally-off Ga2O3 MOSFET devices are divided into two categories. One category is lateral devices, which generally use thin film depletion to achieve normally-off performance and are simple to manufacture. However, due to the lateral voltage resistance of lateral devices, their voltage-resistant layers are very long, resulting in very large specific on-resistance, which is far higher than the theoretical Baliga figure of merit of Ga2O3. Therefore, such devices are not suitable for high-voltage and high-power applications. Another type is the fin-gate vertical device developed by Cornell University (W. Li, et al., "Single and multi-fin normally-off Ga2O3 vertical transistors with a breakdown voltage over 2.6kV," IEEE IEDM, 2019). This device still lacks an inversion layer and instead relies on an accumulation layer for conduction. It requires a very narrow gate width (~200nm) to deplete the N-type region within the fin gate, thus achieving a normally-off device. However, such a small linewidth is rare in power device fabrication, making it difficult and costly to manufacture. Processing is currently unavailable in China. Furthermore, the threshold voltage of this type of device is very low, hindering reliable operation. Furthermore, the reverse conduction voltage drop of this device is positively correlated with the threshold voltage. Power electronics systems typically desire a high threshold voltage, such as 4V. In this case, the reverse conduction voltage drop of a fin-gate device would be higher than 4V, hindering power consumption during reverse operation. In addition, due to the lack of P-type doping, this structure cannot make a P-type electric field shielding area at the bottom of the groove to suppress the strong electric field at the bottom of the gate dielectric layer like SiC or GaN MOSFET. However, since the critical breakdown electric field of Ga2O3 reaches 8MV / cm, when it breaks down, the bottom of the gate dielectric layer groove has actually broken down. For this reason, it is impossible to truly bring into play the advantage of the high critical breakdown electric field that Ga2O3 materials should have. Another type is to use heavily doped ions to implant nitrogen or magnesium to form a high-resistance region similar to the P-type region to block the forward current (MHWong, et.al "Enhancement-Modeβ-Ga2O3 Current Aperture Vertical MOSFETsWith N-Ion-Implanted Blocker", IEEE, EDL, 2020), thereby realizing a normally-off device.However, such devices still cannot achieve a truly effective P-type Ga2O3 region, that is, they cannot use the PN junction reverse bias to block the device. Its high-resistance region is equivalent to a large resistor and cannot effectively block current like a PN junction. Its leakage current is very large (up to A / cm). 2 The device is only on the order of magnitude (which is practically equivalent to conducting a small current), and its magnitude increases further with increasing drain voltage, making it unsuitable for high-voltage, high-power applications. Furthermore, the gate dielectric layer also suffers from the aforementioned premature breakdown issue. To date, these technical bottlenecks remain unresolved. Summary of the Invention

[0005] In order to solve the above technical problems and bottlenecks, the present invention provides a heterogeneous, heterostructured wide-bandgap and ultra-wide-bandgap trench-gate MOSFET device cell. The technical solution adopted by the present invention is as follows:

[0006] 1. A heterojunction, heterostructured, wide-bandgap and ultra-wide-bandgap trench-gate MOSFET device cell with an integrated heterojunction diode, comprising:

[0007] A substrate 1 of a first semiconductor material, an N-type voltage-resistant layer 2 of the first semiconductor material arranged on the substrate 1; a P-type semiconductor channel region 11 of a second semiconductor material is arranged on the N-type voltage-resistant layer 2 of the first semiconductor material, and an N-type heavily doped source region 6 of a third semiconductor material is arranged on the P-type semiconductor channel region 11 of the second semiconductor material; a groove gate region is arranged in the middle position of the cell surface, the groove gate region penetrates into the voltage-resistant layer 2 of the first semiconductor material, the groove gate region includes a groove dielectric layer 10, a gate conductor 4 is arranged in the dielectric layer 10, and deep gates are arranged on both sides of the groove gate region. A groove is formed in the semiconductor voltage-resistant layer 2, the inner surface of the groove is covered with a P-type semiconductor region 3 of a fourth semiconductor material, the dielectric layer 10 also covers the surfaces of the N-type heavily doped source regions 6 of the third semiconductor material on both sides of the groove, the gate conductor 4 and the dielectric layer 10 located on the surface of the N-type heavily doped source region 6 of the third semiconductor material are covered with an isolation dielectric layer 7, an ohmic contact metal 8 is provided on the surface of the dielectric isolation layer 7, the surface of the P-type semiconductor region 3 of the fourth semiconductor material in the groove, and the N-type heavily doped source region 6 of the third semiconductor material, and a drain ohmic contact metal 9 is provided at the bottom of the substrate 1;

[0008] The invention is characterized in that the first semiconductor material and the second semiconductor material are different materials; the third semiconductor material and the second semiconductor material are the same semiconductor material, or the third semiconductor material and the second semiconductor material are different semiconductor materials, and the N-type doping concentration of the third semiconductor material is between 1×10 18 cm -3The P-type semiconductor region 3 of the fourth semiconductor material and the N-type voltage-resistant layer 2 of the first semiconductor material are different materials, and the P-type doping is generally 1×10 18 cm -3 As mentioned above, the two constitute a first heterojunction diode; the N-type voltage-withstanding layer 2 composed of the first semiconductor material and the P-type channel region 11 composed of the second semiconductor material form a second heterojunction diode.

[0009] Furthermore, the heterogeneous and heterogeneous trench-gate MOSFET device cell with integrated heterojunction diode is characterized in that the depth of the trench deep into the semiconductor voltage-resistant layer 2 is not less than the depth of the trench gate.

[0010] Furthermore, the heterogeneous, heterogeneous trench-gate MOSFET device cell with an integrated heterojunction diode is characterized in that when the first semiconductor material is Ga2O3, the second semiconductor material can be 4H-SiC, 3C-SiC, GaN, NiO, SnO2, ZnO, or any other P-type semiconductor material with a bandgap greater than 2eV that can be manufactured. By using P-type SiC, GaN, NiO, SnO2, ZnO, or any other P-type semiconductor material with a bandgap greater than 2eV that can be manufactured and N-type Ga2O3 to form a heterostructure, and using P-type SiC or GaN as the channel body region of the MOSFET, this completely resolves the technical bottleneck of Ga2O3 being unable to produce P-type doping for the first time, thus enabling the fabrication of an inversion layer enhancement-mode MOSFET.

[0011] Furthermore, the heterogeneous trench-gate MOSFET device cell with an integrated heterojunction diode is characterized in that when the first semiconductor material is 4H-SiC, the second semiconductor material can be Si or 3C-SiC. By utilizing the high inversion layer electron mobility of Si or 3C-SiC, the channel resistance of the device is further reduced.

[0012] Furthermore, the heterogeneous trench gate MOSFET device cell with integrated heterojunction diode is characterized in that when the first semiconductor material is GaN, AlGaN, or AlN, the second semiconductor material can be 4H-SiC or 3C-SiC. By taking advantage of SiC's high inversion layer electron mobility, the channel resistance of the device is further reduced.

[0013] Furthermore, the heterogeneous trench-gate MOSFET device cell with an integrated heterojunction diode is characterized in that the semiconductor of the third semiconductor material can be n-type polysilicon, n-type NiO, n-type IGZO, n-type ZnO, or the like. The fabrication process of n-type polysilicon, n-type NiO, n-type IGZO, or n-type ZnO is simple and low-cost, thus avoiding the process difficulties associated with fabricating a homogeneous N-type source region (i.e., the third semiconductor material and the second semiconductor material are the same material).

[0014] Furthermore, the heterojunction diode-integrated heterogeneous trench-gate MOSFET device cell is characterized in that the fourth semiconductor material can be a common wide-bandgap semiconductor material such as p-NiO or p-SnO2, which can be fabricated using simple processes such as sputtering. The resulting heterojunction diode is simple to fabricate, and by selecting the fourth semiconductor material, the turn-on voltage drop of the heterojunction can be reduced to less than 3V, thereby reducing reverse conduction loss and reverse recovery loss.

[0015] Furthermore, the heterogeneous, heterogeneous trench-gate MOSFET device cell with an integrated heterojunction diode is characterized in that a P-type semiconductor region 12 of a fifth semiconductor material is disposed below the P-type semiconductor region 3 of the fourth semiconductor material extending deep into the voltage-withstand layer 2, and extending deep into the N-type voltage-withstand layer 2 of the first semiconductor material. The P-type semiconductor region 12 of the fifth semiconductor material and the N-type voltage-withstand layer 2 of the first semiconductor material form a superjunction structure, i.e., the horizontal dose of the P-type semiconductor region 12 of the fifth semiconductor material below each P-type semiconductor region 3 in a single cell is equal to half the horizontal dose of the N-type voltage-withstand layer 2 of the first semiconductor material.

[0016] Furthermore, the heterogeneous trench-gate MOSFET device cell with an integrated heterojunction diode is characterized in that the fifth semiconductor material region and the first semiconductor material region are made of the same material. The first semiconductor material can be SiC, GaN, AlGaN, or AlN. All of these materials have P-type doping, allowing for direct fabrication of superjunction devices.

[0017] Furthermore, the heterogeneous trench-gate MOSFET device cell with an integrated heterojunction diode is characterized in that the fifth semiconductor material region and the first semiconductor material region are made of different materials. When the first semiconductor material is SiC, GaN, AlGaN, AlN, or Ga2O3, the fifth semiconductor material can be a wide-bandgap or ultra-wide-bandgap semiconductor material such as NiO, SnO2, or diamond. This solution increases manufacturing flexibility and feasibility and addresses the bottleneck of Ga2O3 not being able to form a superjunction without P-type doping.

[0018] 2. A heterogeneous, heterogeneous, wide-bandgap trench-gate MOSFET device cell, comprising:

[0019] A substrate 1 of a first semiconductor material, an N-type voltage-resistant layer 2 of the first semiconductor material arranged on the substrate 1, a second semiconductor material arranged on the N-type voltage-resistant layer 2 of the first semiconductor material; an N-type heavily doped source region 6 of a third semiconductor material arranged on the second semiconductor material; a groove gate region arranged in the middle position of the cell surface, the groove gate region penetrates into the semiconductor voltage-resistant layer 2, the groove gate region includes a dielectric layer 10 in the groove, a gate conductor 4 is arranged in the dielectric layer 10, and the side of the second semiconductor material close to the groove gate region is a partial P-type semiconductor channel region 11; grooves are respectively arranged on both sides of the groove gate region and penetrate into the semiconductor voltage-resistant layer 2; the grooves penetrate into the semiconductor voltage-resistant layer 2 and penetrate into the semiconductor voltage-resistant layer 2. A P-type electric field shielding region 3 of the first semiconductor material and a P-type connecting region 5 of the second semiconductor material are respectively provided around the groove in the layer 2, in the first semiconductor material, and in the second semiconductor material; the dielectric layer 10 also covers the surface of the N-type heavily doped source region 6 of the third semiconductor material on both sides of the groove; the gate conductor 4 and the dielectric layer 10 located on the surface of the N-type heavily doped source region 6 of the third semiconductor material are covered with an isolation dielectric layer 7; an ohmic contact metal 8 is provided on the surface of the dielectric isolation layer 7, in the groove deep into the semiconductor voltage-resistant layer 2, and on the N-type heavily doped source region 6 of the third semiconductor material; and a drain ohmic contact metal 9 is provided at the bottom of the substrate 1;

[0020] The invention is characterized in that the first semiconductor material and the second semiconductor material are different materials; the voltage-resistant layer 2 composed of the first semiconductor material and the P-type channel region 11 composed of the second semiconductor material form a heterojunction diode; the doping of the P-type electric field shielding region 3 and the P-type connecting region 5 is generally 1×10 18 cm -3 The third semiconductor material and the second semiconductor material are the same semiconductor material or the third semiconductor material and the second semiconductor material are different semiconductor materials, and the N-type doping concentration of the third semiconductor material is between 1×10 18 cm -3 above;

[0021] Furthermore, the heterogeneous wide bandgap trench gate MOSFET device cell is characterized in that the depth of the trench deep into the semiconductor voltage-resistant layer 2 is not less than the trench gate depth.

[0022] Furthermore, the heterogeneous, wide-bandgap trench-gate MOSFET device cell is characterized in that the third semiconductor material can be n-type polysilicon, NiO, IGZO, or ZnO. The fabrication process for n-type polysilicon, n-type NiO, n-type IGZO, or n-type ZnO is simple and low-cost, thus avoiding the process difficulties associated with fabricating a homogeneous n-type source region (i.e., the third semiconductor material and the second semiconductor material are the same material).

[0023] Furthermore, the heterogeneous wide bandgap trench-gate MOSFET device cell is characterized in that when the first semiconductor material is 4H-SiC, the second semiconductor material can be Si or 3C-SiC. By utilizing Si or 3C-SiC with high inversion layer electron mobility, the total resistance of the MOSFET device fabricated with 4H-SiC is reduced.

[0024] Furthermore, the heterogeneous wide bandgap trench-gate MOSFET device cell is characterized in that when the first semiconductor material is GaN, AlGaN, or AlN, the second semiconductor material can be 4H-SiC or 3C-SiC. By utilizing 4H-SiC or 3C-SiC, which has high inversion layer electron mobility (relative to GaN, AlGaN, and AlN), the total resistance of the MOSFET device made of GaN, AlGaN, or AlN is reduced.

[0025] The effective effects of the present invention are:

[0026] 1. The present invention uses heterogeneous heterostructures to form a P-type channel region 11. This region can flexibly adopt a variety of existing P-type semiconductor materials with high inversion layer electron mobility. This completely solves the international technical problem that Ga2O3 does not have an effective P-type semiconductor and cannot be used to manufacture normally-off MOSFET devices with inversion layer channels. By selecting different semiconductor materials, ultra-low inversion layer electron mobility can be flexibly provided to obtain low specific on-resistance. It also solves the technical problems of low inversion layer channel electron mobility and high channel resistance in MOSFETs made of 4H-SiC and GaN. It also solves the technical problem that AlGaN and AlN are currently difficult to manufacture normally-off MOSFET devices with inversion layer channels, as well as the technical problem of low inversion layer electron mobility and high on-resistance in the homojunctions.

[0027] 2. The bandgap of the semiconductor material used in the P-type channel region is often lower than that of the voltage-withstand layer 2 of the first semiconductor material. Therefore, the narrower bandgap of the P-type region 11 in the heterogeneous PN junction (composed of the P-type region 11 and the N-type region 2) is prone to premature breakdown during voltage withstand, failing to maintain the high breakdown voltage expected of the wider bandgap of the first semiconductor material 2. Therefore, the present invention further provides a P-type semiconductor region 3 of a fourth semiconductor material, or a P-type electric field shielding region 3 and a connecting region 5 composed of the first and second materials, on both sides of the trench gate. The P-type semiconductor region 3 of the fourth semiconductor material mentioned above adopts common wide bandgap semiconductor materials such as p-NiO and p-SnO2, which can be produced by simple and low-cost methods such as sputtering and CVD, and adopts a heavy doping setting. Even if its bandgap width is smaller than the bandgap width of the semiconductor material of the voltage-resistant layer 2, its critical breakdown electric field will increase exponentially under heavy doping conditions, so it can ensure a breakdown electric field of more than 10MV / cm, which is even much larger than the breakdown electric field of 8MV / cm of Ga2O3 material; and the P-type electric field shielding area 3 and the connecting area 5 composed of the first material mentioned above have the same critical breakdown electric field as the voltage-resistant layer 2 because the strongest electric field occurs at the bottom of the P-type area 3 of the first material, and will not break down prematurely. Therefore, the present invention utilizes the P-type semiconductor region 3 of the fourth semiconductor material or the P-type electric field shielding region 3 of the first material to form an effective electric field shield for the P-type channel region 11 of the second semiconductor material, so that when the voltage-resistant layer 2 of the first material breaks down, the strongest electric field of the P-type channel region 11 of the second semiconductor material is still lower than its critical breakdown electric field. Therefore, it is ensured that the voltage-resistant advantage of the first semiconductor material with a wider bandgap is brought into play. In addition, the P-type semiconductor region 3 of the fourth semiconductor material or the P-type electric field shielding region 3 of the first material also forms an effective electric field shield for the gate oxide layer 10, so that its strongest electric field is within a suitable range (for example, SiO2 needs to be suppressed below 4MV / cm), ensuring that the dielectric layer 10 will not break down prematurely and long-term gate oxide reliability. By increasing the depth of the groove deep into the semiconductor voltage-resistant layer 2, the trade-off optimization relationship between the electric field shielding effect and the breakdown voltage and the specific on-resistance can be flexibly adjusted.

[0028] 3. For heterojunction diode-integrated wide-bandgap and ultra-wide-bandgap trench-gate MOSFET device cells, the currently suitable second heterojunction diodes, consisting of a P-type channel region 11 of a second semiconductor material and an N-type voltage-resistant layer 2 of a first semiconductor material, have a high reverse conduction voltage drop, which is not conducive to reducing reverse conduction losses. However, the present invention selects a P-type semiconductor region 3 of a fourth semiconductor material for electric field shielding. This, together with the first semiconductor material region 2, forms a first heterojunction diode with a low conduction voltage drop. This significantly reduces the reverse conduction voltage drop, avoids the use of the second heterojunction diode for conduction, and thus significantly reduces reverse conduction losses. Furthermore, the heterojunction diode operates in a unipolar conduction mode, avoiding the increased reverse recovery losses caused by conductivity modulation in homojunction PN junction diodes and the increase in reverse recovery losses caused by temperature increases. For example, a first heterojunction diode composed of p-NiO and n-Ga2O3 has a reverse turn-on voltage drop of approximately 2V and a conduction voltage drop of approximately 3V. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 Schematic diagram of a heterojunction-type wide-bandgap and ultra-wide-bandgap trench-gate MOSFET device cell with an integrated heterojunction diode in the present invention.

[0030] Figure 2 This is a schematic diagram of another heterojunction diode integrated heterojunction type wide bandgap and ultra-wide bandgap trench gate MOSFET device cell in the present invention.

[0031] Figure 3 This is a schematic diagram of a heterojunction heterostructure wide bandgap trench gate superjunction MOSFET device cell with an integrated heterojunction diode in the present invention.

[0032] Figure 4 This is a schematic diagram of another heterojunction heterojunction diode integrated heterojunction MOSFET device cell in the present invention.

[0033] Figure 5 This is a schematic diagram of a heterojunction-type wide bandgap trench-gate MOSFET device cell with an integrated heterojunction diode in the present invention.

[0034] Figure 6 This is a schematic diagram of another heterojunction diode integrated heterojunction type wide bandgap trench gate MOSFET device cell in the present invention.

[0035] Figure 7 The transfer characteristics of the device simulation corresponding to a design in Example 1 of the present invention are compared with those of the traditional structure.

[0036] Figure 8 The reverse conduction characteristics of a device corresponding to a design in Example 1 of the present invention are compared with those of a traditional structure.

[0037] Figure 9 (a) (b) are the electric field distribution diagrams of the device during breakdown corresponding to the two parameters in Example 1 of the present invention.

[0038] In the figure: 1 is the substrate of the first semiconductor material; 2 is the N-type voltage-resistant layer of the first semiconductor material; 3 is the P-type electric field shielding region of the first or fourth semiconductor material; 4 is the gate conductor; 5 is the P-type connection region of the second semiconductor material; 6 is the N-type heavily doped source region of the third semiconductor material; 7 is the isolation dielectric layer; 8 is the ohmic contact metal; 9 is the drain ohmic contact metal; 10 is the dielectric layer in the trench; 11 is the P-type channel region composed of the second semiconductor material; 12 is the P-type semiconductor region of the fifth semiconductor material. DETAILED DESCRIPTION

[0039] In order to make the purpose, technical solution and technical effect of the present invention clearer, the technical solution in the embodiment of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiment is only a part of the embodiment of the present invention, rather than all the embodiments.

[0040] Example 1

[0041] This embodiment provides a heterojunction-type heterostructured trench-gate Ga2O3 MOSFET device with an integrated heterojunction diode, the structure of which is as follows: Figure 1 and Figure 2 Shown, including:

[0042] N-type heavily doped Ga2O3 substrate 1, N-type Ga2O3 voltage-resistant layer 2 arranged on substrate 1; groove gate region arranged in the middle position of cell surface, groove gate region includes groove inner dielectric layer 10, and gate conductor 4 is arranged in dielectric layer 10; grooves ( Figure 1 The depth of the groove is the same as the groove grid. Figure 2 The depth of the groove is greater than the depth of the groove gate), and the groove is covered with a layer of heavily doped heterogeneous (different from the material of the voltage-resistant layer 2) semiconductor film 3; the heterogeneous semiconductor film 3 can be p-NiO or p-SnO2 or other P-type wide bandgap semiconductor materials (bandgap width is greater than 2eV) that can be produced by simple processes such as sputtering and CVD; a P-type channel region 11 of another semiconductor material is provided on the N-type Ga2O3 voltage-resistant layer 2 between the heavily doped heterogeneous semiconductor film 3 and the groove gate, and a heavily doped N + The source region 6. The gate conductor 4 and the heavily doped N + The dielectric layer 10 on the surface of the source region 6 is covered with an isolation dielectric layer 7. The surface of the dielectric isolation layer 7, the surface of the P-type heterogeneous semiconductor region 3 in the trench and the heavily doped N +An ohmic contact metal 8 is provided on the source region 6, and a drain ohmic contact metal 9 is provided at the bottom of the substrate 1;

[0043] The P-type channel region 11 and the N + The source region 6 is made of the same semiconductor material, which can be any P-type semiconductor with a band gap greater than 2eV, such as 3C-SiC or 4H-SiC or GaN or NiO or ZnO or SnO2; or the P-type channel region 11 is any P-type semiconductor with a band gap greater than 2eV, such as 3C-SiC or 4H-SiC or GaN or NiO or ZnO or SnO2, and the N + The source region 6 is any N-type semiconductor that can be made by simple processes such as sputtering, CVD, etc., such as polysilicon, NiO, IGZO, or ZnO, and is made of a different material from the P-type channel region 11 to avoid making the same material (the P-type channel region 11 and the N + The source region 6 is made of the same material) + The source region 6 brings process difficulties. The doping concentration of the P-type channel region 11 is generally 5×10 16 cm -3 to 5×10 17 cm -3 The P-type doping of the P-type heterogeneous semiconductor region 3 is generally between 1×10 18 cm -3 In the above, the depth of the trench is not less than the trench gate depth. In this embodiment, the P-type channel region 11 of the second semiconductor material cannot be made of Si. This is because Ga2O3 has a very high critical breakdown electric field, while the critical breakdown electric field of Si is too low, making it difficult to use an electric field shielding structure to suppress its electric field within the breakdown electric field, thereby failing to fully utilize the high breakdown electric field advantage of Ga2O3.

[0044] The working principle of the MOSFET power device in this embodiment is as follows:

[0045] This implementation, for the first time, completely overcomes the technical bottleneck of Ga2O3 devices, which prevent them from fabricating normally-off MOSFET devices with inversion layer channels. By providing a P-type 3C-SiC, 4H-SiC, GaN, or NiO, ZnO, or SnO2 channel layer on the Ga2O3 voltage-sustaining layer, when the gate voltage is less than the threshold voltage, the second heterojunction diode formed by the P-type 3C-SiC, 4H-SiC, GaN, or NiO, ZnO, or SnO2 channel layer and the Ga2O3 withstands the reverse voltage. This withstand voltage is achieved without the need for a high-resistance region formed by a fin-gate or nitrogen or magnesium implantation, and the reverse leakage current of the heterojunction diode is extremely low. Furthermore, the junction depth of the first heterojunction diode, formed by the P-type heavily doped heterogeneous semiconductor region 3 on both sides of the trench gate and the Ga2O3 voltage-sustaining layer 2, is greater than that of the second heterojunction diode, thereby accelerating the expansion of the depletion region of the N-type region 2 during reverse voltage withstand. Therefore, the primary withstand voltage is borne by the first heterojunction diode, creating a strong electric field shielding effect on the interface of the second heterojunction diode, ensuring that breakdown occurs in the Ga2O3 N-type withstand voltage layer 2 rather than the P-type heterojunction channel region with a lower breakdown electric field. Furthermore, during reverse freewheeling conduction, the turn-on voltage of the first heterojunction diode is typically no higher than 3V, ensuring a low reverse conduction voltage drop, low reverse recovery loss for a unipolar diode, and low turn-on loss for adjacent diodes.

[0046] When the gate voltage is greater than the threshold voltage of the P-type heterogeneous channel region, an inversion layer is formed at the interface of the P-type channel body region 11 composed of 4H-SiC, 3C-SiC or GaN or NiO with simple process, or ZnO or SnO2 adjacent to the gate oxide layer 10, so that the N + The source region 6 is connected to the Ga2O3 N-type voltage-resistant layer 2, and the device is conductive. 3C-SiC has a very high inversion layer electron mobility (~300cm 2 / Vs) can ensure that Ga2O3 MOSFET obtains a specific on-resistance close to the theoretical limit. Although the inversion layer channel electron mobility of 4H-SiC and GaN is relatively low (less than 100cm 2 ·V -1 s -1 ), the electron mobility of the inversion layer of NiO, ZnO or SnO2 is predicted to be lower than that of 4H-SiC and GaN, but they can all be used to realize normally-off Ga2O3 MOSFET devices with inversion layer channel conduction, breaking through the technical bottleneck of the existing technology that cannot make a P-type channel body region to make an inversion layer normally-off MOSFET, and their channel resistance is also very small compared to the drift region resistance of high-voltage Ga2O3 MOSFET.

[0047] In one specific case of this embodiment, the P-type channel body region 11 is 4H-SiC with a thickness of 0.5 μm and a doping ratio of 3.3×10 17 cm -3 , source N + Region 6 is doped with 1×10 19 cm -3 , 4H-SiC with a thickness of 0.2 μm, N-type Ga2O3 voltage-resistant layer 2 with a thickness of 9 μm, doped with 1×10 16 cm -3 , substrate 1 is doped with 1×10 19 cm -3 Ga2O3 (due to heavy doping, it is only set to 2um in simulation), the dielectric layer 10 is 50nm Al2O3, and the heavily doped heterogeneous semiconductor film 3 is doped 5×10 19 cm -3 , p-NiO with a thickness of 200nm, the gate conductor 4 is Ni metal, the source metal 8 and the drain metal 9 are 100nm Ti metal (metal is replaced by electrode in the simulation program), and the dielectric isolation layer 7 is 500nm SiO2.

[0048] Figure 7 The transfer characteristic curve is compared with the traditional Fin-gate structure. The depth of the trench gate is 1μm, and the depth of the trench where the heterogeneous semiconductor film 3 is located is T HJ There are two cases of 1μm and 1.5μm. At the same time, different Fin widths (W Fin ) of the traditional Fin-gate device. It can be seen that although the Fin-gate device can obtain a lower specific on-resistance (R on,sp ), but in order to obtain the same threshold voltage, the width of the Fin is only 50nm, which greatly increases the process difficulty and cost. In addition, if the P-type channel body region 11 of the present invention adopts 3C-SiC, the specific on-resistance of the present invention can be further reduced.

[0049] Figure 8 The reverse conduction characteristics of the two are compared. It can be seen that the present invention is due to the integration of the first heterojunction diode with low turn-on voltage (composed of P-type heterojunction semiconductor region 3 and N-type voltage-resistant layer 2). When conducting in the reverse direction, the current flows through the first heterojunction diode, thereby reducing the reverse conduction voltage drop (V r ) is ~2V lower than Fin-gate, which can significantly reduce reverse conduction loss. Figure 9 The figure shows the electric field shielding effect of the P-type heterogeneous semiconductor region 3 (p-NiO) on the P-type channel region 11 (4H-SiC) and the trench gate dielectric layer 10 (Al2O3) of the second semiconductor material with a lower critical breakdown electric field. It can be seen that when the device breaks down, T HJ=1um and 1.5um, the electric field in the Ga2O3 voltage-resistant layer 2 reaches ~8MV / cm and 9MV / cm. The electric field of 4H-SiC is only ~1.1MV / cm and 0.4MV / cm, which is lower than its critical breakdown electric field of 3MV / cm. Therefore, the device breakdown occurs in the Ga2O3, giving full play to the advantage of Ga2O3's high critical breakdown electric field. In addition, T HJ =1μm, the strongest electric field of Al2O3 in this embodiment reaches 11.5MV / cm, which means that the gate dielectric has already broken down before Ga2O3 breaks down. HJ = 1 μm of the present embodiment is close (not shown), in fact, the gate dielectric has already broken down before Ga2O3 breaks down, that is, the breakdown voltage of the conventional Fin-gate device is much lower than that of the present invention. HJ =1.5um breakdown voltage. In this embodiment, the depth of the groove where the heterogeneous semiconductor film 3 is located is increased from 1μm to 1.5μm, and the strongest electric field of Al2O3 is shielded below 4.9MV / cm, thereby ensuring the reliability of the gate oxide layer. HJ Only slightly increase the specific on-resistance and reverse conduction voltage drop, such as Figure 7 、 8 shown.

[0050] When the P-type heterogeneous semiconductor region 3 is 3C-SiC or GaN or NiO or ZnO or SnO2, the present invention will have similar effects to the above-mentioned specific embodiments, specifically, it can easily realize a normally-off Ga2O3 MOSFET device with adjustable threshold voltage, low specific on-resistance and low reverse conduction voltage drop. In terms of specific on-resistance, due to the higher electron mobility of the inversion layer of 3C-SiC (~300cm 2 / Vs), the channel resistance is lower. Therefore, when the P-type heterogeneous semiconductor region 3 is 3C-SiC, the specific on-resistance of the heterogeneous heterogeneous MOSFET device is lower than that of the heterogeneous heterogeneous MOSFET device composed of 4H-SiC materials. When the P-type heterogeneous semiconductor region 3 is GaN, NiO, ZnO, or SnO2, since the inversion layer electron mobility is lower than that of the 4H-SiC inversion layer electron mobility, the specific on-resistance of the heterogeneous heterogeneous MOSFET device will be slightly higher than that of the heterogeneous heterogeneous MOSFET device composed of 4H-SiC materials.

[0051] Example 2

[0052] This embodiment provides a heterojunction-type heterostructured trench-gate SiC MOSFET device with an integrated heterojunction diode, the structure of which is as follows: Figure 1 、 Figure 2 Shown, including:

[0053] An N-type heavily doped 4H-SiC substrate 1, an N-type 4H-SiC voltage-resistant layer 2 provided on the substrate; a trench gate region provided in the middle of the cell surface, the trench gate region including a trench dielectric layer 10, a gate conductor 4 provided in the dielectric layer; trenches ( Figure 1 The depth of the groove is the same as the groove grid. Figure 2 The depth of the groove is greater than the depth of the groove gate), and a heavily doped heterogeneous semiconductor film 3 is provided in the groove to cover it; the heterogeneous semiconductor film 3 is p-NiO or p-SnO2 or other P-type wide bandgap semiconductor materials that can be produced by simple processes such as sputtering and CVD. A P-type channel region 11 made of another semiconductor material is provided on the N-type 4H-SiC voltage-resistant layer 2 between the heavily doped heterogeneous semiconductor film 3 and the groove gate, and a heavily doped N + The source region 6. The gate conductor 4 and the heavily doped N + The dielectric layer 10 on the surface of the source region 6 is covered with an isolation dielectric layer 7. The surface of the dielectric isolation layer 7, the surface of the P-type heterogeneous semiconductor region 3 in the trench and the heavily doped N + An ohmic contact metal 8 is provided on the source region 6, and a drain ohmic contact metal 9 is provided at the bottom of the substrate 1;

[0054] The P-type channel region 11 and the N + The source region 6 is made of the same semiconductor material, which can be 3C-SiC or Si; or N + The source region 6 is an N-type semiconductor such as polysilicon or NiO or IGZO or ZnO which can be produced by simple processes such as sputtering and CVD, thereby avoiding the production of homogeneous (P-type channel region 11 and N + The source region 6 is made of the same material) + The source region 6 brings process difficulties. The doping concentration of the P-type channel region 11 is generally 5×10 16 cm -3 to 5×10 17 cm -3 The P-type doping of the P-type heterogeneous semiconductor region 3 is generally between 1×10 18 cm -3 Above, the depth of the groove is not less than the groove gate depth.

[0055] The working principle and beneficial effects of this embodiment are the same as those of Example 1, except that the substrate 1 and the voltage-resistant layer 2 are made of SiC material, and the second P-type channel region can be Si or 3C-SiC material. 3C-SiC or Si with high inversion layer electron mobility is used to reduce the resistance of the 4H-SiC inversion layer channel, and the first heterojunction diode formed by the P-type heterogeneous semiconductor region 3 and the voltage-resistant layer 2 is used to reduce the reverse conduction voltage drop, and to form an electric field shield for the P-type channel region 11 of the second semiconductor material and the bottom of the gate oxide layer. In addition, when Si is used as the P-type channel region, the second heterojunction diode formed by Si and the SiC voltage-resistant layer 2 has a lower conduction voltage drop than the first heterojunction diode described above.

[0056] Example 3

[0057] This embodiment provides a heterojunction diode integrated heterojunction type trench gate GaN or AlGaN or AlN MOSFET device, the structure of which is as follows: Figure 1-2 As shown, including:

[0058] N-type heavily doped GaN or AlGaN or AlN substrate 1, N-type GaN or AlGaN or AlN voltage-resistant layer 2 arranged on the substrate; a groove gate region arranged in the middle position of the cell surface, the groove gate region includes a groove dielectric layer 10, and a gate conductor 4 is arranged in the dielectric layer; grooves ( Figure 1 The depth of the groove is the same as the groove grid. Figure 2 The depth of the groove is greater than the depth of the groove gate), and a heavily doped heterogeneous semiconductor film 3 is provided in the groove to cover it; the heterogeneous semiconductor film 3 is p-NiO or p-SnO2 or other P-type wide bandgap semiconductor materials that can be produced by simple processes such as sputtering and CVD; a P-type channel region 11 of another semiconductor material is provided on the N-type GaN or AlGaN or AlN voltage-resistant layer 2 between the heavily doped heterogeneous semiconductor film 3 and the groove gate, and a heavily doped N + The source region 6. The gate conductor 4 and the heavily doped N + The dielectric layer 10 on the surface of the source region 6 is covered with an isolation dielectric layer 7. The surface of the dielectric isolation layer 7, the surface of the P-type heterogeneous semiconductor region 3 in the trench and the heavily doped N + An ohmic contact metal 8 is provided on the source region 6, and a drain ohmic contact metal 9 is provided at the bottom of the substrate 1;

[0059] The P-type channel region 11 and the N + The source region 6 is made of the same semiconductor material, which can be 3C-SiC or 4H-SiC; or N +The source region 6 is an N-type semiconductor such as polysilicon or NiO or IGZO or ZnO which can be produced by simple processes such as sputtering and CVD, thereby avoiding the production of homogeneous N + The source region 6 brings process difficulties. The doping concentration of the P-type channel region 11 is generally 5×10 16 cm -3 to 5×10 17 cm -3 The P-type doping of the P-type heterogeneous semiconductor region 3 is generally between 1×10 18 cm -3 Above, the depth of the groove is not less than the groove gate depth.

[0060] The working principle and beneficial effects of this embodiment are the same as those of embodiment 1 or embodiment 2, except that the substrate 1 and the voltage-resistant layer 2 are made of GaN, AlGaN, or AlN materials, and the second P-type channel region can be made of 4H-SiC or 3C-SiC material. 3C-SiC or 4H-SiC with high inversion layer electron mobility (the channel mobility of 4H-SiC is lower than that of 3C-SiC, but higher than that of GaN, AlGaN, and AlN) is used to reduce the resistance of the GaN, AlGaN, or AlN inversion layer channel, and a heterojunction diode formed by the P-type heterogeneous semiconductor region 3 and the voltage-resistant layer 2 is used to reduce the reverse conduction voltage drop, and to form an electric field shield for the P-type channel region 11 of the second semiconductor material and the bottom of the gate oxide layer.

[0061] In this embodiment, it is not recommended to use Si for the P-type channel region 11 of the second semiconductor material. This is because GaN, AlGaN, and AlN have a higher critical breakdown electric field than SiC, and the critical breakdown electric field of Si is too low, and it is difficult to use an electric field shielding structure to suppress its electric field within the breakdown electric field, thereby failing to fully utilize the advantages of the high breakdown electric field of GaN, AlGaN, and AlN.

[0062] Example 4

[0063] This embodiment provides a heterojunction heterostructure wide bandgap and ultra-wide bandgap trench gate MOSFET superjunction device cell with integrated heterojunction diode, such as Figure 3 and 4 ( Figure 3 The depth of the groove is the same as the groove grid. Figure 4The depth of the trench is greater than the trench gate depth. In addition to Embodiment 2 or 3, a P-type semiconductor region 12 of a fifth semiconductor material is provided below the P-type semiconductor region 3 of the fourth semiconductor material extending deep into the voltage-withstand layer 2, extending deep into the N-type voltage-withstand layer 2 of the first semiconductor material. The P-type semiconductor region 12 of the fifth semiconductor material and the N-type voltage-withstand layer 2 of the first semiconductor material form a superjunction structure, i.e., the horizontal dose of the P-type semiconductor region 12 of the fifth semiconductor material below each P-type semiconductor region 3 in a single cell is equal to half the horizontal dose of the N-type voltage-withstand layer 2 of the first semiconductor material.

[0064] The fifth semiconductor material region and the first semiconductor material region are made of the same material, which may be SiC, GaN, AlGaN or AlN.

[0065] The fifth semiconductor material region and the first semiconductor material region are made of different materials, and may be wide bandgap or ultra-wide bandgap semiconductor materials such as NiO, SnO2, or diamond.

[0066] The working principle and beneficial effects of this embodiment are similar to those of Embodiments 2 and 3. By introducing a superjunction region, the breakdown voltage is further increased and the specific on-resistance is reduced. Furthermore, diamond has high thermal conductivity, which can reduce the thermal resistance of the device and lower the device operating temperature.

[0067] Example 5

[0068] This embodiment provides a heterojunction Ga2O3 trench gate MOSFET superjunction device cell with an integrated heterojunction diode, such as Figure 3 and 4 ( Figure 3 The depth of the groove is the same as the groove grid. Figure 4 The depth of the groove is greater than the depth of the trench gate). On the basis of Example 1, a P-type semiconductor region 12 of a fifth semiconductor material that penetrates into the N-type voltage-resistant layer 2 of the first semiconductor material is further provided below the P-type semiconductor region 3 of the fourth semiconductor material that penetrates into the voltage-resistant layer 2. The P-type semiconductor region 12 of the fifth semiconductor material and the N-type voltage-resistant layer 2 of the first semiconductor material constitute a super junction structure, that is, the horizontal dose of the P-type semiconductor region 12 of the fifth semiconductor material below each P-type semiconductor region 3 in a single cell is equal to half the horizontal dose of the N-type voltage-resistant layer 2 of the first semiconductor material. The fifth semiconductor material region and the first semiconductor material region are different materials. It can be a wide bandgap or ultra-wide bandgap semiconductor material such as NiO or SnO2 or diamond.

[0069] The operating principle and beneficial effects of this embodiment are similar to those of Example 1. Since Ga2O3 is not P-type doped, this embodiment uses heavily P-type doped NiO (increasing its breakdown electric field to reach that of Ga2O3) or heavily P-type doped SnO2 (increasing its breakdown electric field to reach that of Ga2O3) or diamond to implement a P-type charge compensation region, thereby achieving a superjunction structure to further increase the breakdown voltage and reduce the specific on-resistance. Diamond also has high thermal conductivity, which can reduce the thermal resistance of the device and lower the device operating temperature.

[0070] Example 6

[0071] A heterogeneous and heterogeneous SiC trench gate MOSFET device cell, its structure is as follows Figure 5 、 Figure 6 As shown ( Figure 5 The depth of the groove is the same as the groove grid. Figure 6 The depth of the trench is greater than the trench gate depth), including:

[0072] An N-type heavily doped 4H-SiC substrate 1, an N-type 4H-SiC voltage-resistant layer 2 arranged on the substrate 1, a groove gate region arranged in the middle position of the cell surface, the groove gate region including a dielectric layer 10 in the groove, a gate conductor 4 arranged in the dielectric layer 10, grooves deep into the semiconductor voltage-resistant layer 2 are respectively arranged on both sides of the groove gate region, a second semiconductor material is arranged between the groove gate region and the groove deep into the semiconductor voltage-resistant layer 2 and above the semiconductor region 2; a side of the second semiconductor material close to the N-type voltage-resistant layer 2 is a partial P-type semiconductor channel region 11, and an N-type heavily doped source region 6 of a third semiconductor material is arranged above the P-type semiconductor channel region 11; the deep semiconductor voltage-resistant layer 2, in the 4H-SiC material, and in the second semiconductor material, a P-type 4H-SiC electric field shielding region 3 and a P-type connection region 5 of the second semiconductor material are respectively provided; the dielectric layer 10 also covers the surface of the N-type semiconductor region 6 of the third semiconductor material on both sides of the groove; the gate conductor 4 and the dielectric layer 10 located on the surface of the N-type semiconductor region 6 of the third semiconductor material are covered with an isolation dielectric layer 7; an ohmic contact metal 8 is provided on the surface of the dielectric isolation layer 7, in the groove deep into the semiconductor voltage-resistant layer 2, and on the N-type heavily doped source region 6 of the third semiconductor material; and a drain ohmic contact metal 9 is provided at the bottom of the substrate 1;

[0073] The second semiconductor material and the third semiconductor material can be the same, Si or 3C-SiC; or the third semiconductor material can be polysilicon or NiO or IGZO, which can be made by simple processes such as sputtering and CVD, and can avoid making homogeneous N + The process difficulty brought by the source region 6. The doping of the P-type channel region 11 is generally 5×10 16cm -3 to 5×10 17 cm -3 The doping of the P-type electric field shielding region 3 composed of 4H-SiC and the P-type connecting region 5 composed of Si or 3C-SiC is generally 1×10 18 cm -3 The depth of the trench extending into the semiconductor voltage-resistant layer 2 is not less than the trench gate depth.

[0074] The operating principles and beneficial effects of this embodiment are similar to those of Example 2. Si or 3C-SiC materials with high inversion layer electron mobility are used to form a P-type channel region 11, reducing the device channel resistance. Furthermore, the P-type 4H-SiC electric field shielding regions 3 on both sides of the trench gate provide electric field protection for the Si or 3C-SiC with a low breakdown electric field, thereby achieving the high breakdown voltage expected of 4H-SiC. This embodiment does not form a first heterojunction diode with a low forward voltage drop as in Example 2. However, the reverse forward voltage drop of the heterojunction diode formed by the 4H-SiC voltage-resistant layer 2 and the second semiconductor material (Si or 3C-SiC) is still lower than that of the PN junction diode of the 4H-SiC homojunction.

[0075] Example 7

[0076] A heterogeneous heterogeneous GaN or AlGaN or AlN trench gate MOSFET device cell, the structure of which is as follows Figure 5 、 Figure 6 As shown ( Figure 5 The depth of the groove is the same as the groove grid. Figure 6 The depth of the trench is greater than the trench gate depth), including:

[0077] An N-type heavily doped GaN or AlGaN or AlN substrate 1, a homogeneous N-type GaN or AlGaN or AlN voltage-resistant layer 2 arranged on the substrate 1; a groove gate region arranged in the middle position of the cell surface, the groove gate region including a dielectric layer 10 in the groove, a gate conductor 4 is arranged in the dielectric layer 10, grooves are respectively arranged on both sides of the groove gate region that penetrate into the semiconductor voltage-resistant layer 2, a second semiconductor material is arranged between the groove gate region and the grooves that penetrate into the semiconductor voltage-resistant layer 2, and above the semiconductor region 2; the side of the second semiconductor material close to the N-type voltage-resistant layer 2 is a partial P-type semiconductor channel region 11, and an N-type heavily doped source region 6 of a third semiconductor material is arranged above the P-type semiconductor channel region 11; the grooves that penetrate into the semiconductor voltage-resistant layer 2 are arranged in the middle position of the cell surface; A P-type GaN, AlGaN, or AlN electric field shielding region 3 and a P-type connection region 5 of the second semiconductor material are respectively provided around the groove in the layer 2, in the GaN, AlGaN, or AlN material, and in the second semiconductor material; the dielectric layer 10 also covers the surface of the N-type semiconductor region 6 of the third semiconductor material on both sides of the groove; the gate conductor 4 and the dielectric layer 10 located on the surface of the N-type semiconductor region 6 of the third semiconductor material are covered with an isolation dielectric layer 7; an ohmic contact metal 8 is provided on the surface of the dielectric isolation layer 7, in the groove deep into the semiconductor voltage-resistant layer 2, and on the N-type heavily doped source region 6 of the third semiconductor material; and a drain ohmic contact metal 9 is provided at the bottom of the substrate 1;

[0078] The second semiconductor material and the third semiconductor material can be the same, 3C-SiC or 4H-SiC; or the third semiconductor material can be polycrystalline silicon or NiO or IGZO, which can be made by simple processes such as sputtering and CVD, and can avoid making homogeneous N + The process difficulty brought by the source region 6. The doping of the P-type channel region 11 is generally 5×10 16 cm -3 to 5×10 17 cm -3 The doping of the P-type electric field shielding region 3 composed of GaN or AlGaN or AlN and the P-type connecting region 5 composed of 3C-SiC or 4H-SiC is generally 1×10 18 cm -3 The depth of the trench extending into the semiconductor voltage-resistant layer 2 is not less than the trench gate depth.

[0079] The operating principle and beneficial effects of this embodiment are similar to those of Example 3. A P-type channel region 11 is formed using 3C-SiC or 4H-SiC materials with high inversion layer electron mobility (the channel mobility of 4H-SiC is lower than that of 3C-SiC, but higher than that of GaN, AlGaN, and AlN) to reduce the device channel resistance. Furthermore, an electric field shielding region 3 formed of P-type GaN, AlGaN, or AlN on both sides of the trench gate and a P-type connection region 5 formed of 3C-SiC or 4H-SiC provide electric field protection for the low breakdown electric field of the 3C-SiC or 4H-SiC, thereby achieving the high breakdown voltage expected of GaN, AlGaN, or AlN. This embodiment does not form the first type of heterojunction diode with a low on-state voltage drop as in Example 3. However, the reverse conduction voltage drop of the heterojunction diode formed by the 3C-SiC or 4H-SiC and the GaN, AlGaN, or AlN of the voltage-resistant layer 2 is still lower than that of the PN junction diode of the homojunction of GaN, AlGaN, or AlN.

[0080] The above description is only a specific embodiment of the present invention. Any feature disclosed in this specification, unless otherwise stated, can be replaced by other equivalent or alternative features with similar purposes; all disclosed features, or all steps in the methods or processes, except for mutually exclusive features and / or steps, can be combined in any way.

Claims

1. A heterojunction, heterostructured, wide-bandgap and ultra-wide-bandgap trench-gate MOSFET device cell with an integrated heterojunction diode, comprising: A substrate 1 made of a first semiconductor material, and an N-type voltage-resistant layer 2 made of the first semiconductor material disposed on the substrate 1; A P-type semiconductor channel region 11 of a second semiconductor material is provided on the N-type voltage-resistant layer 2 of the first semiconductor material, and an N-type heavily doped source region 6 of a third semiconductor material is provided on the P-type semiconductor channel region 11 of the second semiconductor material; a groove gate region is provided in the middle position of the cell surface, the groove gate region penetrates into the voltage-resistant layer 2 of the first semiconductor material, the groove gate region includes a groove inner dielectric layer 10, a gate conductor 4 is provided in the dielectric layer 10, grooves are respectively provided on both sides of the groove gate region that penetrate into the semiconductor voltage-resistant layer 2, and the inner surface of the groove is covered with a The P-type semiconductor region 3 is covered with a fourth semiconductor material. The dielectric layer 10 also covers the surfaces of the N-type heavily doped source region 6 of the third semiconductor material on both sides of the trench. The gate conductor 4 and the dielectric layer 10 located on the surface of the N-type heavily doped source region 6 of the third semiconductor material are covered with an isolation dielectric layer 7. Ohmic contact metal 8 is provided on the surface of the dielectric isolation layer 7, the surface of the P-type semiconductor region 3 of the fourth semiconductor material in the trench, and the N-type heavily doped source region 6 of the third semiconductor material. A drain ohmic contact metal 9 is provided at the bottom of the substrate 1. The invention is characterized in that the first semiconductor material and the second semiconductor material are different materials; the third semiconductor material and the second semiconductor material are the same semiconductor material, or the third semiconductor material and the second semiconductor material are different semiconductor materials, and the N-type doping concentration of the third semiconductor material is between 1×10 18 cm -3 The P-type semiconductor region 3 of the fourth semiconductor material and the N-type voltage-resistant layer 2 of the first semiconductor material are different materials, and the P-type doping is generally 1×10 18 cm -3 As mentioned above, the two constitute a first heterojunction diode; the N-type voltage-withstanding layer 2 composed of the first semiconductor material and the P-type channel region 11 composed of the second semiconductor material form a second heterojunction diode.

2. The heterojunction diode integrated heterojunction type wide bandgap and ultra-wide bandgap trench gate MOSFET device cell according to claim 1, characterized in that The depth of the groove extending deep into the semiconductor voltage-resistant layer 2 is not less than the depth of the trench gate.

3. The heterojunction diode integrated heterojunction type wide bandgap and ultra-wide bandgap trench gate MOSFET device cell according to claim 1, characterized in that When the first semiconductor material is Ga2O3, the second semiconductor material is 4H-SiC or 3C-SiC or GaN or NiO or SnO2 or ZnO or any other P-type semiconductor material that can be manufactured with a band gap greater than 2eV.

4. The heterojunction diode integrated heterojunction type wide bandgap and ultra-wide bandgap trench gate MOSFET device cell according to claim 1, characterized in that When the first semiconductor material is 4H-SiC, the second semiconductor material is Si or 3C-SiC.

5. The heterojunction diode integrated heterojunction type wide bandgap and ultra-wide bandgap trench gate MOSFET device cell according to claim 1, characterized in that When the first semiconductor material is GaN, AlGaN, or AlN, the second semiconductor material is 4H-SiC or 3C-SiC.

6. The heterojunction diode integrated heterojunction type wide bandgap and ultra-wide bandgap trench gate MOSFET device cell according to claim 1, characterized in that The semiconductor of the third semiconductor material is n-type polysilicon, n-type NiO, n-type IGZO, n-type ZnO, etc.

7. The heterojunction diode-integrated wide-bandgap and ultra-wide-bandgap trench-gate MOSFET device cell according to claim 1, characterized in that The semiconductor of the fourth semiconductor material is common wide bandgap semiconductor materials such as p-NiO and p-SnO2.

8. The heterojunction diode-integrated wide-bandgap and ultra-wide-bandgap trench-gate MOSFET device cell according to claims 1, 2, 3, 4, 5, 6, and 7, characterized in that A P-type semiconductor region 12 of a fifth semiconductor material is arranged below the P-type semiconductor region 3 of the fourth semiconductor material that penetrates into the voltage-resistant layer 2; the P-type semiconductor region 12 of the fifth semiconductor material and the N-type voltage-resistant layer 2 of the first semiconductor material constitute a super junction structure, that is, the horizontal dose of the P-type semiconductor region 12 of the fifth semiconductor material below each P-type semiconductor region 3 in a single cell is equal to half of the horizontal dose of the N-type voltage-resistant layer 2 of the first semiconductor material.

9. The heterojunction diode-integrated wide-bandgap and ultra-wide-bandgap trench-gate MOSFET device cell according to claim 8, characterized in that The fifth semiconductor material region and the first semiconductor material region are made of the same material.

10. The heterojunction diode-integrated wide-bandgap and ultra-wide-bandgap trench-gate MOSFET device cell according to claim 8, characterized in that The fifth semiconductor material region and the first semiconductor material region are made of different materials.

11. A heterogeneous, heterostructured wide bandgap trench gate MOSFET device cell, comprising: A substrate 1 of a first semiconductor material, an N-type voltage-resistant layer 2 of the first semiconductor material arranged on the substrate 1, a second semiconductor material arranged on the N-type voltage-resistant layer 2 of the first semiconductor material; an N-type heavily doped source region 6 of a third semiconductor material arranged on the second semiconductor material; a groove gate region arranged in the middle position of the cell surface, the groove gate region penetrates into the semiconductor voltage-resistant layer 2, the groove gate region includes a dielectric layer 10 in the groove, a gate conductor 4 is arranged in the dielectric layer 10, and the side of the second semiconductor material close to the groove gate region is a partial P-type semiconductor channel region 11; grooves are respectively arranged on both sides of the groove gate region and penetrate into the semiconductor voltage-resistant layer 2; the grooves penetrate into the semiconductor voltage-resistant layer 2 and penetrate into the semiconductor voltage-resistant layer 2. A P-type electric field shielding region 3 of the first semiconductor material and a P-type connecting region 5 of the second semiconductor material are respectively provided around the groove in the layer 2, in the first semiconductor material, and in the second semiconductor material; the dielectric layer 10 also covers the surface of the N-type heavily doped source region 6 of the third semiconductor material on both sides of the groove; the gate conductor 4 and the dielectric layer 10 located on the surface of the N-type heavily doped source region 6 of the third semiconductor material are covered with an isolation dielectric layer 7; an ohmic contact metal 8 is provided on the surface of the dielectric isolation layer 7, in the groove deep into the semiconductor voltage-resistant layer 2, and on the N-type heavily doped source region 6 of the third semiconductor material; and a drain ohmic contact metal 9 is provided at the bottom of the substrate 1; The invention is characterized in that the first semiconductor material and the second semiconductor material are different materials; the P-type channel region 11 composed of the first semiconductor material and the voltage-resistant layer 2 composed of the second semiconductor material form a heterojunction diode; the doping of the P-type electric field shielding region 3 and the P-type connecting region 5 is generally 1×10 18 cm -3 The third semiconductor material and the second semiconductor material are the same semiconductor material or the third semiconductor material and the second semiconductor material are different semiconductor materials, and the N-type doping concentration of the third semiconductor material is 1×10 18 cm -3 above.

12. The heterogeneous, heterostructured wide bandgap trench gate MOSFET device cell according to claim 11, characterized in that The depth of the groove extending deep into the semiconductor voltage-resistant layer 2 is not less than the depth of the trench gate.

13. The heterogeneous, heterostructured wide bandgap trench gate MOSFET device cell according to claim 11, characterized in that The third semiconductor material is N-type polysilicon, NiO, IGZO, ZnO, etc.

14. The heterogeneous, heterostructured wide bandgap trench gate MOSFET device cell according to claim 11, characterized in that When the first semiconductor material is 4H-SiC, the second semiconductor material is Si or 3C-SiC.

15. The heterogeneous, heterostructured wide bandgap trench gate MOSFET device cell according to claim 11, characterized in that When the first semiconductor material is GaN, AlGaN, or AlN, the second semiconductor material is 4H-SiC or 3C-SiC.

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