A Schottky source power metal oxide semiconductor field effect transistor including a heterojunction diode

Abstract

The present invention discloses a Schottky source power metal oxide semiconductor field effect transistor including a heterojunction diode, comprising a drain metal layer (1), a heavily doped first conductive type substrate layer (2), a lightly doped first conductive type drift region (3), a first conductive type conduction region (4), a retrograde doped second conductive type body region (5), a heavily doped second conductive type contact region (6), a source metal layer (7), an oxide layer (8), a heavily doped first conductive type gate polysilicon layer (9), a gate metal layer (10), a second conductive type germanium silicon region (11), and a germanium silicon region source metal layer (12). The present invention improves the single particle gate punch-through resistance of the device. Compared with the existing traditional Schottky source vertical metal oxide semiconductor field effect transistor (SBMOS), the oxide layer of the present invention has a smaller peak electric field and better single particle gate punch-through resistance.

Description

Technical Field

[0001] The invention relates to the technical field of power semiconductor power electronic devices, in particular to a Schottky source power metal oxide semiconductor field effect transistor comprising a heterojunction diode. Background Art

[0002] With the development of power integrated circuits, the development of power semiconductor devices is booming. Vertical power metal oxide semiconductor field effect transistor (VDMOS) came into being in this context, with high cell density, low on-resistance and low switching loss, making it very promising in aerospace and nuclear applications, especially in the low voltage range.

[0003] However, in aerospace and nuclear applications, devices are exposed to single-particle radiation for a long time. VDMOS is easily burned out in single-particle radiation environments, resulting in permanent damage to the device. In this context, Schottky source vertical metal oxide semiconductor field effect transistor (SBMOS) is improved, and its structure is as follows Figure 1 It has good single-particle burnout resistance, high breakdown voltage and low drive power.

[0004] When the device is hit by cosmic rays or heavy ions, high-energy charged particles transfer energy to the lattice structure step by step, resulting in a large number of electron-hole pairs along the heavy ion path. The holes drift to the Si / SiO2 interface and accumulate under the gate oxide layer, generating a significant transient electric field in the gate oxide layer. If this transient electric field exceeds the critical electric field of the gate oxide layer, gate punchthrough will occur. Although SBMOS has excellent single-particle burnout resistance, it still has the risk of single-particle gate punchthrough. Therefore, how to improve the single-particle gate punchthrough resistance of SBMOS is an urgent problem to be solved. Summary of the invention

[0005] The object of the present invention is to provide a Schottky source power metal oxide semiconductor field effect transistor including a heterojunction diode, comprising a drain metal layer, a heavily doped first conductive type substrate layer, a lightly doped first conductive type drift region, a first conductive type conduction region, a retrograde doped second conductive type body region, a heavily doped second conductive type contact region, a source metal layer, an oxide layer, a heavily doped first conductive type gate polysilicon layer, a gate metal layer, a second conductive type germanium silicon region, and a germanium silicon region source metal layer.

[0006] The gate metal layer is located on the heavily doped first conductivity type gate polysilicon layer.

[0007] The heavily doped first conductivity type gate polysilicon layer is located on the oxide layer.

[0008] The oxide layer is located on the first conductive type conduction region.

[0009] The source metal layer is located on the heavily doped second conductivity type contact region.

[0010] The heavily doped second conductivity type contact region is located on the retrograde doped second conductivity type body region.

[0011] The retrograde doped second conductivity type body region is located above the first conductivity type conduction region.

[0012] The silicon germanium region source metal layer is located on the second conductivity type silicon germanium region.

[0013] The second conductive type silicon germanium region is located on the first conductive type conductive region.

[0014] The first conductivity type conduction region is located above the lightly doped first conductivity type drift region.

[0015] The lightly doped first conductivity type drift region is located on the heavily doped first conductivity type substrate layer.

[0016] The heavily doped first conductive type substrate layer is located on the drain metal layer.

[0017] Furthermore, a portion of the source metal layer is located on the heavily doped second conductivity type contact region, and a portion of the source metal layer is located on the retrograde doped second conductivity type body region.

[0018] Furthermore, a portion of the oxide layer is located on the retrograde doped second conductivity type body region, a portion is located on the first conductivity type conduction region, and a portion is located on the second conductivity type germanium silicon region.

[0019] Furthermore, the source metal layer contacts the retrograde doped second conductivity type body region, and a Schottky contact is formed at the contact point.

[0020] Furthermore, there is a gap between the ion implantation position of the retrogradely doped second conductivity type body region and the device surface, and the gap serves as a hole discharge channel to assist in the discharge of holes, improve the single particle gate penetration resistance, and constitute a protective structure for the device gate oxide layer.

[0021] Furthermore, the second conductive type germanium silicon region and the first conductive type conductive region form a heterojunction diode.

[0022] Furthermore, the oxide layer is partially located on the retrograde doped second conductivity type body region.

[0023] When the power metal oxide semiconductor field effect transistor operates in a forward conduction state, a current conduction channel is formed at the contact between the oxide layer and the reverse doped second conductivity type body region.

[0024] Furthermore, the second conductive type germanium silicon region and the first conductive type conductive region form a heterojunction diode.

[0025] When the power metal oxide semiconductor field effect transistor operates in a reverse conduction state, the second conductive type germanium silicon region and the first conductive type conduction region form a heterojunction diode, and a current conduction channel is formed.

[0026] Furthermore, the second conductive type germanium silicon region and the first conductive type conductive region form a heterojunction diode.

[0027] When the power metal oxide semiconductor field effect transistor operates in a single particle irradiation environment, the second conductive type germanium silicon region and the first conductive type conduction region form a heterojunction diode, and a hole discharge channel is formed to constitute a protective structure of the device gate oxide layer.

[0028] The technical effect of the present invention is unquestionable. In view of the problem that the traditional SBMOS has poor single-particle gate penetration resistance, the present invention proposes a Schottky source power metal oxide semiconductor field effect transistor device including a heterojunction diode. The device is provided with a retrograde doped second conductivity type body region. During the heavy ion bombardment process, it can be used as a hole discharge channel in the edge region of the device to assist in discharging holes, reduce the number of holes accumulated under the gate oxide layer, and improve the single-particle gate penetration resistance. In addition, since the second conductivity type germanium silicon region and the first conductivity type conduction region form a heterojunction diode, the hole discharge channel in the central region of the device is formed, and the protection of the retrograde doped second conductivity type body region in the device structure assists each other, and together constitutes the protection of the gate oxide layer. Therefore, when a single particle is incident, the peak electric field inside the oxide layer is small. The power metal oxide semiconductor field effect transistor with enhanced single-particle gate penetration resistance proposed by the present invention improves the single-particle gate penetration resistance by introducing a heterojunction structure of germanium silicon and silicon and retrograde doping of the second conductivity type body region.

[0029] Compared with the existing traditional Schottky source vertical metal oxide semiconductor field effect transistor (SBMOS), the technical solution of the present invention provides a Schottky source power metal oxide semiconductor field effect transistor including a heterojunction diode, which has a low oxide layer peak electric field and improves the single particle gate penetration resistance of the SBMOS. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1It is a schematic diagram of the cross-sectional structure of an existing conventional Schottky source vertical metal oxide semiconductor field effect transistor device;

[0031] Figure 2 It is a schematic diagram of the cross-sectional structure of a Schottky source power metal oxide semiconductor field effect transistor device including a heterojunction diode;

[0032] Figure 3 This is a comparison chart of the anti-single-particle gate penetration characteristics;

[0033] In the figure: drain metal layer 1, heavily doped first conductivity type substrate layer 2, lightly doped first conductivity type drift region 3, first conductivity type conduction region 4, retrograde doped second conductivity type body region 5, heavily doped second conductivity type contact region 6, source metal layer 7, oxide layer 8, heavily doped first conductivity type gate polysilicon layer 9, gate metal layer 10, second conductivity type germanium silicon region 11, germanium silicon region source metal layer 12, second conductivity type body region 30. DETAILED DESCRIPTION

[0034] The present invention is further described below in conjunction with the embodiments, but it should not be understood that the above subject matter of the present invention is limited to the following embodiments. Without departing from the above technical ideas of the present invention, various substitutions and changes are made according to the common technical knowledge and customary means in the art, which should all be included in the protection scope of the present invention.

[0035] Embodiment 1:

[0036] See also Figures 2 to 3 A Schottky source power metal oxide semiconductor field effect transistor including a heterojunction diode includes a drain metal layer 1, a heavily doped first conductivity type substrate layer 2, a lightly doped first conductivity type drift region 3, a first conductivity type conduction region 4, a retrograde doped second conductivity type body region 5, a heavily doped second conductivity type contact region 6, a source metal layer 7, an oxide layer 8, a heavily doped first conductivity type gate polysilicon layer 9, a gate metal layer 10, a second conductivity type germanium silicon region 11, and a germanium silicon region source metal layer 12.

[0037] The gate metal layer 10 is located on the heavily doped first conductivity type gate polysilicon layer 9 .

[0038] The heavily doped first conductivity type gate polysilicon layer 9 is located on the oxide layer 8 .

[0039] The oxide layer 8 is located on the first conductive type conduction region 4 .

[0040] The source metal layer 7 is located on the heavily doped second conductivity type contact region 6 .

[0041] The heavily doped second conductivity type contact region 6 is located on the retrograde doped second conductivity type body region 5 .

[0042] The retrograde doped second conductivity type body region 5 is located on the first conductivity type conduction region 4 and can serve as a hole discharge channel in the edge region of the device to assist in the discharge of holes.

[0043] The SiGe region source metal layer 12 is located on the second conductivity type SiGe region 11 .

[0044] The second conductive type silicon germanium region 11 is located on the first conductive type conductive region 4 .

[0045] The first conductive type conduction region 4 is located on the lightly doped first conductive type drift region 3 .

[0046] The lightly doped first conductivity type drift region 3 is located on the heavily doped first conductivity type substrate layer 2 .

[0047] The heavily doped first conductive type substrate layer 2 is located on the drain metal layer 1 .

[0048] A portion of the source metal layer 7 is located on the heavily doped second conductivity type contact region 6 , and a portion of the source metal layer 7 is located on the retrograde doped second conductivity type body region 5 .

[0049] The oxide layer 8 is partially located on the retrograde doped second conductivity type body region 5 , partially located on the first conductivity type conduction region 4 , and partially located on the second conductivity type germanium silicon region 11 .

[0050] The source metal layer 7 contacts the retrograde doped second conductivity type body region 5 and forms a Schottky contact at the contact point.

[0051] There is a gap between the ion implantation position of the retrograde doped second conductivity type body region 5 and the device surface, and the position is not on the device surface, thus forming a protective structure of the device gate oxide layer 8 .

[0052] The second conductive type silicon germanium region 11 and the first conductive type conductive region 4 form a heterojunction diode.

[0053] The oxide layer 8 is partially located on the retrograde doped second conductivity type body region 5 .

[0054] When the power metal oxide semiconductor field effect transistor operates in a forward conduction state, a current conduction channel is formed at the contact between the oxide layer 8 and the reverse doped second conductivity type body region 5 .

[0055] The second conductive type silicon germanium region 11 and the first conductive type conductive region 4 form a heterojunction diode.

[0056] When the power metal oxide semiconductor field effect transistor operates in a reverse conduction state, the second conductive type germanium silicon region 11 and the first conductive type conduction region 4 form a heterojunction diode and a current conduction channel.

[0057] The second conductive type silicon germanium region 11 and the first conductive type conductive region 4 form a heterojunction diode.

[0058] When the power metal oxide semiconductor field effect transistor operates in a single particle irradiation environment, the second conductive type germanium silicon region 11 and the first conductive type conduction region 4 form a heterojunction diode, and a hole discharge channel is formed to constitute a protection structure for the device gate oxide layer 8. The protection structure and the protection structure of the reversely doped second conductive type body region in the device structure assist each other and together constitute protection for the gate oxide layer.

[0059] Embodiment 2:

[0060] A Schottky source power metal oxide semiconductor field effect transistor including a heterojunction diode comprises a drain metal layer 1, a heavily doped first conductivity type substrate layer 2, a lightly doped first conductivity type drift region 3, a first conductivity type conduction region 4, a retrograde doped second conductivity type body region 5, a heavily doped second conductivity type contact region 6, a source metal layer 7, an oxide layer 8, a heavily doped first conductivity type gate polysilicon layer 9, a gate metal layer 10, a second conductivity type germanium silicon region 11, and a germanium silicon region source metal layer 12.

[0061] The gate metal layer 10 is located on the heavily doped first conductivity type gate polysilicon layer 9 .

[0062] The heavily doped first conductivity type gate polysilicon layer 9 is located on the oxide layer 8 .

[0063] The oxide layer 8 is located on the first conductive type conduction region 4 .

[0064] The source metal layer 7 is located on the heavily doped second conductivity type contact region 6 .

[0065] The heavily doped second conductivity type contact region 6 is located on the retrograde doped second conductivity type body region 5 .

[0066] The retrograde doped second conductivity type body region 5 is located on the first conductivity type conduction region 4 .

[0067] The SiGe region source metal layer 12 is located on the second conductivity type SiGe region 11 .

[0068] The second conductive type silicon germanium region 11 is located on the first conductive type conductive region 4 .

[0069] The first conductive type conduction region 4 is located on the lightly doped first conductive type drift region 3 .

[0070] The lightly doped first conductivity type drift region 3 is located on the heavily doped first conductivity type substrate layer 2 .

[0071] The heavily doped first conductive type substrate layer 2 is located on the drain metal layer 1 .

[0072] Embodiment 3:

[0073] A Schottky source power metal oxide semiconductor field effect transistor including a heterojunction diode, the technical content of which is the same as that of Example 2, further, a portion of the source metal layer 7 is located on a heavily doped second conductivity type contact region 6, and a portion is located on a retrogradely doped second conductivity type body region 5.

[0074] Embodiment 4:

[0075] A Schottky source power metal oxide semiconductor field effect transistor including a heterojunction diode, the technical content of which is the same as any one of Examples 2-3, further, a portion of the oxide layer 8 is located on a retrogradely doped second conductivity type body region 5, a portion is located on a first conductivity type conduction region 4, and a portion is located on a second conductivity type germanium silicon region 11.

[0076] Embodiment 5:

[0077] A Schottky source power metal oxide semiconductor field effect transistor including a heterojunction diode, the technical content of which is the same as any one of embodiments 2-4, further, the source metal layer 7 contacts the retrograde doped second conductivity type body region 5, and a Schottky contact is formed at the contact point.

[0078] Embodiment 6:

[0079] A Schottky source power metal oxide semiconductor field effect transistor including a heterojunction diode, the technical content of which is the same as any one of Examples 2-5, and further, there is a gap between the ion implantation position of the retrogradely doped second conductive type body region 5 and the device surface, and the gap serves as a hole discharge channel to assist in the discharge of holes, improve the single particle gate penetration resistance, and constitute a protective structure of the device gate oxide layer 8.

[0080] Embodiment 7:

[0081] A Schottky source power metal oxide semiconductor field effect transistor including a heterojunction diode, the technical content of which is the same as any one of embodiments 2-6, and further, the second conductive type germanium silicon region 11 and the first conductive type conduction region 4 form a heterojunction diode.

[0082] Embodiment 8:

[0083] A Schottky source power metal oxide semiconductor field effect transistor including a heterojunction diode, the technical content of which is the same as any one of embodiments 2-7, and further, the oxide layer 8 is partially located on the retrograde doped second conductivity type body region 5.

[0084] When the power metal oxide semiconductor field effect transistor operates in a forward conduction state, a current conduction channel is formed at the contact between the oxide layer 8 and the reverse doped second conductivity type body region 5 .

[0085] Embodiment 9:

[0086] A Schottky source power metal oxide semiconductor field effect transistor including a heterojunction diode, the technical content of which is the same as any one of embodiments 2-8, and further, the second conductive type germanium silicon region 11 and the first conductive type conduction region 4 form a heterojunction diode.

[0087] When the power metal oxide semiconductor field effect transistor operates in a reverse conduction state, the second conductive type germanium silicon region 11 and the first conductive type conduction region 4 form a heterojunction diode and a current conduction channel.

[0088] Embodiment 10:

[0089] A Schottky source power metal oxide semiconductor field effect transistor including a heterojunction diode, the technical content of which is the same as any one of embodiments 2-9, and further, the second conductive type germanium silicon region 11 and the first conductive type conduction region 4 form a heterojunction diode.

[0090] When the power metal oxide semiconductor field effect transistor operates in a single particle irradiation environment, the second conductive type germanium silicon region 11 and the first conductive type conduction region 4 form a heterojunction diode and a hole discharge channel, forming a protection structure of the device gate oxide layer 8.

[0091] Embodiment 11:

[0092] A Schottky source power metal oxide semiconductor field effect transistor including a heterojunction diode, the technical content of which is the same as any one of Examples 2-10, and further, the thickness of the oxide layer 8 under the heavily doped first conductive type gate polysilicon layer 9 ranges from 30nm to 50nm.

[0093] Embodiment 12:

[0094] A Schottky source power metal oxide semiconductor field effect transistor including a heterojunction diode, the technical content of which is the same as any one of Examples 2-11, and further, the thickness of the oxide layer 8 under the heavily doped first conductive type gate polysilicon layer 9 is 30nm.

[0095] Embodiment 13:

[0096] A Schottky source power metal oxide semiconductor field effect transistor including a heterojunction diode, the technical content of which is the same as any one of Examples 2-12, and further, the thickness of the oxide layer 8 under the heavily doped first conductive type gate polysilicon layer 9 is 40nm.

[0097] Embodiment 14:

[0098] A Schottky source power metal oxide semiconductor field effect transistor including a heterojunction diode, the technical content of which is the same as any one of Examples 2-13, and further, the thickness of the oxide layer 8 under the heavily doped first conductive type gate polysilicon layer 9 is 50nm.

[0099] Embodiment 15:

[0100] A Schottky source power metal oxide semiconductor field effect transistor including a heterojunction diode, the technical content of which is the same as any one of Examples 2-14, and further, the thickness of the oxide layer 8 on the side of the heavily doped first conductive type gate polysilicon layer 9 ranges from 15nm to 20nm.

[0101] Embodiment 16:

[0102] A Schottky source power metal oxide semiconductor field effect transistor including a heterojunction diode, the technical content of which is the same as any one of Examples 2-15, and further, the thickness of the oxide layer 8 on the side of the heavily doped first conductive type gate polysilicon layer 9 is 15nm.

[0103] Embodiment 17:

[0104] A Schottky source power metal oxide semiconductor field effect transistor including a heterojunction diode, the technical content of which is the same as any one of Examples 2-16, and further, the thickness of the oxide layer 8 on the side of the heavily doped first conductive type gate polysilicon layer 9 is 17nm.

[0105] Embodiment 18:

[0106] A Schottky source power metal oxide semiconductor field effect transistor including a heterojunction diode, the technical content of which is the same as any one of Examples 2-17, and further, the thickness of the oxide layer 8 on the side of the heavily doped first conductive type gate polysilicon layer 9 is 20nm.

[0107] Embodiment 19:

[0108] A Schottky source power metal oxide semiconductor field effect transistor including a heterojunction diode, the technical content of which is the same as any one of embodiments 2-18, further, the ion implantation peak position of the retrograde doped second conductivity type body region 5 is 0.7 μm away from the device surface, and the value range of the implantation peak concentration is 1×10 18 cm -3 Up to 2×10 18 cm -3 .

[0109] Embodiment 20:

[0110] A Schottky source power metal oxide semiconductor field effect transistor including a heterojunction diode, the technical content of which is the same as any one of embodiments 2-19, further, the device main body material is Si material; the doping concentration of the first conductive type conduction region 4 is in the range of 1×10 16 cm -3 Up to 5×10 16 cm -3 The doping concentration of the heavily doped first conductive type substrate layer 2 ranges from 1×10 19 cm -3 Up to 5×10 19 cm -3 The doping concentration of the heavily doped first conductive type gate polysilicon layer 9 is in the range of 1×10 20 cm -3 Up to 1×10 21 cm -3 .

[0111] Embodiment 21:

[0112] A Schottky source power metal oxide semiconductor field effect transistor including a heterojunction diode, the technical content of which is the same as any one of embodiments 2-20, further, the device germanium silicon heterojunction material adopts SiGe material; the doping concentration of the second conductive type germanium silicon region 11 ranges from 1×10 17 cm -3 Up to 2×10 17 cm -3 The width of the second conductive type germanium silicon region 11 is in the range of 0.2 μm to 0.8 μm. The depth of the second conductive type germanium silicon region 11 is in the range of 0.2 μm to 0.5 μm.

[0113] Embodiment 22:

[0114] A Schottky source power metal oxide semiconductor field effect transistor including a heterojunction diode, the technical content of which is the same as any one of Examples 2-21, and further, the device germanium silicon heterojunction material adopts SiGe material; the key process steps of the second conductive type germanium silicon region 11 are: first, using epitaxial growth technology to form a first conductive type conduction region 4 on a lightly doped first conductive type drift region 3; secondly, forming a groove region of the first conductive type conduction region 4 by etching; finally, using ultra-high vacuum chemical vapor deposition (UHVCVD) to selectively grow a second conductive type germanium silicon region 11 on a silicon material substrate of the first conductive type conduction region 4.

[0115] Figure 3 The device of Example 1 and Figure 1 Comparison of single-particle gate punch-through characteristics of traditional Schottky source vertical metal oxide semiconductor field effect transistor (SBMOS).

[0116] Compared to Figure 1 The traditional Schottky source vertical metal oxide semiconductor field effect transistor (SBMOS) is combined with Figure 3 The single-particle gate punch-through characteristics comparison diagram shows that the oxide layer peak electric field of the device structure of the present invention is smaller and has better resistance to single-particle gate punch-through performance.

Claims

1. A Schottky source power metal oxide semiconductor field effect transistor including a heterojunction diode, characterized in that: It comprises a drain metal layer (1), a heavily doped first conductivity type substrate layer (2), a lightly doped first conductivity type drift region (3), a first conductivity type conduction region (4), a retrograde doped second conductivity type body region (5), a heavily doped second conductivity type contact region (6), a source metal layer (7), an oxide layer (8), a heavily doped first conductivity type gate polysilicon layer (9), a gate metal layer (10), a second conductivity type germanium silicon region (11), and a germanium silicon region source metal layer (12); The gate metal layer (10) is located on the heavily doped first conductivity type gate polysilicon layer (9); The heavily doped first conductivity type gate polysilicon layer (9) is located on the oxide layer (8); The oxide layer (8) is located on the first conductive type conduction region (4); The source metal layer (7) is located on the heavily doped second conductivity type contact region (6); The heavily doped second conductivity type contact region (6) is located on the retrograde doped second conductivity type body region (5); The retrograde doped second conductivity type body region (5) is located above the first conductivity type conduction region (4); The germanium silicon region source metal layer (12) is located on the second conductivity type germanium silicon region (11); The second conductive type germanium silicon region (11) is located on the first conductive type conductive region (4); The first conductive type conduction region (4) is located on the lightly doped first conductive type drift region (3); The lightly doped first conductivity type drift region (3) is located on the heavily doped first conductivity type substrate layer (2); The heavily doped first conductive type substrate layer (2) is located on the drain metal layer (1); A portion of the source metal layer (7) is located on the heavily doped second conductivity type contact region (6), and a portion of the source metal layer (7) is located on the retrogradely doped second conductivity type body region (5); The source metal layer (7) contacts the retrograde doped second conductivity type body region (5), and a Schottky contact is formed at the contact point; A portion of the oxide layer (8) is located on the retrograde doped second conductivity type body region (5), a portion is located on the first conductivity type conduction region (4), and a portion is located on the second conductivity type germanium silicon region (11).

2. A Schottky source power metal oxide semiconductor field effect transistor comprising a heterojunction diode according to claim 1, characterized in that: There is a gap between the ion implantation position of the retrograde doped second conductivity type body region (5) and the device surface, and the gap serves as a hole discharge channel to assist in the discharge of holes, improve the single particle gate penetration resistance performance, and form a protective structure of the device gate oxide layer (8).

3. The Schottky source power metal oxide semiconductor field effect transistor including a heterojunction diode according to claim 1, characterized in that: The second conductive type germanium silicon region (11) and the first conductive type conductive region (4) form a heterojunction diode.

4. The Schottky source power metal oxide semiconductor field effect transistor including a heterojunction diode according to claim 1, characterized in that: The oxide layer (8) is partially located on the retrograde doped second conductivity type body region (5); When the power metal oxide semiconductor field effect transistor operates in a forward conduction state, a current conduction channel is formed at the contact point between the oxide layer (8) and the reverse doped second conductivity type body region (5).

5. The Schottky source power metal oxide semiconductor field effect transistor including a heterojunction diode according to claim 1, characterized in that: The second conductive type germanium silicon region (11) and the first conductive type conductive region (4) form a heterojunction diode; When the power metal oxide semiconductor field effect transistor operates in a reverse conduction state, the second conductive type germanium silicon region (11) and the first conductive type conduction region (4) form a heterojunction diode and a current conduction channel.

6. The Schottky source power metal oxide semiconductor field effect transistor including a heterojunction diode according to claim 1, characterized in that: The second conductive type germanium silicon region (11) and the first conductive type conductive region (4) form a heterojunction diode; When the power metal oxide semiconductor field effect transistor operates in a single particle irradiation environment, the second conductive type germanium silicon region (11) and the first conductive type conduction region (4) form a heterojunction diode and a hole discharge channel, thereby forming a protective structure of the device gate oxide layer (8).

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