Noise suppression circuit, isolation decoder, chip and electronic device

Abstract

The present application provides a noise suppression circuit, an isolation decoder, a chip and an electronic device, wherein the noise suppression circuit includes: a differential operational amplifier circuit for gaining an input differential signal; a first filter circuit, whose input end is connected to the output end of the operational amplifier circuit, for filtering the signal after gaining the operational amplifier circuit, and outputting a first frequency signal; a second filter circuit, whose input end is connected to the output end of the operational amplifier circuit, for filtering the signal after gaining the operational amplifier circuit, and outputting a second frequency signal; a third filter circuit, whose input end is respectively connected to the output end of the first filter circuit and the output end of the second filter circuit, for further filtering the first frequency signal and the second frequency signal to remove excess noise and unnecessary frequency components, and output a pulse width modulation signal. The present application can improve signal quality and anti-interference ability.

Description

Technical Field

[0001] The present application relates to the field of signal processing technology, and in particular to a noise suppression circuit, an isolation decoder, a chip and an electronic device. Background Art

[0002] High-frequency OOK (On-Off Keying) technology is a modulation technology used for digital signal transmission. It transmits PWM (Pulse Width Modulation) information from the low-voltage side to the high-voltage side through high-frequency signals and envelope comparators. However, in actual system applications, there is often transient ground noise with a frequency range of 50MHz to 250MHz. These noises may have an adverse effect on normal OOK signal transmission through coupling of the isolation channel or coupling of the secondary ground line. Summary of the invention

[0003] The present application provides a noise suppression circuit, an isolation decoder, a chip and an electronic device to solve the problem of how to suppress noise interference in OOK signal transmission.

[0004] In a first aspect, the present application provides a noise suppression circuit, the noise suppression circuit comprising:

[0005] An operational amplifier circuit, used for gaining the input differential signal;

[0006] A first filter circuit, whose input end is connected to the output end of the operational amplifier circuit, is used to filter the signal after the operational amplifier circuit performs gain processing to filter out the signal below the preset cutoff frequency and output a first frequency signal;

[0007] A second filter circuit, whose input end is connected to the output end of the operational amplifier circuit, is used to filter the signal after the gain is obtained by the operational amplifier circuit to filter out the signal that does not meet the preset frequency range and output a second frequency signal;

[0008] The third filter circuit has an input end connected to the output end of the first filter circuit and the output end of the second filter circuit respectively, and is used to further filter the first frequency signal and the second frequency signal and output a pulse width modulation signal, wherein the frequency of the first frequency signal is higher than the frequency of the second frequency signal.

[0009] In one embodiment of the present application, the first filtering circuit includes:

[0010] A first filter, whose input end is connected to the output end of the operational amplifier circuit, is used to receive the signal after being amplified by the operational amplifier circuit, and filter out the signal below the preset cutoff frequency according to the preset cutoff frequency;

[0011] A first comparator, whose input end is connected to the output end of the first filter, is used to convert the periodic ripple signal output by the first filter into a level signal; when the amplitude of the periodic ripple signal is greater than the threshold of the first comparator, the first comparator outputs a high level signal, otherwise the first comparator outputs a low level signal.

[0012] In one embodiment of the present application, the second filtering circuit includes:

[0013] A second comparator, whose input end is connected to the output end of the operational amplifier circuit, is used to amplify the signal after the gain is obtained by the operational amplifier circuit and output a square wave signal;

[0014] an OR gate circuit, a first input terminal of which is connected to the output terminal of the second comparator, and a second input terminal of which is connected to the output terminal of the third filter, for performing a logic “OR” operation on the square wave signal and the pulse width modulation signal output by the third filter, and outputting a first pulse width modulation control signal;

[0015] The second filter, whose input end is connected to the output end of the OR gate circuit, is used to receive the first pulse width modulation control signal, filter out signals that do not conform to the preset frequency range, and output the second pulse width modulation control signal after filtering as the second frequency signal.

[0016] In an embodiment of the present application, the third filtering circuit includes:

[0017] an AND gate circuit, a first input terminal of which is connected to the output terminal of the first comparator, and a second input terminal of which is connected to the output terminal of the second filter, for performing a logic “AND” operation on the first frequency signal and the second frequency signal, and outputting a pulse width modulation pre-signal;

[0018] The third filter has an input end connected to the output end of the AND gate circuit and is used to filter the input pulse width modulation pre-signal and output the pulse width modulation signal after filtering.

[0019] In one embodiment of the present application, the second filter includes a rising edge filter circuit, a falling edge filter circuit and a trigger; the rising edge filter circuit is used to filter out the falling edge portion of the signal, the falling edge filter circuit is used to filter out the rising edge portion of the signal, and the trigger is used to control the change of the output level when the rising edge and falling edge of the input signal appear.

[0020] In one embodiment of the present application, the operational amplifier circuit includes at least one stage of differential operational amplifier, which is used to amplify, filter and perform computation on the input signal.

[0021] In an embodiment of the present application, the at least one stage differential op amp includes a first stage differential op amp and a second stage differential op amp, and the first stage differential op amp and the second stage differential op amp are connected in series.

[0022] In one embodiment of the present application, the noise suppression circuit further includes a fourth filter, which serves as a first-order high-pass filter, and whose output end is connected to the input end of the operational amplifier circuit; the first filter serves as a second-order high-pass filter.

[0023] In one embodiment of the present application, the first-stage high-pass filter and the second-stage high-pass filter are RC filters or IC filters.

[0024] In an embodiment of the present application, the trigger is any one of a NAND gate RS trigger, a NOR gate RS trigger and a D trigger.

[0025] In a second aspect, the present application further provides an isolation decoder, wherein the isolation decoder comprises the noise suppression circuit as described in any one of the first aspect.

[0026] In a third aspect, the present application further provides a chip, comprising the noise suppression circuit as described in any one of the first aspects.

[0027] In a fourth aspect, the present application further provides an electronic device, comprising the noise suppression circuit as described in any one of the first aspects.

[0028] The present application provides a noise suppression circuit, an isolation decoder, a chip, and an electronic device. The noise suppression circuit performs signal gain through an operational amplifier circuit, and then filters out signals below a preset cutoff frequency and not in accordance with a preset frequency range after being processed by a first filter circuit and a second filter circuit, and outputs a first frequency signal and a second frequency signal. The third filter circuit further performs filtering processing on the first frequency signal and the second frequency signal to remove excess noise and unnecessary frequency components.

[0029] Therefore, the first filter circuit of the present application can effectively filter out low-frequency noise by filtering signals below the preset cutoff frequency. The second filter circuit can effectively filter out unnecessary frequency components and noise by filtering signals that do not meet the preset frequency range. Moreover, the third filter circuit further filters the first frequency signal and the second frequency signal to remove excess noise and frequency components, thereby further improving signal quality and anti-interference capability. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions in the present application or the prior art, a brief introduction will be given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0031] Figure 1 It is a circuit diagram of an OOK modulation and demodulation circuit;

[0032] Figure 2 It is a circuit diagram of another OOK modulation and demodulation circuit;

[0033] Figure 3 is a circuit diagram of a noise suppression circuit provided in Embodiment 1 of the present application;

[0034] Figure 4 is a circuit diagram of a noise suppression circuit provided in Embodiment 2 of the present application;

[0035] Figure 5 It is an OOK transmission waveform diagram when PWM is high provided in an embodiment of the present application;

[0036] Figure 6 It is a noise transmission waveform diagram of 50-250 MHz provided in an embodiment of the present application;

[0037] Figure 7 This is a noise transmission waveform diagram below 50 MHz provided in an embodiment of the present application. DETAILED DESCRIPTION

[0038] In order to make the purpose, technical solutions and advantages of this application clearer, the technical solutions in this application will be clearly and completely described below in conjunction with the drawings in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0039] The terms "first", "second", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments described herein can be implemented in an order other than that illustrated or described herein.

[0040] The following is an explanation of the terms used in this application.

[0041] OOK technology: is a modulation technology, namely On-Off Keying. It is a pulse-based modulation method that converts digital signals into analog signals for transmission. In OOK technology, digital signals are encoded into two signals with different levels or amplitudes. One level (usually a high level) represents the transmitted logic 1, and the other level (usually a low level) represents the transmitted logic 0. The sender converts the digital signal into the corresponding level or amplitude and sends these levels at a certain time interval. The receiver decodes the signal by detecting the change in level or amplitude. Since there are only two discrete signal levels, OOK technology is sensitive to noise and interference during transmission, so additional signal processing and error correction mechanisms may be required in long-distance transmission or high-noise environments.

[0042] When a PWM (Pulse Width Modulation) signal needs to be transmitted from the low voltage side to the high voltage side, a high-frequency OOK technology can be used. The OOK technology encodes the PWM signal into a high-frequency switching signal and transmits it to the high voltage side through an electrical isolator. On the high voltage side, an envelope comparator (EnvelopeDetector) can be used for decoding.

[0043] Please refer to Figure 1 , Figure 1 This is a circuit diagram of an OOK modulation and demodulation circuit. The PWM signal is output from the primary side (OOK modulation circuit). In OOK modulation, the digital signal is encoded into two modulation signals of different levels, namely the positive phase state and the negative phase state. The positive phase state represents logic 1, and the negative phase state represents logic 0. The positive phase state signal OOK_TXP and the negative phase state signal OOK_TXN of the OOK signal are output respectively.

[0044] In the isolation channel, the OOK signal is transmitted through an electrical isolation device (such as an optical coupler, a magnetic coupler, etc.) to achieve electrical separation and isolation. Through the output end of the isolation channel, the OOK_INP signal and the OOK_INN signal of the isolated OOK signal can be obtained.

[0045] The OOK_INP signal and the OOK_INN signal are input to the two-stage bandpass fully differential op amps DAMP1 and DAMP2 in the secondary side (OOK demodulation circuit). A bandpass fully differential op amp is an electronic component that can amplify, filter, and perform operations on the input signal. In this signal processing process, DAMP1 and DAMP2 are used to process the input OOK signals (OOK_INP signal and OOK_INN signal) and adjust the amplitude and frequency characteristics of the signal by amplification and filtering. Bandpass fully differential op amps usually have high gain, wide bandwidth, and differential input and output characteristics, making them suitable for applications that require processing differential signals.

[0046] After being processed by the bandpass fully differential op amps of DAMP1 and DAMP2, the INP2 signal and INN2 signal are output. After the INP2 signal and INN2 signal pass through the envelope comparator, the PWM_PRE signal is output. The envelope comparator detects the envelope curve of the input signal and outputs the corresponding envelope signal. Finally, the PWM_PRE signal is processed by the PWM filter to obtain the final PWM output signal, namely PWM_OUT.

[0047] Figure 1 The overall process shown is to process, decode and convert the input OOK signal to obtain the corresponding PWM output signal.

[0048] Because in the system application, there is transient ground noise of 50MHz to 250MHz in the system. These noises may affect the transmission of normal OOK signals through the coupling of the isolation channel or the coupling of the secondary side GND. In this system, although the frequency of the OOK signal is generally set at a higher frequency than the system ground noise (for example, above 350MHz), in order to use a bandpass filter to reduce the gain of the noise frequency band and improve the gain and signal-to-noise ratio (SNR) of the signal frequency band. However, when the amplitude of the local noise interference is high, even if the gain of the filter is low, it may cause the decoder on the high-voltage side to flip, causing the isolation chip to mistakenly send the PWM waveform. In severe cases, this may cause system oscillation or damage.

[0049] Therefore, in a half-bridge or full-bridge drive system, it is usually required to have GNTI (Ground Noise Transient Immunity, if the interference comes from a different ground from the chip) or CMTI (Common Mode Transient Immunity, if the interference comes from the chip's own ground). This can suppress the interference of transient noise between high-voltage ground and low-voltage ground, between high-voltage ground and high-voltage ground, and the chip's own ground on the OOK signal.

[0050] In order to solve the problem of high local noise interference amplitude, one technical solution is to add a high-pass filter on the output side of the differential op amp or the input side of the envelope comparator to introduce a pole in the signal path, which can reduce the gain in the low frequency band. Please refer to Figure 2 , Figure 2 This is another circuit diagram of an OOK modulation and demodulation circuit. For example, an RC (resistance-capacitance) filter is added to the signal path. The RC filter can achieve the desired frequency cutoff by selecting appropriate resistance and capacitance values. By introducing a pole, the energy of low-frequency noise is filtered out, thereby improving the signal path's response to high-frequency signals and thus improving the signal-to-noise ratio.

[0051] Figure 2 The processing method shown can reduce the impact of low-frequency noise on the signal, so that the noise interference of the signal during transmission is smaller, thereby achieving the effect of improving the signal-to-noise ratio. However, this method usually requires a large difference between the noise frequency and the signal frequency. For example, if the signal frequency is 100Hz, and the noise frequency is higher or lower than 1kHz or higher / lower orders of magnitude of the signal frequency, it can be considered that the difference between the noise frequency and the signal frequency is large. If the difference between the two is small, the gain attenuation of the high-pass filter pole will affect the normal signal transmission. Moreover, this method can only reduce the low-frequency gain by, for example, 3dB at most.

[0052] Moreover, in normal applications, the difference between the signal frequency and the noise frequency is usually only 2 to 3 times, so the improvement of the signal-to-noise ratio by using a high-pass filter is limited. This is because the effect of the high-pass filter is limited under relatively small frequency differences, and it cannot completely filter out the influence of low-frequency noise. This means that when facing signals and noise with small frequency differences, using only a high-pass filter may not achieve a good enough signal-to-noise ratio improvement effect.

[0053] Another technical solution is to use some isolated OOK solutions to increase the signal amplitude on the isolated low voltage side, which can be achieved by increasing Figure 1 In addition, when a capacitive isolation structure or a magnetic isolation solution is adopted, the amplitude of the signal can also be increased by increasing the size of the isolation capacitor or the isolation inductor.

[0054] But the purpose of doing this is to increase the amplitude of the input signal to make it easier to distinguish and extract relative to the noise. Since the noise is usually introduced on the high voltage side, increasing the amplitude of the input signal and increasing the size of the isolation device will not directly affect the amplitude of the noise.

[0055] Therefore, when using techniques such as increasing the input signal amplitude or increasing the isolation capacitor, there are some limitations and considerations involved:

[0056] First, increasing the amplitude of the input signal may have higher power requirements. This means that increasing the amplitude of the input signal may require more energy and may result in increased power consumption. In addition, increasing the signal amplitude may also affect the transmission frequency. For example, in a 5V system, it may be difficult to accurately implement a 500MHz oscillator.

[0057] Secondly, increasing the size of the isolation capacitor will affect the voltage resistance and cost of the chip. If the isolation capacitor spacing is reduced, the voltage resistance of the isolation capacitor may drop significantly, thus limiting the application scenarios of the device. If the size of the isolation capacitor is increased, the area of ​​the isolation capacitor needs to be increased. However, as the area increases, the parasitic capacitance will also increase proportionally. Therefore, in order to achieve a 2-fold increase in signal amplitude, not only may the power consumption increase by 2 times, but the area of ​​the isolation capacitor may need to increase by 3 times, which will have a greater impact on the power consumption and the overall cost of the chip.

[0058] In order to solve the problems existing in the above technical solution in terms of noise suppression. And these problems will cause the chip to erroneously output a high level under intermediate frequency noise with a large amplitude. The noise suppression circuit provided in the present application solves this problem by combining a high-pass filter and an OOK bilateral filtering method. And, the noise suppression circuit described in the present application can completely suppress the influence of noise within a certain frequency band according to application requirements. This will greatly improve the ground noise transient immunity (GNTI) and common mode transient immunity (CMTI) capabilities within this frequency band. At the same time, due to the effects of the high-pass filter and the bandpass fully differential op amp, the present application can also perform well in the low-frequency region.

[0059] During normal signal transmission, the noise suppression circuit described in the present application uses bilateral filtering to suppress and shield noise, thereby preventing noise interference from occurring during the pulse width modulation (PWM) process that requires a high level output, causing the output to be turned on at a low level, thereby solving the problem of noise interference and ensuring the accuracy and stability of signal transmission.

[0060] Please refer to Figure 3 , Figure 3 3 is a circuit diagram of a noise suppression circuit provided in Embodiment 1 of the present application. A noise suppression circuit includes an operational amplifier circuit 301 , a first filter circuit 302 , a second filter circuit 303 and a third filter circuit 304 .

[0061] Exemplarily, the operational amplifier circuit 301 is used to gain the input differential signal.

[0062] Specifically, the differential signal is composed of two signals with opposite directions but equal amplitudes. The differential operational amplifier amplifies the two differential signals and generates an amplified differential output signal. The design of the operational amplifier circuit 301 aims to improve the dynamic range and anti-interference ability of the signal by expanding the amplitude of the differential signal. By using the operational amplifier circuit 301, the gain of the differential signal can be achieved, thereby improving the reliability and accuracy of the signal. At the same time, the operational amplifier circuit also has the common mode suppression capability, which effectively reduces the interference of common mode noise and improves the signal-to-noise ratio of the system.

[0063] Specifically, the operational amplifier circuit 301 includes at least one differential operational amplifier, and the at least one differential operational amplifier includes a first differential operational amplifier DAMP1 and a second differential operational amplifier DAMP2, and the first differential operational amplifier DAMP1 and the second differential operational amplifier DAMP2 are connected in series. The first differential operational amplifier DAMP1 and the second differential operational amplifier DAMP2 are two bandpass fully differential operational amplifiers (Fully Differential Amplifiers), which can amplify, filter and perform operation processing on the input signal.

[0064] In the signal processing process, DAMP1 and DAMP2 are used to process the input OOK signal and output INP2 signal and INN2 signal. The OOK signal is two differential signals OOK_INP and OOK_INN transmitted by the isolation channel. For example, each bandpass fully differential op amp can achieve a gain of about 8 times.

[0065] Exemplarily, the input end of the first filter circuit 302 is connected to the output end of the operational amplifier circuit 301, and is used to filter the signal after the gain is passed through the operational amplifier circuit 301 to filter out the signal below the preset cutoff frequency and output the first frequency signal.

[0066] For example, if the interference frequency range to be processed is 50MHz to 250MHz, and the frequency range of the OOK signal is 400MHz to 600MHz, in order to ensure that the signal is not affected by the filter and to achieve good interference suppression capability, the preset cutoff frequency of the first filter circuit 302 can be set to 400MHz, which can ensure that the OOK signal in the range of 400MHz to 600MHz is not affected.

[0067] Specifically, the first filtering circuit 302 includes a first filter 3021 and a first comparator 3022. The input end of the first filter 3021 is connected to the output end of the operational amplifier circuit 301, and is used to receive the signal after the operational amplifier circuit performs gain, and filter out the signal below the preset cutoff frequency according to the preset cutoff frequency. The input end of the first comparator 3022 is connected to the output end of the first filter 3021, and is used to convert the periodic ripple signal output by the first filter 3021 into a level signal; when the amplitude of the periodic ripple signal is greater than the threshold of the first comparator 3022, the first comparator 3022 outputs a high level signal, otherwise the first comparator 3022 outputs a low level signal.

[0068] For example, the first filter 3021 may use a high-pass filter to process the INP2 signal and the INN2 signal to remove signal components below a preset cutoff frequency. The high-pass filter may use an RC filter, etc., such as Figure 3The high-pass filter shown can be composed of a positive resistor R2 and a capacitor C2 and a negative resistor R3 and a capacitor C3. These components form an RC network, and by properly selecting the values ​​of the resistors and capacitors, the cutoff frequency of the high-pass filter can be adjusted. The cutoff frequency is defined as the frequency at which the high-pass filter begins to significantly attenuate the signal, and the desired filtering effect is achieved by configuring the appropriate cutoff frequency.

[0069] The INP2 signal and INN2 signal after gain processing are input to the high-pass filter for filtering. The high-pass filter will filter out the frequency components below the preset cutoff frequency from the signal. In other words, the output signal will only contain frequency components above the preset cutoff frequency. And output the INP3 signal and INN3 signal. Compared with the original input OOK_INP signal and OOK_INN signal, the INP3 signal and INN3 signal have filtered out the parts below the preset cutoff frequency, and have the characteristics of clearer and target frequency range.

[0070] After being processed by the high-pass filter, the INP3 signal and the INN3 signal are input to the first comparator 3022, and the first comparator 3022 can use the envelope comparator COMP1. The envelope comparator COMP1 is used to detect the envelope or amplitude change of the signal in signal processing. It determines whether the envelope of the signal exceeds the threshold by comparing the input signal with a threshold. In this case, the output signal of the high-pass filter (i.e., the INP3 signal and the INN3 signal) is a periodic ripple signal. The signal is processed by the envelope comparator COMP1. When the amplitude of the periodic ripple signal is higher than the threshold of the envelope comparator COMP1, the envelope comparator COMP1 will output a high-level signal; if the amplitude is lower than the threshold, the envelope comparator COMP1 outputs a low-level signal.

[0071] Therefore, by using the envelope comparator COMP1, the periodic ripple signal (ie, the INP3 signal and the INN3 signal) can be converted into a level signal (ie, the PWM_PRE signal), which is the first frequency signal, and the state of the PWM_PRE signal (ie, high level or low level) is determined according to the threshold.

[0072] Exemplarily, the input end of the second filter circuit 303 is connected to the output end of the operational amplifier circuit 301, and is used to filter the signal after the gain is passed through the operational amplifier circuit 301 to filter out the signal that does not meet the preset frequency range and output a second frequency signal.

[0073] For example, if the interference frequency range to be processed is interference signals within the range of 50 MHz to 250 MHz so that the interference signals within these frequency ranges are effectively eliminated, the preset frequency range of the second filtering circuit 303 can be set to 50 MHz to 250 MHz.

[0074] Specifically, the second filtering circuit 303 includes a second comparator 3031, an OR gate circuit 3032 and a second filter 3033. The input end of the second comparator 3031 is connected to the output end of the operational amplifier circuit 301, and is used to amplify the signal after the operational amplifier circuit 301 performs gain, and output a square wave signal. The first input end of the OR gate circuit 3032 is connected to the output end of the second comparator 3031, and the second input end thereof is connected to the output end of the third filter 3042, and is used to perform a logic "OR" operation on the square wave signal and the pulse width modulation signal output by the third filter 3042, and output a first pulse width modulation control signal. The input end of the second filter 3033 is connected to the output end of the OR gate circuit 3032 (i.e., OR0), and is used to receive the first pulse width modulation control signal, and filter out the signal that does not conform to the preset frequency range according to the preset frequency range, and output the second pulse width modulation control signal after filtering as the second frequency signal.

[0075] For example, Figure 3 As shown, the INP2 signal and the INN2 signal after being amplified by the operational amplifier circuit 301 are input to the second comparator 3031. The second comparator 3031 uses a high-speed comparator COMP2, which can amplify the INP2 signal and the INN2 signal into a square wave signal COMP_OUT. The first input end of the OR gate circuit OR0 receives the square wave signal COMP_OUT, and the second input end of the OR gate circuit OR0 receives the pulse width modulation signal PWM_OUT of the third filter 3042. The square wave signal COMP_OUT and the pulse width modulation signal PWM_OUT are logically "OR" operated, and the first pulse width modulation control signal PWM_CTRL is output.

[0076] The second filter 3033 can adopt an OOK noise bilateral filter, which is used to receive the first pulse width modulation control signal PWM_CTRL, and filter out noise that does not conform to the specific frequency range according to the set specific frequency range, and output the second pulse width modulation control signal PWM_CTRL_FILT after filtering as the second frequency signal.

[0077] Specifically, the second filter 3033 includes a rising edge filter circuit 30331, a falling edge filter circuit 30332, and a trigger 30333. The rising edge filter circuit 30331 is used to filter out the falling edge portion of the signal, and the falling edge filter circuit 30332 is used to filter out the rising edge portion of the signal, so that the rising edge filter circuit 30331 and the falling edge filter circuit 30332 meet the signal requirements within a specific range. The trigger 30333 is used to control the change of the output level when the rising edge and the falling edge of the input signal appear so that the second filter 3033 completes the corresponding filtering function.

[0078] Wherein, the rising edge filtering circuit 30331 includes an NMOS transistor NM0, a PMOS transistor PM0, a resistor R0, a capacitor C0 and an inverter INV0. The output end of the OR gate circuit OR0 is connected to the gate of the NMOS transistor NM0 and the gate of the PMOS transistor PM0 respectively. The drain of the NMOS transistor NM0 and the drain of the PMOS transistor PM0 are both grounded. The source of the NMOS transistor NM0 is connected to the source of the PMOS transistor PM0 and the input end of the inverter INV0 respectively after passing through the resistor R0. The drain of the NMOS transistor NM0 is connected to its source through the capacitor C0.

[0079] The falling edge filter circuit 30332 includes an NMOS transistor NM1, a PMOS transistor PM1, a resistor R1, a capacitor C1, and an inverter INV1. The output end of the OR gate circuit OR0 is connected to the gate of the NMOS transistor NM1 and the gate of the PMOS transistor PM1 respectively. The drain of the NMOS transistor NM1 and the drain of the PMOS transistor PM1 are both grounded. The source of the NMOS transistor NM1 is connected to the source of the PMOS transistor PM1 and the input end of the inverter INV1 respectively through the resistor R1. The drain of the NMOS transistor NM1 is connected to its source through the capacitor C1.

[0080] It should be noted that the second filter 3033 includes an OOK noise bilateral filter circuit composed of a rising edge filter circuit 30331 and a falling edge filter circuit 30332, which is used to process signals under the OOK modulation mode and reduce noise by filtering. The OOK noise bilateral filter circuit can also be implemented in the form of an IC filter, which uses a constant current to charge and discharge the capacitor to achieve the filtering function, and a specific filtering time T can be set. In addition, Figure 3 The embodiment shown is realized by using an RC filter. The RC filter is based on a combination of a resistor and a capacitor, and filtering is achieved by changing the charging and discharging time constant (RC time constant) of the capacitor.

[0081] The trigger 30333 includes a NAND gate NAND0, a NAND gate NAND1, and an inverter INV2. The first input end of the NAND gate NAND0 is connected to the output end of the inverter INV0, and the first input end of the NAND gate NAND1 is connected to the output end of the inverter INV1. The second input end of the NAND gate NAND0 is connected to the output end of the NAND gate NAND1, and the second input end of the NAND gate NAND1 is connected to the output end of the NAND gate NAND0. The output end of the NAND gate NAND0 is also connected to the input end of the inverter INV2, and the output end of the inverter INV2 outputs the second pulse width adjustment control signal PWM_CTRL_FILT as the second frequency signal.

[0082] It should be noted that the trigger 30333 can also be a trigger made of a NOR gate. For example, the trigger 30333 can be any one of a NAND gate RS trigger, a NOR gate RS trigger and a D trigger.

[0083] Exemplarily, the input end of the third filter circuit 304 is respectively connected to the output end of the first filter circuit 302 and the output end of the second filter circuit 303, and is used to further filter the first frequency signal PWM_PRE and the second frequency signal PWM_CTRL_FILT to remove excess noise and unnecessary frequency components, and output the pulse width modulation signal PWM_OUT, wherein the frequency of the first frequency signal PWM_PRE is higher than the frequency of the second frequency signal PWM_CTRL_FILT.

[0084] That is, when the third filter circuit 304 receives the output signals from the first filter circuit 302 and the second filter circuit 303, it will perform more sophisticated frequency selective filtering processing on these signals. By adjusting the parameters of the filter or designing a more complex filtering algorithm, the third filter circuit 303 can filter out the frequency components that do not belong to the desired signal in a targeted manner, while retaining and enhancing the relevant parts of the desired signal, thereby improving the system's anti-interference ability and signal-to-noise ratio.

[0085] For example, assume that the frequency of the first frequency signal PWM_PRE is 500MHz and the frequency of the second frequency signal PWM_CTRL_FILT is 200MHz. The first filter circuit 302 and the second filter circuit 303 respectively perform preliminary filtering processing on the two signals, and remove the part below the preset cut-off frequency of 200MHz. Next, the third filter circuit 303 will further process the two frequency signals to remove excess noise and unnecessary frequency components, and output the pulse width modulation signal PWM_OUT. In this example, the third filter circuit 303 can perform more refined filtering processing on the signals with a frequency of 500MHz (first frequency signal) and a frequency of 200MHz (second frequency signal) according to the specific design and system requirements. It can remove the noise of the second frequency signal while retaining and enhancing the relevant part of the first frequency signal. It should be noted that the above examples are for illustrative purposes only and do not represent the specific circuit design or filtering parameters of this application. The actual filter settings and design parameters should be adjusted and optimized according to specific needs and system requirements.

[0086] Specifically, Figure 3As shown, the third filter circuit 304 includes an AND gate circuit 3041 (i.e., AND1) and a third filter 3042. The third filter 3042 can be a PWM filter. The first input end of the AND gate circuit AND1 is connected to the output end of the first comparator 3022, and the second input end of the AND gate circuit AND1 is connected to the output end of the second filter 3033, for performing a logic "AND" operation on the first frequency signal PWM_PRE and the second frequency signal PWM_CTRL_FILT, and outputting a pulse width modulation pre-signal PWM_PRE_FILT. The input end of the PWM filter is connected to the output end of the AND gate circuit AND1, for filtering the input pulse width modulation pre-signal PWM_PRE_FILT, and outputting a pulse width modulation signal PWM_OUT after filtering.

[0087] It should be noted that in the above OOK noise bilateral filter and PWM filter, the RC constant and the filtering time T_PWM_FILT can be adjusted according to the requirements of different applications. The RC constant is a combination of the resistor and capacitor in the RC filter, which determines the frequency response and time characteristics of the filter. By changing the RC constant, the filtering effect of the filter for signals of different frequencies can be adjusted. According to the requirements of the specific application, a suitable RC constant can be selected to obtain the desired filtering effect.

[0088] Similarly, the filter time T_PWM_FILT of the PWM filter can also be adjusted according to specific application requirements. The filter time T_PWM_FILT determines the response time and smoothness of the PWM signal after passing through the filter. According to different application requirements, the value of T_PWM_FILT can be adjusted to achieve the desired filtering effect.

[0089] It can be understood that the frequency detection circuit composed of the above-mentioned components, the operational amplifier circuit 301 (DAMP1, DAMP2), the second comparator 3031 (COMP2), the OR gate circuit 3032 (OR0) and the second filter 3033 (i.e., the OOK noise bilateral filter circuit), is intended to determine whether the frequency of the input signal exceeds a specific value F0. If the frequency of the input signal is greater than F0, a normally high level signal PWM_PRE is output; if the frequency of the input signal is lower than F0, a square wave signal COMP2_OUT corresponding to the frequency is output. In this way, different countermeasures can be taken according to different frequencies, thereby improving the signal-to-noise ratio between the signal and the noise. During operation, the function of the OR gate circuit OR0 is to shield the influence of the OOK noise bilateral filter when PWM is communicating normally. The purpose of this is to avoid interference of the OOM noise bilateral filter with the normal isolated OOK signal transmission. In other words, through the OR gate circuit OR0, it can be ensured that the OOK noise bilateral filter will not affect the normal isolated OOK signal transmission. This design is intended to improve the signal-to-noise ratio and ensure effective signal processing.

[0090] It can be understood that the OOK decoding circuit composed of the above-mentioned operational amplifier circuit 301 (DAMP1, DAMP2), the first filter 3021 (such as a high-pass filter), the first comparator 3022 (i.e., envelope comparator COMP1), the AND gate circuit 3041 (i.e., AND1) and the third filter 3042 (i.e., PWM filter) is intended to realize the decoding of the OOK signal. The original data is restored from the modulated signal by analysis. The noise below the filtering frequency of the OOK noise bilateral filtering circuit can be reduced by setting the center frequency of DAMP1 and DAMP2, the pole of the high-pass filter, and the filtering time of the PWM filtering circuit, thereby achieving wide-band noise suppression. The details are as follows:

[0091] DAMP1 and DAMP2: are bandpass fully differential circuits. By adjusting their center frequencies, the desired bandwidth range can be selected to locate and receive OOK signals of a specific frequency.

[0092] High-pass filter: It is used to reduce the noise below the filtering frequency of the OOK noise bilateral filter. It can control the cutoff frequency of the filter by setting the pole to filter out low-frequency noise.

[0093] Envelope comparator: used to detect and extract the envelope of the OOK signal, that is, the amplitude information of the signal.

[0094] PWM filter: used to filter and restore the baseband part of the PWM signal. By setting the filter time (or filter coefficient), the response speed and smoothness of the PWM signal can be adjusted.

[0095] Therefore, by reasonably configuring and adjusting the parameters of the above components and technologies, the OOK decoding circuit can achieve wideband noise suppression, thereby improving the decoding quality and signal-to-noise ratio of the OOK signal.

[0096] It can be understood that the rising edge filter circuit 30331 (including NMOS transistor NM0, PMOS transistor PM0, resistor R0, capacitor C0 and inverter INV0), the falling edge filter circuit 30332 (including NMOS transistor NM1, PMOS transistor PM1, resistor R1, capacitor C1 and inverter INV1), and the trigger 30333 (including NAND gate NAND0, NAND gate NAND1 and inverter INV2). These circuits together constitute an OOK noise bilateral filter. The function of the OOK noise bilateral filter is to separate the signal frequency band and the noise frequency band, and set the noise filtering within a specific frequency range as required. By using the rising edge filter circuit 30331 and the falling edge filter circuit 30332, the filtering of the rising edge and falling edge parts of the input signal can be achieved. In other words, the OOK noise bilateral filter circuit is used to filter out the noise within a specific frequency range. No matter how large the noise amplitude is, as long as its frequency is within the range of the noise filter, it can be shielded. This greatly improves the circuit's anti-interference ability and reduces the impact of noise, thereby improving signal quality and system reliability. The trigger 30333 is used for control and synchronization to ensure the normal operation of the filter.

[0097] The following is an example based on the frequency range of the input signal.

[0098] like Figure 3 As shown, in the OOK noise bilateral filter, the time constant (RC time constant) is R0C0. Since the threshold of the inverter is usually 60% to 70% of the VDD voltage, the filtering time of the filter can be determined to be approximately R0C0 by this threshold. If the value of R0C0 is 4 nanoseconds, the filtering frequency is approximately 250 megahertz (MHz). In other words, low-level signals below 5ns (nanoseconds) or signals above 250MHz (duty cycle of 50%) will be filtered out, and only signals below 250MHz can be smoothly transmitted through the falling edge filter circuit 30331. Similarly, the rising edge filter circuit 30332 can filter out high-level signals below 5 nanoseconds.

[0099] The trigger 30333 combines the delay circuits of the rising edge and the falling edge to form a bilateral filter circuit with a filtering time of 5 nanoseconds. If the frequency of the PWM signal is higher than 250MHz, the output of the trigger 30333 will be low, and the output of the inverter INV2 will be high. If the signal frequency is lower than 250MHz, the trigger 30333 generates a square wave signal of this frequency, which is then filtered by the PWM filter. The filtering time of the PWM filter is set to 20 nanoseconds, which can ensure that signals above 50MHz are filtered out.

[0100] therefore, Figure 3 The circuit shown can eliminate interference in the range of 50MHz to 250MHz commonly encountered in applications. Assuming that the frequency of the OOK signal is between 400MHz and 600MHz, it is only necessary to ensure that the maximum frequency of the filter formed by R0C0 does not exceed 400MHz, so as to ensure that the signal will not be affected by the filter. At the same time, by setting the appropriate values ​​of C2, R2 of the high-pass filter and DAMP1, DAMP2 of the op amp circuit, it can be ensured that the high-pass filter reduces the gain of signals below 50MHz, thereby achieving good interference suppression capability below 200MHz.

[0101] In some embodiments of the present application, if it is desired to obtain better noise suppression capability within the 50 MHz range, it may be considered to Figure 3 On the basis of, add the first stage high pass filter at the input of OOK modulation circuit, such as Figure 4 shown. Figure 4 is a circuit diagram of the noise suppression circuit provided in Example 2 of the present application.

[0102] Exemplarily, the noise suppression circuit described in the present application also includes a fourth filter, which is used as a first-order high-pass filter, and its output is connected to the input of the operational amplifier circuit. The first filter in the figure is used as a second-order high-pass filter. By configuring the first-order high-pass filter and the second-order high-pass filter, the ability to suppress noise within a preset frequency range can be improved. In other words, the effect of designing the first-order high-pass filter is to further reduce the gain of low-frequency noise, which can be attenuated by about 3 decibels (3dB). At the same time, for high-frequency OOK signals, the first-order high-pass filter has a relatively small effect on it.

[0103] This improvement can further improve the suppression capability in the 50MHz range, because low-frequency noise will be filtered out more effectively, thereby improving the signal-to-noise ratio between noise and signal. At the same time, the transmission effect of the high-frequency OOK signal is not affected too much.

[0104] Please refer to Figure 5 , Figure 5This is an OOK transmission waveform diagram when PWM is high provided in an embodiment of the present application. During normal PWM signal transmission, when the OOK frequency of the PWM signal is high (for example, greater than 400MHz), the PWM_CTRL_FILT signal output by the OOK noise bilateral filter circuit will remain at a high level. This means that the OOK signal can be converted by the envelope comparator COMP1 after one cycle, and the output PWM_PRE signal will become a high level.

[0105] Subsequently, after the PWM_PRE signal is filtered by the 20 nanosecond PWM filter, the output PWM_OUT signal will also become high. At the same time, when PWM_OUT becomes high, the OR gate circuit OR0 will turn off the noise suppression function of the OOK noise bilateral filter circuit, that is, set its output to high. The purpose of this is to ensure that the signal is not affected by low-frequency noise when the PWM signal is high. If low-frequency noise appears when the PWM signal is high, the system will set the PWM signal to a low level. Because in normal applications, it is not desirable to see the PWM signal being interfered by low-frequency noise when it is high.

[0106] In summary, in the normal PWM signal transmission process, in order to maintain the accuracy and stability of the signal, the system will turn off the noise suppression function through the OR0 circuit and ensure the effective transmission of the PWM signal. This allows the PWM signal to remove noise with the help of the PWM filter, thereby obtaining the desired output result.

[0107] Please refer to Figure 6 , Figure 6 This is a noise transmission waveform diagram of 50-250 MHz provided in an embodiment of the present application. Figure 6 It shows the anti-interference ability for noise signals. When the PWM signal (i.e., the PWM signal sent by the system on the primary side, which needs to be converted into an OOK signal, i.e., OOK_INP, OOK_INN signal) is low in the application, that is, no OOK signal is sent on the low-voltage side, but the amplitude of the noise signal is large, and the noise frequency is between 50MHz and 250MHz, the OOK noise bilateral filter circuit cannot filter out the noise generated by the COMP2_OUT signal. Since the PWM signal is low at the beginning, the output of the PWM_OUT signal also remains low.

[0108] In this case, the PWM_CTRL_FILT signal will follow the periodic oscillation of the COMP2_OUT signal. Although the envelope comparator COMP1 can decode the noise signal and set the PWM_PRE signal to a high level, the PWM_PRE_FILT signal will follow the oscillation of the PWM_CTRL_FILT signal due to the AND gate circuit AND1.

[0109] Finally, since the PWM filter has a filtering time of 20 nanoseconds, it can filter out square wave signals in the range of 50MHz to 250MHz. Therefore, the PWM_OUT signal will remain at a low level, and the entire circuit will not respond to noise from 50MHz to 250MHz, achieving a better anti-interference effect.

[0110] In summary, when the PWM signal is low level and there is noise in the range of 50MHz to 250MHz, the circuit effectively suppresses and eliminates the influence of noise through the coordinated work of the filter and the logic circuit, thereby maintaining the correct PWM signal output. This ensures that the system can still work normally in the presence of strong noise interference.

[0111] Please refer to Figure 7 , Figure 7 This is a noise transmission waveform diagram below 50 MHz provided in an embodiment of the present application. Figure 7 The figure shows the case where the noise frequency is lower than the lowest frequency of the OOK noise bilateral filter (e.g., 50 MHz). When the noise frequency is lower than the lowest frequency of the OOK noise bilateral filter, the high and low times of the COMP2_OUT signal exceed the time of the PWM filter (e.g., 20 nanoseconds), that is, it exceeds the ripple time that the PWM filter can filter out. Therefore, the PWM filter cannot filter out ripples greater than 20 nanoseconds, which depends on the fact that the PWM_PRE signal cannot flip to a high level at this time.

[0112] In order to cope with this situation, the noise suppression circuit described in the present application adopts a high-pass filter (such as an RC high-pass filter circuit), which can filter out lower frequency noise. At the same time, since the gap between the 50MHz frequency and the OOK frequency of the PWM signal (about 500MHz) is 10 times, the pole of the high-pass filter can be set to a relatively low frequency, thereby reducing the gain of the 50MHz frequency. In this way, the noise signal will be greatly attenuated after passing through the high-pass filter, while the signal frequency will be less affected, thereby achieving the effect of suppressing noise within the 50MHz frequency range.

[0113] In summary, when the noise frequency is lower than the lowest frequency of the OOK noise bilateral filter, the use of a high-pass filter and appropriate pole settings can effectively filter out the lower frequency noise while keeping the signal frequency less affected. In this way, the system can suppress noise within the 50MHz frequency range.

[0114] In some other embodiments of the present application, the present application further provides an isolation decoder, wherein the isolation decoder includes the noise suppression circuit as described in any of the above embodiments.

[0115] Specifically, the isolation decoder is used to decode the input signal and generate a corresponding output signal, while ensuring that the input signal is not affected by interference and noise. Such an isolation decoder can improve the reliability and stability of the system.

[0116] By using the noise suppression circuit as part of the isolated decoder, noise and interference in the input signal can be effectively filtered out to ensure that the decoder can accurately identify and decode the required signal. This design can improve the processing capability of the entire system for input signals with low signal-to-noise ratio or strong interference.

[0117] In some other embodiments of the present application, the present application further provides a chip, wherein the chip includes the noise suppression circuit as described in any of the above embodiments.

[0118] Specifically, the chip is based on the aforementioned noise suppression circuit design and layout, and the noise suppression circuit is implemented on a chip through integrated circuit technology. Such a chip can be used to be integrated into various electronic systems and devices to complete specific tasks and functions.

[0119] In some other embodiments of the present application, the present application further provides an electronic device, which includes the noise suppression circuit as described in any of the above embodiments.

[0120] Specifically, the electronic device includes the aforementioned noise suppression circuit, which can be an independent module or embedded in other circuit boards or devices. The electronic device can be used in various applications, such as audio amplifiers, sensor signal processing, automatic control and other fields.

[0121] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A noise suppression circuit, characterized in that: The noise suppression circuit comprises: An operational amplifier circuit, used for gaining the input differential signal; a first filtering circuit, whose input end is connected to the output end of the operational amplifier circuit, wherein the first filtering circuit comprises a first filter and a first comparator, wherein the first filter is a high-pass filter, and is used to filter the signal after the operational amplifier circuit performs gain processing, so as to filter out the signal below the preset cutoff frequency, and output a first frequency signal; a second filtering circuit, whose input end is connected to the output end of the operational amplifier circuit, wherein the second filtering circuit comprises a second comparator, an OR gate circuit and a second filter, and is used to filter the signal after the operational amplifier circuit performs gain processing, so as to filter out the signal that does not conform to the preset frequency range, and output a second frequency signal, wherein the second filter comprises a rising edge filtering circuit, a falling edge filtering circuit and a trigger; the rising edge filtering circuit is used to filter out the falling edge part of the signal, the falling edge filtering circuit is used to filter out the rising edge part of the signal, and the trigger is used to control the change of the output level when the rising edge and falling edge of the input signal appear; The third filter circuit has an input end connected to the output end of the first filter circuit and the output end of the second filter circuit respectively, and is used to further filter the first frequency signal and the second frequency signal and output a pulse width modulation signal, wherein the frequency of the first frequency signal is higher than the frequency of the second frequency signal.

2. The noise suppression circuit according to claim 1, characterized in that: The first filter, whose input end is connected to the output end of the operational amplifier circuit, is used to receive the signal after being amplified by the operational amplifier circuit, and filter out the signal below the preset cutoff frequency according to the preset cutoff frequency; The first comparator, whose input end is connected to the output end of the first filter, is used to convert the periodic ripple signal output by the first filter into a level signal as the first frequency signal; when the amplitude of the periodic ripple signal is greater than the threshold of the first comparator, the first comparator outputs a high level signal, otherwise the first comparator outputs a low level signal.

3. The noise suppression circuit according to claim 2, characterized in that: The second comparator, whose input end is connected to the output end of the operational amplifier circuit, is used to amplify the signal after the gain is obtained by the operational amplifier circuit and output a square wave signal; The OR gate circuit has a first input terminal connected to the output terminal of the second comparator and a second input terminal connected to the output terminal of the third filter, and is used to perform a logic "OR" operation on the square wave signal and the pulse width modulation signal output by the third filter, and output a first pulse width modulation control signal; The second filter, whose input end is connected to the output end of the OR gate circuit, is used to receive the first pulse width modulation control signal, filter out signals that do not conform to the preset frequency range, and output the second pulse width modulation control signal after filtering as the second frequency signal.

4. The noise suppression circuit according to claim 3, characterized in that: The third filtering circuit further includes an AND gate circuit and a third filter, wherein: The AND gate circuit has a first input terminal connected to the output terminal of the first comparator and a second input terminal connected to the output terminal of the second filter, and is used to perform a logic "AND" operation on the first frequency signal and the second frequency signal, and output a pulse width modulation pre-signal; The third filter, whose input end is connected to the output end of the AND gate circuit, is used to filter the input pulse width modulation pre-signal and output the pulse width modulation signal after filtering.

5. The noise suppression circuit according to claim 1, characterized in that: The operational amplifier circuit includes at least one differential operational amplifier, which is used to amplify, filter and perform operation processing on the input signal.

6. The noise suppression circuit according to claim 5, characterized in that: The at least one stage differential operational amplifier comprises a first stage differential operational amplifier and a second stage differential operational amplifier, and the first stage differential operational amplifier and the second stage differential operational amplifier are connected in series.

7. The noise suppression circuit according to claim 2, characterized in that: The noise suppression circuit also includes a fourth filter, which serves as a first-stage high-pass filter, and an output end of which is connected to an input end of the operational amplifier circuit; the first filter serves as a second-stage high-pass filter.

8. The noise suppression circuit according to claim 7, characterized in that: The first-stage high-pass filter and the second-stage high-pass filter are RC filters or IC filters.

9. The noise suppression circuit according to claim 1, characterized in that: The trigger is any one of a NAND gate RS trigger, a NOR gate RS trigger and a D trigger.

10. An isolation decoder, characterized in that: The isolation decoder comprises a noise suppression circuit as claimed in any one of claims 1 to 9.

11. A chip, characterized in that: The chip comprises the noise suppression circuit according to any one of claims 1 to 9.

12. An electronic device, characterized in that: The electronic device comprises the noise suppression circuit according to any one of claims 1 to 9.

Images