A level conversion circuit and a level conversion method

Abstract

The present invention discloses a level conversion circuit and a level conversion method, which relate to the technical field of integrated circuits, and are used to improve the voltage conversion speed of the level conversion circuit, thereby improving the reliability and stability of the level conversion circuit. The level conversion circuit includes: a first input module, a second input module, a potential control module, and a switch module. The first input module is configured to control the voltage of the first node to decrease under the drive of the potential control module when the input signal flips from a low level to a high level. The second input module is configured to control the voltage of the second node to rise to the high-voltage domain power supply voltage under the drive of the potential control module when the inverted signal of the input signal flips from a high level to a low level. The switch module is configured to be in a conducting state when the input signal flips, so that the charge of the first node moves to the second node. The switch module is further configured to be in an off state after the input signal completes flipping.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technologies, and particularly to a level conversion circuit and a level conversion method. Background Art

[0002] In circuit design, digital circuits are used to process control signals and configure circuit functions, while analog circuits are used to process continuous signals. Since analog circuits have higher requirements for signal accuracy and reliability, a high-voltage domain voltage is generally used as the power supply voltage. Digital signals, on the other hand, are at a lower voltage domain. When a low-voltage domain signal is used to drive a high-voltage domain device, a level conversion circuit is required to establish a path between circuits in different voltage domains.

[0003] In existing level conversion circuits, the gates of the N-type and P-type transistors in the input pair are both used to receive the input voltage. When the input voltage is VDD in the low-voltage domain, when the N-type transistor is turned on under the action of the voltage VCC, since the source of the P-type transistor may be connected to the power supply voltage VDDH in a higher voltage domain, it may cause the P-type transistor to not turn off in time, resulting in competition between the N-type and P-type transistors. To enable smooth voltage conversion, the size of the N-type transistor needs to be increased, but this does not improve the voltage conversion speed, and the larger transistor size will also increase the node capacitance, further reducing the voltage conversion speed.

[0004] Based on this, how to improve the voltage conversion speed of the level conversion circuit has become an urgent problem to be solved. Summary of the Invention

[0005] The purpose of the present invention is to provide a level conversion circuit and a level conversion method to improve the voltage conversion speed of the level conversion circuit, thereby improving the reliability and stability of the level conversion circuit.

[0006] The present invention provides a level conversion circuit, which includes a first input module, a second input module, a potential control module, and a switching module. The first end of the potential control module is electrically connected to the high-voltage domain power supply terminal, the second end of the potential control module is electrically connected to the first input module and the second input module respectively, the output end of the first input module, the first end of the switching module, and the first control end of the potential control module are all coupled to a first node, and the output end of the second input module, the second end of the switching module, and the second control end of the potential control module are all coupled to a second node. The first input module is configured to control the voltage of the first node to decrease under the drive of the potential control module when the input signal flips from a low level to a high level. The second input module is configured to control the voltage of the second node to rise to the high-voltage domain power supply voltage under the drive of the potential control module when the inverted signal of the input signal flips from a high level to a low level. The switching module is configured to be in a conducting state when the input signal flips, so that the charge of the first node moves to the second node. The switching module is further configured to be in an off state after the input signal finishes flipping.

[0007] Compared with the prior art, in the level conversion circuit provided by the present invention, when the input signal flips from a low level to a high level, after receiving the output signal of the first input module, the potential control module can control the voltage of the first node to decrease, and after receiving the output signal of the second input module, control the voltage of the second node to rise to the high-voltage domain power supply voltage. At this time, since the switching module is in a conducting state when the input signal flips, the charge of the first node can move towards the second node through the switching module to accelerate the rising speed of the voltage of the second node, further shortening the time for the voltage of the second node to reach the high-voltage domain power supply voltage, and finally converting the input signal into a high-voltage domain power supply voltage that meets the requirements and outputting it through the second node, thereby improving the voltage conversion speed. In addition, after the input signal finishes flipping, the switching module is in an off state, which can reduce the static power consumption of the circuit to a certain extent and improve the reliability and stability of the circuit.

[0008] In a second aspect, the present invention further provides a level conversion method, which is applied to the level conversion circuit provided in the first aspect. The level conversion method includes:

[0009] When the input signal flips from a low level to a high level, the first input module controls the voltage of the first node to decrease under the drive of the potential control module;

[0010] When the inverted signal of the input signal flips from a high level to a low level, the second input module controls the voltage of the second node to rise to the high-voltage domain power supply voltage under the drive of the potential control module;

[0011] When the input signal flips, control the switching module to be in a conducting state so that the charge of the first node moves to the second node;

[0012] After the input signal is flipped, the control switch module is in the off state.

[0013] Compared with the prior art, the beneficial effects of the level conversion method provided by the present invention are the same as those of the level conversion circuit described in the above technical solution, and will not be elaborated here. Description of the Drawings

[0014] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The schematic embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation to the present invention. In the drawings:

[0015] Figure 1 is a schematic structural diagram of a level conversion circuit in the prior art;

[0016] Figure 2 is a schematic structural diagram of the level conversion circuit provided by the embodiment of the present invention.

[0017] Reference Signs:

[0018] 1 - First input module, 2 - Second input module,

[0019] 3 - Potential control module, 4 - Switch module,

[0020] 5 - Pulse signal generation module, 31 - First control sub-module,

[0021] 32 - Second control sub-module, 6 - Inverter. Detailed Embodiments

[0022] In order to clearly describe the technical solutions of the embodiments of the present invention, in the embodiments of the present invention, terms such as "first" and "second" are used to distinguish the same items or similar items with basically the same functions and effects. For example, the first threshold and the second threshold are only used to distinguish different thresholds and do not limit their order. Those skilled in the art can understand that the terms "first" and "second" do not limit the quantity and execution order, and the terms "first" and "second" do not necessarily mean different.

[0023] It should be noted that in the present invention, words such as "exemplary" or "for example" are used to indicate examples, illustrations or explanations. Any embodiment or design solution described as "exemplary" or "for example" in the present invention should not be construed as being more preferred or having more advantages than other embodiments or design solutions. Rather, the use of words such as "exemplary" or "for example" is intended to present relevant concepts in a specific manner.

[0024] In the present invention, "at least one" means one or more, and "a plurality" means two or more. "And / or" describes the association relationship of associated objects and indicates that three relationships may exist. For example, A and / or B may represent: A exists alone, A and B exist simultaneously, and B exists alone, where A and B may be singular or plural. The character " / " generally represents an "or" relationship between the associated objects before and after. "At least one (item)" or a similar expression refers to any combination of these items, including any combination of a single item or plural items. For example, at least one (item) of a, b, or c may represent: a, b, c, the combination of a and b, the combination of a and c, the combination of b and c, or the combination of a, b, and c, where a, b, and c may be single or multiple.

[0025] Figure 1 An example of a level conversion circuit in the prior art is shown. The inverted signal INB is the signal obtained after inverting the input signal IN. The N-type transistor N1' and the P-type transistor P1' form an inverter, and the N-type transistor N2' and the P-type transistor P2' form another inverter. The input signal IN and the inverted signal INB are respectively input to the input terminals of the two inverters. The sources of the N-type transistor N1' and the N-type transistor N2' are grounded. The drains of the N-type transistor N1' and the N-type transistor N2' are also respectively connected to the high-voltage domain power supply voltage terminal through the P-type transistor P3' and the P-type transistor P4'. The gate terminal of the P-type transistor P3' is connected to the output terminal A' of the N-type transistor N2' and the P-type transistor P2'. The gate of the P-type transistor P4' is connected to the output terminal B' of the N-type transistor N1' and the P-type transistor P1'. When the input signal IN is at a low level, the voltage at the output terminal A' is the voltage VDDH of the high-voltage domain power supply voltage terminal, and the voltage at the output terminal B' is the voltage 0 of the ground terminal GND.

[0026] When the input signal IN changes from a low level to a high level VDD, the N-type transistor N1' will conduct, causing the voltage at the output terminal A' to drop, and the P-type transistor P4' gradually turns on. At this time, the inverted signal INB changes to a low level, the P-type transistor P2' conducts, and the voltage at the output terminal B' gradually rises. Eventually, the voltage at point A' changes to 0, and the voltage at point B' changes to VDDH.

[0027] During the conversion process, since the voltage of the input signal IN is the power supply voltage VDD, while the source voltage of the P-type transistor P1' is VDDH, the P-type transistor P1' cannot be turned off, resulting in competition between the N-type transistor N1' and the P-type transistor P1'. To enable smooth voltage conversion, it is necessary to increase the sizes of the N-type transistors N1' and N2', but this measure cannot improve the voltage conversion speed, and the larger transistor sizes will increase the node capacitance, which will further reduce the voltage conversion speed.

[0028] In view of this, as Figure 2 shown, an embodiment of the present invention provides a level conversion circuit, including a first input module 1, a second input module 2, a potential control module 3, and a switch module 4. The first end of the potential control module 3 is electrically connected to the high-voltage domain power supply terminal, the second end of the potential control module 3 is respectively electrically connected to the first input module 1 and the second input module 2, the output end of the first input module 1, the first end of the switch module 4, and the first control end of the potential control module 3 are all coupled to the first node A, and the output end of the second input module 2, the second end of the switch module 4, and the second control end of the potential control module 3 are all coupled to the second node B. The first input module 1 is configured to control the voltage of the first node A to decrease under the drive of the potential control module 3 when the input signal IN flips from a low level to a high level. The second input module 2 is configured to control the voltage of the second node B to rise to the high-voltage domain power supply voltage under the drive of the potential control module 3 when the inverted signal INB of the input signal IN flips from a high level to a low level. The switch module 4 is configured to be in a conducting state when the input signal IN flips, so that the charge of the first node A moves towards the second node B. The switch module 4 is further configured to be in an off state after the input signal IN completes flipping.

[0029] From the structure of the above level conversion circuit, when the input signal IN flips from a low level to a high level, the potential control module 3 can control the voltage of the first node A to decrease after receiving the output signal of the first input module 1, and control the voltage of the second node B to rise to the high-voltage domain power supply voltage after receiving the output signal of the second input module 2. At this time, since the switch module 4 is in a conducting state when the input signal IN flips, the charge of the first node A can move towards the second node B through the switch module 4 to accelerate the voltage rising speed of the second node B, further shortening the time for the voltage of the second node B to reach the high-voltage domain power supply voltage, and finally converting the input signal IN into a high-voltage domain power supply voltage that meets the requirements and outputting it through the second node B, thereby improving the voltage conversion speed. In addition, when the input signal IN completes flipping, the switch module 4 is in an off state, which can reduce the static power consumption of the circuit to a certain extent and improve the reliability and stability of the circuit.

[0030] It can be understood that when the input signal IN flips from a high level to a low level, correspondingly, the first input module 1 can control the voltage of the first node A to rise to the high-voltage domain power supply voltage under the drive of the potential control module 3. After receiving the output signal of the second input module 2, the potential control module 3 can control the voltage of the second node B to drop. When the switch module 4 is in the conducting state, the charge of the second node B can move towards the first node A through the switch module 4 to accelerate the voltage drop speed of the second node B. Thus, it can be seen that the level conversion circuit provided by the embodiment of the present invention can also accelerate the voltage conversion speed of the circuit when the input signal IN flips from a high level to a low level.

[0031] In the present application, the above-mentioned level conversion circuit further includes an inverter 6. The first end of the inverter 6 is electrically connected to the control end of the first input module 1, and the second end of the inverter 6 is electrically connected to the control end of the second input module 2. Based on this, the inverter 6 is connected between the control end of the first input module 1 and the control end of the second input module 2, and can perform an inversion process on the input signal IN to output the inverted signal INB of the input signal IN to the control end of the second input module 2.

[0032] In a possible implementation manner, the level conversion circuit further includes a pulse signal generation module 5 electrically connected to the switch module 4. The first end of the pulse signal generation module 5 is used to receive the input signal IN, and the second end of the pulse signal generation module 5 is electrically connected to the control end of the switch module 4. The pulse signal generation module 5 is used to output a corresponding pulse signal to control the switch module 4 to be in the conducting state when the input signal IN flips. The pulse signal generation module 5 is further used to control the switch module 4 to be in the off state after the input signal IN completes the flip.

[0033] In an optional manner, as Figure 2 shown, the switch module 4 includes an N-type switch transistor N5. The control end of the N-type switch transistor N5 is electrically connected to the output end of the pulse signal generation module 5. The first end of the N-type switch transistor N5 is coupled to the first node A, and the second end of the N-type switch transistor N5 is coupled to the second node B.

[0034] Specifically, the above-mentioned pulse signal generation module 5 can actually be an edge detection flip-flop. When the input signal IN flips from a low level to a high level, the edge detection flip-flop can generate a pulse signal when the input signal IN undergoes a transition, so that the N-type switching transistor N5 can be briefly turned on at the initial stage when the input signal IN flips, enabling the charge at the first node A to flow to the second node B through the turned-on N-type switching transistor N5, accelerating the voltage drop rate at the first node A and the voltage rise rate at the second node B, and improving the voltage conversion speed. It should be understood that when the N-type switching transistor N5 is turned on for a long time, it will also increase the static power consumption of the circuit. Therefore, after the input signal IN has completed the flip, the edge detection flip-flop can drive the N-type switching transistor N5 to turn off, so that the N-type switching transistor N5 is in an off state.

[0035] In a possible implementation, as Figure 2 shown, the potential control module 3 includes a first control sub-module 31 and a second control sub-module 32. The first end of the first control sub-module 31 and the second end of the second control sub-module 32 are both electrically connected to the high-voltage domain power supply terminal. The first control terminal of the first control sub-module 31 is used to receive the inverted signal INB. The second control terminal of the first control sub-module 31 is coupled to the second node B. The second end of the first control sub-module 31 is electrically connected to the first input module 1. The first control terminal of the second control sub-module 32 is coupled to the first node A. The second control terminal of the second control sub-module 32 is used to receive the input signal IN. The second end of the second control sub-module 32 is electrically connected to the second input module 2.

[0036] Exemplarily, as Figure 2 shown, the first control sub-module 31 includes a first N-type transistor N1 and a first P-type transistor P1. The drain of the first N-type transistor N1 and the source of the first P-type transistor P1 are both electrically connected to the high-voltage domain power supply terminal. The source of the first N-type transistor N1 and the drain of the first P-type transistor P1 are electrically connected to the first input module 1. The gate of the first N-type transistor N1 is used to receive the inverted signal INB. The gate of the first P-type transistor P1 is used to receive the output signal of the second input module 2.

[0037] Exemplarily, as Figure 2 shown, the second control sub-module 32 includes a second N-type transistor N2 and a second P-type transistor P2. The drain of the second N-type transistor N2 and the source of the second P-type transistor P2 are both electrically connected to the high-voltage domain power supply terminal. The source of the second N-type transistor N2 and the drain of the second P-type transistor P2 are electrically connected to the second input module 2. The gate of the second N-type transistor N2 is used to receive the input signal IN. The gate of the second P-type transistor P2 is used to receive the output signal of the first input module 1.

[0038] Specifically, a first N-type transistor N1 is connected in parallel to the first P-type transistor P1. The gate of the first N-type transistor N1 is connected to the inverted signal INB. A second N-type transistor N2 is connected in parallel to the second P-type transistor P2. The gate of the second N-type transistor N2 is connected to the input signal IN. Taking the voltage of the input signal IN transitioning from a low level to VDD as an example, at this time, the first N-type transistor N1 is cut off, and the second N-type transistor N2 is partially conducting, causing the source voltage of the second N-type transistor N2 to rise, thereby accelerating the rise of the second node B, which in turn causes the current of the first P-type transistor P1 to decrease, further weakening the competition between the P-type and N-type transistors in the first input module 1.

[0039] In a possible implementation, as Figure 2 shown, the first input module 1 includes a third N-type transistor N3 and a third P-type transistor P3. The drain of the third N-type transistor N3 and the drain of the third P-type transistor P3 are both coupled to the first node A. The source of the third P-type transistor P3 is electrically connected to the second end of the potential control module 3. The source of the third N-type transistor N3 is grounded. The gates of the third N-type transistor N3 and the third P-type transistor P3 are both used to receive the input signal IN.

[0040] In a possible implementation, as Figure 2 shown, the second input module 2 includes a fourth N-type transistor N4 and a fourth P-type transistor P4. The drain of the fourth N-type transistor N4 and the drain of the fourth P-type transistor P4 are both coupled to the second node B. The source of the fourth P-type transistor P4 is electrically connected to the second end of the potential control module 3. The source of the fourth N-type transistor N4 is grounded. The gates of the fourth N-type transistor N4 and the fourth P-type transistor P4 are both used to receive the inverted signal INB of the input signal IN.

[0041] Specifically, taking the case where the voltage of the input signal IN transitions from a low level to VDD as an example, when the input signal IN flips, the gate-source voltage Vgs of the third N-type transistor N3 is VDD. At this time, the third N-type transistor N3 conducts, while the gate-source voltage Vgs of the third P-type transistor P3 is (VDD - VDDH), and the third P-type transistor P3 also conducts; the gate-source voltage Vgs of the fourth N-type transistor N4 is 0, and the fourth N-type transistor N4 is cut off; the gate-source voltage Vgs of the second P-type transistor P2 is 0, and the second P-type transistor P2 is cut off. After the N-type switch transistor N5 conducts, the charge at the first node A can move towards the second node B through the N-type switch transistor N5, thereby causing the voltage at the first node A to drop rapidly and the voltage at the second node B to rise rapidly. At this time, the current of the first P-type transistor P3 starts to decrease, the pull-up current flowing through the third P-type transistor P3 decreases, the voltage at the first node A drops further rapidly, the second P-type transistor P2 gradually turns on, and the voltage at the second node B rises further rapidly, thus accelerating the voltage conversion speed of the level conversion circuit.

[0042] An embodiment of the present invention further provides a level conversion method, which is applied to the level conversion circuit provided in the above embodiment. The level conversion method includes:

[0043] When the input signal IN flips from a low level to a high level, the first input module 1, under the drive of the potential control module 3, controls the voltage at the first node A to drop;

[0044] When the inverted signal INB of the input signal IN flips from a high level to a low level, the second input module 2, under the drive of the potential control module 3, controls the voltage at the second node B to rise to the high-voltage domain power supply voltage;

[0045] When the input signal IN flips, control the switch module 4 to be in a conducting state so that the charge at the first node A moves towards the second node B;

[0046] After the input signal IN finishes flipping, control the switch module 4 to be in an off state.

[0047] Compared with the prior art, the beneficial effects of the level conversion method provided by the embodiment of the present invention are the same as those of the level conversion circuit described in the above technical solution, and will not be elaborated here.

[0048] Although the present invention has been described in connection with specific features and their embodiments, it will be apparent that various modifications and combinations can be made without departing from the spirit and scope of the invention. Accordingly, the present specification and drawings are merely illustrative of the invention as defined by the appended claims and are considered to cover any and all modifications, variations, combinations or equivalents within the scope of the invention. Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention is also intended to include these changes and modifications.

Claims

1. A level conversion circuit, characterized in that, It includes a first input module, a second input module, a potential control module and a switch module, where: The first end of the potential control module is electrically connected to the high-voltage domain power supply terminal. The second end of the potential control module is respectively electrically connected to the first input module and the second input module. The output end of the first input module, the first end of the switch module and the first control end of the potential control module are all coupled to a first node. The output end of the second input module, the second end of the switch module and the second control end of the potential control module are all coupled to a second node; The first input module is used to control the voltage of the first node to decrease under the drive of the potential control module when the input signal flips from a low level to a high level; The second input module is used to control the voltage of the second node to rise to the high-voltage domain power supply voltage under the drive of the potential control module when the inverted signal of the input signal flips from a high level to a low level; The switch module is used to be in a conducting state when the input signal flips, so that the charge of the first node moves to the second node; The switch module is further used to be in an off state after the input signal finishes flipping.

2. The level conversion circuit according to claim 1, wherein The level conversion circuit further includes a pulse signal generation module electrically connected to the switch module. The first end of the pulse signal generation module is used to receive the input signal. The second end of the pulse signal generation module is electrically connected to the control end of the switch module. The pulse signal generation module is used to output a corresponding pulse signal to control the switch module to be in a conducting state when the input signal flips; The pulse signal generation module is further used to control the switch module to be in an off state after the input signal finishes flipping.

3. The level conversion circuit according to claim 2, wherein The switch module includes an N-type switch transistor. The control end of the N-type switch transistor is electrically connected to the output end of the pulse signal generation module. The first end of the N-type switch transistor is coupled to the first node. The second end of the N-type switch transistor is coupled to the second node.

4. The level conversion circuit according to claim 1, wherein The potential control module includes a first control sub-module and a second control sub-module, where: The first end of the first control sub-module and the second end of the second control sub-module are both electrically connected to the high-voltage domain power supply terminal. The first control end of the first control sub-module is used to receive the inverted signal. The second control end of the first control sub-module is coupled to the second node. The second end of the first control sub-module is electrically connected to the first input module; The first control end of the second control sub-module is coupled to the first node. The second control end of the second control sub-module is used to receive the input signal. The second end of the second control sub-module is electrically connected to the second input module.

5. The level conversion circuit according to claim 4, wherein The first control sub-module includes a first N-type transistor and a first P-type transistor, where: the drain of the first N-type transistor and the source of the first P-type transistor are both electrically connected to the high-voltage domain power supply terminal. The source of the first N-type transistor and the drain of the first P-type transistor are electrically connected to the first input module; The gate of the first N-type transistor is used to receive the inverted signal, and the gate of the first P-type transistor is used to receive the output signal of the second input module.

6. The level conversion circuit according to claim 4, characterized in that The second control sub-module includes a second N-type transistor and a second P-type transistor, where: the drain of the second N-type transistor and the source of the second P-type transistor are both electrically connected to the high-voltage domain power supply terminal, and the source of the second N-type transistor and the drain of the second P-type transistor are electrically connected to the second input module; The gate of the second N-type transistor is used to receive the input signal, and the gate of the second P-type transistor is used to receive the output signal of the first input module.

7. The level conversion circuit according to claim 1, characterized in that, The first input module includes a third N-type transistor and a third P-type transistor, where: The drain of the third N-type transistor and the drain of the third P-type transistor are both coupled to the first node, the source of the third P-type transistor is electrically connected to the second end of the potential control module, the source of the third N-type transistor is grounded, and the gates of the third N-type transistor and the third P-type transistor are both used to receive the input signal.

8. The level conversion circuit according to claim 1, wherein The second input module includes a fourth N-type transistor and a fourth P-type transistor, where: The drain of the fourth N-type transistor and the drain of the fourth P-type transistor are both coupled to the second node, the source of the fourth P-type transistor is electrically connected to the second end of the potential control module, the source of the fourth N-type transistor is grounded, and the gates of the fourth N-type transistor and the fourth P-type transistor are both used to receive the inverted signal of the input signal.

9. The level conversion circuit according to claim 1, characterized in that The level conversion circuit further includes an inverter, the first end of the inverter is electrically connected to the control end of the first input module, and the second end of the inverter is electrically connected to the control end of the second input module.

10. A level conversion method, characterized in that Applied to the level conversion circuit according to any one of claims 1 to 9, the level conversion method includes: When the input signal flips from a low level to a high level, the first input module, under the drive of the potential control module, controls the voltage of the first node to drop; When the inverted signal of the input signal flips from a high level to a low level, the second input module, under the drive of the potential control module, controls the voltage of the second node to rise to the high-voltage domain power supply voltage; When the input signal flips, control the switch module to be in a conducting state so that the charge of the first node moves to the second node; After the input signal completes the flip, control the switch module to be in an off state.

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