Display pixel comprising a light emitting diode for a display screen

Abstract

The present invention relates to a display unit (28) comprising a photoelectric circuit (26) including light-emitting diodes (LEDs) of at least two display pixels and having a first emitting surface (39) for emitting light from the LEDs; and a diffuser structure (52) covering the photoelectric circuit (26), each diffuser structure contacting a portion of the first emitting surface (39) and having a second emitting surface (54) for emitting light from one of the LEDs of the display pixels, the sum of the areas of the second emitting surfaces (54) being greater than 2 in ratio to the area of ​​the first emitting surface (39).

Description

[0001] This patent application claims priority to French patent applications FR21 / 12579 and FR21 / 12580, which are incorporated herein by reference. Technical Field

[0002] This disclosure generally relates to display pixels, including light-emitting diodes, for use in a display screen. Background Technology

[0003] A pixel in an image corresponds to a unit element of the image displayed on a screen. For the display of color images, the screen typically includes at least three components, also called display subpixels, for each pixel of the image. Each component emits light radiation in essentially a single color (e.g., red, green, and blue). The superposition of the radiation emitted by the three display subpixels provides the observer with a colored sensation corresponding to the pixel of the displayed image. In this case, the component formed by these three display subpixels for displaying the image pixels is called the display pixel of the screen. Each display subpixel may include a light source, particularly a light-emitting diode (LED).

[0004] Display pixels can be distributed in an array, with each display pixel located at the intersection of rows (or lines) and columns of the array. Typically, display pixels in each row are selected sequentially, and the display pixels in the selected rows are programmed to display the desired image pixels.

[0005] An active array is a screen driving architecture that allows all rows of pixels to remain active for the entire duration of an image. This contrasts with an array called a passive array, where each row is active only for a period of time T = Tframe / N (where Tframe is the duration of the image and N is the number of rows on the screen). This allows for optimized operation of the LEDs. Furthermore, low voltage or low current levels can be sent on the array control lines, enabling the display of larger data streams.

[0006] In the context of screens based on micrometer-scale light-emitting diodes (LEDs), the size of LEDs is typically smaller than the surface area available on the screen for image pixels due to their high inherent luminance. One method of manufacturing a display involves depositing these unit LEDs onto a support (also known as a flat panel) containing driving electronics. Another method involves using display pixels that include LEDs and circuitry for controlling them. These are therefore referred to as smart pixels. This particularly simplifies the formation of active arrays because the control electronics for the LEDs of the display pixels are largely embedded within the display pixels themselves. An example of a smart pixel is described in document WO 2018 / 185433.

[0007] There is a trend towards increasing numbers of display pixels on screens. This leads to increased costs and durations in display manufacturing, particularly depending on the number of operations required to install display pixels on a tablet, which is undesirable.

[0008] The goal is to minimize the size of display pixels to reduce the amount of semiconductor material used to form them, thereby lowering their manufacturing cost. However, bonding small display pixels to a flat panel can be challenging, especially ensuring proper electrical connections between the conductive pads of the display pixels and the conductive traces on the flat panel. This issue is even more critical given the current trend of increasing pixel counts in screens. Summary of the Invention

[0009] The purpose of this embodiment is to provide a display pixel including a light-emitting diode for a display screen that overcomes all or part of the disadvantages of existing display pixels including light-emitting diodes.

[0010] The purpose of this embodiment is to reduce the number of operations required to mount display pixels onto a tablet displaying a screen.

[0011] The purpose of this embodiment is to reduce the precision constraints for connecting display pixels to a flat panel.

[0012] An embodiment provides a display block, including:

[0013] - An optoelectronic circuit comprising light-emitting diodes for at least two display pixels, and having a first emitting surface for light radiation from the light-emitting diodes; and

[0014] - A diffuse structure covering the photoelectric circuit, each diffuse structure contacting a portion of the first emitting surface and having a second emitting surface emitting light from one of the light-emitting diodes in the display pixels, the sum of the areas of the second emitting surfaces being greater than 2 times the area of ​​the first emitting surface.

[0015] This allows for the use of small display pixels while maintaining a significant emission surface area for each display pixel.

[0016] According to one embodiment, the display pixels are separated by a first separating element that prevents light radiation from the light-emitting diodes from passing through, and the diffuser structure is separated by a second separating element that prevents light radiation from the light-emitting diodes from passing through, the first separating element being aligned with the second separating element at the level of the first emitting surface. Each diffuser structure can receive light radiation from only one light-emitting diode of the display pixels. This makes it possible to avoid optical crosstalk between display pixels of the same display block.

[0017] The purpose of each diffuser structure is to distribute the light radiation emitted by the light-emitting diodes of the display pixels in contact with the diffuser structure across the entire second emitting surface associated with the diffuser structure. According to one embodiment, the second emitting surface is a diffuser surface. According to one embodiment, each diffuser structure is at least partially made of a diffuser material. According to one embodiment, each diffuser structure is at least partially formed of a waveguide. According to one embodiment, each diffuser structure includes a pattern distributed on the surface that reflects or diffuses light radiation. According to one embodiment, the surface density of the pattern increases with distance from the optoelectronic circuitry.

[0018] According to one embodiment, the display block includes an electrically insulating sheath surrounding the optoelectronic circuitry, the diffuse structure covering the sheath, and contacting or separating from the sheath via an air film through a spacer inserted between the sheath and the diffuse structure.

[0019] According to one embodiment, the optoelectronic circuit includes a third surface opposite to the first surface and a first conductive pad exposed on the third surface, the display block including conductive traces that contact the first conductive pads and are continued by second conductive pads extending on the sheath.

[0020] An embodiment provides a display block, including:

[0021] - An optoelectronic circuit, comprising a light-emitting diode for at least one display pixel, a first surface emitting light radiation from the light-emitting diode, a third surface opposite to the first surface, and a first conductive pad exposed on the third surface.

[0022] - An electrically insulating sheath surrounding the optoelectronic circuit; and

[0023] - A conductive trace that contacts the first conductive pad and is continued by a second conductive pad extending on the sheath.

[0024] The spacing between the second conductive pads can be increased relative to the spacing between the first conductive pads. This simplifies the subsequent laying of pixel blocks on the plate by reducing constraints on pixel block positioning accuracy when transferring pixel blocks onto the plate.

[0025] According to one embodiment, at least one of the diffuse structures includes a light emitter. According to one embodiment, the light emitter includes a quantum dot. According to one embodiment, at least two diffuse structures include different light emitters. According to one embodiment, each of the light-emitting diodes emits a first light radiation of a first wavelength, and wherein the diffuse structure includes a first diffuse structure and a second diffuse structure, the first diffuse structure including a first light emitter adapted to convert the first light radiation into a second light radiation of a second wavelength different from the first wavelength, and the second diffuse structure including a second light emitter adapted to convert the first light radiation into a third light radiation of a third wavelength different from both the first and second wavelengths.

[0026] According to one embodiment, the display pixels of the photoelectric circuit are contiguous, and the first emitting surface is centered relative to the surface formed by the second emitting surface. According to one embodiment, the photoelectric circuit includes four display pixels.

[0027] According to one embodiment, the optoelectronic circuit includes a single circuit for controlling all the light-emitting diodes (LEDs) of the display pixels. Therefore, the optoelectronic circuit includes LEDs associated with multiple display pixels controlled by the same control circuit. This advantageously makes it possible to reduce the number of conductive pads required for power supply / control of these display pixels. This simplifies the subsequent laying of the pixel blocks on the flat panel by reducing constraints on pixel block positioning accuracy when transferring the pixel blocks onto the flat panel.

[0028] The embodiment also provides a display screen including a flat panel and a plurality of display blocks, such as previously defined display blocks, attached to the flat panel.

[0029] According to one embodiment, the display pixels of the display block are arranged in rows and columns, and the optoelectronic circuit of each display block includes at least four display pixels belonging to at least two adjacent rows and at least two adjacent columns.

[0030] The embodiment also provides a method for manufacturing a display block such as previously defined, comprising the steps of: a) forming a wafer including a plurality of said optoelectronic circuits;

[0031] b) Cutting the wafer to separate the optoelectronic circuit; and

[0032] c) For each individual optoelectronic circuit, form a diffuse structure covering the optoelectronic circuit.

[0033] According to one embodiment, the method further includes: in step a), forming a first separating element in each photoelectric circuit to separate the display pixels; and in step c), forming a second separating element to separate the diffuse structure and aligned with the first separating element.

[0034] The embodiment also provides a method for manufacturing a display such as the previously defined display, the method comprising mounting display blocks onto a flat panel. The number of first conductive pads for each display pixel is small, and the formation of second conductive pads allows for an increased spacing between the second conductive pads. This simplifies the subsequent laying of the pixel blocks on the flat panel by reducing constraints regarding pixel block positioning accuracy when transferring the pixel blocks onto the flat panel.

[0035] According to one embodiment, the sheath completely surrounds the optoelectronic circuit, and the minimum dimension of the sheath in a plane parallel to the third surface is in the range of 5 μm to 5 mm. According to one embodiment, the maximum dimension of the optoelectronic circuit in a plane parallel to the third surface is in the range of 10 μm to 200 μm, and the maximum dimension of the display block in the plane parallel to the third surface is in the range of 100 μm to 500 μm. According to one embodiment, the maximum spacing between the centers of the first conductive pads is in the range of 0.5 μm to 2 mm, and the minimum spacing between the centers of the second conductive pads is in the range of 1 μm to 5 mm, preferably in the range of 5 μm to 3 mm.

[0036] According to one embodiment, the optoelectronic circuit includes only four first conductive pads.

[0037] The embodiment also provides a method for manufacturing a display block such as previously defined, comprising the steps of: a') forming a wafer including a plurality of said optoelectronic circuits;

[0038] b') Cutting the wafer to separate the optoelectronic circuitry; and

[0039] c') For each separate optoelectronic circuit, an electrically insulating sheath is formed surrounding the optoelectronic circuit; and d') For each separate optoelectronic circuit, a conductive trace is formed that contacts a first conductive pad and is continued by a second conductive pad extending on the sheath. Attached Figure Description

[0040] The above-described features and advantages, as well as other features and advantages, will be described in detail in the remainder of this disclosure with reference to the accompanying drawings and specific embodiments given by way of illustration rather than limitation, wherein:

[0041] Figure 1 An example of a display screen is shown partially and schematically;

[0042] Figure 2 This is a partial, simplified top view of an example of the arrangement of display pixels on a screen;

[0043] Figure 3 This is a partial, simplified top view of another example of the arrangement of the display pixels on a screen;

[0044] Figure 4It is a local simplified cross-section of an embodiment of a set of pixels;

[0045] Figure 5 yes Figure 4 A partial simplified top view of an embodiment of the pixel group;

[0046] Figure 6 yes Figure 4 A partial simplified bottom view of an embodiment of a pixel group;

[0047] Figure 7 This is a partial simplified top view of an embodiment of the display screen;

[0048] Figure 8 This is a partial simplified cross-sectional view illustrating an embodiment of the diffuse structure;

[0049] Figure 9 This is a partial simplified cross-sectional view illustrating another embodiment of the diffuse structure;

[0050] Figure 10 This is a partial simplified cross-sectional view illustrating another embodiment of the diffuse structure;

[0051] Figure 11 This is a partial simplified cross-sectional view illustrating another embodiment of the diffuse structure;

[0052] Figure 12 This is a partial simplified cross-sectional view illustrating another embodiment of the diffuse structure;

[0053] Figure 13 This is a partial simplified cross-sectional view illustrating another embodiment of the diffuse structure;

[0054] Figure 14 yes Figure 4 A partial simplified cross-sectional view of a more detailed embodiment of the structure of display pixels in a pixel group;

[0055] Figure 15 The steps of an embodiment of a method for manufacturing a display screen are shown;

[0056] Figure 16 This illustrates another step of the method;

[0057] Figure 17 This illustrates another step of the method;

[0058] Figure 18 This illustrates another step of the method;

[0059] Figure 19 This illustrates another step of the method;

[0060] Figure 20 This illustrates another step of the method;

[0061] Figure 21 This illustrates another step of the method;

[0062] Figure 22 This illustrates another step of the method;

[0063] Figure 23 This illustrates another step of the method;

[0064] Figure 24 This illustrates another step of the method;

[0065] Figure 25 This illustrates another step of the method;

[0066] Figure 26 This illustrates another step of the method;

[0067] Figure 27 The image shown is displayed on a known display screen;

[0068] Figure 28 An image is shown displayed by a known display screen having display pixels including light-emitting diodes;

[0069] Figure 29 An image is shown displayed by a known display screen having display pixels including light-emitting diodes;

[0070] Figure 30 The arrangement of pixel groups is shown in the diagram. Figure 4 The image displayed on the screen with pixel groups;

[0071] Figure 31 This illustrates another arrangement based on pixel groups in a configuration including Figure 4 The image displayed on the screen of the pixel group; and

[0072] Figure 32 This illustrates another arrangement based on pixel groups in a configuration including Figure 4 The image displayed on the screen is composed of pixels. Detailed Implementation

[0073] In the various figures, similar features are indicated by similar reference numerals. In particular, common structural and / or functional features in various embodiments may have the same reference numerals and may be arranged with the same structure, dimensions, and material properties. For clarity, only the steps and elements used to understand the embodiments described herein are shown and described in detail.

[0074] Unless otherwise stated, when referring to two elements connected together, it means there is no direct connection of any intermediate element other than a conductor, and when referring to two elements coupled together, it means that the two elements can be connected or they can be coupled via one or more other elements. Furthermore, the terms "insulating" and "conductive" are considered herein to mean "electrically insulating" and "conductive," respectively.

[0075] In the following description, when referring to terms such as “front,” “back,” “top,” “bottom,” “left,” “right,” etc., which define absolute position, or terms such as “above,” “below,” “upper,” “lower,” etc., which define relative position, or terms such as “horizontal,” “vertical,” etc., which define direction, unless otherwise specified, they refer to the orientation of the accompanying drawings or the display screen in its normal use position.

[0076] Unless otherwise stated, expressions such as “approximately,” “about,” “basically,” and “around” indicate addition or subtraction of 10%, preferably 5%.

[0077] In the following description, the internal transmittance of a layer corresponds to the ratio of the intensity of radiation exiting the layer to the intensity of radiation entering the layer. The absorptivity of a layer is equal to the difference between the number 1 (which corresponds to the ideal transmittance that transmits all incident light) and the internal transmittance. In the following description, a layer is said to be transparent to radiation when the absorptivity of radiation passing through the layer is less than 75%. In the following description, a layer is said to be absorbing or opaque to radiation when the absorptivity of radiation in the layer is greater than 75%. In the remainder of this disclosure, the refractive index of a material corresponds to the refractive index of the material over the wavelength range of radiation emitted by the light source. Unless otherwise stated, the refractive index is considered to be substantially constant over the wavelength range of radiation emitted by the light source, for example, equal to the average refractive index over the wavelength range of radiation emitted by the light source.

[0078] Figure 1 An example of display screen 10 is shown partially and schematically. Display screen 10 includes, for example, display pixels 12 arranged in M ​​rows and N columns. i,j M is an integer ranging from 1 to 8000, N is an integer ranging from 1 to 16000, i is an integer ranging from 1 to M, and j is an integer ranging from 1 to N. As an example, in... Figure 1 In this context, M and N equal 6. Each display pixel is 12. i,j via electrode 14 i A source (e.g., ground) coupled to a low reference potential Gnd, and via electrode 16 j A source coupled to a high reference potential Vcc. As an example, electrode 14. i Shown as along Figure 1 The rows are aligned, and electrode 16 j Shown as along Figure 1 The columns are aligned correctly, but the reverse layout is also possible. The display's power supply voltage corresponds to the voltage between the high reference potential Vcc and the low reference potential Gnd.

[0079] For each row, the display pixels in that row are 12. i,j Coupled to row electrode 18 i For each column, the display pixels in that column are 12. i,j Coupled to column electrode 20 j The display screen 10 includes a selection circuit 22 coupled to the row electrode 18. i And suitable for 18 electrodes in each row i Upload selection and timing signal Com i The display screen 10 includes a data delivery circuit 24 coupled to the column electrodes 20. j And suitable for 20 electrodes in each column j Data signal delivered up j The selection circuit 22 and the control circuit 24 are controlled by, for example, a circuit 23 including a microprocessor.

[0080] When the display pixel corresponds to a smart pixel, the manufacturing method may include individually mounting each display pixel on a flat panel. The flat panel may include conductive traces, and each display pixel is bonded to the flat panel to connect the contact pads of the display pixel to the conductive traces. With the trend towards higher display resolutions, the number of individual mounting operations for display pixels can be substantial, thereby increasing the duration and cost of display manufacturing.

[0081] Each display pixel may include control circuitry covering display circuitry. The display circuitry includes at least one light-emitting diode (LED), preferably at least three LEDs. The control circuitry may correspond to an integrated circuit including electronic components, particularly an insulated-gate field-effect transistor (also known as a MOS transistor) or a thin-film transistor (also known as a TFT transistor). The control circuitry also includes contact pads. A method of manufacturing a display pixel includes: forming a plurality of display circuitry on a wafer called a photoelectric wafer, forming a plurality of control circuitry on a wafer called a logic wafer, bonding the photoelectric wafer to the logic wafer, and dicing the stack of the photoelectric wafer and the logic wafer to separate the display pixels.

[0082] One possibility for reducing the number of operations required to mount display pixels on a flat panel display is to group multiple display pixels into display pixel groups, each group comprising, for example, four display pixels. When display pixels are manufactured from a stack of optoelectronic and logic wafers as described above, this is equivalent to cutting the stack of optoelectronic and logic wafers to separate the pixel groups, rather than separating the display pixels individually. The mounting operation is performed on the display pixel groups rather than on individual pixels, thus reducing the number of operations. Thus, each pixel group comprises a stack of overall control circuitry (integrating circuitry for controlling the display pixels in that group) and overall display circuitry (including the display circuitry for the display pixels in that group).

[0083] Figure 2 and Figure 3 Each is a simplified top view of a portion of an example of a display screen 25 comprising multiple groups of pixels 26. Figure 2 and Figure 3 The diagram shows four groups of pixels 26, each group of pixels 26 comprising four display pixels (Pix).

[0084] exist Figure 2 In this design, the light-emitting diodes (CA) of each group of 26 display pixels (Pix) are connected in series. The drawback is that when the lateral size of the display pixels (Pix) decreases, the display pixels within the same group of 26 may become indistinguishable to the observer, resulting in the observer perceiving only a single image pixel.

[0085] exist Figure 3 In this design, each group of pixels 26 includes a logic circuit CL on which light-emitting diodes (LEDs) CA for displaying the pixel are arranged. The logic circuit CL has a sufficiently large lateral dimension so that the LEDs CA of the display pixels within the same group of pixels 26 are not connected. Therefore, the display pixels Pix within the same group of pixels 26 can be distinguished individually by the observer, and the observer will perceive different image pixels. The disadvantage is that, in a top view, a large portion of the surface area of ​​the pixel group 26 does not participate in light emission, and there are also costs associated with manufacturing the overall control circuitry and the overall display circuitry.

[0086] Figure 4 , Figure 5 and Figure 6 These are corresponding partial simplified cross-sectional views, top views, and bottom views of an embodiment of pixel block 28. Figure 4 The cross section is along Figure 5 and Figure 6 It is intercepted by line IV-IV in the middle.

[0087] Block 28 includes pixel group 26, which includes at least two display pixels. Figure 4 , Figure 5 and Figure 6In this configuration, pixel group 26 includes four display pixels (Pix). Pixel group 26 includes a master control circuit 30, which integrates circuitry for controlling the display pixels (Pix) and covers a master display circuit 32, which integrates the display circuitry for the display pixels (Pix). According to one embodiment, each display pixel can be controlled independently of the others. The master control circuit 30 is then configured to control each display pixel independently.

[0088] The overall control circuit 30 includes a lower surface 34 and an upper surface 35 opposite to the lower surface 34, preferably parallel to each other. The lower surface 34 of the overall control circuit 30 forms the lower surface of the pixel group 26. The overall control circuit 30 also includes conductive pads 36 exposed on the lower surface 34. The overall control circuit 30 may include a semiconductor substrate (not shown) covered with at least one metallization layer (not shown). In particular, the overall control circuit 30 may correspond to an integrated circuit including electronic components, especially a MOS transistor or a TFT transistor. The overall control circuit 30 may also include a conductive via 37 extending across a portion of the thickness of the overall control circuit 30 and enabling the conductive pads 36 to be connected to other electronic components of the overall control circuit or directly connected to the overall display circuit 32.

[0089] The main display circuit 32 includes a lower surface 38 and an upper surface 39 opposite to the lower surface 38, and surfaces 38 and 39 are preferably parallel. The upper surface 39 of the main display circuit 32 forms the upper surface of the pixel group 26. The lower surface 38 of the main display circuit 32 is bonded to the upper surface 35 of the main control circuit 30.

[0090] The overall display circuit 32 includes at least one light-emitting diode (LED) for each display pixel (Pix), preferably at least three LEDs. The overall display circuit 32 may include a single-layer or multi-layer structure 33 covering the LEDs and forming a top surface 39. Most, preferably all, of the radiation emitted by the LEDs of the display pixels is emitted from the top surface 39 of the overall display circuit 32. Preferably, the overall display circuit 32 includes only LEDs and their conductive elements, and the overall control circuit 30 includes all electronic components necessary for controlling the LEDs of the overall display circuit 32. Alternatively, the overall display circuit 32 may include other electronic components besides the LEDs. The LEDs may be 2D LEDs, also known as planar LEDs, comprising a stack of planar layers; or they may be 3D LEDs, each comprising a three-dimensional semiconductor element covered by an active region.

[0091] Pixel block 28 also includes a sheath 40 surrounding pixel group 26. Sheath 40 extends over the entire side surface of pixel group 26. Sheath 40 includes a lower surface 44 and an upper surface 45 opposite to the lower surface 44, surfaces 44 and 45 preferably being flat and parallel. The lower surface 44 of sheath 40 and the lower surface 34 of pixel group 26 form the lower surface 46 of pixel block 28, hereinafter also referred to as the contact surface. Preferably, the lower surface 44 of sheath 40 and the lower surface 34 of pixel group 26 are flat and coplanar, such that contact surface 46 is flat. Preferably, the upper surface 45 of sheath 40 and the upper surface 39 of pixel group 26 are planar and coplanar. Sheath 40 is preferably made of an insulating material. As an example, sheath 40 is made of silicon oxide (SiO2).

[0092] Pixel block 28 includes conductive traces 48 and conductive pads 50, with four conductive traces 48 and four conductive pads 50 in... Figure 6 The diagram is shown as an example. Conductive traces 48 extend onto the lower surface 34 of the pixel group 26 and the lower surface 44 of the sheath 40, and conductive pads 50 rest on the lower surface 44 of the sheath 40. Each trace 48 is connected at one end to one of the conductive pads 50 and at the first end to one of the conductive pads 36 of the pixel group 26. The conductive traces 48 and conductive pads 50 are made, for example, of aluminum (Al) or copper (Cu).

[0093] Pixel block 28 also includes diffuser structures 52, the number of which is equal to the number of display pixels (Pixes) in pixel group 26. Each diffuser structure 52 receives radiation emitted by one of the display pixels (Pixes). Each diffuser structure 52 covers a portion of the upper surface 45 of the sheath 40 and a portion of the upper surface 39 of the pixel group 26. Transmission of radiation from the total display circuitry 32 from pixel group 26 to diffuser structures 52 occurs specifically through the upper surface 39 of pixel group 26 in contact with diffuser structures 52. Each diffuser structure 52 includes an upper surface 54 for emitting radiation emitted by one of the display pixels (Pixes).

[0094] Pixel block 28 includes a first separating element 55 present in the overall display circuitry 32 and separating the display pixels Pix, and a second separating element 56 separating the diffuse structure 52. The first separating element 55 and the second separating element 56 prevent radiation emitted by the light-emitting diodes (LEDs) from passing through. The first separating element 55 is aligned with the second separating element 56. The first separating element 55 extends, for example, over a large portion, preferably at least 75%, and more preferably all of the thickness of the single-layer or multi-layer structure 33 and the LEDs, extending into the overall control circuitry 30. The second separating element 56 may correspond to an air-filled trench extending across the entire thickness of the diffuse structure 52, or to a wall that reflects the radiation emitted by the display pixels. Therefore, these separating elements 55, 56 enable the prevention of light emitted by the display pixels Pix from scattering on adjacent display pixels, which alters their emission spectrum and intensity and adversely affects the sharpness of the displayed image. According to one embodiment, all sidewalls of each diffuse structure 52 prevent radiation emitted by the LEDs from passing through. To this end, the outer wall of the diffuse structure 52 may be covered with a coating and / or an air film that is opaque to and / or reflects radiation emitted by the LED. This makes it possible to avoid optical crosstalk between adjacent pixel blocks 28.

[0095] For each display pixel Pix, the diffuse structure 52 partially functions as a waveguide for the radiation emitted by the display pixel Pix, such that in operation, at least 50%, preferably at least 75%, more preferably at least 90%, and even more preferably 100% of the surface 54 of the diffuse structure 52 emits light. The ratio of the total area of ​​the emitting surfaces 54 of the diffuse structure 52 to the area of ​​the upper surface 39 of the pixel group 26 is greater than 2, preferably greater than 5, preferably greater than 50, and even more preferably greater than 500.

[0096] According to one embodiment, each display pixel includes first, second, and third display sub-pixels adapted to emit radiation of first, second, and third wavelengths. According to one embodiment, the first wavelength corresponds to blue light, i.e., radiation with a wavelength in the range of 430 nm to 490 nm. According to one embodiment, the second wavelength corresponds to green light and is in the range of 510 nm to 570 nm. According to one embodiment, the third wavelength corresponds to red light and is in the range of 600 nm to 720 nm.

[0097] The sheath 40 may be reflective of radiation emitted by the display pixels. As an example, the sheath 40 may be formed of a material that is opaque to radiation emitted by the display pixels and reflective. The sheath 40 may be made of a transparent or diffuse material. In this case, a portion of the radiation emitted by the total display circuitry 32 can reach the diffuse structure 52 through the sheath 40. Preferably, the separation element 55 further includes a third separation element extending in the sheath 40 aligned with the second separation element 56. As a variation, a wall reflecting radiation emitted by the display pixels may be inserted between the sheath 40 and the sidewalls of the pixel group 26 to prevent a portion of the radiation emitted by the total display circuitry 32 from penetrating into the sheath 40.

[0098] Pixel block 28 can have a generally cylindrical shape, and its cross-section can have different shapes, such as, for example, elliptical, circular, or polygonal, particularly triangular, rectangular, square, or hexagonal shapes. As an example, in Figure 5 and Figure 6 In the diagram, pixel block 28 is shown as having a square cross-section. Pixel group 26 may have a generally cylindrical shape, and its cross-section may have different shapes, such as, for example, elliptical, circular, or polygonal, particularly triangular, rectangular, square, or hexagonal shapes. As an example, in Figure 5 and Figure 6 In the diagram, pixel group 26 is shown with a square cross-section. The maximum lateral dimension of pixel block 28 in the top view can range from 100 μm to 500 μm. The maximum lateral dimension of pixel group 26 in the top view can range from 10 μm to 200 μm. The sheath 40 can completely surround pixel group 26, and the minimum dimension of sheath 40 in the plane of lower surface 34 can range from 5 μm to 5 mm. The thickness of pixel block 28 can range from 20 μm to 750 μm. The thickness of pixel group 26 can range from 20 μm to 750 μm. The thickness of sheath 40, measured orthogonally to lower surface 34, can be the same as the thickness of pixel group 26. The thickness of the overall control circuit 30 can range from 10 μm to 725 μm. The thickness of the overall display circuit 32 can range from 10 μm to 725 μm. In the bottom view, the distance between the center of pad 50 and the center of pixel group 26 can range from 50 μm to 300 μm. The thickness of each discrete element 56, 55, measured in the top view, can range from 2 μm to 3 μm. The maximum spacing between the centers of each conductive pad 36 can range from 0.5 μm to 2 mm, and the minimum spacing between the centers of each pad 50 can range from 1 μm to 5 mm, preferably from 5 μm to 3 mm.

[0099] Figure 7 This is a simplified top view of a portion of an example of a display screen 60 including pixel blocks 28. Figure 7 The diagram shows four pixel blocks 28, each comprising four display pixels (Pix). A gap 61 may exist between two adjacent pixel blocks 28. The gap 61 may have a thickness ranging from 1 μm to 50 μm. At least 50%, preferably at least 75%, of the surface area of ​​the display screen 60 as seen by an observer corresponds to the emitting surface area of ​​the pixel group 26. Display pixels (Pix) within the same pixel group 26 can be individually distinguished by an observer, who will then perceive different image pixels. Furthermore, the entire upper surface 39 of the pixel group 26 participates in light emission.

[0100] Each diffuser structure 52 may have a single-layer or multi-layer structure. The percentage between the optical power emanating from surface 54 per unit area at the given location and the optical power injected into the diffuser structure 52 by the total display circuitry 32 is called the diffuse power of surface 54 at a given location. According to one embodiment, the diffuse power of surface 54 is in the range of 0.5% to 50% at any location on surface 54.

[0101] Figure 8 This is a partially simplified cross-sectional view of an embodiment of the diffuse structure 52. According to one embodiment, the diffuse structure 52 includes a texture on the emitting surface 54. The diffuse structure 52 may correspond to a transparent material layer to which the surface texture is applied. The texture may correspond to polishing. The transparent material layer may be made of a polymer, silicone, or silicon oxide. The thickness of the transparent material layer may range from 0.01 μm to 100 μm. The arithmetic mean height Ra of the emitting surface 54 ranges from 0.1 μm to 5 μm.

[0102] According to one embodiment, each diffuse structure 52 is a diffuse material layer.

[0103] Figure 9 This is a simplified view illustrating an example of a diffuse material including a matrix 62 in which reflective particles 63 are dispersed. The matrix 62 can be made of a material that is transparent to radiation emitted by the display pixels (Pix). The matrix 62 can include silicon oxide (SiO2), silicone polymers, epoxy polymers, acrylic polymers, or polycarbonate. The particles 63 are, for example, titanium oxide particles (TiO2). The thickness of the layer made of the diffuse material can range from 2 μm to 2 mm.

[0104] Each diffuser structure 52 may have at least a partial waveguide structure. This advantageously enables the radiation emitted by the display pixel Pix to be guided throughout the diffuser structure 52, such that the emission of radiation occurs across the entire corresponding emitting surface 54.

[0105] Figure 10This is a partially simplified cross-sectional view of another embodiment of the diffuse structure 52, which partially has a waveguide structure and includes, from top to bottom:

[0106] -The upper protective layer 64 defines the launching surface 54;

[0107] -Core 66;

[0108] - Lower sheath 68, core 66 sandwiched between lower sheath 68 and upper sheath 64; and

[0109] - A raised pattern 70 in the micrometer range rests on the lower sheath 68 on one side of the core 66.

[0110] The core 66 can have a single-layer or multi-layer structure. In the case of a multi-layer core, all layers forming the core 66 have substantially the same refractive index. The upper cladding 64, lower cladding 68, and pattern 70 can be made of the same or different materials. Pattern 70 can be made of the same material as the lower cladding 68. Specifically, pattern 70 and lower cladding 68 can form a monolithic structure. Specifically, pattern 70 and lower cladding 68 can correspond to an air film for at least the portion of the diffuser structure 52 facing the cladding 40. As a variation, for the portion of the diffuser structure 52 facing the cladding 40, the lower cladding 68 corresponds to an air film, and pattern 70 is formed by inserting a spacer between the cladding 40 and the core 66. The refractive index of the material forming the core 66 is greater than that of the materials forming the upper sheath 64, lower sheath 68, and pattern 70. Alternatively, if the upper sheath 64, lower sheath 68, and / or pattern 70 are made of different materials, the refractive index of the material forming the core 66 is greater than that of the materials forming the upper sheath 64, lower sheath 68, and pattern 70. The upper sheath 64 may be absent, in which case the emitting surface 54 corresponds to the upper surface of the core 66. The lower sheath 68 may be absent between the core 66 and the sheath 40, and can instead be replaced by an air film between the core 66 and the sheath 40, held by a spacer inserted between the core 66 and the sheath 40. The refractive index of the lower sheath 68, which contacts the upper surface 39 of the pixel group 26, is lower than that of the single-layer or multi-layer structure 33. The upper sheath 64 includes a surface 72 that contacts the core 66. Preferably, surface 72 is flat and parallel to the upper surface 54. The lower sheath 68 includes a surface 74 on which the pattern 70 rests and is in contact with the core 66 on the outside of the pattern 70. The upper sheath 64 may also serve as a protective coating for the core 66.

[0111] Pattern 70 increases the extraction of radiation injected into waveguide 52. Patterns 70 can have the same shape or different shapes. As an example, each pattern 70 may include a flat surface 76 inclined relative to the upper surface 54. As an example, each pattern 70 may have a prism shape. As a variation, pattern 70 may rest on the upper sheath 64 on one side of the core 66.

[0112] According to one embodiment, the thickness of the core 66 can range from 2 μm to 1 mm. According to one embodiment, the thickness of the upper sheath 64 can range from 1 μm to 150 μm, preferably from 30 μm to 80 μm. According to one embodiment, the thickness of the lower sheath 68 can range from 1 μm to 150 μm. The maximum height of each pattern 70, measured relative to the surface 74, can range from 0.5 μm to 100 μm, preferably from 1 μm to 10 μm. Each pattern 70 can have a width of less than 20 μm, preferably less than 12 μm, more preferably between 2 μm and 6 μm.

[0113] According to one embodiment, the core 66 may be made of polycarbonate (PC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), or cyclic olefin polymer (COP). According to one embodiment, the upper sheath 64, lower sheath 68, and / or pattern 70 may be composed of an optically clear adhesive (OCA), particularly a liquid optically clear adhesive (LOCA), or a material with a low refractive index, or an epoxy / acrylate adhesive, or a film of a gas or gas mixture. According to one embodiment, the refractive index of the core 66 is in the range of 1.45 to 1.7, and the refractive indices of the upper sheath 64, lower sheath 66, and pattern 70 are in the range of 1 to 1.55. The difference between the refractive index of the core 66 and the refractive indices of the upper sheath 64, lower sheath 66, and pattern 70 is greater than 0.07, preferably greater than 0.1. The waveguide 52 may be formed according to a sheet-by-sheet process or a roll-by-roll process. The pattern 70 may be formed by pressure molding or by inkjet printing.

[0114] Figure 11 This is a partially simplified cross-sectional view of another embodiment of the diffuse structure 52, which partially has a waveguide structure having a... Figure 10 The structure shown is similar to the one described above, except that pattern 70 is located at the interface between the core 66 and the upper sheath 64. Furthermore, in... Figure 11 In this embodiment, the emitting surface 54 has a texture that improves the diffusion of emitted light. As an example, the texture includes forming cavities in the upper surface 54 to form lenses with micrometer-scale dimensions.

[0115] Figure 12 This is a partially simplified cross-sectional view of another embodiment of the diffuse structure 52, which partially has a waveguide structure having a... Figure 10 The structure shown is similar to the one described, except that pattern 70 facilitates the diffusion of light guided by the waveguide. As a variant, pattern 70 is absent. In this case, the interface between the lower sheath 68 and the core 66 is tilted relative to the interface between the upper sheath 64 and the core 66, and relative to the emitting surface 54.

[0116] Figure 13 This is a partially simplified cross-sectional view of another embodiment of the diffuse structure 52, which partially has the same characteristics as... Figure 12 The structure shown is similar to the one shown, except that the pattern 70 that facilitates the diffusion of light guided by the waveguide is located on the upper surface 54.

[0117] The surface density of the pattern 70 in the diffuse structure 52 may not be constant. Specifically, the surface density of the pattern 70 may increase with distance from the region into which radiation is injected into the diffuse structure 52. For example, when radiation is injected into the diffuse structure 52 at its edge, the surface density of the pattern 70 increases with distance from that edge. This variation in the pattern surface density allows for the maintenance of uniformity in the spectral density of the forward radiation flux emitted by the emitting surface 54, while the spectral density of the radiation flux propagating into the diffuse structure 52 decreases with distance from the region into which radiation is injected into the diffuse structure 52.

[0118] Figure 14 This is a partial simplified cross-sectional view of a more detailed embodiment of a pixel group 26 including three display sub-pixels.

[0119] According to one embodiment, the overall control circuit 30 is in Figure 14 From bottom to top, the middle includes:

[0120] - Semiconductor substrate 80 (e.g., single-crystal silicon), insulating layer 82 defining lower surface 34, and conductive pads 36 exposed on lower surface 34;

[0121] - Other types of transistors 84 commonly used in MOS-type or integrated circuits, such as bipolar junction transistors (BJTs), are formed inside and on top of the substrate 80. These transistors can also be thin-film transistors (TFTs) deposited on a substrate of a different nature than silicon (e.g., a polymer substrate), or even deposited directly on the back side of the light-emitting diode (LED). In this case, the LED forms the substrate, and the manufacturing process is performed in the reverse order of what was previously described, i.e., first the metallization layers (stack 85), and finally the passive and active components;

[0122] - For example, a stack 85 of insulating layers made of silicon oxide and / or silicon nitride, which covers the substrate 80 and conductive traces 86 of a plurality of metallization levels formed between the insulating layers of the stack 85, particularly having pads 88 exposed on the upper surface 35 of the overall control circuit 30, wherein the conductive traces 86 of the first metallization level may be made of polysilicon and particularly form the gate of the MOS transistor 82, and wherein the conductive traces 86 of the other metallization levels may be metal traces, for example, made of aluminum, silver, copper or zinc; and - a conductive and laterally insulating through-hole 37, also known as a TSV (through silicon via), which passes through the substrate 80 and couples the pads 36 to the pads 90 of the first metallization level of the stack 85.

[0123] According to one embodiment, the overall display circuit 32 is in Figure 14 From bottom to top, the middle includes:

[0124] - Support member 91, which forms a lower surface 38 of the total display circuit 32 that contacts the upper surface 35 of the total control circuit 30, and includes conductive pads 92 exposed on the lower surface 38 that contact pads 90, and a multilayer insulating structure 93, which is made of, for example, silicon oxide or silicon nitride, extends between and covers the pads 92, and includes an opening 94 that exposes a portion of the pads 92.

[0125] - Microwires or nanowires 95, hereinafter referred to as wires (six wires are shown), each wire 95 contacts one of the pads 92 through one of the openings 94;

[0126] - Insulation layer 96 extends on the side of the lower portion of each conductor 95 and on the insulation layer 93 between each conductor 95;

[0127] - A housing 98 comprising a stack of semiconductor layers covering the upper portion of each wire 95 and extending over an insulating layer 96 between the wires 95. The housing 98 particularly includes an active layer that emits most of the radiation supplied by a light-emitting diode and includes, for example, confinement devices such as a plurality of quantum wells; - A conductive reflective layer 100 extending over the housing 98 between the wires 95.

[0128] - A transparent conductive layer 102 is formed to cover electrodes for each wire 95 and housing 98, and further extends on the conductive layer 100 between each wire 95.

[0129] - A photoluminescent block 104 or a block transparent to radiation emitted by a light-emitting diode (LED) covering certain components of the LED, each photoluminescent block including a light-emitting body adapted to emit light with a wavelength different from the wavelength of the light emitted by the associated LED when excited by light emitted by the LED;

[0130] - An insulating layer 106 covering the upper surface of each block 104, which may be absent;

[0131] -A protective layer 108 covering the insulating layer 106, the side surfaces of the block 104, and the electrode layer 102 between the blocks 104;

[0132] - A wall 110 between the photoluminescent blocks 104, wherein each wall 110 may include a core 112 surrounded by a coating 114 that reflects radiation emitted by the photoluminescent blocks 104 and / or light-emitting diodes (LEDs) at wavelengths; - a color filter 116 covering at least some of the photoluminescent blocks 104; and

[0133] - Encapsulation layer 118 covering the entire structure.

[0134] The previously described separating element 55 was not in Figure 4 As shown in the diagram, it can surround all display subpixels.

[0135] Each wire 95 may have an elongated semiconductor structure. Each wire 95 may have a generally cylindrical shape, and its cross-section may have different shapes, such as, for example, elliptical, circular, or polygonal, particularly triangular, rectangular, square, or hexagonal shapes. Each wire 95 has, for example, an average diameter, corresponding to the diameter of a disk having the same cross-sectional area as the wire 94, ranging from 5 nm to 5 μm, preferably from 100 nm to 2 μm, more preferably from 200 nm to 1.5 μm, and a height greater than or equal to 1 times the average diameter, preferably greater than or equal to 3 times the average diameter, and more preferably greater than or equal to 5 times the average diameter, particularly greater than 500 nm, preferably in the range of 1 μm to 50 μm. The wire 95 comprises at least one semiconductor material. The semiconductor material may be silicon, germanium, silicon carbide, III-V compounds (e.g., GaN, AlN, InN, InGaN, AlGaN, or AlInGaN), II-VI compounds, or combinations of at least two of these compounds.

[0136] The conductive layer 102 can bias the active layer of the housing 98 and allow electromagnetic radiation emitted by the light-emitting diode to pass through. The material forming the conductive layer 102 can be a transparent conductive material such as graphene or silver, or a transparent conductive oxide (TCO), particularly indium tin oxide (ITO); or zinc oxide doped or undoped with aluminum, gallium, or boron. As an example, the thickness of the conductive layer 102 is in the range of 20 nm to 500 nm, preferably in the range of 20 nm to 100 nm.

[0137] The conductive layer 100, conductive trace 86, and conductive pads 36, 88, and 92 may be made of metals such as aluminum, silver, platinum, nickel, copper, gold, or ruthenium, or of alloys comprising at least two of these compounds, particularly PdAgNiAu alloy or PtAgNiAu alloy.

[0138] Each of insulating layers 85, 93, 96, 106, 108, and 118 is made of a material selected from the group consisting of: silicon oxide (SiO2), silicon nitride (SiO2), and silicon oxide (SiO2). x N y Where x is approximately equal to 3 and y is approximately equal to 4, for example, Si3N4), silicon oxynitride (especially the general formula SiO2), where x is approximately equal to 3 and y is approximately equal to 4. x N y For example, Si2ON2), hafnium oxide (HfO2), titanium oxide (TiO2), or aluminum oxide (Al2O3).

[0139] According to one embodiment, all light-emitting diodes of the display pixel Pix emit light radiation of the same wavelength. The diffuser structure 52 covering the display pixel Pix can contain a light emitter adapted to emit light of a desired color when excited by the light emitted by the display pixel. This allows wavelength conversion of the radiation to be performed at the level of the diffuser structure 52 rather than at the level of the display pixel. Therefore, in conjunction with the foregoing Figure 14 Compared to the described display pixel structure, the photoluminescent block 104 and color filter 116 may be absent. Furthermore, the power density received by the light emitters present in the diffuse structure 52 is lower than the power density they receive when the light emitters are directly integrated into the display pixel. This is particularly advantageous when the light emitters include quantum dots with conversion properties (which, due to their high power density, decrease more rapidly over time).

[0140] Figures 15 to 26 Is Figure 7 A partially simplified cross-sectional view of the structure obtained in the successive steps of the embodiment of the display screen 60 shown.

[0141] Figure 15 The diagram illustrates the structure obtained after the steps of forming the optoelectronic wafer 120 and the logic wafer 122. The optoelectronic wafer 120 includes a support 124 having an upper surface 126 and a lower surface 128, and light-emitting diodes (LEDs) formed on the upper surface 126. The optoelectronic wafer 120 includes LEDs representing the overall display circuitry of multiple pixel groups. The logic wafer 122 includes overall logic control circuitry for multiple pixel groups.

[0142] Figure 16The diagram shows the structure obtained after bonding a photoelectric wafer 120 to a logic wafer 122 on one side of a light-emitting diode (LED) and removing the support member 124 from the photoelectric wafer 120. The stack 130 of the logic wafer 122 and the photoelectric wafer 122 minus the support member 124 is referred to hereinafter as a display pixel wafer.

[0143] Figure 17 The diagram illustrates the structure obtained after the steps of forming an optical structure 132 on an optoelectronic wafer 120 and forming a second discrete element 55 in the optical structure 132 and the light-emitting diode (LED). The optical structure 132 may have a single-layer or multi-layer structure. The second discrete element 55 may include opaque and / or reflective walls. The optical structure 132 may include the aforementioned photoluminescent block and color filter. As a variation, the optical structure 132 may be absent.

[0144] Figure 18 The diagram shows the structure obtained after the step of attaching the pixel wafer 130 to the handle 134 on one side of the optoelectronic wafer 120.

[0145] Figure 19 The diagram shows the structure obtained after the steps of thinning the logic wafer 122, forming the TSV 37 by the thinned logic wafer 122, and forming conductive pads 36 electrically connected to the TSV 37 on the lower surface side of the display pixel wafer 130.

[0146] Figure 20 The diagram shows the structure obtained after the step of dicing the display pixel wafer 130 to separate the pixel groups 26. This step can be performed by sawing. Each pixel group 26 thus defined includes a total display circuit 32 and a total control circuit 30. The total display circuit 32 includes light-emitting diodes (LEDs) for at least two display pixels (preferably four display pixels), and the total control circuit 30 controls the LEDs of the display pixels in the pixel group 26.

[0147] Figure 21 The diagram shows the structure obtained after the step of transferring at least one pixel group 26 from handle 134 to handle 136, with the pixel group 26 attached to handle 136 on one side of the overall display circuitry 32. According to one embodiment, the transfer step may include a first transfer of the pixel group 26 from handle 134 to a middle handle (not shown) (where the pixel group 26 is attached to the middle handle on one side of the overall control circuitry 30) and a transfer of the pixel group 26 from the middle handle to handle 136.

[0148] Figure 22The diagram illustrates the structure obtained after the steps of forming a dielectric layer on the handle 136 and the display pixel block, a planarization step exposing the overall control circuitry 30 of the pixel group 26 and thereby defining the sheath 40 surrounding the pixel group 26, and a step of forming traces 48 and contact pads 50, wherein the traces 48 extend on the overall control circuitry 30 of the pixel group 26 and the sheath 40, and the contact pads 50 rest on the sheath 40. The planarization step may include a CMP step. Pixel blocks 28 are then partially formed. For each pixel block 28, the pixel group 26 of the pixel block 28 includes light-emitting diodes associated with a plurality of display pixels controlled by the same overall control circuitry 30. This advantageously makes it possible to reduce the number of conductive pads 36 necessary for powering / controlling these display pixels. The reduced number of conductive pads 36 for each display pixel and the formation of contact pads 50 make it possible to reduce the spacing between the contact pads 50. This simplifies the subsequent laying of the pixel blocks 28 on the flat panel (described below) by reducing constraints on the positioning accuracy of the pixel blocks 28 during transfer to the flat panel.

[0149] Figure 23 The structure is shown after the step of transferring the partially formed pixel block 28 from one side of the overall control circuit 30 of the pixel group 26 (e.g., via adhesive layer 138) to another handle 137 from handle 136.

[0150] Figure 24 The diagram illustrates the structure obtained after the step of forming a diffuse layer 139 on the protective layer 40 and the pixel group 26. According to one embodiment, forming the diffuse layer 139 includes forming a diffuse material layer on the emitting surface of the display pixel block. According to another embodiment, forming the diffuse layer includes forming a transparent material layer on the emitting surface of the display pixel block and forming a texture on the surface of that layer.

[0151] Figure 25 The structure obtained after forming a second separating element 56 in the diffuse layer 139 to obtain the diffuse structure 52 is shown. The second separating element 56 is formed to be aligned with a first separating element 55 of the pixel group 26 and with third separating elements present in the sheath 40 (when they are present). According to one embodiment, the formation of the first separating element 56 includes forming a trench in the diffuse structure 52. According to another embodiment, the formation of the second separating element 56 includes forming a reflective wall across the entire thickness of the diffuse structure 52 in the diffuse layer 52. Compared to obtaining alignment by depositing the pixel group 26 containing the first separating element 55 on the diffuse structure 52 containing the second separating element 56, it is advantageously easier and more accurate to form the alignment of the second separating element 56 with the first separating element 55 by forming the second separating element 56 in the diffuse structure 52 resting on the pixel group 26 and the sheath 40. Pixel block 28 is then obtained.

[0152] Figure 26 The diagram illustrates the structure obtained after the step of transferring pixel blocks 28 onto the display panel 140. The panel 140 may include a support 142 having conductive traces 144 extending thereon. Each contact pad 50 of each pixel block 28 contacts one of the conductive traces 144. This transfer can be performed by individual pixel blocks 28 or by a group of pixel blocks 28. The enlargement of the contact pads 50 relative to the conductive pads 36 and the corresponding spacing advantageously enable a reduction in precision constraints and allow for faster and cheaper positioning of the pixel blocks 28 on the panel 140.

[0153] The function of displaying on different screens has been implemented. Figure 27 The images were tested. For these tests, each pixel group consisted of four display pixels. The results were obtained through simulation. Figure 28 , Figure 29 , Figure 30 , Figure 31 and Figure 32 .

[0154] Figure 28 and Figure 29 Each shows when the display screen has Figure 2 The structure shown is the image as seen by the observer; in the top view, the surface area occupied by the pixel group is... Figure 28 The area corresponding to 1% of the surface area of ​​the display screen and in Figure 29 The area corresponds to 1% of the surface area of ​​the display screen. Image pixels of four display pixels in the same group may not be easily distinguishable by an observer.

[0155] Figure 30 , Figure 31 and Figure 32 Each shows when the display screen has Figure 7 The structure shown is the image as seen by the observer; in the top view, the surface area occupied by the pixel blocks is... Figure 30 The area corresponding to 100% of the surface area of ​​the display screen is in Figure 31 The middle corresponds to 80% of the surface area of ​​the display screen, in Figure 32 The center corresponds to 64% of the surface area of ​​the display screen. The image pixels of the four display pixels in the same group can be distinguished by the observer.

[0156] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations can be combined, and other variations will occur to them. Specifically, in the foregoing embodiments, the pixel group 26 of pixel block 28 includes a plurality of display pixels (Pixes). However, it should be understood that pixel group 26 may correspond to an optoelectronic circuit including a single display pixel. Furthermore, in the foregoing embodiments, pixel block 28 includes a diffuse structure 52. However, it should be understood that the diffuse structure 52 may not be present. Additionally, the diffuse structure may include features such as... Figures 10 to 13 The waveguide portion and the portion made of diffuser material are shown. Furthermore, although in the foregoing embodiment, pixel group 26 includes two chips bonded to each other, it should be understood that a pixel group may include a single chip, and the LED control circuitry may be integrated with or not integrated into the pixel group. Finally, based on the functional indications given above, the actual implementation of the described embodiments and variations is within the capabilities of those skilled in the art.

Claims

1. A display block (28), comprising: - An optoelectronic circuit (26) comprising light-emitting diodes (LEDs) for at least two display pixels (Pixes) and having a first emitting surface (39) for light radiation from the LEDs; and - A diffuse structure (52) covering the photoelectric circuit (26), each diffuse structure contacting a corresponding portion of the first emitting surface (39) associated with a corresponding display pixel and having light radiation from the light-emitting diode of the corresponding display pixel, the sum of the areas of the second emitting surfaces (54) being greater than 2 to the area of ​​the first emitting surface (39), wherein at least two display pixels (Pixes) of the photoelectric circuit (26) are in contact, and wherein the first emitting surface (39) is centered relative to the surface formed by the second emitting surfaces (54).

2. The display block according to claim 1, wherein the display pixel is separated by a first separating element that prevents light radiation from the light-emitting diode (LED) from passing through, and wherein the diffuse structure (52) is separated by a second separating element (56) that prevents light radiation from the light-emitting diode (LED) from passing through, the first separating element (55) being aligned with the second separating element (56) at the level of the first emitting surface (39).

3. The display block according to claim 1, wherein each second emitting surface (54) is a diffuse surface.

4. The display block according to claim 1, wherein each diffuse structure (52) is at least partially made of a diffuse material.

5. The display block according to claim 1, wherein each diffuse structure (52) is at least partially formed by a waveguide.

6. The display block according to claim 1, wherein each diffuse structure (52) comprises a pattern (70) distributed on the surface and reflecting or diffusing the light radiation.

7. The display block according to claim 6, wherein the surface density of the pattern (70) increases with distance from the photoelectric circuit (26).

8. The display block according to any one of claims 1 to 7, comprising an electrically insulating sheath (40) surrounding the optoelectronic circuit (26), the diffuser structure (52) covering the sheath and contacting the sheath or separating from the sheath via an air film through a spacer inserted between the sheath and the diffuser structure.

9. The display block according to claim 8, wherein the photoelectric circuit (26) includes a third surface (34) opposite to the first emitting surface (39) and a first conductive pad (36) exposed on the third surface, the display block (28) including a conductive trace (48) contacting the first conductive pad (36) and being continued by a second conductive pad (50) extending on the sheath (40).

10. The display block according to any one of claims 1 to 7, wherein each diffuse structure (52) receives light radiation from only one of the light-emitting diodes (LEDs) of the display pixels.

11. The display block according to any one of claims 1 to 7, wherein at least one of the diffuse structure (52) comprises a light emitter.

12. The display block according to claim 11, wherein the light emitter comprises a quantum dot.

13. The display block according to claim 11, wherein at least two diffuse structures (52) contain different light emitters.

14. The display block according to claim 13, wherein each of the light-emitting diodes (LEDs) emits a first light radiation of a first wavelength, and wherein the diffuser structure (52) includes a first diffuser structure and a second diffuser structure, the first diffuser structure including a first emitter adapted to convert the first light radiation into a second light radiation of a second wavelength different from the first wavelength, and the second diffuser structure including a second emitter adapted to convert the first light radiation into a third light radiation of a third wavelength different from the first wavelength and the second wavelength.

15. The display block according to any one of claims 1 to 7, wherein the photoelectric circuit (26) comprises four display pixels (Pix).

16. The display block according to any one of claims 1 to 7, wherein the photoelectric circuit (26) comprises a single circuit (30) for controlling all light-emitting diodes (LEDs) of the display pixel (Pix).

17. A display screen (60) comprising a flat panel (140) and a plurality of display blocks (28) according to any one of claims 1 to 16 bonded to said flat panel.

18. The display screen according to claim 17, wherein the display pixels (Pix) of the display block (28) are arranged in rows and columns, and wherein the photoelectric circuit (26) of each display block includes at least four display pixels (Pix) belonging to at least two adjacent rows and at least two adjacent columns.

19. A method for manufacturing a display block (28) according to any one of claims 1 to 16, comprising the following steps: a) Forming a wafer (130) comprising a plurality of the aforementioned optoelectronic circuits (26); b) Cut the wafer to separate the optoelectronic circuit; as well as c) For each individual optoelectronic circuit, form the diffuse structure (52) covering the optoelectronic circuit (26).

20. The method of claim 19, further comprising: In step a), a first separation element (55) is formed in each photoelectric circuit (26) to separate the display pixel (Pix); And in step c), a second separating element (56) is formed to separate the diffuse structure and align with the first separating element.

21. A method of manufacturing a display screen (60) according to claim 17, comprising: The display block (28) is mounted on the flat plate (140).

Images