Chip password acquisition method, device, storage medium and computer equipment

Abstract

The present application provides a chip password acquisition method, device, storage medium and computer equipment, the method comprising: acquiring a target chip and a circuit diagram of the target chip; the target chip comprises a plurality of transistor groups; according to the circuit diagram, obtaining a target layer corresponding to an electrode node of each transistor group, performing a layer removal process on the target chip to expose the target layer; obtaining electrical parameters of each transistor group through the electrode nodes of each transistor group located in the target layer; obtaining character data corresponding to each transistor group according to the electrical parameters; obtaining the chip password of the target chip according to the character data. The present application can efficiently and accurately detect the chip password of the target chip.

Description

Technical Field

[0001] The present application relates to the technical field of chip password acquisition, and in particular to a chip password acquisition method, device and computer equipment. Background Art

[0002] Physical Unclonable Function (PUF) is a hardware information security technology that uses the inherent chip password to generate a unique device response to a given input that cannot be cloned, which can be used as a chip identifier. In the chip password acquisition method, the electrodes of the chip's transistors need to be made into pads with larger areas by circuit patching, so as to detect the electrical parameters of the transistors on the pads to obtain the chip password. However, during the circuit patching process, the deposited metal wires are prone to short circuit or open circuit of the metal wires on the chip. Therefore, the traditional chip password acquisition method has the technical defect of being unable to accurately obtain the chip password. Summary of the invention

[0003] The purpose of this application is to overcome the shortcomings and deficiencies in the prior art and to provide a chip password acquisition method, device and computer equipment that can avoid short circuits or open circuits and accurately acquire chip passwords.

[0004] A first aspect of an embodiment of the present application provides a chip password acquisition method, comprising:

[0005] Acquire a target chip and a circuit diagram of the target chip; the target chip includes a plurality of transistor groups;

[0006] According to the circuit diagram, the target layer corresponding to the electrode node of each transistor group is obtained, and the target chip is delayered to expose the target layer;

[0007] Acquiring electrical parameters of each transistor group through electrode nodes of each transistor group located in the target layer;

[0008] According to the electrical parameters, character data corresponding to each transistor group is obtained;

[0009] The chip password of the target chip is obtained according to the character data.

[0010] A second aspect of an embodiment of the present application provides a chip password acquisition device, comprising:

[0011] A target chip acquisition module, used to acquire a target chip and a circuit diagram of the target chip; the target chip includes a plurality of transistor groups;

[0012] A target layer exposure module, used to obtain the target layer corresponding to the electrode node of each transistor group according to the circuit diagram, and perform layer removal processing on the target chip to expose the target layer;

[0013] An electrical parameter detection module, used for acquiring electrical parameters of each transistor group through electrode nodes of each transistor group located in the target layer;

[0014] A transistor data acquisition module, used for obtaining character data corresponding to each transistor group according to the electrical parameters;

[0015] The chip password acquisition module is used to obtain the chip password of the target chip according to the character data.

[0016] A third aspect of an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the chip password acquisition method as described above are implemented.

[0017] The fourth aspect of an embodiment of the present application provides a computer device, including a storage device, a processor, and a computer program stored in the storage device and executable by the processor, wherein the processor implements the steps of the chip password acquisition method as described above when executing the computer program.

[0018] Compared with the related art, the present application can obtain the target layer corresponding to the electrode nodes of each transistor group of the target chip according to the circuit diagram of the target chip, and then de-layer the target chip to expose the target layer, and then obtain the electrical parameters of each transistor group and the character data obtained according to the electrical parameters through the electrode nodes of each transistor group located in the target layer, so as to obtain the chip secret of the target chip according to the character data, and can efficiently and accurately obtain the chip password of the target chip.

[0019] In order to provide a clearer understanding of the present application, the specific implementation of the present application will be described below in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 Schematic diagram of metal lines for circuit repair according to the prior art.

[0021] Figure 2 This is a flow chart of a chip password acquisition method according to an embodiment of the present application.

[0022] Figure 3 This is a schematic diagram of a chip password acquisition device according to an embodiment of the present application.

[0023] 1. Chip password acquisition device; 101. Target chip acquisition module; 102. Target layer exposure module; 103. Electrical parameter detection module; 104. Transistor data acquisition module; 105. Chip password acquisition module. DETAILED DESCRIPTION

[0024] In order to make the objectives, technical solutions and advantages of the present application more clear, the embodiments of the present application will be further described in detail below with reference to the accompanying drawings.

[0025] It should be clear that the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the embodiments of the present application.

[0026] When the following description relates to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. In the description of the present application, it should be understood that the terms "first", "second", "third", etc. are only used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence, nor can they be understood as indicating or implying relative importance. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to the specific circumstances. The singular forms of "a", "said" and "the" used in the present application and the appended claims are also intended to include the majority form, unless the context clearly indicates other meanings. The words "if" / "if" used herein can be interpreted as "at the time of" or "when" or "in response to determination".

[0027] In addition, in the description of this application, unless otherwise specified, "plurality" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the associated objects are in an "or" relationship.

[0028] See also Figure 1 , which is a chip password acquisition method provided by the first embodiment of the present application, comprising:

[0029] S1: Acquire a target chip and a circuit diagram of the target chip; the target chip includes a plurality of transistor groups.

[0030] A target chip is an integrated circuit that includes multiple groups of transistors. An integrated circuit can integrate analog and digital circuits on a single chip to make devices such as analog-to-digital converters and digital-to-analog converters. A target chip can provide a smaller size and lower cost.

[0031] After the target chip is manufactured, it needs to be packaged to prevent dust, moisture and radiation in the air from damaging the chip circuit. In addition, in order to ensure the normal use of the chip, the metal pins of the chip need to be pulled out during the packaging process. Since the chip is a tiny integrated short circuit, the distance between the metal pins needs to be maintained, and the chip needs to have good heat dissipation. Therefore, the target chip needs to be removed from the package before it can be de-layered to maintain the accuracy of the chip de-layering process.

[0032] S2: According to the circuit diagram, the target layer corresponding to the electrode node of each transistor group is obtained, and the target chip is delayered to expose the target layer.

[0033] The target layer refers to the chip layer where the electrode nodes of each transistor group are located. Therefore, the motor nodes of the same transistor group can correspond to different target layers, and one electrode node can also correspond to multiple target layers.

[0034] However, when there are many target layers corresponding to the electrode nodes of the same transistor group, too many target layers need to be exposed during layer removal, which increases the difficulty of layer removal. Therefore, in step S2, obtaining the target layer can also be achieved by the following steps:

[0035] S21: According to the circuit diagram, a plurality of node candidate layers where each electrode node of each transistor is located are obtained to obtain a first candidate layer set of each transistor;

[0036] S22: Obtain an intersection of first candidate layer sets of transistors of the same transistor group to obtain a second candidate layer set corresponding to the transistor group;

[0037] S23: From the second candidate layer set, determine the node candidate layer closest to the outside world as the target layer of the transistor group.

[0038] Through the above steps, the target layers corresponding to the electrode nodes of the same transistor group can be subjected to intersection processing to obtain the target layers with more electrode nodes corresponding to the transistor group, so as to reduce the difficulty of the de-layering process.

[0039] S3: Acquire electrical parameters of each transistor group through electrode nodes of each transistor group located in the target layer.

[0040] Among them, nanoprobes can be used to detect the electrical parameters of each transistor group. Specifically, a plurality of nanoprobes are used to simultaneously abut against the electrode nodes of the transistor group whose electrical parameters need to be detected, so as to obtain the electrical parameters of each transistor group.

[0041] Nanoprobe is a new type of ultra-microbial sensor that can detect single living cells. The probe size is only nanometers and can be used to measure the electrical parameters of connected transistors, such as the Vt of the transistor.

[0042] S4: Obtaining character data corresponding to each of the transistor groups according to the electrical parameters.

[0043] For example, a group of transistors includes 4 transistors, which are represented as PMOS1, NMOS1, PMOS2 and NMOS2. The electrical parameters of PMOS1, NMOS1, PMOS2 and NMOS2, such as the Vt of each transistor, can be measured in sequence by a nanoprobe, and then the character data corresponding to each transistor group can be determined according to the value of the Vt of each pair of transistors. Among them, the character data corresponding to each transistor group can adopt a binary counting method, that is, "1" and "0" are used as the character data corresponding to each transistor group. If the sum of the absolute values ​​of Vt of PMOS1 and NMOS1 is smaller than the sum of the absolute values ​​of Vt of PMOS2 and NMOS2, the character number corresponding to the group of transistors is determined to be "1"; if the sum of the absolute values ​​of Vt of PMOS1 and NMOS1 is larger than the sum of the absolute values ​​of Vt of PMOS2 and NMOS2, the character number corresponding to the group of transistors is determined to be "0". The character data of the group of transistors can be obtained.

[0044] S5: Obtaining the chip password of the target chip according to the character data.

[0045] The character data corresponding to each transistor group is sorted according to a preset sequence to obtain the chip password of the target chip.

[0046] Compared with the related art, the present application can obtain the target layer corresponding to the electrode nodes of each transistor group of the target chip according to the circuit diagram of the target chip, and then de-layer the target chip to expose the target layer, and then obtain the electrical parameters of each transistor group and the character data obtained according to the electrical parameters through the electrode nodes of each transistor group located in the target layer, so as to obtain the chip secret of the target chip according to the character data, and can efficiently and accurately obtain the chip password of the target chip.

[0047] In a feasible embodiment, the step of S3: performing a layer removal process on the target chip to expose the target layer includes:

[0048] The target chip is subjected to mechanical grinding to expose the target layer, thereby exposing electrode nodes of multiple pairs of transistors of the target chip.

[0049] Among them, mechanical grinding can achieve a large area of ​​observation range, and the steps of mechanical masking can include four steps: mechanical cutting, cold burying, grinding, and polishing.

[0050] In this embodiment, through mechanical grinding, multiple groups of transistors of the chip can be exposed from the through-hole layer, so that it is convenient for users to detect the electrical parameters of each transistor group.

[0051] In a feasible embodiment, the step of S3: performing a layer removal process on the target chip to expose the target layer includes:

[0052] The target chip is subjected to plasma focused ion beam microscopy analysis to expose the target layer, thereby exposing electrode nodes of multiple pairs of transistors of the target chip.

[0053] Among them, for 3D-IC semiconductor process technology, if you do not want to destroy the entire chip by grinding, you can consider using plasma focused ion beam microscopy (Plasma FIB, abbreviated as PFIB) analysis techniques, which combines plasma ion etching processing and SEM observation functions. It is suitable for analysis within a distance of 50-500um, and can perform cross-sectional analysis, de-layering observation, and electrical testing. Even for specific areas, it can also be cut and observed and electrical testing can be performed simultaneously. There is no need to worry about accidentally damaging the target area due to blind cutting, ensuring the integrity of abnormal or specific observation structures.

[0054] In this embodiment, plasma focused ion beam microscopy analysis can be performed to reduce damage to the integrity of the chip, thereby facilitating users to more accurately detect the electrical parameters of each transistor group exposed in the through-hole layer.

[0055] In a feasible embodiment, the electrical property includes a voltage parameter; the transistor group includes a first PMOS transistor, a first NMOS transistor, a second PMOS transistor and a second NMOS; the step S4: obtaining character data corresponding to each transistor group according to the electrical property parameter includes:

[0056] S41: If the sum of the absolute value of the voltage parameter of the first PMOS tube and the absolute value of the voltage parameter of the first NMOS tube is greater than the sum of the absolute value of the voltage parameter of the second PMOS tube and the absolute value of the voltage parameter of the second NMOS tube, it is determined that the first character is the character data corresponding to the transistor group.

[0057] S42: If the sum of the absolute value of the voltage parameter of the first PMOS tube and the absolute value of the voltage parameter of the first NMOS tube is less than the sum of the absolute value of the voltage parameter of the second PMOS tube and the absolute value of the voltage parameter of the second NMOS tube, determine that the second character is the character data corresponding to the transistor group.

[0058] In this embodiment, the character data corresponding to the transistor group can be determined based on the sum of the absolute value of the voltage parameter of the first PMOS tube and the absolute value of the voltage parameter of the first NMOS tube, and the absolute value of the voltage parameter of the second PMOS tube and the absolute value of the voltage parameter of the second NMOS tube, thereby accurately obtaining the character data.

[0059] In a feasible embodiment, the step of obtaining the chip password of the target chip according to the character data corresponding to each transistor group in S5 includes:

[0060] S51: Determine the arrangement order of the circuit sequences of the transistor groups.

[0061] Among them, the circuit order of each transistor group can be a preset order or the order when each transistor group is activated in the circuit, for example, the order of the transistor individuals that are first activated in the circuit of each transistor group, or the average order of the transistor individuals that are first activated in the circuit of each transistor group.

[0062] S52: Arrange the character data according to the arrangement order to obtain the chip password of the target chip.

[0063] By arranging the character data, the chip password of the target chip can be obtained.

[0064] In this embodiment, the character data may be arranged in a circuit sequence of transistor groups to accurately obtain the chip password of the target chip.

[0065] In a feasible embodiment, after the step of arranging the character data according to the arrangement order to obtain the chip password of the target chip in S5, the method further includes:

[0066] The chip password is stored according to the chip type and the detection time of the target chip, so as to store the chip passwords corresponding to different chip types and detection times.

[0067] Among them, the chip password is stored according to the chip type and detection time, which is conducive to the reasonable storage of the chip password and convenient for the user to find the chip password according to the chip type or detection time, thereby finding the chip password of the corresponding chip type and / or detection time, thereby improving the efficiency of the user in finding the chip password.

[0068] See also Figure 3 The second embodiment of the present application provides a chip password acquisition device 1, comprising:

[0069] A target chip acquisition module 101 is used to acquire a target chip and a circuit diagram of the target chip; the target chip includes a plurality of transistor groups;

[0070] A target layer exposing module 102 is used to obtain the target layer corresponding to the electrode node of each transistor group according to the circuit diagram, and perform layer removal processing on the target chip to expose the target layer;

[0071] An electrical parameter detection module 103, configured to obtain electrical parameters of each transistor group through electrode nodes of each transistor group located in the target layer;

[0072] A transistor data acquisition module 104, used for acquiring character data corresponding to each transistor group according to the electrical parameters;

[0073] The chip password acquisition module 105 is used to obtain the chip password of the target chip according to the character data.

[0074] It should be noted that the chip password acquisition device 1 provided in the second embodiment of the present application only uses the division of the above-mentioned functional modules as an example when executing the chip password acquisition method. In actual applications, the above-mentioned functions can be assigned to different functional modules as needed, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above. In addition, the chip password acquisition device 1 provided in the second embodiment of the present application and the chip password acquisition method of the first embodiment of the present application belong to the same concept. The implementation process thereof is detailed in the method embodiment and will not be repeated here.

[0075] A third aspect of an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the chip password acquisition method as described above are implemented.

[0076] The fourth aspect of an embodiment of the present application provides a computer device, including a storage device, a processor, and a computer program stored in the storage device and executable by the processor, wherein the processor implements the steps of the chip password acquisition method as described above when executing the computer program.

[0077] The device embodiments described above are merely illustrative, wherein the components described as separate parts may or may not be physically separated, and the parts displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the present application. Ordinary technicians in this field can understand and implement it without creative work.

[0078] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that include computer-usable program code.

[0079] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 These computer program instructions can also be stored in a computer-readable memory that can guide a computer or other programmable data processing device to work in a specific way, so that the instructions stored in the computer-readable memory produce a product including an instruction device, which implements the function selected in the process. Figure 1 A process or multiple processes and / or boxes Figure 1 function selected in a box or multiple boxes.

[0080] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 steps for the function selected in a box or multiple boxes.

[0081] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0082] The memory may include non-permanent memory in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM. The memory is an example of a computer-readable medium.

[0083] Computer readable media include permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. Information can be computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include temporary computer readable media (transitory media), such as modulated data signals and carrier waves.

[0084] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0085] The above are only embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included within the scope of the claims of the present application.

Claims

1. A chip password acquisition method, characterized in that: include: Acquire a target chip and a circuit diagram of the target chip; the target chip includes a plurality of transistor groups; According to the circuit diagram, the target layer corresponding to the electrode node of each transistor group is obtained, and the target chip is delayered to expose the target layer; Acquiring electrical parameters of each transistor group through electrode nodes of each transistor group located in the target layer; According to the electrical parameters, character data corresponding to each transistor group is obtained; wherein the transistor group includes a plurality of transistors, and the character data corresponding to the transistor group is obtained according to the size of the electrical parameters of the plurality of transistors in the same transistor group; The character data is sorted according to a preset sequence to obtain the chip password of the target chip.

2. The chip password acquisition method according to claim 1, characterized in that: The transistor group includes a plurality of transistors; the step of obtaining the target layer corresponding to the electrode node of each transistor group according to the circuit diagram includes: According to the circuit diagram, a plurality of node candidate layers where each electrode node of each transistor is located are obtained to obtain a first candidate layer set of each transistor; Obtaining the intersection of the first candidate layer sets of the transistors of the same transistor group to obtain a second candidate layer set corresponding to the transistor group; From the second candidate layer set, a node candidate layer closest to the outside world is determined as a target layer of the transistor group.

3. The chip password acquisition method according to claim 1, characterized in that: The step of sorting the character data according to a preset order to obtain the chip password of the target chip includes: Determining the circuit sequence of each of the transistor groups as an arrangement sequence; The character data is arranged according to the arrangement order to obtain the chip password of the target chip.

4. The chip password acquisition method according to claim 3, characterized in that: After the step of arranging the character data according to the arrangement order to obtain the chip password of the target chip, the method further includes: The chip password is stored according to the chip type and the detection time of the target chip, so as to store the chip passwords corresponding to different chip types and detection times.

5. The chip password acquisition method according to claim 1, characterized in that: The electrical parameter includes a voltage parameter; the transistor group includes a first PMOS transistor, a first NMOS transistor, a second PMOS transistor and a second NMOS transistor; the step of obtaining character data corresponding to each of the transistor groups according to the electrical parameter includes: If the sum of the absolute value of the voltage parameter of the first PMOS tube and the absolute value of the voltage parameter of the first NMOS tube is greater than the sum of the absolute value of the voltage parameter of the second PMOS tube and the absolute value of the voltage parameter of the second NMOS tube, it is determined that the first character is the character data corresponding to the transistor group; If the sum of the absolute value of the voltage parameter of the first PMOS tube and the absolute value of the voltage parameter of the first NMOS tube is less than the sum of the absolute value of the voltage parameter of the second PMOS tube and the absolute value of the voltage parameter of the second NMOS tube, it is determined that the second character is the character data corresponding to the transistor group.

6. The chip password acquisition method according to any one of claims 1 to 5, characterized in that: The step of performing a layer removal process on the target chip to expose the target layer comprises: The target chip is subjected to mechanical grinding to expose the target layer, thereby exposing electrode nodes of multiple pairs of transistors of the target chip.

7. The chip password acquisition method according to any one of claims 1 to 5, characterized in that: The step of performing a layer removal process on the target chip to expose the target layer comprises: The target chip is subjected to plasma focused ion beam microscopy analysis to expose the target layer, thereby exposing electrode nodes of multiple pairs of transistors of the target chip.

8. A chip password acquisition device, characterized in that: include: A target chip acquisition module, used to acquire a target chip and a circuit diagram of the target chip; the target chip includes a plurality of transistor groups; A target layer exposure module, used to obtain the target layer corresponding to the electrode node of each transistor group according to the circuit diagram, and perform layer removal processing on the target chip to expose the target layer; An electrical parameter detection module, used for acquiring electrical parameters of each transistor group through electrode nodes of each transistor group located in the target layer; A transistor data acquisition module, used to obtain character data corresponding to each transistor group according to the electrical parameters; wherein the transistor group includes a plurality of transistors, and the character data corresponding to the transistor group is obtained according to the size of the electrical parameters of the plurality of transistors in the same transistor group; The chip password acquisition module is used to sort the character data according to a preset sequence to obtain the chip password of the target chip.

9. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the steps of the chip password acquisition method as described in any one of claims 1 to 7 are implemented.

10. A computer device, characterized in that: The device comprises a memory, a processor and a computer program stored in the memory and executable by the processor, wherein the processor implements the steps of the chip password acquisition method as described in any one of claims 1 to 7 when executing the computer program.

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