An in-memory computing method and chip design

Abstract

The present application discloses an in-memory computing method and chip design, wherein the method includes: storing input values ​​into an input buffer module, storing weight values ​​into a static random access memory array; reading out input values ​​and weight values ​​and transmitting them into a multiplier module; in the multiplier module, obtaining the multiplication and accumulation results of the input values ​​and weight values ​​through an XOR logic operation; in the adder tree module, performing addition calculations on the multiplication and accumulation results; in the shift accumulation module, accumulating the calculation results of the adder tree module in multiple cycles with the results of adding the corresponding bias values, and obtaining output data. The present application adopts a data flow reconfigurable solution. At the architectural level, different in-memory computing cores can better schedule resources, solve computing problems of different precisions, and greatly reduce the power consumption, area and other overheads of digital memory computing chips.

Description

Technical Field

[0001] The present application belongs to the field of data processing technology, and in particular, relates to an in-memory computing method and chip design. Background Art

[0002] In recent years, the fields of big data, big models, VR / AR, autonomous driving, AIoT, etc. have developed vigorously, and the problems of insufficient computing power and high power consumption of traditional architecture chips need to be solved urgently. Storage and computing chips have advantages such as high bandwidth, low power consumption, and high energy efficiency. Compared with traditional chips using von Neumann structure, their structure is inherently suitable for deep learning tasks such as convolution calculations and large-scale multiplication and addition operations. Nowadays, with the development of fields such as neural networks, various AI application scenarios have further increased their requirements for storage and computing chips (for example, cloud-based deep learning requires high computing power and high precision). Digital storage and computing chips are superior to analog storage and computing chips in such application scenarios because of their higher and wider precision, high energy efficiency, high reliability, and mature technology.

[0003] This application is designed as a reconfigurable digital storage and computing chip rather than a reconfigurable analog storage and computing chip, which can improve its accuracy and energy efficiency on the basis of flexibility, achieving a balance of the three; currently similar implementation schemes include:

[0004] 1. A reconfigurable digital in-memory computing core with variable weight and input bit precision from 1 to 16 bits proposed by Hyunjoon Kim's team at Nanyang Technological University in 2019. The disadvantage is that its multiplier module uses a traditional multiplier, which has low efficiency, large area, and high power consumption;

[0005] 2. A scalable and reconfigurable digital in-memory computing core array designed by Naveen Verma's team at Princeton University in 2021. The disadvantage is that its reconfigurable mode is relatively complex and difficult to implement, and it uses four in-memory computing cores as a unit to establish a reconfigurable mode, which is not flexible enough; the way it implements multiplication and accumulation operations is the traditional way, which has low energy efficiency and large area;

[0006] 3. A type of XOR multiplication in the BNN (Binary Neural Network) network. Its disadvantage is that it can only support 1bit×1bit calculation and cannot be extended to multi-precision calculation. Summary of the invention

[0007] In order to solve the deficiencies in the prior art, the present application proposes an in-memory computing method and chip design.

[0008] In a first aspect, an in-memory computing method is proposed, which is implemented in an in-memory computing core, wherein the in-memory computing core includes: a static random access memory array, a multiplier module, an adder tree module, and a shift-accumulate module; the method includes:

[0009] Storing input values ​​into an input buffer module and storing weight values ​​into a static random access memory array;

[0010] Read out the input value and weight value and transmit them into the multiplier module;

[0011] In the multiplier module, the multiplication and accumulation result of the input value and the weight value is obtained through the XOR logic operation;

[0012] In the adder tree module, the multiplication and accumulation results are added;

[0013] In the shift-accumulate module, the calculation results of the adder tree module in multiple cycles are respectively accumulated with the results of adding the corresponding offset values ​​to obtain output data.

[0014] In a preferred embodiment of the present application, the steps of the XOR logic operation include:

[0015] Step S3.1: Determine whether the input value is 1 bit. If so, execute step S3.2.A. If not, go to step S3.2.B.

[0016] Step S3.2.A: Determine whether the weight value is 1, if so, execute step S3.3.A, if not, go to step S3.3.C;

[0017] Step S3.2.B: Determine whether the weight value is 1, if so, execute step S3.3.B, if not, go to step S3.3.C;

[0018] Step S3.3.A: Perform a multiplication and accumulation operation of the 1-bit input value and the 1-bit weight value;

[0019] Step S3.3.B: Perform multiplication and accumulation operations on the multi-bit input value and the 1-bit weight value;

[0020] Step S3.3.C: Perform multiplication and accumulation operations on the 1-bit input value and the multi-bit weight value;

[0021] Step S3.3.D: Perform multiplication and accumulation operations on the multi-bit input value and the multi-bit weight value.

[0022] In a preferred embodiment of the present application, the multiplication and accumulation operation of the 1-bit input value and the 1-bit weight value is specifically as follows: use the mapping value 1 to represent the input value -1 and the weight value -1 respectively, and the mapping value 0 to represent the input value +1 and the weight value +1 respectively, and perform an XOR logic operation on the mapping value of the input value and the mapping value of the weight value to obtain a first multiplication and accumulation result.

[0023] In a preferred embodiment of the present application, the multiplication and accumulation operation of the multi-bit input value and the 1-bit weight value is specifically: performing a bitwise exclusive OR logic operation on the input value and the weight value to obtain a second multiplication and accumulation result, and the input value is input in the form of a complement code.

[0024] In a preferred embodiment of the present application, the multiplication and accumulation operation of the 1-bit input value and the multi-bit weight value is specifically: performing a bitwise XOR logical operation on the input value and the weight value to obtain a second multiplication and accumulation result, and the weight value is input in the form of a complement code.

[0025] In a preferred embodiment of the present application, the multiplication and accumulation operation of the multi-bit input value and the multi-bit weight value includes:

[0026] The input value is input in the form of complement, using mapping value 1 to represent weight value -1, and mapping value 0 to represent weight value +1;

[0027] The different digits of the weight value are assigned a power of 2 weight, each weight value is replaced by the mapping value, and then a bitwise XOR logic operation is performed with the input value to obtain the third multiplication and accumulation result.

[0028] In a second aspect, a chip design is proposed, including: a plurality of cores; the cores include: a binarization module, a reshaping module, a CIM core array, an integration module, a single process processing module, and a serial processing module;

[0029] Binarization module: used to binarize the data transferred from the global buffer to the in-memory computing core;

[0030] Reshape module: used to rearrange the binary data;

[0031] CIM core array: composed of in-memory computing cores, wherein the in-memory computing cores use the in-memory computing method described in the first aspect to calculate the rearranged data;

[0032] Integration module: used to integrate the data results calculated by the CIM core array;

[0033] Single-process processing module: used for parallel processing of integration results;

[0034] Serial processing module: used to perform serial processing on the parallel processing results;

[0035] Among them, the binarization module, the reshaping module, the CIM core array, the integration module, the single-process processing module and the serial processing module are connected in sequence.

[0036] The beneficial effects brought about by the technical solutions provided by some embodiments of the present application include at least:

[0037] (1) This application constructs a set of multiplication-accumulation calculation paradigms based on different mapping schemes and using XOR logic operations instead of multiplication; this paradigm can solve many problems of traditional multipliers. This application only requires 10 transistors for a multiplier, which greatly reduces the area overhead of the circuit and improves the calculation efficiency;

[0038] (2) The chip design of this application is more flexible and versatile, using resource scheduling between 16, 32 or even more in-memory computing cores, and can support operations with weight input bit precision as high as 8-bit and 16-bit;

[0039] (3) This application deploys a complete computing paradigm to storage and computing chips, which can realize operations of arbitrary bit precision based on chip resources and support the deployment and application of more neural network model reasoning.

[0040] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or understood by practicing the present application. The purpose and other advantages of the present application are realized and obtained by the structures specifically pointed out in the description, claims and drawings.

[0041] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, preferred embodiments are specifically cited below and described in detail with reference to the attached drawings.

[0042] Advantages of additional aspects of the present application will be given in part in the following description, and in part will become apparent from the following description, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments of the present application or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0044] Figure 1 This is a diagram of the in-memory computing core structure shown in an embodiment of the present application;

[0045] Figure 2 A flowchart of the in-memory computing method shown in an embodiment of the present application;

[0046] Figure 3 A flowchart of the XOR logic operation steps shown in an embodiment of the present application;

[0047] Figure 4 This is an example diagram of the multiplication and accumulation operation of a 1-bit input value and a 1-bit weight value shown in an embodiment of the present application;

[0048] Figure 5 This is an example diagram of the multiplication and accumulation operation of a 4-bit input value and a 1-bit weight value shown in the embodiment of the present application;

[0049] Figure 6 This is an example diagram of the multiplication and accumulation operation of a 1-bit input value and a 4-bit weight value shown in an embodiment of the present application;

[0050] Figure 7 This is an example diagram of the multiplication and accumulation operation of a 4-bit input value and a 4-bit weight value shown in the embodiment of the present application;

[0051] Figure 8 This is a design diagram of the storage and computing chip shown in the embodiment of this application. DETAILED DESCRIPTION

[0052] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that the disclosure will be more comprehensive and complete and to fully convey the concepts of the example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0053] In addition, the accompanying drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the figures represent the same or similar parts, and their repeated description will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software form, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and / or processor devices and / or microcontroller devices.

[0054] In-memory computing: The principle of data operation in the kernel, such as Figure 1 As shown, in this in-memory computing core, the data processing flow is as follows: (1) The input value is stored in the input buffer (Input Buffer), and the weight value is stored in the SRAM (Static Random-Access Memory) array; (2) The input value and weight value are read out from the Input Buffer and the SRAM array respectively, and transmitted to the multiplier module; (3) The result obtained by XOR multiplication in the multiplier module is transmitted to the adder tree module, and the adder tree module performs addition calculation on the multiplication and accumulation results. (4) The calculation result of the adder tree module enters the shift accumulation module, and the shift accumulation module shifts and accumulates the results of several cycles respectively, and finally obtains the output data.

[0055] This application adopts a data flow reconfigurable solution. At the architectural level, the in-memory computing core array can be arbitrarily composed of any number of in-memory computing core units. Different in-memory computing cores can better schedule resources to solve computing problems of different precisions, greatly reducing the power consumption, area and other overheads of digital storage computing chips.

[0056] Combine the following Figure 2 to Figure 8 The in-memory computing method and chip design provided in this application are further described.

[0057] Embodiment 1

[0058] This application proposes an in-memory computing method, which is implemented in an in-memory computing core, such as Figure 2 As shown, the following steps are included:

[0059] Step S1: storing the input value into the input buffer module and storing the weight value into the static random access memory array;

[0060] Step S2: read out the input value and weight value and transmit them into the multiplier module;

[0061] Step S3: In the multiplier module, the multiplication and accumulation result of the input value and the weight value is obtained by an XOR logic operation;

[0062] Specifically in this embodiment, the XOR logic operation is as follows: Figure 3 As shown, the following steps are included:

[0063] Step S3.1: Determine whether the input value is 1 bit. If so, execute step S3.2.A. If not, go to step S3.2.B.

[0064] Step S3.2.A: Determine whether the weight value is 1, if so, execute step S3.3.A, if not, go to step S3.3.C;

[0065] Step S3.2.B: Determine whether the weight value is 1, if so, execute step S3.3.B, if not, go to step S3.3.D;

[0066] Step S3.3.A: Perform a multiplication and accumulation operation of the 1-bit input value and the 1-bit weight value;

[0067] In a specific implementation process, a mapping value of 1 is used to represent an input value of -1 and a weight value of -1, and a mapping value of 0 is used to represent an input value of +1 and a weight value of +1, and an XOR logic operation is performed on the mapping value of the input value and the mapping value of the weight value to obtain a first multiplication-accumulation result;

[0068] Step S3.3.B: Perform multiplication and accumulation operations on the multi-bit input value and the 1-bit weight value;

[0069] In a specific implementation process, a bitwise XOR logic operation is performed on the input value and the weight value to obtain a second multiplication-accumulation result, and the input value is input in the form of a complement code;

[0070] Step S3.3.C: Perform multiplication and accumulation operations on the 1-bit input value and the multi-bit weight value;

[0071] In a specific implementation process, a bitwise XOR logic operation is performed on the input value and the weight value to obtain a second multiplication-accumulation result, and the weight value is input in the form of a complement code;

[0072] Step S3.3.D: performing a multiplication and accumulation operation of the multi-bit input value and the multi-bit weight value;

[0073] In the specific implementation process, the input value is input in the form of complement, using the mapping value 1 to represent the weight value -1, and the mapping value 0 to represent the weight value +1;

[0074] The different digits of the weight value are assigned a power of 2 weight, each weight value is replaced by the mapping value, and then a bitwise XOR logic operation is performed with the input value to obtain the third multiplication and accumulation result.

[0075] Step S4: in the adder tree module, performing addition calculation on the multiplication and accumulation results;

[0076] Step S5: In the shift accumulation module, the calculation results of the adder tree modules in multiple cycles are accumulated with the results of adding the corresponding offset values ​​to obtain output data.

[0077] Specifically in this embodiment, the bias value is determined according to the number of 1s, and this number of 1s can be obtained outside the chip, that is, the bias value is obtained from external input like the input and weight;

[0078] Specifically, the number of 1s is determined through software layer training; the training results are as follows:

[0079] For the multiplication and accumulation operation of a 1-bit input value and a 1-bit weight value, the bias value is 0.

[0080] For the multiplication and accumulation operation of the input value represented by the multi-bit complement code and the 1-bit weight value, the bias value is the number of times the mapping value of the weight value is 1.

[0081] For the multiplication and accumulation operation of the input value represented by the multi-bit complement code and the multi-bit weight value, the bias value is 1 multiplied by the power of 2 of the bit where the weight value with the mapping value of 1 is located.

[0082] In order to more clearly illustrate the technical solution of the in-memory computing method, a specific chip example is given below:

[0083] This example chip uses a specific mapping method combined with XOR logic operation, and uses the bias value at the statistical training level to accelerate the result operation. In this example, the XOR logic operation is classified into three operation modes, namely, 1-bit input value and 1-bit weight value multiplication and accumulation, multi-bit input value and 1-bit weight value multiplication and accumulation, 1-bit input value and multi-bit weight value multiplication and accumulation, multi-bit input value and multi-bit weight value multiplication and accumulation; the specific design of the multiplier module in this example chip is as follows:

[0084] a. For the multiplication and accumulation operation of 1-bit input value and 1-bit weight value, such as Figure 4 As shown, the mapping value 1 is used to represent the input value -1 and the weight value -1, and the mapping value 0 is used to represent the input value +1 and the weight value +1. After such mapping, the multiplication operation can be replaced by the XOR logic operation, and the results are all accurate results. There is no need to add bias, and the multiplication and accumulation results can be directly accumulated. At the hardware level, the circuit power consumption and area overhead caused by the XOR gate are much smaller than those of the multiplier, while greatly improving the computing efficiency.

[0085] b. For the multi-bit complement representation of the input value and the 1-bit weight value multiplication and accumulation operation (such as Figure 5 As shown in the figure, taking 4bit×1bit as an example), the mapping value 1 is used to represent the weight value -1, and the mapping value 0 is used to represent the weight value +1. After such mapping, the 4-bit complement input value and the mapping value of the 1-bit weight value are bitwise XORed to obtain the first step result. At this time, if the mapping value of the 1-bit weight value is 1, the calculated multiplication result is 1 less than the actual multiplication result. Therefore, during training, the number of times the mapping value of the weight value is 1 is counted, and this number is used as a bias and added to the first step result to obtain an accurate multiplication-accumulation result. At the hardware level, compared with the method mentioned in Solution 2 in the technical background, this method has a greatly reduced area overhead. At the same time, counting the number of 1s during training also further reduces the circuit overhead.

[0086] c. For the multiplication and accumulation operation of 1-bit input value and multi-bit complement code weight value (such as Figure 6 As shown in the figure, taking 1bit×4bit as an example), the mapping value 1 is used to represent the input value -1, and the mapping value 0 is used to represent the input value +1. After mapping, the mapping value of the 1-bit input value and the 4-bit complement weight value are bitwise XORed to obtain the first step result. At this time, if the mapping value of the 1-bit input value is 1, the calculated multiplication result is 1 less than the actual multiplication result. Therefore, during training, the number of times the mapping value of the input value is 1 is counted, and this number is used as a bias and added to the first step result to obtain an accurate multiplication-accumulation result. At the hardware level, compared with the method mentioned in Solution 2 in the technical background, this method has a greatly reduced area overhead. At the same time, counting the number of 1s during training also further reduces the circuit overhead.

[0087] d. For the multi-bit complement code input value and the multi-bit weight value multi-accumulation operation (such as Figure 7 As shown, taking 4bit×4bit as an example), the mapping value 1 represents the weight value -1, and the mapping value 0 represents the weight value +1;

[0088] Furthermore, the different digits of the weight value are assigned a power of 2 weight, each weight value is replaced by the mapping value, and then multiplied with the input value to obtain the result of the first step;

[0089] Furthermore, the number of digits whose weight value is 1 after the mapping is completed is counted, and the weight of the digit raised to the power of 2 is multiplied by 1 as a bias and added to the result of the first step to obtain an accurate multiplication-accumulation result.

[0090] This example chip achieves better resource scheduling between different in-memory computing cores, solves computing problems of different precisions, and greatly reduces the power consumption, area and other overheads of digital memory computing chips.

[0091] The advantages of this embodiment over the prior art are mainly as follows:

[0092] 1. Scheme 1 uses a traditional multiplier, which has low efficiency, large area and high power consumption. This application constructs a set of multiplication and accumulation calculation paradigms based on different mapping schemes and replaces multiplication with XOR logic operations. This paradigm can solve many problems of traditional multipliers. An XOR multiplier only needs 10 transistors, which greatly reduces the area overhead of the circuit and improves the calculation efficiency.

[0093] 2. The reconfigurable mode of Scheme 2 is relatively complex and difficult to implement. In addition, it uses 4 in-memory computing cores as a unit to establish a reconfigurable mode, which is not flexible enough. The way it implements multiplication and accumulation operations is the traditional way, which has low energy efficiency and large area. The in-memory computing core of this application freely selects array component units by controlling the data flow path scheme, and the design is more flexible and more universal. It uses 16, 32 or even more in-memory computing cores for resource scheduling, and can support operations with weight input bit precision as high as 8 bits and 16 bits.

[0094] 3. The XOR logic operation of Scheme 3 only supports 1-bit × 1-bit calculation and cannot be extended to multi-bit calculation; the XOR gate is a choice combined with a series of mapping schemes and calculation modes. This application realizes multi-bit expansion through XOR calculation logic, constructs a new computing paradigm and completes the design of a reconfigurable digital storage and computing chip that can achieve multi-precision; the complete computing paradigm is deployed to the storage and computing chip, and arbitrary bit precision calculations can be achieved based on the resources on the chip, supporting the deployment and application of more neural network model reasoning.

[0095] Embodiment 2

[0096] This application proposes a chip design, such as Figure 8 As shown; comprising: multiple cores; the cores include: a binarization module, a reshaping module, a CIM core array, an integration module, a single-process processing module and a serial processing module.

[0097] Binarization module: used to binarize the data transferred from the global buffer to the in-memory computing core;

[0098] Specifically, the value input from the global buffer to the in-memory computing core is quantized to the corresponding number of bits according to the requirements of the neural network; for example, an 8-bit number can be quantized to "0" or "1" based on 127 as the boundary;

[0099] Reshape module: used to rearrange the binary data;

[0100] Specifically, they are arranged in a convolutional form (3×3) to facilitate entering the in-memory computing kernel array for convolution (i.e., multiplication and accumulation) calculations;

[0101] CIM (compute-in-memory) core array: composed of in-memory computing cores, wherein the in-memory computing cores use the in-memory computing method described in Example 1 to calculate the rearranged data;

[0102] Specifically, in the in-memory computing core is an SRAM array, usually with a large number of SRAM arrays (64*64, 256*16, etc.), which is a storage array, also called a storage cell array;

[0103] Integration module: used to integrate the data results calculated by the CIM core array;

[0104] Specifically, since a single in-memory computing core can process limited data, it is necessary to integrate the data before outputting the results;

[0105] Single-process processing module: used for parallel processing of integration results (such as adding bias, etc.);

[0106] Serial processing module: used to perform serial processing on parallel processing results (such as serial addition, etc.);

[0107] Among them, the binarization module, the reshaping module, the CIM core array, the integration module, the single-process processing module and the serial processing module are connected in sequence.

[0108] The data processing flow is:

[0109] (1) External input values ​​first enter multiple cores through the global buffer, such as core 1, core 2, core 3, and core n. The data flow path is adjusted according to external demand, and the resource allocation and scheduling between the cores are reconstructed.

[0110] (2) Each core performs data binarization, reshaping, CIM core array, integration, parallel processing, and serial processing steps through a binarization module, a reshaping module, a CIM core array, an integration module, a single process processing module, and a serial processing module.

[0111] (3) The data after kernel processing is transferred back to the global buffer for further processing.

[0112] Compared with the prior art, the beneficial effects of this embodiment are:

[0113] Through the chip design of this embodiment, the in-memory computing core in the CIM core array adopts the in-memory computing method described in Example 1, and the same beneficial effects as Example 1 are achieved. In addition, this embodiment also supports multiple neural network formats (for example, after binarization, it can support the deployment of BNN), and neural networks of other precisions are just quantized to the corresponding precision.

[0114] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any modification, use or adaptation of the present disclosure, which follows the general principles of the present disclosure and includes common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present disclosure are indicated by the appended claims.

Claims

1. An in-memory computing method implemented in an in-memory computing core, the in-memory computing core comprising: A static random access memory array, a multiplier module, an adder tree module and a shift-accumulate module; characterized in that it comprises: Storing input values ​​into an input buffer module and storing weight values ​​into a static random access memory array; Read out the input value and weight value and transmit them into the multiplier module; In the multiplier module, the multiplication and accumulation result of the input value and the weight value is obtained through the XOR logic operation; In the adder tree module, the multiplication and accumulation results are added; In the shift accumulation module, the calculation results of the adder tree module in multiple cycles are respectively accumulated with the results of adding the corresponding offset values ​​to obtain output data; The steps of the XOR logic operation include: Step S3.1: Determine whether the input value is 1 bit. If so, execute step S3.2.A. If not, go to step S3.2.B. Step S3.2.A: Determine whether the weight value is 1, if so, execute step S3.3.A, if not, go to step S3.3.C; Step S3.2.B: Determine whether the weight value is 1, if so, execute step S3.3.B, if not, go to step S3.3.C; Step S3.3.A: Perform a multiplication and accumulation operation of the 1-bit input value and the 1-bit weight value; Step S3.3.B: Perform multiplication and accumulation operations on the multi-bit input value and the 1-bit weight value; Step S3.3.C: Perform multiplication and accumulation operations on the 1-bit input value and the multi-bit weight value; Step S3.3.D: Perform multiplication and accumulation operations on the multi-bit input value and the multi-bit weight value.

2. The in-memory computing method according to claim 1, characterized in that: The multiplication and accumulation operation of the 1-bit input value and the 1-bit weight value is specifically: Use mapping value 1 to represent input value -1 and weight value -1, and use mapping value 0 to represent input value +1 and weight value +1, and perform XOR logic operation on the mapping value of the input value and the mapping value of the weight value to obtain the first multiplication and accumulation result.

3. The in-memory computing method according to claim 1, characterized in that: The multiplication and accumulation operation of the multi-bit input value and the 1-bit weight value is specifically: A bitwise exclusive OR logic operation is performed on the input value and the weight value to obtain a second multiplication-accumulation result, wherein the input value is input in the form of a complement code.

4. The in-memory computing method according to claim 1, characterized in that: The multiplication and accumulation operation of the 1-bit input value and the multi-bit weight value is specifically: A bitwise exclusive OR logic operation is performed on the input value and the weight value to obtain a second multiplication-accumulation result, and the weight value is input in the form of a complement code.

5. The in-memory computing method according to claim 1, characterized in that: The multiplication and accumulation operation of the multi-bit input value and the multi-bit weight value includes: The input value is input in the form of complement, using mapping value 1 to represent weight value -1, and mapping value 0 to represent weight value +1; The different digits of the weight value are assigned a power of 2 weight, each weight value is replaced by the mapping value, and then a bitwise XOR logic operation is performed with the input value to obtain the third multiplication and accumulation result.

6. A chip design, characterized in that: include: Multiple cores; The core includes: a binarization module, a reshaping module, a CIM core array, an integration module, a single process processing module and a serial processing module; Binarization module: used to binarize the data transferred from the global buffer to the in-memory computing core; Reshape module: used to rearrange the binary data; CIM core array: composed of in-memory computing cores, wherein the in-memory computing cores use the in-memory computing method described in any one of claims 1 to 5 to calculate the rearranged data; Integration module: used to integrate the data results calculated by the CIM core array; Single-process processing module: used for parallel processing of integration results; Serial processing module: used to perform serial processing on parallel processing results.

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