A super AB class transconductance amplifier

Abstract

This invention discloses a super AB-class transconductance amplifier, relating to the field of amplifier circuits. The circuit includes: an input stage circuit module, an adaptive bias circuit module, a local common-mode feedback circuit module, and an output stage circuit module. The adaptive bias circuit module, the local common-mode feedback circuit module, and the output stage circuit module are all connected to the input stage circuit module. The input stage circuit module receives the input signal. The adaptive bias circuit module provides an adaptive bias current based on the input signal. The local common-mode feedback circuit module performs rate and gain conversion on the input signal and the bias current to obtain converted data. The output stage circuit module outputs the converted data. This invention improves the amplifier's gain, bandwidth, and stability.

Description

Technical Field

[0001] This invention relates to the field of amplifier circuits, and in particular to a super AB class transconductance amplifier. Background Technology

[0002] In recent years, the miniaturization and functional complexity demands of IoT devices such as smart homes and mobile communications have made low-power design increasingly important to chip designers and is integrated throughout the entire design process. Transconductance amplifiers, as one of the most common modules in mixed-signal and analog circuits, are widely used in IoT device integrated circuits, such as multi-stage amplifier circuits, buffer circuits, and switched-capacitor filter circuits. Active load differential pairs offer extremely limited gain, while folded cascode transconductance amplifiers achieve a better balance between gain and signal swing compared to traditional transconductance amplifiers. However, folded cascode transconductance amplifiers are not suitable for operation under low power and low supply requirements. The tail current source in the folded section limits the slew rate of the folded cascode transconductance amplifier, requiring additional slew rate enhancement circuitry to provide large current to the output node dynamically, which further increases system power consumption and reduces gain and bandwidth. The transconductance, unity gain bandwidth (UGBW), and slew rate (SR) of the cyclic folded cascode transconductance amplifier are improved. However, the current mirror also amplifies the quiescent current, and the slew rate is still limited by the quiescent current IQ. The current mirror increases the parasitic capacitance at the drain of the input pair transistors and reduces the phase margin. Summary of the Invention

[0003] The purpose of this invention is to provide a super AB class transconductance amplifier that can improve the amplifier's gain, bandwidth, and stability.

[0004] To achieve the above objectives, the present invention provides the following solution:

[0005] A super AB class transconductance amplifier, the circuit comprising: an input stage circuit module, an adaptive bias circuit module, a local common-mode feedback circuit module, and an output stage circuit module;

[0006] The adaptive bias circuit module, the local common-mode feedback circuit module, and the output stage circuit module are all connected to the input stage circuit module.

[0007] The input stage circuit module is used to acquire the input signal;

[0008] The adaptive bias circuit module is used to provide an adaptive bias current according to the input signal;

[0009] The local common-mode feedback circuit module is used to convert the input signal and the bias current into rate and gain data.

[0010] The output stage circuit module is used to output the converted data.

[0011] Optionally, the circuit further includes: a flip voltage follower;

[0012] The flip-flop voltage follower is connected to the input stage circuit module and the adaptive bias circuit module, respectively.

[0013] The flip voltage follower is used to perform common-mode level shifting on the input signal and input it to the adaptive bias circuit module.

[0014] Optionally, the input stage circuit module includes: transistor M1, transistor M2, transistor M3 and transistor M4;

[0015] The gate of transistor M1 is connected to the positive terminal of the input power supply, the flip voltage follower, and the gate of transistor M2, respectively; the source of transistor M1 is connected to the source of transistor M2, the source of transistor M3, and the source of transistor M4, respectively.

[0016] The drains of transistors M1, M2, M3, and M4 are all connected to the local common-mode feedback circuit module.

[0017] The gates of transistor M3 and M4 are connected, and both the gates of transistor M3 and M4 are connected to the negative terminal of the input power supply.

[0018] Optionally, the local common-mode feedback circuit module includes: transistor M5, transistor M6, transistor M7 and transistor M8, resistor R1 and resistor R2;

[0019] The drain of transistor M5 is connected to one end of resistor R1, and after the drain of transistor M5 is connected to one end of resistor R1, it is connected to the drain of transistor M1 and the drain of transistor M3 respectively.

[0020] The source of transistor M5 is connected to the drain of transistor M7; the gate of transistor M5 is connected to the other end of resistor R1, the gate of transistor M6, and the gate of transistor M7, respectively.

[0021] The source of transistor M7 is grounded; the gate of transistor M7 is also connected to the gate of transistor M8; the source of transistor M8 is grounded.

[0022] One end of resistor R2 is connected to the other end of resistor R1; the other end of resistor R2 is connected to the drain of transistor M6, the drain of transistor M2, and the drain of transistor M4, respectively.

[0023] The source of transistor M6 is connected to the drain of transistor M8; the source of transistor M8 is grounded.

[0024] Optionally, the output stage circuit module includes: transistor M11, transistor M12, transistor M13, transistor M14, transistor M15 and transistor M16;

[0025] The source of transistor M11 is connected to the drain of transistor M4; the gate of transistor M11 is connected to the gate of transistor M12; the source of transistor M12 is connected to the drain of transistor M4; the drain of transistor M12 is connected to the output voltage and the drain of transistor M14 respectively.

[0026] The drain of transistor M11 is connected to the drain of transistor M13, the gate of transistor M13, the gate of transistor M14, the gate of transistor M15, and the gate of transistor M16, respectively; the gate of transistor M13 is connected to the gate of transistor M14; the gate of transistor M15 is connected to the gate of transistor M16; the drain of transistor M14 is also connected to the output voltage.

[0027] The source of transistor M13 is connected to the drain of transistor M15; the source of transistor M14 is connected to the drain of transistor M16.

[0028] Optionally, the adaptive bias circuit module includes: transistor M17, transistor M18, transistor M19, transistor M20, transistor M21, resistor R3, resistor R4, and an active load differential pair circuit submodule.

[0029] The drain of transistor M17 is connected to the source of transistor M1, the source of transistor M2, the source of transistor M3, and the source of transistor M4, respectively.

[0030] The gate of transistor M17 is connected to the output terminal of the active load differential pair circuit submodule, the gate of transistor M18, and the gate of transistor M19, respectively.

[0031] The positive input terminal of the active load differential pair circuit submodule is connected to the source of transistor M2; the negative input terminal of the active load differential pair circuit submodule is connected to one end of resistor R3 and one end of resistor R4 respectively; the other end of resistor R3 is connected to the flip voltage follower.

[0032] The other end of resistor R4 is connected to the drain of transistor M20 and the source of transistor M21, respectively.

[0033] The gate of transistor M20 is connected to the gate of transistor M21, the drain of transistor M21, the drain of transistor M19, and the gate of transistor M4, respectively.

[0034] The gate of transistor M18 is also connected to the gate of transistor M19; the drain of transistor M18 is connected to the flip voltage follower.

[0035] Optionally, the active load differential pair circuit submodule includes: transistor M24, transistor M25, transistor M26, transistor M27 and transistor M28;

[0036] The source of transistor M24 is grounded; the drain of transistor M24 is connected to the source of transistor M25 and the source of transistor M26, respectively.

[0037] The gate of transistor M24 serves as the output terminal and is connected to the gate of transistor M17.

[0038] The gate of transistor M25 is used as the positive input terminal; the gate of transistor M26 is used as the negative input terminal.

[0039] The drain of transistor M25 is connected to the drain of transistor M27, the gate of transistor M27, and the gate of transistor M28, respectively; the gate of transistor M27 is also connected to the gate of transistor M28.

[0040] The drain of transistor M26 is connected to the drain of transistor M28;

[0041] The source of transistor M27 is connected to the source of transistor M28.

[0042] Optionally, the flip voltage follower includes transistor M22 and transistor M23;

[0043] The gate of transistor M23 is connected to the gate of transistor M22 and the drain of transistor M22, respectively; the drain of transistor M22 is also connected to the drain of transistor M18.

[0044] The source of transistor M22 is connected to the drain of transistor M23 and the other end of resistor R3, respectively.

[0045] Optionally, the circuit further includes transistor M9 and transistor M10;

[0046] The source of transistor M9 is grounded; the source of transistor M10 is grounded; the drain of transistor M9 is connected to the source of transistor M12 and the drain of transistor M4, respectively.

[0047] The gates of transistors M9 and M10 are both connected to the local common-mode feedback circuit module.

[0048] The drain of transistor M10 is connected to the drain of transistor M1.

[0049] According to specific embodiments provided by the present invention, the present invention discloses the following technical effects:

[0050] This invention discloses a super AB-class transconductance amplifier, which employs a super AB-class folded cascode transconductance amplifier circuit. It improves upon the traditional cyclic folded cascode transconductance amplifier based on adaptive bias and local common-mode feedback technology. Addressing the high power consumption of cyclic folded cascode transconductance amplifiers, adaptive bias reduces the quiescent power consumption of the input stage and improves the common-mode rejection ratio. The local common-mode feedback circuit overcomes the limitation of slew rate by quiescent current, improving current efficiency to near 1, while further enhancing the amplifier's gain, bandwidth, and stability. Attached Figure Description

[0051] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0052] Figure 1 This is a schematic diagram of the structure of a super AB class transconductance amplifier provided in an embodiment of the present invention;

[0053] Figure 2 This is a schematic diagram of the structure of the active load differential pair circuit submodule provided in an embodiment of the present invention.

[0054] Symbol explanation:

[0055] Input stage circuit module-1, adaptive bias circuit module-2, local common-mode feedback circuit module-3, output stage circuit module-4, flip-flop voltage follower-5. Detailed Implementation

[0056] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0057] The purpose of this invention is to provide a super AB class transconductance amplifier, which aims to improve the amplifier's gain, bandwidth, and stability.

[0058] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0059] Example 1

[0060] like Figure 1As shown in the figure, an embodiment of the present invention provides a super AB class transconductance amplifier, the circuit of which includes: an input stage circuit module 1, an adaptive bias circuit module 2, a local common-mode feedback circuit module 3, and an output stage circuit module 4.

[0061] The adaptive bias circuit module 2, the local common-mode feedback circuit module 3, and the output stage circuit module 4 are all connected to the input stage circuit module 1.

[0062] Input stage circuit module 1 is used to acquire input signals.

[0063] Specifically, the input stage circuit module 1 includes transistors M1, M2, M3, and M4.

[0064] The gate of transistor M1 is connected to the positive terminal of the input power supply, the gate of the flip voltage follower 5, and the gate of transistor M2, respectively; the source of transistor M1 is connected to the source of transistor M2, the source of transistor M3, and the source of transistor M4, respectively.

[0065] The drains of transistors M1, M2, M3, and M4 are all connected to the local common-mode feedback circuit module 3.

[0066] The gates of transistor M3 and M4 are connected, and both the gates of transistor M3 and M4 are connected to the negative terminal of the input power supply.

[0067] The adaptive bias circuit module 2 is used to provide an adaptive bias current based on the input signal.

[0068] The adaptive bias circuit module 2 includes: transistors M17, M18, M19, M20, and M21, resistors R3 and R4, and an active load differential pair circuit submodule OP.

[0069] The drain of transistor M17 is connected to the source of transistor M1, the source of transistor M2, the source of transistor M3, and the source of transistor M4, respectively.

[0070] The gate of transistor M17 is connected to the output terminal of the active load differential pair circuit submodule, the gate of transistor M18, and the gate of transistor M19, respectively.

[0071] The positive input terminal of the active load differential pair circuit submodule is connected to the source of transistor M2; the negative input terminal of the active load differential pair circuit submodule is connected to one end of resistor R3 and one end of resistor R4 respectively; the other end of resistor R3 is connected to the flip voltage follower 5.

[0072] The other end of resistor R4 is connected to the drain of transistor M20 and the source of transistor M21, respectively.

[0073] The gate of transistor M20 is connected to the gate of transistor M21, the drain of transistor M21, the drain of transistor M19, and the gate of transistor M4, respectively.

[0074] The gate of transistor M18 is also connected to the gate of transistor M19; the drain of transistor M18 is connected to the flip voltage follower 5.

[0075] like Figure 2 As shown, the active load differential pair circuit submodule includes: transistor M24, transistor M25, transistor M26, transistor M27 and transistor M28.

[0076] The source of transistor M24 is grounded; the drain of transistor M24 is connected to the source of transistor M25 and the source of transistor M26, respectively.

[0077] The gate of transistor M24 serves as the output terminal and is connected to the gate of transistor M17.

[0078] The gate of transistor M25 is used as the positive input terminal; the gate of transistor M26 is used as the negative input terminal.

[0079] The drain of transistor M25 is connected to the drain of transistor M27, the gate of transistor M27, and the gate of transistor M28, respectively; the gate of transistor M27 is also connected to the gate of transistor M28.

[0080] The drain of transistor M26 is connected to the drain of transistor M28.

[0081] The source of transistor M27 is connected to the source of transistor M28.

[0082] The local common-mode feedback circuit module 3 is used to convert the input signal and bias current into rate and gain to obtain converted data.

[0083] The local common-mode feedback circuit module 3 includes: transistors M5, M6, M7 and M8, resistors R1 and R2.

[0084] The drain of transistor M5 is connected to one end of resistor R1, and after the drain of transistor M5 is connected to one end of resistor R1, it is connected to the drain of transistor M1 and the drain of transistor M3 respectively.

[0085] The source of transistor M5 is connected to the drain of transistor M7; the gate of transistor M5 is connected to the other end of resistor R1, the gate of transistor M6, and the gate of transistor M7, respectively.

[0086] The source of transistor M7 is grounded; the gate of transistor M7 is also connected to the gate of transistor M8; the source of transistor M8 is grounded.

[0087] One end of resistor R2 is connected to the other end of resistor R1; the other end of resistor R2 is connected to the drain of transistor M6, the drain of transistor M2, and the drain of transistor M4, respectively.

[0088] The source of transistor M6 is connected to the drain of transistor M8; the source of transistor M8 is grounded.

[0089] Output stage circuit module 4 is used to output the converted data.

[0090] The output stage circuit module 4 includes transistors M11, M12, M13, M14, M15, and M16.

[0091] The source of transistor M11 is connected to the drain of transistor M4; the gate of transistor M11 is connected to the gate of transistor M12; the source of transistor M12 is connected to the drain of transistor M4; and the drain of transistor M12 is connected to the output voltage and the drain of transistor M14.

[0092] The drain of transistor M11 is connected to the drain of transistor M13, the gate of transistor M13, the gate of transistor M14, the gate of transistor M15, and the gate of transistor M16, respectively; the gate of transistor M13 is connected to the gate of transistor M14; the gate of transistor M15 is connected to the gate of transistor M16; and the drain of transistor M14 is also connected to the output voltage.

[0093] The source of transistor M13 is connected to the drain of transistor M15; the source of transistor M14 is connected to the drain of transistor M16.

[0094] In one embodiment, the circuit further includes a flip voltage follower 5.

[0095] The flip voltage follower 5 is connected to the input stage circuit module 1 and the adaptive bias circuit module 2 respectively; the flip voltage follower 5 is used to perform common-mode level shifting on the input signal and input it to the adaptive bias circuit module 2.

[0096] Specifically, the flip voltage follower 5 includes transistors M22 and M23.

[0097] The gate of transistor M23 is connected to the gate of transistor M22 and the drain of transistor M22, respectively; the drain of transistor M22 is also connected to the drain of transistor M18.

[0098] The source of transistor M22 is connected to the drain of transistor M23 and the other end of resistor R3, respectively.

[0099] In one embodiment, the circuit further includes transistor M9 and transistor M10.

[0100] The source of transistor M9 is grounded; the source of transistor M10 is grounded; the drain of transistor M9 is connected to the source of transistor M12 and the drain of transistor M4, respectively.

[0101] The gates of transistors M9 and M10 are both connected to the local common-mode feedback circuit module 3; the drain of transistor M10 is connected to the drain of transistor M1.

[0102] The super AB class transconductance amplifier provided by this invention is a transconductance amplifier with high slew rate, low power consumption, and high gain. It improves upon the traditional cyclic folded cascode transconductance amplifier based on adaptive bias and local common-mode feedback technology. The adaptive bias section mainly employs common-mode sensing technology implemented with an FVF buffer. In static conditions, it clamps the source potential of the input pair transistors, keeping the static power consumption at a very low level. By sensing the common-mode input voltage and applying it to the gate of the tail current transistor, the static current becomes independent of the input common-mode voltage, thereby achieving a high common-mode rejection ratio (CMRR). Since the common-source output impedance of the input transistors is low, a buffer is introduced for impedance conversion. An active load differential pair is used to convert the sensed common-mode level into the current of the tail current source.

[0103] To further increase the dynamic current, local common-mode feedback technology is used. By utilizing the voltage drop between a pair of matching resistors with the same impedance, a large push-pull current is generated, achieving the characteristics of super AB. At the same time, the adjustment resistor is used to adjust the bandwidth, gain, and phase margin of the amplifier to eliminate process variations.

[0104] Specifically, in practical applications, the circuit structure is as follows: Figure 1 As shown.

[0105] In input stage circuit module 1, the sources of the differential pair transistors M1, M2, M3, and M4 are connected together. The gate-source voltages of transistors M1-M4 in input stage circuit module 1 are controlled to be slightly higher than the threshold voltage. When a large positive signal is received at the input, transistors M1-M4 are quickly driven to the strong inversion region, and the slew rate is not limited by the bias current. The common-mode input voltage is sensed through an FVF buffer and clamped to the gate of transistor M17 through an active load differential pair, so that the quiescent current is independent of the input common-mode voltage, thereby achieving a high common-mode rejection ratio (CMRR). If input stage circuit module 1 is controlled to be in the weak inversion region or even the subthreshold region, very low quiescent power consumption can be achieved. When the input signal is large, the voltage change sensed by the FVF buffer is applied to the input of the active load differential pair circuit submodule OP through resistors R3 and R4. The output of OP drives the tail current source to supply a large current to the individual transistors in input stage circuit module 1, enhancing the input stage slew rate.

[0106] A pair of matching resistors R1 and R2 with identical impedance are connected to the two gates of the active current mirror, that is, to the gates of transistors M9 and M10. When the input signal is 0, there is no voltage drop across resistors R1 and R2, and its characteristics are the same as those of a traditional cyclic folded cascode transconductance amplifier. When the input signal is a large positive signal, the current in the input pair, namely transistor M1, is much greater than the current in transistor M2. The current difference between the two causes a voltage drop between resistors R1 and R2, the magnitude of which is V = R × (I1 - I2) / 2. This causes the gate voltage of transistor M3 to rise and the gate voltage of transistor M4 to fall, thus generating a large push current. Similarly, when the input signal is a large positive or negative signal, a large pull current is generated, realizing the characteristics of CLASS AB.

[0107] Input stage circuit module 1 is mainly responsible for inputting the input signal through the gate of the input stage transistor. Adaptive bias circuit module 2 mainly provides bias current that is adaptive to the input signal. Active load differential pair circuit submodule is responsible for clamping the output voltage of the flip voltage follower 5. Local common mode feedback circuit module 3 is mainly responsible for further improving the conversion rate and gain. Output stage circuit module 4 is mainly responsible for outputting current to the load.

[0108] Under static conditions, transistors M1 through M4 are biased by equal static current. If the control input pair, i.e., transistors M1 and M4, are located in the weak inversion region or even the subthreshold region, very low static power consumption can be achieved. Common-mode sensing is achieved by the flip-flop voltage follower 5, which can shift the input common-mode level to the level of the input common-mode voltage plus the gate-source voltage of M23. Since the drains of transistors M23 and M20 have low common-source output impedances with the input transistors, a buffer is introduced for impedance transformation. An active load differential pair is used to drive the current source, i.e., transistor M17. Under static conditions, transistors M1 through M4 are biased in the subthreshold region to improve current efficiency. With proper matching of transistors M1 through M4, M23, and M20, static power consumption is well controlled.

[0109] When the input signal is 0, there is no voltage drop across resistors R1 and R2, exhibiting characteristics similar to a traditional cyclic folded cascode transconductance amplifier. When the input signal is a large positive signal, the current in transistor M1 is much greater than that in transistor M2. This current difference creates a voltage drop across resistors R1 and R2, with a magnitude of V = R × (I1 - I2) / 2. This causes the gate voltage of transistor M3 to rise and the gate voltage of transistor M4 to fall, resulting in a large push current. Similarly, when the input signal is a large positive or negative signal, a large pull current is generated, achieving the characteristics of a CLASS AB amplifier.

[0110] Traditional PMOS input-type folded cascode transconductance amplifiers suffer from low current power because the dynamic current generated by the folded transistors during signal changes is used only to drive the load and provides no gain. Furthermore, even long-channel input stage transistors cannot provide high intrinsic gain in low-supply-voltage applications. Cyclic folded cascode transconductance amplifiers address the low quiescent current efficiency issue, and active current mirrors provide high gain; however, the current mirrors also amplify the quiescent current, and the slew rate is still limited by the quiescent current. The super-class AB transconductance amplifier circuit designed in this invention effectively overcomes these limitations.

[0111] Advantages of this invention:

[0112] 1. Adaptive biasing technology based on common-mode sensing and pseudo-differential pairs is introduced into the cyclic folded cascode transconductance amplifier, effectively reducing static power consumption. The relationship between the input differential voltage and the input stage dynamic current is converted to a square relationship, improving the slew rate and current efficiency of the input stage.

[0113] 2. A local common-mode feedback LCMFB is used in the folding section, which increases the slew rate and gain-bandwidth product. The relationship between the output current and the input differential voltage is transformed into a fourth-power relationship, improving the current efficiency to near 1. Both large-signal and small-signal performance are improved.

[0114] 3. By using adjustment resistors, the impact of process errors on amplifier gain, slew rate, bandwidth and stability is reduced, and design redundancy is increased.

[0115] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0116] This document uses specific examples to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the circuit and core ideas of the present invention. Furthermore, those skilled in the art will recognize that, based on the ideas of the present invention, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A super-AB class transconductance amplifier characterized by, The circuit comprises an input stage circuit module, an adaptive bias circuit module, a local common-mode feedback circuit module and an output stage circuit module. The adaptive bias circuit module, the local common-mode feedback circuit module and the output stage circuit module are connected with the input stage circuit module. The input stage circuit module is used for acquiring an input signal. The adaptive bias circuit module is used for providing an adaptive bias current according to the input signal. The local common-mode feedback circuit module is used for performing rate and gain conversion on the input signal and the bias current to obtain conversion data. The output stage circuit module is used for outputting the conversion data. The circuit further comprises a flip voltage follower. The flip voltage follower is connected with the input stage circuit module and the adaptive bias circuit module respectively. The flip voltage follower is used for performing common-mode level shift processing on the input signal and inputting the input signal to the adaptive bias circuit module. The input stage circuit module comprises transistors M1, M2, M3 and M4. The gate of the transistor M1 is connected with the positive pole of an input power supply, the flip voltage follower and the gate of the transistor M2 respectively; the source of the transistor M1 is connected with the source of the transistor M2, the source of the transistor M3 and the source of the transistor M4 respectively. The drain of the transistor M2 and the drain of the transistor M3 are connected with the local common-mode feedback circuit module. The gate of the transistor M3 and the gate of the transistor M4 are connected, and the gate of the transistor M3 and the gate of the transistor M4 are connected with the negative pole of the input power supply. The local common-mode feedback circuit module comprises transistors M5, M6, M7 and M8, resistors R1 and R2. The drain of the transistor M5 is connected with one end of the resistor R1, and after the drain of the transistor M5 is connected with one end of the resistor R1, the drain of the transistor M5 is connected with the drain of the transistor M3. The source of the transistor M5 is connected with the drain of the transistor M7; the gate of the transistor M5 is connected with the gate of the transistor M6. The source of the transistor M7 is grounded; the gate of the transistor M7 is also connected with the gate of the transistor M8; the source of the transistor M8 is grounded. One end of the resistor R2 is connected with the other end of the resistor R1; the other end of the resistor R2 is connected with the drain of the transistor M6 and the drain of the transistor M2 respectively. The source of the transistor M6 is connected with the drain of the transistor M8. The adaptive bias circuit module comprises transistors M17, M18, M19, M20, M21, resistors R3 and R4 and an active load differential pair circuit submodule. The drain of the transistor M17 is connected with the source of the transistor M1, the source of the transistor M2, the source of the transistor M3 and the source of the transistor M4 respectively. The gate of the transistor M17 is connected with the output end of the active load differential pair circuit submodule. The positive input end of the active load differential pair circuit submodule is connected with the source of the transistor M2; the negative input end of the active load differential pair circuit submodule is connected with one end of the resistor R3 and one end of the resistor R4 respectively; the other end of the resistor R3 is connected with the flip voltage follower. ​ The other end of the resistor R4 is connected with the drain of the transistor M20 and the source of the transistor M21 respectively; The gate of the transistor M20 is connected with the drain of the transistor M21 and the drain of the transistor M19 respectively; The gate of the transistor M18 is also connected with the gate of the transistor M19; the drain of the transistor M18 is connected with the flip voltage follower; the source of the transistor M17 is connected with the power supply; the source of the transistor M20 is connected with the power supply; the source of the transistor M18 is grounded; the source of the transistor M19 is grounded; the gate of the transistor M21 is connected with the negative electrode of the input power supply.

2. The super-AB class transconductance amplifier of claim 1, wherein, The output stage circuit module comprises the transistor M11, the transistor M12, the transistor M13, the transistor M14, the transistor M15 and the transistor M16; The source of the transistor M11 is connected with the drain of the transistor M1; the gate of the transistor M11 is connected with the gate of the transistor M12; the source of the transistor M12 is connected with the drain of the transistor M4; the drain of the transistor M12 is connected with the output voltage and the drain of the transistor M14 respectively; The drain of the transistor M11 is connected with the drain of the transistor M13, the gate of the transistor M15 and the gate of the transistor M16 respectively; the gate of the transistor M13 is connected with the gate of the transistor M14; the gate of the transistor M15 is connected with the gate of the transistor M16; the drain of the transistor M14 is also connected with the output voltage; The source of the transistor M13 is connected with the drain of the transistor M15; the source of the transistor M14 is connected with the drain of the transistor M16; the source of the transistor M15 is connected with the power supply; the source of the transistor M16 is connected with the power supply.

3. The super-AB class transconductance amplifier of claim 1, wherein, The active load differential pair circuit submodule comprises the transistor M24, the transistor M25, the transistor M26, the transistor M27 and the transistor M28; The source of the transistor M24 is grounded; the drain of the transistor M24 is connected with the source of the transistor M25 and the source of the transistor M26 respectively; The gate of the transistor M24 is connected with the power supply; the drain of the transistor M28 is connected with the drain of the transistor M26 and then connected with the gate of the transistor M17; The gate of the transistor M25 is the positive input end; the gate of the transistor M26 is the negative input end; The drain of the transistor M25 is connected with the drain of the transistor M27, the gate of the transistor M27 and the gate of the transistor M28 respectively; the gate of the transistor M27 is also connected with the gate of the transistor M28; The drain of the transistor M26 is connected with the drain of the transistor M28; The source of the transistor M27 is connected with the source of the transistor M28; the source of the transistor M27 and the source of the transistor M28 are also connected with the power supply.

4. The super-AB class transconductance amplifier of claim 1, wherein, The flip voltage follower comprises the transistor M22 and the transistor M23; The gate of the transistor M23 is connected with the drain of the transistor M22; the drain of the transistor M22 is also connected with the drain of the transistor M18; the gate of the transistor M22 is connected with the positive electrode of the input power supply; the source of the transistor M23 is connected with the power supply; The source of the transistor M22 is connected with the drain of the transistor M23 and the other end of the resistor R3 respectively.

5. The super-AB class transconductance amplifier of claim 2, wherein, The circuit further comprises a transistor M9 and a transistor M10; a source of the transistor M9 is connected with a ground; a source of the transistor M10 is connected with the ground; a drain of the transistor M9 is connected with a source of a transistor M12 and a drain of a transistor M4 respectively; a gate of the transistor M9 is connected with a drain of a transistor M6 in the local common-mode feedback circuit module; a gate of the transistor M10 is connected with a drain of a transistor M5 in the local common-mode feedback circuit module; a drain of the transistor M10 is connected with a drain of the transistor M1.

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