High-speed zero-crossing comparator with low walking error and control method thereof

Abstract

This application discloses a high-speed zero-crossing comparator with low walk error and its control method. The high-speed zero-crossing comparator includes a differential amplifier module, a five-transistor operational amplifier module, a hysteresis control module, and a driver stage circuit. The output terminal of the differential amplifier module and the output terminal of the five-transistor operational amplifier module are connected to a first connection point. The first connection point is connected to the input terminal of the driver stage circuit and the input terminal of the hysteresis control module, respectively. The output terminal of the hysteresis control module is connected to the input terminal of the differential amplifier module. This application embodiment can enhance the comparator's processing capability for input signals with different slew rates and overdrive while consuming relatively low static power consumption, and reduce propagation delay dispersion under wide input slew rates and overdrive, thereby reducing the zero-crossing drift error and kickback noise of the high-speed zero-crossing comparator. This application can be widely applied in the field of integrated circuit technology.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a high-speed zero-crossing comparator with low walking error and its control method. Background Technology

[0002] Currently, in lidar time discrimination methods, comparators only consider the impact of the comparator's input signal overdrive voltage on propagation delay spread, neglecting the influence of the input signal slew rate. However, in time discrimination, the impact of the input signal slew rate is more significant than that of the overdrive voltage. While some methods consider both slew rate and overdrive voltage, delay spread can still reach several hundred ps when the input signal slew rate varies over a wide range. Other methods employ multi-stage amplification of the input signal until saturation to equalize the speed of signals with different slew rates and overdrive voltages, thereby reducing travel errors; however, this approach results in higher static power consumption.

[0003] In summary, the technical problems existing in the relevant technologies need to be improved. Summary of the Invention

[0004] The main objective of this application is to propose a high-speed zero-crossing comparator with low walking error and its control method. It can enhance the comparator's ability to process input signals with different slew rates and overdrive under conditions of low static power consumption, reduce the propagation delay spread under wide input slew rates and overdrive, thereby reducing the drift error and kickback noise at the zero-crossing point of the high-speed zero-crossing comparator.

[0005] To achieve the above objectives, one aspect of this application proposes a high-speed zero-crossing comparator with low travel error. The high-speed zero-crossing comparator includes a differential amplifier module, a five-transistor operational amplifier module, a hysteresis control module, and a driver stage circuit. The output terminal of the differential amplifier module and the output terminal of the five-transistor operational amplifier module are connected to a first connection point. The first connection point is connected to the input terminal of the driver stage circuit and the input terminal of the hysteresis control module, respectively. The output terminal of the hysteresis control module is connected to the input terminal of the differential amplifier module, wherein:

[0006] The differential amplifier module is used to acquire differential input signals and perform amplification and conversion processing to output single-ended signals;

[0007] The five-transistor operational amplifier module is used to acquire the differential input signal and amplify it to generate a current signal related to the slew rate of the differential input signal.

[0008] The hysteresis control module is used to control the positive and negative hysteresis thresholds of the differential amplifier module;

[0009] The driver stage circuit is used to perform output driving processing based on the single-ended signal and the current signal, and output a digital signal containing phase information.

[0010] In some embodiments, the differential amplifier module includes a hysteresis-controlled fully differential amplifier, a low-gain, high-bandwidth fully differential amplifier module, a decision circuit, and a differential input single-ended output amplifier. The output terminal of the hysteresis-controlled fully differential amplifier is connected to the input terminal of the low-gain, high-bandwidth fully differential amplifier module, the output terminal of the low-gain, high-bandwidth fully differential amplifier module is connected to the input terminal of the decision circuit, and the output terminal of the decision circuit is connected to the input terminal of the differential input single-ended output amplifier.

[0011] The hysteresis-controlled fully differential amplifier is used to acquire the differential input signal and amplify it, and output a differential signal after one stage of amplification.

[0012] The low-gain high-bandwidth fully differential amplifier module includes a first low-gain high-bandwidth fully differential amplifier, a second low-gain high-bandwidth fully differential amplifier, a third low-gain high-bandwidth fully differential amplifier, a fourth low-gain high-bandwidth fully differential amplifier, and a fifth low-gain high-bandwidth fully differential amplifier. The low-gain high-bandwidth fully differential amplifier module is used to amplify the differential signal after the first stage of amplification step by step, and output a differential signal after six stages of amplification.

[0013] The decision circuit is used to compare and latch the six-stage amplified differential signal and output the compared differential signal.

[0014] The differential input single-ended output amplifier is used to convert the compared differential signal and output the single-ended signal.

[0015] In some embodiments, the hysteresis-controlled fully differential amplifier includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a first resistor, and a second resistor. The gate of the first transistor is connected to the hysteresis control module. The sources of the first transistor, the second transistor, the seventh transistor, and the eighth transistor are connected to the first low-gain, high-bandwidth fully differential amplifier and connected to a high level. The drains of the first transistor and the second transistor are connected to the source of the third transistor. The drain of the third transistor, the gate of the third transistor, and the drain of the fourth transistor are connected to the first... A low-gain, high-bandwidth fully differential amplifier is connected. The drains of the seventh and eighth transistors are connected to the source of the sixth transistor. The gate, drain, and drain of the sixth and fifth transistors are connected to the first low-gain, high-bandwidth fully differential amplifier. The source of the fourth transistor is connected to the source of the fifth transistor and grounded. The gate of the fourth transistor is connected to the first differential input signal. The gate of the fifth transistor is connected to the second differential input signal. The gate of the second transistor is connected to the first terminal of the first resistor, and the second terminal of the first resistor is grounded. The gate of the seventh transistor is connected to the first terminal of the second resistor, and the second terminal of the second resistor is grounded.

[0016] In some embodiments, the first low-gain high-bandwidth fully differential amplifier, the second low-gain high-bandwidth fully differential amplifier, the third low-gain high-bandwidth fully differential amplifier, the fourth low-gain high-bandwidth fully differential amplifier, and the fifth low-gain high-bandwidth fully differential amplifier all have the same structure. The first low-gain high-bandwidth fully differential amplifier includes a ninth transistor, a tenth transistor, an eleventh transistor, and a twelfth transistor. The source of the ninth transistor is connected to the source of the twelfth transistor, the gate and drain of the ninth transistor are connected to the drain of the tenth transistor, the gate and drain of the twelfth transistor are connected to the drain of the eleventh transistor, and the source of the tenth transistor is connected to the source of the eleventh transistor.

[0017] In some embodiments, the decision circuit includes a 29th transistor, a 30th transistor, a 31st transistor, a 32nd transistor, a 33rd transistor, and a 34th transistor. The source of the 29th transistor is connected to the source of the 34th transistor. The gate of the 29th transistor is connected to the fifth low-gain high-bandwidth fully differential amplifier. The gate of the 34th transistor is connected to the fifth low-gain high-bandwidth fully differential amplifier. The drain of the 29th transistor, the gate of the 32nd transistor, the drain of the 31st transistor, the gate of the 30th transistor, and the drain of the 30th transistor are connected to the differential input single-ended output amplifier. The drain of the 34th transistor, the gate of the 31st transistor, the drain of the 32nd transistor, the gate of the 33rd transistor, and the drain of the 33rd transistor are connected to the differential input single-ended output amplifier. The sources of the 30th transistor, the 31st transistor, the 32nd transistor, and the 33rd transistor are connected.

[0018] In some embodiments, the differential input single-ended output amplifier includes a 35th transistor, a 36th transistor, a 37th transistor, a 38th transistor, a 39th transistor, and a 40th transistor. The source of the 37th transistor is connected to both the decision circuit and the driver stage circuit. The gate of the 37th transistor, the drain of the 35th transistor, the drain of the 36th transistor, and the gate of the 38th transistor are connected. The drain of the 37th transistor, the source of the 35th transistor, and the source of the 39th transistor are connected. The gates of the 35th transistor and the 36th transistor are connected to the decision circuit. The gates of the 39th transistor and the 40th transistor are connected to the decision circuit. The drains of the 39th transistor and the 40th transistor are connected to the driver stage circuit. The sources of the 36th transistor, the 40th transistor, and the drain of the 38th transistor are connected. The source of the 38th transistor is grounded.

[0019] In some embodiments, the five-transistor operational amplifier module includes a first five-transistor operational amplifier, a second five-transistor operational amplifier, a third five-transistor operational amplifier, a fourth five-transistor operational amplifier, and a fifth five-transistor operational amplifier. These five amplifiers are connected sequentially and have the same structure. The first five-transistor operational amplifier includes a fifty-fifth transistor. The system comprises transistors 56, 57, and 58, wherein the source of transistor 55 is connected to the source of transistor 58 and is connected to a high level; the gate of transistor 55, the drain of transistor 55, and the drain of transistor 56 are connected; the drain of transistor 58, the drain of transistor 57, and the second five-transistor operational amplifier are connected; the gate of transistor 56 is connected to the first differential input signal; the gate of transistor 57 is connected to the second differential input signal; and the sources of transistor 56 and 57 are connected to ground.

[0020] In some embodiments, the hysteresis control module includes a 51st transistor, a 52nd transistor, a 53rd transistor, and a 54th transistor. The source of the 51st transistor is connected to the source of the 53rd transistor and is connected to a high level. The drains of the 51st transistor and the 52nd transistor are connected to the hysteresis control fully differential amplifier. The gates of the 51st transistor, the 52nd transistor, the 53rd transistor, and the 54th transistor are connected to the hysteresis control fully differential amplifier. The source of the 52nd transistor is connected to the source of the 54th transistor and is grounded. The gates of the 53rd transistor and the 54th transistor are connected to the differential input single-ended output amplifier.

[0021] In some embodiments, the driving stage circuit includes a first-stage driving unit, a second-stage driving unit, a third-stage driving unit, a fourth-stage driving unit, and a fifth-stage driving unit. The first-stage driving unit is connected to the second-stage driving unit and the third-stage driving unit, respectively. The second-stage driving unit is connected to the fourth-stage driving unit, and the third-stage driving unit is connected to the fifth-stage driving unit. The first-stage driving unit, the second-stage driving unit, the third-stage driving unit, the fourth-stage driving unit, and the fifth-stage driving unit have the same structure. The first-stage driving unit includes a forty-first transistor and a forty-second transistor. The gates of the forty-first transistor and the forty-second transistor are connected to the differential input single-ended output amplifier. The source of the forty-first transistor is connected to the differential amplifier module and the second-stage driving unit, respectively. The source of the forty-second transistor is connected to the differential amplifier module and the third-stage driving unit, respectively. The drains of the forty-first transistor and the forty-second transistor are connected to the second-stage driving unit and the third-stage driving unit.

[0022] To achieve the above objectives, another aspect of this application proposes a control method for a high-speed zero-crossing comparator with low travel error, the method comprising:

[0023] Determine the positive and negative hysteresis thresholds;

[0024] Based on the positive and negative hysteresis thresholds, the differential input signal is acquired and amplified to generate a current signal;

[0025] The differential input signal is converted and processed to output a single-ended signal;

[0026] Based on the single-ended signal and the current signal, output driving processing is performed to output a digital signal containing phase information.

[0027] The embodiments of this application include at least the following beneficial effects: This application provides a high-speed zero-crossing comparator with low travel error and its control method. The scheme includes a differential amplifier module, a five-transistor operational amplifier module, a hysteresis control module, and a driver stage circuit. The differential amplifier module can obtain a very high open-loop gain-bandwidth product, so for input signals with different slew rates and overdrive voltages, the comparator's response speed is basically the same, thereby reducing the propagation delay spread under on-rail input slew rate. Furthermore, through the five-transistor operational amplifier module, when the slope and overdrive of the input signal are both large, the output of the five-transistor operational amplifier has a strong pull-up capability, thereby slowing down the fully differential amplifier. The discharge speed of each key output node of the amplifier slightly increases the propagation delay of input signals with large slew rates and large overdrive, while for input signals with small slew rates and small overdrive, the propagation delay spread is significantly reduced from more than 300ps to less than 100ps. Finally, based on the driver stage circuit to improve the output driving capability of the comparator and the hysteresis control module to control the positive and negative hysteresis thresholds of the comparator respectively, the comparator's ability to process input signals with different slew rates and overdrive can be enhanced under conditions of low static power consumption, and the propagation delay spread under wide input slew rates and overdrive can be reduced, thereby reducing the zero-crossing drift error and kickback noise of the high-speed zero-crossing comparator. Attached Figure Description

[0028] Figure 1 This is a schematic diagram of a high-speed zero-crossing comparator with low walking error provided in an embodiment of this application;

[0029] Figure 2 This is a schematic diagram of the circuit principle of the high-speed zero-crossing comparator provided in the embodiments of this application;

[0030] Figure 3 The waveform simulation diagrams of INP, INN, and OUTP provided in the embodiments of this application, which employ a multi-stage low-gain high-bandwidth and five-transistor operational amplifier compensation structure;

[0031] Figure 4 This is a simulation diagram of the walking error provided in the embodiments of this application, which adopts a multi-stage low-gain high-bandwidth and five-transistor operational amplifier compensation structure;

[0032] Figure 5 This is a simulation diagram of the walking error provided in the embodiments of this application, which only uses a multi-stage low-gain high-bandwidth structure;

[0033] Figure 6 This is a simulation diagram of the walking error of a conventional high-speed comparator structure provided in the embodiments of this application;

[0034] Figure 7 This is a flowchart illustrating the steps of a control method for a high-speed zero-crossing comparator with low travel error provided in an embodiment of this application. Detailed Implementation

[0035] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit it. In the following description, when referring to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with those of this application; they are merely examples of comparators and methods consistent with some aspects of the embodiments of this application as detailed in the appended claims.

[0036] It is understood that the terms “first,” “second,” etc., used in this application may be used herein to describe various concepts, but unless otherwise stated, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another. For example, without departing from the scope of the embodiments of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the words “if,” “when,” or “in response to a determination” as used herein may be interpreted as “when…” or “when…” or “in response to a determination.”

[0037] As used in this application, the terms "at least one", "multiple", "each", "any", etc., "at least one" includes one, two or more, "multiple" includes two or more, "each" refers to each of the corresponding multiples, and "any" refers to any one of the multiples.

[0038] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0039] First, before providing a detailed description of the embodiments of this application, some of the nouns and terms involved in the embodiments of this application will be explained. The nouns and terms involved in the embodiments of this application are subject to the following interpretations, and examples are given to illustrate some shortcomings of the prior art.

[0040] LiDAR, due to its strong anti-interference capabilities, high resolution, and small size, is widely used in fields such as autonomous driving, smart homes, and terrain mapping. LiDAR emits laser pulses, which reflect back when they encounter obstacles and are received by a receiving system. The processor then processes the transmitted and received signals to obtain detection information. Therefore, accurately determining the laser's time of flight is crucial for ensuring the ranging accuracy of LiDAR. While the laser's emission time is largely deterministic and unaffected by the environment, its termination time is highly influenced by both environmental factors and the circuitry itself. Therefore, improving the accuracy of the termination time is essential for enhancing the ranging accuracy of LiDAR. The time discrimination circuit converts the analog signal of the echo pulse into a digital signal containing the termination time information, facilitating subsequent processing by the processor.

[0041] Commonly used time discrimination circuits include leading-edge time discrimination circuits, constant-ratio timing time discrimination circuits, and pulse shaping (also called high-pass RC method) time discrimination circuits. While these methods can achieve time discrimination, they each have their own drawbacks. The leading-edge time discrimination method uses a fixed threshold to obtain the termination time of the echo pulse signal. However, this method is very sensitive to changes in echo pulse amplitude, threshold settings, and circuit noise, introducing significant travel errors and resulting in inaccurate time information. The constant-ratio timing method splits the echo signal into two paths: one delayed and the other attenuated. These two signals are then compared using a high-speed comparator to determine the termination time of the echo signal. However, this method is relatively complex, and if the echo signal is distorted, the time point will change significantly, leading to inaccurate timing. The high-pass RC method converts the peak point of the echo pulse into a zero-crossing point, then uses a comparator to detect the zero-crossing point to obtain the termination time. This method is simple and highly accurate, but requires a clear peak value.

[0042] In all the aforementioned time discrimination methods, comparators are used. The comparator's function is to detect the arrival time of the echo pulse and output a digital signal representing this time information. Therefore, the input swing of the comparator affects the dynamic range of the lidar receiving system, and its swing rate affects the lidar's detection efficiency and accuracy. Thus, neglecting the comparator's performance will introduce additional walking errors, thereby reducing ranging accuracy. The slope and overdrive voltage of the comparator's input signal vary considerably with the echo pulse amplitude, causing the comparator's propagation delay to change with the echo amplitude. In the worst case (maximum and minimum echo amplitude), this can introduce errors of several nanoseconds. Therefore, the key performance characteristics of the comparator need to be carefully considered. On the one hand, the propagation delay of the zero-crossing comparator should be as small as possible to enable a fast response to narrow pulse signals and allow time for the output to set up at the termination time; on the other hand, the propagation delay spread of the zero-crossing comparator should also be as small as possible to reduce the introduced walking errors. However, in time discrimination, the performance of the propagation delay spread is more important than the magnitude of the propagation delay. Propagation delay spread refers to the range of changes in the propagation delay of the output signal when both the slope (slew rate) and overdrive voltage of the input signal change. This directly determines the magnitude of the walking error introduced by the zero-crossing comparator.

[0043] Currently, there is limited research addressing these requirements. Some techniques only consider the impact of the comparator's input signal overdrive voltage on propagation delay spread, neglecting the influence of the input signal slew rate. However, in timing discrimination, the impact of the input signal slew rate is more significant than that of the overdrive voltage. Other techniques consider both slew rate and overdrive voltage, but when the input signal slew rate varies over a wide range, the delay spread still reaches several hundred ps. Still other techniques employ multi-stage amplification of the input signal until saturation, thereby speeding up signals with different slew rates and overdrive voltages to the same speed, thus reducing travel errors. However, this method has high static power consumption, ranging from 20mA to 30mA.

[0044] However, some techniques do not consider the zero-crossing comparator itself, but rather the overall timing discrimination circuitry or circuits outside of it. For example, some techniques incorporate automatic gain control before the timing discrimination circuit, which minimizes the amplitude variation of the comparator input signal and thus reduces the introduced error. However, such circuits are extremely complex and costly. Alternatively, a high-bandwidth open-loop amplifier can be introduced before the comparator, but the gain of the open-loop amplifier varies significantly with the PVT, still introducing substantial timing discrimination errors, and it is unsuitable for constant ratio timing methods. Other techniques utilize multiple discrete components, such as combining an LVDS comparator with a high-speed CMOS comparator, to achieve smaller travel errors, but suffer from low integration density and high cost (LVDS comparators are more expensive).

[0045] In view of this, the present invention provides a high-speed zero-crossing comparator circuit with a wide input swing and low travel error. When the slew rate and overdrive voltage of the input signal vary over a wide range, the propagation delay dispersion of the output signal is very small, and the propagation delay is also small. In addition, the hysteresis range can be externally adjusted to eliminate the misalignment caused by the manufacturing process, thereby achieving better robustness.

[0046] Reference Figure 1 , Figure 1 This is a schematic diagram of a high-speed zero-crossing comparator with low walking error provided in an embodiment of the present invention, referring to... Figure 1 The high-speed zero-crossing comparator includes a differential amplifier module, a five-transistor operational amplifier module, a hysteresis control module, and a driver stage circuit. The output of the differential amplifier module and the output of the five-transistor operational amplifier module are connected to a first connection point. The first connection point is connected to the input of the driver stage circuit and the input of the hysteresis control module, respectively. The output of the hysteresis control module is connected to the input of the differential amplifier module.

[0047] It should be noted that, as Figure 1 As shown, the overall structure of the high-speed zero-crossing comparator in this embodiment mainly includes amplifiers A1-A8, five-transistor operational amplifiers OP1-OP5, a hysteresis control module, and a driver stage circuit. The comparator is constructed using a pre-amplified regenerative latch structure, which, in addition to its significant speed advantage, also exhibits a lower offset voltage. Furthermore, adding a preamplifier before the latch comparator effectively reduces kickback noise.

[0048] Amplifiers A1-A7 are all fully differential amplifiers, while A8 is a differential input single-ended output amplifier. OP1-OP5 are all five-transistor operational amplifiers with identical structures. The driver stage circuit includes INV1-INV5. The hysteresis control module includes INV6, INV7, and A1. Specifically: the non-inverting input of A1 is connected to the non-inverting input INP of the entire comparator; the inverting input of A1 is connected to the inverting input INN of the entire comparator; the inverting output of A1 is connected to the non-inverting input of A2; and the non-inverting output of A1 is connected to the inverting input of A2. Furthermore, the output of INV6 in the hysteresis control module is connected to the HyN port of A1, and the output of INV7 is connected to the HyP port of A1. The positive and negative hysteresis thresholds of the comparator can be controlled by adjusting the voltage levels at the VCTL_Hy_P and VCTL_Hy_N ports. The non-inverting input of A2 is connected to the inverting output of A1. The inverting input of A2 is connected to the non-inverting output of A1. The inverting output of A2 is connected to the non-inverting input of A3. The non-inverting output of A2 is connected to the inverting input of A3. The non-inverting input of A3 is connected to the inverting output of A2. The inverting output of A3 is connected to the non-inverting input of A4. The non-inverting output of A3 is connected to the inverting input of A4. The non-inverting input of A4 is connected to the inverting output of A3. The inverting output of A4 is connected to the non-inverting input of A5. The non-inverting output of A4 is connected to the inverting input of A5. The non-inverting input of A5 is connected to the inverting output of A4. The inverting input of A5 is connected to the non-inverting output of A4. The inverting output of A5 is connected to the non-inverting input of A6. The non-inverting output of A5 is connected to the inverting input of A6. The non-inverting input of A6 is connected to the inverting output of A5. The inverting output of A6 is connected to the non-inverting input of A7. The non-inverting output of A6 is connected to the inverting input of A7. The non-inverting input of A7 is connected to the inverting output of A6. The inverting output of A7 is connected to the non-inverting input of A8. The non-inverting output of A7 is connected to the inverting input of A8. The non-inverting input of A8 is connected to the inverting output of A7, the inverting input of A8 is connected to the non-inverting output of A7, and the output of A8 is connected to the input of INV1 in the driver stage.The input of INV1 in the driver stage is connected to the output of A8. The output of INV1 is connected to the inputs of INV2 and INV3 respectively. The output of INV2 is connected to the input of INV4. The output of INV3 is connected to the input of INV5. The output of INV2 is connected to the output of INV3 (acting as a latch). The output of INV4 is connected to the non-inverting output OUTP of the entire comparator. The output of INV5 is connected to the inverting output OUTN of the entire comparator. The non-inverting inputs of OP1-OP5 are all connected to the non-inverting input INP of the entire comparator. The inverting inputs of OP1-OP5 are all connected to the inverting input INN of the entire comparator. The output of OP1 is connected to the non-inverting output of A2. The output of OP2 is connected to the non-inverting output of A3. The output of OP3 is connected to the inverting output of A4. The output of OP4 is connected to the non-inverting output of A5. The output of OP5 is connected to the non-inverting output of A6. The input of INV6 of the hysteresis control module is connected to the output of A8, and the output of INV6 is connected to the input of INV7.

[0049] Amplifier A1 amplifies the input signals INP and INN of the comparator and controls the positive and negative hysteresis thresholds of the comparator. A2-A6 amplify the differential output signal of A1 stage by stage. A1-A6 form a 6-stage low-gain, high-bandwidth amplifier group, providing a sufficiently high open-loop gain-bandwidth product for the entire comparator, ensuring that the comparator's response speed to input signals with different slew rates is as uniform as possible. A7 is the comparator's decision circuit, used to generate the comparison logic and also has a latching function. A8 is a differential-to-single-ended comparator, also with some amplification function, further amplifying the output signal of A7. The driver stage enhances the driving capability of the comparator output, enabling it to drive large load capacitors. The hysteresis control module controls the hysteresis action of the comparator. OP1-OP5 sample the comparator input signal; their outputs are connected to the key output nodes of each stage of the comparator, controlling the discharge rate of each key output node to reduce propagation delay dispersion.

[0050] The differential amplifier module is used to acquire differential input signals and amplify and convert them to output single-ended signals;

[0051] Specifically, the differential amplifier module includes a hysteresis-controlled fully differential amplifier A1, a low-gain, high-bandwidth fully differential amplifier module, a decision circuit A7, and a differential input single-ended output amplifier A8. The output of the hysteresis-controlled fully differential amplifier is connected to the input of the low-gain, high-bandwidth fully differential amplifier module, the output of the low-gain, high-bandwidth fully differential amplifier module is connected to the input of the decision circuit, and the output of the decision circuit is connected to the output of the differential input single-ended output amplifier. The hysteresis-controlled fully differential amplifier is used to acquire the differential input signal and amplify it, outputting a first-stage amplified differential signal. The low-gain, high-bandwidth fully differential amplifier module... The module includes a first low-gain high-bandwidth fully differential amplifier A2, a second low-gain high-bandwidth fully differential amplifier A3, a third low-gain high-bandwidth fully differential amplifier A4, a fourth low-gain high-bandwidth fully differential amplifier A5, and a fifth low-gain high-bandwidth fully differential amplifier A6. The low-gain high-bandwidth fully differential amplifier module is used to amplify the differential signal after one stage of amplification step by step, and output a differential signal after six stages of amplification. The decision circuit is used to compare and latch the differential signal after six stages of amplification, and output the compared differential signal. The differential input single-ended output amplifier is used to convert the compared differential signal and output the single-ended signal.

[0052] In a specific embodiment of the present invention, the hysteresis-controlled fully differential amplifier A1 includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a first resistor R1, and a second resistor R2. The gate of the first transistor is connected to the hysteresis control module. The sources of the first transistor, the second transistor, the seventh transistor, and the eighth transistor are connected to the first low-gain, high-bandwidth fully differential amplifier and connected to a high level. The drains of the first transistor and the second transistor are connected to the source of the third transistor. The drain of the third transistor and the third transistor... The gate of the fourth transistor and the drain of the fifth transistor are connected to the first low-gain high-bandwidth fully differential amplifier. The drains of the seventh and eighth transistors are connected to the source of the sixth transistor. The gate, drain, and drain of the sixth and fifth transistors are connected to the first low-gain high-bandwidth fully differential amplifier. The source of the fourth transistor and the source of the fifth transistor are connected and grounded. The gate of the fourth transistor is connected to the first differential input signal. The gate of the fifth transistor is connected to the second differential input signal. The gate of the second transistor is connected to the first terminal of the first resistor, and the second terminal of the first resistor is grounded. The gate of the seventh transistor is connected to the first terminal of the second resistor, and the second terminal of the second resistor is grounded.

[0053] It should be noted that, as Figure 2As shown, A1 is a fully differential amplifier with hysteresis control. M4 and M5 are differential input transistors, with their gates connected to the differential input signals of the entire comparator. M3 or M6 is connected as a diode MOSFET, achieving a low-gain, high-bandwidth effect. M1 and M8 are the two transistors controlling the hysteresis action of the comparator. The gates of M2 and M7 are pulled down to ground by default through resistors R1 and R2, and M2 and M7 operate in the linear region. Due to unavoidable deviations in the manufacturing process, mismatches may occur in the differential input transistors or current mirror transistors, resulting in comparator offset, i.e., an imbalance between INP and INN. In this case, appropriate voltages can be input externally to the VCTL_Hy_P or VCTL_Hy_N ports to adjust the gate voltage of M2 or M7, thereby changing their resistance values ​​and causing an imbalance in the current between the M3 and M6 branches. This compensates for the offset caused by the manufacturing process deviation and enhances the robustness of the circuit.

[0054] In a specific embodiment of the present invention, the first low-gain high-bandwidth fully differential amplifier, the second low-gain high-bandwidth fully differential amplifier, the third low-gain high-bandwidth fully differential amplifier, the fourth low-gain high-bandwidth fully differential amplifier, and the fifth low-gain high-bandwidth fully differential amplifier all have the same structure. The first low-gain high-bandwidth fully differential amplifier includes a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, and a twelfth transistor M12. The source of the ninth transistor is connected to the source of the twelfth transistor, the gate and drain of the ninth transistor are connected to the drain of the tenth transistor, the gate and drain of the twelfth transistor are connected to the drain of the eleventh transistor, and the source of the tenth transistor is connected to the source of the eleventh transistor.

[0055] It should be noted that the embodiments of the present invention only describe the structure of the first low-gain high-bandwidth fully differential amplifier. The circuit structures of the second, third, fourth, and fifth low-gain high-bandwidth fully differential amplifiers are the same as those of the first low-gain high-bandwidth fully differential amplifier. In particular, by using six stages of low-gain high-bandwidth fully differential amplifiers A1-A6, the entire comparator can obtain a very high open-loop gain-bandwidth product. Thus, for input signals with different slew rates and overdrive voltages, the response speed of the comparator is basically the same, thereby reducing the spread of propagation delay.

[0056] In a specific embodiment of the present invention, the decision circuit includes a 29th transistor M29, a 30th transistor M30, a 31st transistor M31, a 32nd transistor M32, a 33rd transistor M33, and a 34th transistor M34. The source of the 29th transistor is connected to the source of the 34th transistor. The gate of the 29th transistor is connected to a fifth low-gain high-bandwidth fully differential amplifier. The gate of the 34th transistor is also connected to the fifth low-gain high-bandwidth fully differential amplifier. The drain of the 29th transistor, the gate of the 32nd transistor, the drain of the 31st transistor, the gate of the 30th transistor, and the drain of the 30th transistor are connected to a differential input single-ended output amplifier. The drain of the 34th transistor, the gate of the 31st transistor, the drain of the 32nd transistor, the gate of the 33rd transistor, and the drain of the 33rd transistor are also connected to the differential input single-ended output amplifier. The source of the 30th transistor, the source of the 31st transistor, the source of the 32nd transistor, and the source of the 33rd transistor are connected.

[0057] In a specific embodiment of the present invention, the differential input single-ended output amplifier includes a 35th transistor M35, a 36th transistor M36, a 37th transistor M37, a 38th transistor M38, a 39th transistor M39, and a 40th transistor M40. The source of the 37th transistor is connected to both the decision circuit and the drive stage circuit. The gate of the 37th transistor, the drain of the 35th transistor, the drain of the 36th transistor, and the gate of the 38th transistor are connected. The drain of the 37th transistor, the source of the 35th transistor, and the source of the 39th transistor are connected. The gates of the 35th transistor and the 36th transistor are connected to the decision circuit. The gates of the 39th transistor and the 40th transistor are connected to the decision circuit. The drains of the 39th transistor and the 40th transistor are connected to the drive stage circuit. The sources of the 36th transistor, the 40th transistor, and the 38th transistor are connected. The source of the 38th transistor is grounded.

[0058] In this embodiment of the invention, A7 is the decision circuit of the comparator, introducing a cross-coupled pair (latch) of M31 and M32 to form a positive feedback path, used to increase the open-loop gain of the comparator, thus making the difference between the amplified differential signals larger. However, this stage also contributes significantly to the propagation delay spread, so a larger bias current needs to be provided to this stage to increase the open-loop gain-bandwidth product. Furthermore, the sizes of M31 and M32 cannot be too large; conversely, the sizes of M30 and M33 need to be larger to increase the bandwidth of this stage and reduce the gain, thereby further reducing the propagation delay spread contributed by this stage. A8 is the post-amplifier circuit of the self-biased differential structure, used to convert the differential signal into a single-ended signal. Since the swing of the decision circuit is very limited, A8 can be used to increase the output swing and provide additional gain.

[0059] The five-transistor operational amplifier module is used to acquire the differential input signal and amplify it to generate a current signal related to the slew rate of the differential input signal.

[0060] Specifically, the five-transistor operational amplifier module includes a first five-transistor operational amplifier OP1, a second five-transistor operational amplifier OP2, a third five-transistor operational amplifier OP3, a fourth five-transistor operational amplifier OP4, and a fifth five-transistor operational amplifier OP5. The first, second, third, fourth, and fifth five-transistor operational amplifiers are connected sequentially and have the same structure. The first five-transistor operational amplifier includes a fifty-fifth transistor, a fifty-sixth transistor, a fifty-seventh transistor, and a fifty-eighth transistor. The source of the fifty-fifth transistor is connected to the source of the fifty-eighth transistor and connected to a high level. The gate and drain of the fifty-fifth transistor are connected to the drain of the fifty-sixth transistor. The drains of the fifty-eighth transistor and the fifty-seventh transistor are connected to the second five-transistor operational amplifier. The gate of the fifty-sixth transistor is connected to the first differential input signal, the gate of the fifty-seventh transistor is connected to the second differential input signal, and the sources of the fifty-sixth and fifty-seventh transistors are connected and grounded.

[0061] In this embodiment of the invention, five simple five-transistor operational amplifiers with a static power consumption of 600nA are used to sample the input signal of the comparator. The output terminals of the five-transistor operational amplifiers are connected to the key output nodes of each stage of the comparator amplifier, that is, the output terminal of OP1 is connected to the non-inverting output terminal of A2, the output terminal of OP2 is connected to the non-inverting output terminal of A3, the output terminal of OP3 is connected to the inverting output terminal of A4, the output terminal of OP4 is connected to the non-inverting output terminal of A5, and the output terminal of OP5 is connected to the non-inverting output terminal of A6. For example, if the INN level is fixed while INP is changing, when the slope and overdrive of the input signal are both large, the output terminal of the five-transistor operational amplifier will have a strong pull-up capability, thereby slowing down the discharge speed of each key output node of the fully differential amplifier. In other words, the propagation delay of the input signal with a large slew rate and large overdrive is slightly increased, while for the input signal with a small slew rate and small overdrive, the five-transistor operational amplifier has almost no effect. Using this compensation principle, the propagation delay dispersion can be significantly reduced from more than 300ps to less than 100ps.

[0062] The hysteresis control module is used to control the positive and negative hysteresis thresholds of the differential amplifier module;

[0063] Specifically, the hysteresis control module includes transistors M51 (51), M52 (52), M53 (53), and M54 (54). The source of transistor M51 is connected to the source of transistor M53 and is connected to a high level. The drains of transistors M51 and M52 are connected to the hysteresis control fully differential amplifier. The gates of transistors M51, M52, M53, and M54 are connected to the hysteresis control fully differential amplifier. The source of transistor M52 is connected to the source of transistor M54 and is grounded. The gates of transistors M53 and M54 are connected to the differential input single-ended output amplifier.

[0064] The driver stage circuit is used to perform output drive processing based on single-ended signals and current signals, and output a digital signal containing phase information.

[0065] Specifically, the driver stage circuit includes a first-stage driver unit INV1, a second-stage driver unit INV2, a third-stage driver unit INV3, a fourth-stage driver unit INV4, and a fifth-stage driver unit INV5. The first-stage driver unit is connected to the second-stage driver unit and the third-stage driver unit, the second-stage driver unit is connected to the fourth-stage driver unit, and the third-stage driver unit is connected to the fifth-stage driver unit. The first-stage driver unit, the second-stage driver unit, the third-stage driver unit, the fourth-stage driver unit, and the fifth-stage driver unit have the same structure. The first-stage driver unit includes a forty-first transistor M41 and a forty-second transistor M42. The gates of the forty-first transistor and the forty-second transistor are connected to a differential input single-ended output amplifier. The source of the forty-first transistor is connected to the differential amplifier module and the second-stage driver unit, and the source of the forty-second transistor is connected to the differential amplifier module and the third-stage driver unit. The drains of the forty-first transistor and the forty-second transistor are connected to the second-stage driver unit and the third-stage driver unit.

[0066] In summary, the design principle of this invention is as follows: A high open-loop gain-bandwidth product is achieved by employing six stages of low-gain, high-bandwidth fully differential amplifiers A1-A6 to ensure that the comparator response speed is essentially the same for input signals with different slew rates and overdrive voltages, thereby reducing the propagation delay. Amplifier A1, after acquiring and amplifying the differential input signals INP and INN of the entire comparator, outputs a differential voltage signal to the two input terminals of amplifier A2. Amplifier A2, after acquiring and amplifying the differential output signal of amplifier A1, outputs a differential voltage signal to the two input terminals of amplifier A3. Amplifier A3, after acquiring and amplifying the differential output signal of amplifier A2, outputs a differential voltage signal to the two input terminals of amplifier A4. Amplifier A4, after acquiring and amplifying the differential output signal of amplifier A3, outputs a differential voltage signal to the two input terminals of amplifier A5. Amplifier A5, after acquiring and amplifying the differential output signal of amplifier A4, outputs a differential voltage signal to the two input terminals of amplifier A6. Amplifier A6, after acquiring and amplifying the differential output signal from amplifier A5, outputs a differential voltage signal to the two input terminals of amplifier A7. Amplifier A7 is the decision circuit of the comparator, generating the comparison logic. After acquiring and amplifying the differential output signal from amplifier A6, it outputs a differential voltage signal to the two input terminals of amplifier A8. Amplifier A8 is a self-biased differential amplifier stage used to convert the differential signal into a single-ended signal. After acquiring and amplifying the differential output signal from amplifier A7, it outputs a single-ended voltage signal to the input terminal of driver stage INV1. Driver stage INV1 outputs a voltage signal to the input terminal of INV2, while INV4 receives the signal from INV2 and generates the non-inverting output signal OUTP of the comparator. Driver stage INV1 outputs a voltage signal to the input terminal of INV3, while INV5 receives the signal from INV3 and generates the inverting output signal OUTN of the comparator. The driver stage circuit is used to improve the output driving capability of the comparator. OP1-OP5 acquire the differential input signals INP and INN of the entire comparator, amplify them, and then output small currents to the non-inverting output terminals of A2, A3, A4, A5, and A6, respectively, causing changes in the discharge rate of these nodes. When the overdrive voltage or slew rate of the comparator's input signal is very small, the discharge rate of these nodes remains almost constant, resulting in a nearly constant comparator propagation delay. However, when the overdrive voltage or slew rate of the comparator's input signal is very large, the discharge rate of these nodes slows down, increasing the comparator propagation delay. Using this compensation principle, the propagation delay dispersion can be significantly reduced from over 300 ps to less than 100 ps.The hysteresis control module INV6 receives the output voltage signal from amplifier A8 and outputs a signal to the input of INV7. The outputs of INV6 and INV7 control the HyN and HyP ports of A1, respectively, to control the hysteresis operation of the comparator. The positive and negative hysteresis thresholds of the comparator can be controlled by adjusting the voltages at the VCTL_Hy_P and VCTL_Hy_N ports of A1.

[0067] It should also be noted that, as Figure 3 The diagram shows the waveform simulation of INP, INN, and OUTP using a multi-stage low-gain, high-bandwidth, and five-transistor operational amplifier compensation structure provided in this embodiment of the application. From top to bottom, the waveforms of INP, INN, and OUTP are shown. When the voltage value of INP is greater than that of INN, OUTP outputs a high level; conversely, when the voltage value of INP is less than that of INN, OUTP outputs a low level. Therefore, in... Figure 3 The waveform of OUTP is a rising edge signal. The horizontal distance between the midpoint of the rising edge of all OUTP waveforms and the midpoint of the rising edge of the INP waveform is the propagation delay of the comparator. The range of variation of the propagation delay is the propagation delay spread of the comparator, i.e. the walking error.

[0068] Figure 4 This is a simulation diagram of the walking error provided in the embodiment of this application, which adopts a multi-stage low-gain high-bandwidth and five-transistor operational amplifier compensation structure. It shows the range of propagation delay variation under different slew rates and overdriven input signals. It can be seen that when the slew rate (horizontal axis) of the input signal changes from ±5mV to ±1.65V, the range of propagation delay variation (vertical axis) is 96.5ps, that is, the walking error is 96.5ps.

[0069] Figure 5 The simulation diagram of the walking error provided in this application embodiment only adopts a multi-stage low-gain high-bandwidth structure, showing the range of propagation delay variation under different slew rates and overdriven input signals. It can be seen that when the slew rate (horizontal axis) of the input signal changes from ±5mV to ±1.65V, the range of propagation delay variation (vertical axis) is 189.1ps, that is, the walking error is 189.1ps.

[0070] Figure 6 This is a simulation diagram of the walking error of a conventional high-speed comparator structure provided in the embodiments of this application. It shows the range of propagation delay variation under different slew rates and overdriven input signals. It can be seen that when the slew rate (horizontal axis) of the input signal changes from ±5mV to ±1.65V, the range of propagation delay variation (vertical axis) is 385.9ps, that is, the walking error is 385.9ps.

[0071] Please see Figure 7This application also provides a control method for a high-speed zero-crossing comparator with low travel error, which can realize the above-mentioned high-speed zero-crossing comparator with low travel error. The method includes:

[0072] S1. Determine the positive and negative hysteresis thresholds;

[0073] S2. Based on the positive and negative hysteresis thresholds, the differential input signal is acquired and amplified to generate a current signal;

[0074] S3. Convert the differential input signal and output a single-ended signal;

[0075] S4. Based on the single-ended signal and the current signal, perform output drive processing to output a digital signal containing phase information.

[0076] Therefore, the improvements of the embodiments of the present invention compared to the prior art are as follows:

[0077] 1) A six-stage low-gain, high-bandwidth fully differential amplifier is employed. The comparator achieves a very high open-loop gain-bandwidth product, ensuring that the comparator's response speed remains essentially the same for input signals with different slew rates and overdrive voltages. This reduces the propagation delay spread under on-rail input slew rates. Furthermore, the cascading of multiple low-gain, high-bandwidth stages can achieve very high slew rates with minimal zero-crossing drift error.

[0078] 2) Five simple, ultra-low quiescent power operational amplifiers (PVAs) are used to sample the comparator's input signal. The outputs of these PVAs are connected to the critical output nodes of each stage of the comparator. This slightly increases the propagation delay of input signals with large slew rates exceeding the drive, while having almost no effect on input signals with small slew rates less than the drive. This compensation principle further reduces the propagation delay spread under rail-to-rail input swing. Compared to other techniques for reducing propagation delay spread, the structure used in this invention is simple yet ingenious. It achieves a propagation delay spread of 96.5 ps (±48.3 ps travel error) under conditions of very low power consumption (only 5 mA), rail-to-rail input swing (input dynamic range of 1:330), and different input slew rates. Furthermore, the offset caused by process variations can be compensated by externally adjusting the positive and negative thresholds of the hysteresis, enhancing the circuit's robustness.

[0079] 3) The comparator is constructed using a pre-amplified regenerative latch structure. In addition to significantly reducing propagation delay, the comparator also has a lower offset voltage. Furthermore, adding a preamplifier in front of the latch comparator can effectively reduce kickback noise.

[0080] An application scenario of this invention can be as follows: In the time discrimination circuit of a lidar receiving system, the inverting input terminal INN of the comparator is connected to a fixed threshold, while the non-inverting input terminal of the comparator is connected to the echo signal. When the echo pulse arrives, the comparator outputs a rising edge signal to obtain the arrival time of the echo pulse. This rising edge signal serves as the input signal for the subsequent time-to-digital converter. Alternatively, it can be used in a level-crossing analog-to-digital converter, where the inverting input terminal INN of the comparator is connected to a fixed threshold, while the non-inverting input terminal of the comparator is connected to the input signal. When the input signal exceeds a set threshold, a sampling time is triggered, and the analog-to-digital converter begins to sample the signal.

[0081] It is understood that the content of the above method embodiments is applicable to this comparator embodiment. The specific functions implemented by this comparator embodiment are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0082] The preferred embodiments of the present application have been described above with reference to the accompanying drawings, but this does not limit the scope of the claims of the present application. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and substance of the embodiments of the present application shall be within the scope of the claims of the present application.

Claims

1. A high-speed zero-crossing comparator with low travel error, characterized in that, The high-speed zero-crossing comparator includes a differential amplifier module, a five-transistor operational amplifier module, a hysteresis control module, and a driver stage circuit. The output terminal of the differential amplifier module and the output terminal of the five-transistor operational amplifier module are connected to a first connection point. The first connection point is connected to the input terminal of the driver stage circuit and the input terminal of the hysteresis control module, respectively. The output terminal of the hysteresis control module is connected to the input terminal of the differential amplifier module. The differential amplifier module is used to acquire differential input signals and perform amplification and conversion processing to output single-ended signals. The differential amplifier module includes a hysteresis-controlled fully differential amplifier, a low-gain high-bandwidth fully differential amplifier module, a decision circuit, and a differential input single-ended output amplifier. The output terminal of the hysteresis-controlled fully differential amplifier is connected to the input terminal of the low-gain high-bandwidth fully differential amplifier module, the output terminal of the low-gain high-bandwidth fully differential amplifier module is connected to the input terminal of the decision circuit, and the output terminal of the decision circuit is connected to the input terminal of the differential input single-ended output amplifier. The five-transistor operational amplifier module is used to acquire the differential input signal and amplify it to generate a current signal related to the slew rate of the differential input signal. The hysteresis control module is used to control the positive and negative hysteresis thresholds of the differential amplifier module; The driver stage circuit is used to perform output driving processing based on the single-ended signal and the current signal, and output a digital signal containing phase information.

2. The high-speed zero-crossing comparator according to claim 1, characterized in that, The hysteresis-controlled fully differential amplifier is used to acquire the differential input signal and amplify it to output a differential signal after one stage of amplification; the differential input signal includes a first differential input signal and a second differential input signal; The low-gain high-bandwidth fully differential amplifier module includes a first low-gain high-bandwidth fully differential amplifier, a second low-gain high-bandwidth fully differential amplifier, a third low-gain high-bandwidth fully differential amplifier, a fourth low-gain high-bandwidth fully differential amplifier, and a fifth low-gain high-bandwidth fully differential amplifier. The low-gain high-bandwidth fully differential amplifier module is used to amplify the differential signal after the first stage of amplification step by step, and output a differential signal after six stages of amplification. The decision circuit is used to compare and latch the six-stage amplified differential signal and output the compared differential signal. The differential input single-ended output amplifier is used to convert the compared differential signal and output the single-ended signal.

3. The high-speed zero-crossing comparator according to claim 2, characterized in that, The hysteresis-controlled fully differential amplifier includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a first resistor, and a second resistor. The gate of the first transistor is connected to the hysteresis control module. The sources of the first transistor, the second transistor, the seventh transistor, and the eighth transistor are all connected to the first low-gain, high-bandwidth fully differential amplifier and connected to a high level. The drains of the first transistor and the second transistor are both connected to the source of the third transistor. The drain, gate, and fourth transistor of the third transistor are all connected to the first low-gain, high-bandwidth fully differential amplifier. A wide-gain, high-bandwidth, fully differential amplifier is connected. The drains of the seventh and eighth transistors are both connected to the source of the sixth transistor. The gate, drain, and drain of the sixth and fifth transistors are all connected to the first low-gain, high-bandwidth, fully differential amplifier. The source of the fourth transistor is connected to the source of the fifth transistor and grounded. The gate of the fourth transistor is connected to the first differential input signal. The gate of the fifth transistor is connected to the second differential input signal. The gate of the second transistor is connected to the first terminal of the first resistor, and the second terminal of the first resistor is grounded. The gate of the seventh transistor is connected to the first terminal of the second resistor, and the second terminal of the second resistor is grounded.

4. The high-speed zero-crossing comparator according to claim 2, characterized in that, The first, second, third, fourth, and fifth low-gain high-bandwidth fully differential amplifiers all have the same structure. The first low-gain high-bandwidth fully differential amplifier includes a ninth transistor, a tenth transistor, an eleventh transistor, and a twelfth transistor. The source of the ninth transistor is connected to the source of the twelfth transistor, the gate and drain of the ninth transistor are both connected to the drain of the tenth transistor, the gate and drain of the twelfth transistor are both connected to the drain of the eleventh transistor, and the source of the tenth transistor is connected to the source of the eleventh transistor.

5. The high-speed zero-crossing comparator according to claim 2, characterized in that, The decision circuit includes a 29th transistor, a 30th transistor, a 31st transistor, a 32nd transistor, a 33rd transistor, and a 34th transistor. The source of the 29th transistor is connected to the source of the 34th transistor. The gate of the 29th transistor is connected to the fifth low-gain high-bandwidth fully differential amplifier. The gate of the 34th transistor is also connected to the fifth low-gain high-bandwidth fully differential amplifier. The drains of the 29th transistor, the gates of the 32nd transistor, the 31st transistor, the 30th transistor, and the 30th transistor are all connected to the differential input single-ended output amplifier. The drains of the 34th transistor, the gates of the 31st transistor, the 32nd transistor, the 33rd transistor, and the 33rd transistor are all connected to the differential input single-ended output amplifier. The sources of the 30th transistor, the 31st transistor, and the 32nd transistor are all connected to the source of the 33rd transistor.

6. The high-speed zero-crossing comparator according to claim 2, characterized in that, The differential input single-ended output amplifier includes a 35th transistor, a 36th transistor, a 37th transistor, a 38th transistor, a 39th transistor, and a 40th transistor. The source of the 37th transistor is connected to both the decision circuit and the driver stage circuit. The gate of the 37th transistor, the drain of the 35th transistor, and the drain of the 36th transistor are all connected to the gate of the 38th transistor. The drain of the 37th transistor, the source of the 35th transistor, and the source of the 39th transistor are all connected to the source of the 39th transistor. The gates of the 35th transistor and the 36th transistor are all connected to the decision circuit. The gates of the 39th transistor and the 40th transistor are all connected to the decision circuit. The drains of the 39th transistor and the 40th transistor are all connected to the driver stage circuit. The sources of the 36th transistor and the 40th transistor are all connected to the drain of the 38th transistor. The source of the 38th transistor is grounded.

7. The high-speed zero-crossing comparator according to claim 2, characterized in that, The five-transistor operational amplifier module includes a first five-transistor operational amplifier, a second five-transistor operational amplifier, a third five-transistor operational amplifier, a fourth five-transistor operational amplifier, and a fifth five-transistor operational amplifier. These five operational amplifiers are connected sequentially and have the same structure. The first five-transistor operational amplifier includes a fifty-fifth transistor, a fifty-sixth transistor, a fifty-seventh transistor, and a fifty-eighth transistor. The source of the 55th transistor is connected to the source of the 58th transistor and is connected to a high level. The gate and drain of the 55th transistor are both connected to the drain of the 56th transistor. The drain of the 58th transistor and the drain of the 57th transistor are connected together and serve as the output terminal of the first five-transistor operational amplifier. The output terminal of the first five-transistor operational amplifier is connected to the non-inverting output terminal of the first low-gain high-bandwidth fully differential amplifier. The gate of the 56th transistor is connected to the first differential input signal, and the gate of the 57th transistor is connected to the second differential input signal. The sources of the 56th transistor and the 57th transistor are connected together and grounded.

8. The high-speed zero-crossing comparator according to claim 2, characterized in that, The hysteresis control module includes a 51st transistor, a 52nd transistor, a 53rd transistor, and a 54th transistor. The source of the 51st transistor is connected to the source of the 53rd transistor and is connected to a high level. The drains of the 51st transistor and the 52nd transistor are both connected to the hysteresis control fully differential amplifier. The gates of the 51st transistor, the 52nd transistor, the 53rd transistor, and the 54th transistor are all connected to the hysteresis control fully differential amplifier. The source of the 52nd transistor is connected to the source of the 54th transistor and is grounded. The gates of the 53rd transistor and the 54th transistor are both connected to the differential input single-ended output amplifier.

9. The high-speed zero-crossing comparator according to claim 6, characterized in that, The driving stage circuit includes a first-stage driving unit, a second-stage driving unit, a third-stage driving unit, a fourth-stage driving unit, and a fifth-stage driving unit. The first-stage driving unit is connected to the second-stage driving unit and the third-stage driving unit, respectively. The second-stage driving unit is connected to the fourth-stage driving unit, and the third-stage driving unit is connected to the fifth-stage driving unit. The first-stage driving unit, the second-stage driving unit, the third-stage driving unit, the fourth-stage driving unit, and the fifth-stage driving unit have the same structure. The first-stage driving unit includes a forty-first transistor and a forty-second transistor. The gates of the forty-first transistor and the forty-second transistor are both connected to the drain of the thirty-ninth transistor. The source of the forty-first transistor is connected to a high level, and the source of the forty-second transistor is grounded. The drains of the forty-first transistor and the forty-second transistor are connected and then connected to the second-stage driving unit and the third-stage driving unit, respectively.

Images