Perform a read operation before two-pass programming of the memory system

Abstract

Embodiments of the present application relate to performing a read operation prior to two-pass programming of a memory system. Data is read from a first portion of memory cells in a plurality of memory cells. A first programming pass is performed on another memory cell in the plurality of memory cells by providing new data to the other memory cell. A second programming pass is performed on the memory cell by providing additional data to the first portion of the memory cell based on the read of the first portion of the memory cell. The first programming pass and the second programming pass correspond to two programming passes associated with the plurality of memory cells.

Description

[0001] Information about divisional applications

[0002] This application is a divisional application of the invention patent application with the application date of March 7, 2018, application number "201880092010.9", and invention name "Performing a read operation before two-pass programming of a storage system". Technical Field

[0003] The present disclosure relates generally to a memory system, and more particularly, to performing a read operation prior to two-pass programming of the memory system. Background Art

[0004] A storage system (e.g., a solid-state drive) may include one or more memory components that store data. For example, the storage system may include memory devices, such as non-volatile memory devices. The storage system may further include a controller that can manage each of the memory devices and allocate data to be stored in the memory devices. A host system can utilize the storage system and request data from the storage system. The controller can retrieve data from the corresponding memory device and return the retrieved data to the host system. Summary of the Invention

[0005] According to an embodiment of the present disclosure, a system is provided. The system includes a memory and a processing device. The processing device is operably coupled to the memory to perform the following operations: reading data from a first memory cell among a plurality of memory cells; determining whether the data stored in the first memory cell includes an error; upon determining that the data stored in the first memory cell includes the error, determining whether an error correction operation for the data stored in the first memory cell is successful; and in response to determining that the error correction operation for the data stored in the first memory cell is unsuccessful, performing the following operations: identifying a second memory cell among the plurality of memory cells; and performing, by the processing device, a two-pass programming operation on the second memory cell instead of the first memory cell.

[0006] According to an embodiment of the present disclosure, a method is provided. The method includes: reading data from a first memory cell among a plurality of memory cells; determining whether the data stored in the first memory cell includes an error; upon determining that the data stored in the first memory cell includes the error, determining whether an error correction operation for the data stored in the first memory cell is successful; and in response to determining that the error correction operation for the data stored in the first memory cell is unsuccessful, identifying a second memory cell among the plurality of memory cells; and performing, by a processing device, a two-pass programming operation on the second memory cell instead of the first memory cell.

[0007] According to an embodiment of the present disclosure, a non-transitory computer-readable storage medium is provided. The non-transitory computer-readable storage medium includes instructions that, when executed by a processing device, cause the processing device to: read data from a first memory cell among a plurality of memory cells; determine whether the data stored in the first memory cell includes an error; upon determining that the data stored in the first memory cell includes the error, determine whether an error correction operation for the data stored in the first memory cell is successful; and in response to determining that the error correction operation for the data stored in the first memory cell is unsuccessful, identify a second memory cell among the plurality of memory cells; and perform, by the processing device, a two-pass programming operation on the second memory cell instead of the first memory cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The present disclosure will be more fully understood from the detailed description given below and the accompanying drawings of various embodiments of the present disclosure.

[0009] Figure 1 An example computing environment including a storage system according to some embodiments of the present disclosure is described.

[0010] Figure 2 is a flow chart of an example method for performing a read operation prior to two-pass programming, according to some embodiments of the present disclosure.

[0011] Figure 3 is a flow chart of an example method for performing error correction operations on data read at portions of memory cells, according to some embodiments of the present disclosure.

[0012] Figure 4 An example of performing two-pass programming on memory cells of a memory device according to some embodiments of the present disclosure is described.

[0013] Figure 5 is a block diagram of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0014] Aspects of the present disclosure relate to performing a read operation prior to two-pass programming of a storage system. Generally speaking, a host system may utilize a storage system comprising one or more memory devices. An example of a storage system is a solid-state drive (SSD). The host system may provide data to be stored at the storage system and may request retrieval of data from the storage system.

[0015] A storage system may store data in a memory device included in the storage system. The memory device may include memory cells. Each of the memory cells may store one or more bits of binary data corresponding to data received from a host system. The memory device may include quad-level cell (QLC) memory. In QLC memory, each memory cell may store four bits of data. For example, in QLC memory, a memory cell may store four bits of data corresponding to data received from the host system (e.g., 1111, 0000, 1101, etc.). Each bit of the memory cell is stored in a different portion of the memory cell (hereinafter also referred to as a "page"). The memory cells of the QLC memory may have a total of four pages. For example, the memory cell may include a lower page (LP), an upper page (UP), an extra page (XP), and a first page (TP), each of which stores a data bit. For example, a bit may be represented by each of the four pages of the memory cell.

[0016] Generally speaking, a storage system may receive a request from a host system to perform a programming operation to store data in a QLC memory. The storage system may then perform a two-pass programming operation on the memory cells. During the first programming pass of the two-pass programming operation, a controller may program or write data to three portions of the memory cells of the storage system. For example, the controller may program (e.g., write data to) the LP, UP, and XP portions of the memory cells.

[0017] In flash memory, memory cells that are adjacent or proximate to each other can be coupled so that data provided to a first memory cell can modify data previously stored at a second memory cell that is adjacent or proximate to the first memory cell. For example, programming the LP, UP, and XP of a first memory cell can modify the data stored at XP of a second memory cell. The modification can be the result of the voltage applied to program the first memory cell also affecting the voltage of the data stored at the second memory cell. This modification of XP of the second memory cell can result in errors in the data stored at XP of the second memory cell. Therefore, the programming operation performed on the first memory cell during the first programming pass can increase the error rate of the data previously stored at the second memory cell that is adjacent or proximate to the first memory cell. Therefore, during the second programming pass in a conventional two-pass programming operation, the storage system can perform a read operation on the first portion of the second memory cell. For example, the storage system can perform a read operation on XP of the second memory cell.

[0018] During the execution of a read operation, the storage system may determine whether the data stored at XP of the second memory cell includes an error. If the storage system determines that the data stored at XP of the second memory cell includes an error, the storage system may use an error correction operation to correct the error at XP of the second memory cell. During a second programming pass of the second memory cell, the storage system may also program a second portion of the second memory cell. For example, the storage system may perform a programming operation on TP of the second memory cell after performing a read operation and error correction on XP of the second memory cell. The controller may then program the first portion of the second memory cell. For example, the storage system may program XP of the second memory cell by providing data corrected by the error correction operation during the read operation to XP, and may program TP of the second memory cell after the corrected data is provided to XP.

[0019] However, the data transfer rate (hereinafter also referred to as "bandwidth") of a flash memory may change between a first programming pass and a second programming pass. For example, the bandwidth during the first programming pass may be greater than the bandwidth during the second programming pass. Therefore, performing three operations (e.g., a read operation of XP and two programming operations of TP and XP) during the second programming pass having a lower bandwidth than the first programming pass may increase the latency of the memory system when performing programming or writing operations, thereby reducing the performance of the memory system.

[0020] Furthermore, in conventional memory systems, if power is lost during a two-pass programming operation, there may not be sufficient time to read data from the memory device and perform any error correction operations on the data. Consequently, the data may be read after the two-pass programming operation has completed. If the data contains errors and the error correction operation to correct the errors is unsuccessful, the data previously programmed into the memory cells during the two-pass programming operation may be reprogrammed into new memory cells. This results in an increased number of programming operations performed on the memory device because the same data is programmed twice (e.g., once into the memory cells associated with the unsuccessful error correction operation and once into the new memory cells). This may result in increased latency in the memory system when performing programming or write operations, thereby reducing the performance of the memory system.

[0021] Aspects of the present disclosure address the above and other drawbacks by performing a read operation prior to a two-pass programming operation. The read operation may be performed on a first portion of memory cells of a memory device. During the read operation, errors associated with data stored in the first portion of the memory cells may be identified. If errors are identified, an error correction operation may be performed on the data to correct the data. A first programming pass in a two-pass programming operation may be performed by providing data to be stored in another memory cell.

[0022] The second programming pass of the two-pass programming operation is then performed on the memory cells read prior to the first programming pass. The storage system performs the second programming pass by providing data to the first portion of the memory cell based on the read operation performed on the first portion of the memory cell prior to the first programming pass. In one embodiment, data corrected by the error correction operation is provided for storage at the first portion of the memory cell. For example, the corrected data may be provided to the XP of the memory cell. In some embodiments, the data read from the first portion of the memory cell may be determined to contain no errors. Therefore, the data read during the first programming pass may be provided to the first portion of the memory cell to refresh the data stored at the memory cell.

[0023] Thus, by performing an additional operation (e.g., a read operation of memory cells) before a second programming pass having a lower bandwidth than the first programming pass, performing a read operation before a two-pass programming operation can result in improved performance of the memory system. Thus, the overall time required to perform both the first and second programming passes at the memory system is reduced. Thus, the performance of the memory system can be improved by reducing latency in the memory system when programming or writing data to the memory system.

[0024] Additionally, performing a read operation before a two-pass programming operation can improve the performance of the storage system in the event of a power loss. By performing a read operation before performing a two-pass programming operation, an unsuccessful error correction operation on the data can be identified before any programming operation is performed on the memory cells containing the data associated with the unsuccessful error correction operation. In response to the unsuccessful error correction operation, new memory cells can be identified for which a two-pass programming operation will be performed, rather than the memory cells storing the data associated with the unsuccessful error correction operation. This can reduce the number of programming operations performed by the storage system, thereby improving the performance of the storage system by reducing the latency of the storage system in the event of a power loss.

[0025] Figure 1An example computing environment 100 including a memory system according to some embodiments of the present disclosure is illustrated. The memory system may include media, such as memory devices 112A through 112N. Memory devices 112A through 112N may be volatile memory devices, non-volatile memory devices, or a combination of such devices. In some embodiments, the memory system is a storage system (e.g., storage system 110). An example of storage system 110 is a solid-state drive (SSD). Generally speaking, computing environment 100 may include a host system 120 that utilizes storage system 110. In some embodiments, host system 120 may write data to storage system 110 and read data from storage system 110. In some embodiments, the memory system is a hybrid memory / storage system.

[0026] Host system 120 may be a computing device, such as a desktop computer, a laptop computer, a network server, a mobile device, or any other computing device that includes memory and processing devices. Host system 120 may include or be coupled to storage system 110, such that host system 120 can read data from or write data to storage system 110. Host system 120 may be coupled to storage system 110 via a physical host interface. As used herein, "coupled to" generally refers to a connection between components, which may be an indirect communication connection or a direct communication connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical, optical, magnetic, and the like. Examples of physical host interfaces include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), and the like. The physical host interface may be used to transfer data between host system 120 and storage system 110. When storage system 110 is coupled to host system 120 via a PCIe interface, host system 120 may further utilize an NVM Express (NVMe) interface to access memory devices 112A-112N. A physical host interface may provide an interface for passing control, address, data, and other signals between storage system 110 and host system 120.

[0027] like Figure 1As shown in , storage system 110 may include a controller 111 and memory devices 112A-112N. In some embodiments, memory devices 112A-112N may be based on non-volatile memory. In some embodiments, memory devices 112A-112N may be NAND-type flash memory. Each of memory devices 112A-112N may include one or more arrays of memory cells, such as single-level cells (SLC) or multi-level cells (MLC) (e.g., triple-level cells (TLC) or quad-level cells (QLC)). In some embodiments, a particular memory device may include both an SLC portion and an MLC portion of memory cells. Each of the memory cells may store a data bit (e.g., a data block) used by host system 120. Although non-volatile memory devices such as NAND-type flash memory are described, memory devices 112A-112N may be based on any other type of memory, such as volatile memory. In some implementations, memory devices 112A-112N may be, but are not limited to, random access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), phase change memory (PCM), magnetic random access memory (MRAM), NOR (NOR) flash memory, electrically erasable programmable read-only memory (EEPROM), and a cross-point array of non-volatile memory cells. A cross-point array of non-volatile memory may be combined with a stackable cross-grid data access array to perform bit storage based on changes in bulk resistance. Additionally, in contrast to many flash-based memories, cross-point non-volatile memory may perform write-in-place operations, where non-volatile memory cells may be programmed without previously erasing them. Furthermore, the memory cells of memory devices 112A-112N may be grouped into memory pages or data blocks, which may refer to cells of a memory device used to store data.

[0028] Controller 111 can communicate with memory devices 112A-112N to perform operations, such as reading, writing, or erasing data at memory devices 112A-112N, and other such operations. Controller 111 can include hardware, such as one or more integrated circuits and / or discrete components, a processing device, or a buffer memory; software, such as firmware or other instructions; or a combination thereof. Generally, controller 111 can receive commands or operations from host system 120 and convert them into instructions or appropriate commands to achieve the desired access to memory devices 112A-112N. Controller 111 can be responsible for other operations associated with memory devices 112A-112N, such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address translation between logical block addresses and physical addresses. Controller 111 can further include host interface circuitry to communicate with host system 120 via a physical host interface. The host interface circuitry may convert commands received from the host system into command instructions to access the memory devices 112A- 112N, and convert responses associated with the memory devices 112A- 112N into information for the host system 120 .

[0029] refer to Figure 1 , controller 111 may include a programming sequence component 113 that can be used to perform programming operations (e.g., first and second programming passes) on memory devices 112A-112N. Programming sequence component 113 can identify memory cells of memory devices 112A-112N. Programming sequence component 113 can perform a first programming pass on the identified memory cells. Subsequently, programming sequence component 113 can perform a second programming pass on the identified memory cells. In some implementations, programming sequence component 113 can perform error correction operations on data read from the identified memory cells. Additional details regarding the operation of programming sequence component 113 are described below.

[0030] The memory system 110 may also include additional circuitry or components not illustrated. In some implementations, the memory system 110 may include caches and buffers (e.g., DRAM), and address circuitry (e.g., row decoders and column decoders) that can receive and decode addresses from the controller 111 to access the memory devices 112A-112N.

[0031] Figure 2is a flow chart of an example method 200 for performing a read operation before two-pass programming according to some embodiments of the present disclosure. The method 200 may be performed by processing logic, which may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 200 may be performed by Figure 1 The programming sequence component 113 executes.

[0032] At block 210, a first portion of memory cells of a memory device is read. For example, data at XP of the memory cell may be read. In some implementations, the data read from the first portion of the memory cell was written to the memory cell during a previous programming operation (e.g., the previous first programming pass of a previous two-pass programming operation). In one implementation, the first portion of the memory cell is read in response to a request to store additional data in the memory device. In some implementations, a processing device may determine that the data read from the first portion of the memory cell contains an error. Therefore, an error correction operation may be performed on the data read from the first portion. In some implementations, an error correction code (ECC) operation or another type of error detection and correction operation may be used to detect and correct errors. For example, if the data read from the first portion of the memory cell corresponds to a value of 1, the error may be corrected by changing the value from 1 to 0. At block 220, a first programming pass is performed on another memory cell of the memory device. For example, new data may be provided to the other memory cell. In some implementations, the memory cell read at block 210 and the other memory cell may be on the same word line of the memory device. For example, a memory cell can be coupled to another memory cell on the same word line. In one embodiment, data can be provided to the LP, UP, and XP of another memory cell. For example, data received from a host system can be written to the LP, UP, and XP of another memory cell.

[0033] At block 230, a second programming pass is performed on the memory cell by providing additional data to the second portion of the memory cell. For example, the additional data may be provided to the TP of the second memory cell. In some embodiments, the data provided to the TP of the second memory cell may correspond to data received from the host system. At block 240, the second programming pass provides data to the first portion of the memory cell based on the read of the first portion of the memory cell. For example, if the data read at XP of the memory cell at block 210 contains an error, the processing device may provide corrected data to XP of the memory cell. In an embodiment, the processing device may determine that the data read at XP does not contain an error. Therefore, the processing device may provide the data read at block 210 to XP of the memory cell to refresh the data stored at XP of the memory cell.

[0034] Thus, a two-pass programming operation can be performed with respect to the first memory cell and the second memory cell. Before performing the first programming pass of the two-pass programming operation, a read operation can be performed to retrieve data from a portion of the second memory cell. The retrieved data was programmed into the second memory cell during the previous two-pass programming operation. Errors from the retrieved data can be corrected to produce corrected data. The first programming pass of the two-pass programming operation can be performed on the first memory cell. Then, the second programming pass can provide additional data to another portion of the second memory cell. Then, a second programming pass can be performed on the second memory cell by providing the corrected data to the portion of the second memory cell. Therefore, if another programming pass inadvertently changes the data stored at the portion of the second memory cell, providing the corrected data to the second portion of the memory cell can ensure that the data stored at the portion of the second memory cell does not contain errors.

[0035] Figure 3 is a flow chart of an example method 300 for performing error correction operations on data read at a portion of a memory cell according to some embodiments of the present disclosure. The method 300 may be performed by processing logic, which may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, the method 300 may be performed by Figure 1 The programming sequence component 113 executes.

[0036] At block 310, a portion of a memory cell is read. For example, data may be read from the XP of a memory cell that was previously programmed as part of a first programming pass in a previous two-pass programming operation. At block 320, the processing device determines whether the data stored at the portion of the memory cell contains an error. For example, the processing device may determine whether the data stored at the XP of the memory cell contains an error. At block 330, if the portion of the memory cell does not contain an error, data may be provided to the portion of the memory cell. For example, the processing device may provide the data read at block 310 to the XP of the memory cell. In one embodiment, the processing device may provide the data to the portion of the memory cell during a second programming pass of a new two-pass programming operation.

[0037] At block 340, if the processing device determines that the portion of the memory cell contains an error, the processing device may perform an error correction operation on the data. For example, the processing device may perform an error correction operation corresponding to ECC. In one embodiment, the processing device may correct the error by switching a bit value of the data from 0 to 1 or vice versa. At block 350, the corrected data may be provided to the portion of the memory cell. For example, the corrected data from block 340 may be provided to the XP of the memory cell. In one embodiment, the corrected data may be provided to the portion of the second memory cell during the second programming pass of a two-pass programming operation.

[0038] Figure 4 An example of performing a two-pass programming operation on a memory cell 400 of a memory device according to some embodiments of the present disclosure is described. In some implementations, the memory cell 400 may be programmed twice. Figure 1 The programming sequence component 113 performs a two-pass programming operation. As previously discussed, a two-pass programming operation can be performed on a first memory cell and a second memory cell in the memory cell 400 of the memory device. In an embodiment, the first memory cell and the second memory cell can be QLC memory.

[0039] Prior to the first programming pass, a processing device performs a read operation on a memory cell. For example, a read operation may be performed on the XP of a memory cell (e.g., XP1). In some embodiments, an error correction operation may be performed on the data read from the memory cell. During the first programming pass, a programming operation may be performed on a first portion of another memory cell. For example, data may be provided to the LP of another memory cell. In some embodiments, programming of the LP of another memory cell may begin during or after the read operation is performed on the XP of the memory cell. A programming operation may be performed on a second portion of the other memory cell. For example, data may be provided to the UP of another memory cell. In one embodiment, the UP of another memory cell may be programmed during programming of the LP of another memory cell and / or reading of the XP of the memory cell. A programming operation may be performed on a third portion of the other memory cell. For example, data may be provided to the XP of another memory cell (e.g., XP2). In one implementation, the XP of another memory cell can be programmed during programming of the LP of another memory cell, reading of the XP of a memory cell, and / or programming of the UP of another memory cell.

[0040] The processing device may begin performing a second programming pass on the memory cell. The second programming pass may begin by performing a programming operation on the second portion of the memory cell. For example, data may be provided to the TP of the memory cell. The programming operation may be performed on the first portion of the memory cell. For example, data may be provided to the XP of the memory cell (e.g., XP1). In one embodiment, as previously discussed, corrected data may be provided to the XP of the memory cell based on a read operation on the first portion of the memory cell. In some embodiments, the XP of the memory cell may be programmed during programming of the TP of the memory cell.

[0041] Figure 5 An example machine is illustrated as a computer system 500 within which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. For example, the computer system 500 may correspond to a computer system that includes or utilizes a storage system (e.g., Figure 1 storage system 110) of a host system (e.g., Figure 1 host system 120), or can be used to perform operations of the controller (e.g., execute an operating system to perform operations corresponding to Figure 1In some embodiments, the machine may be connected (e.g., using a network) to other machines. The machine may operate in the capacity of a server or a client machine in a client-server network environment, or in the capacity of a server or a client machine in a peer-to-peer (or distributed) network environment.

[0042] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions that specify actions to be taken by the machine. Further, while a single machine is described, the term "machine" shall also be taken to include any collection of machines that individually or collectively execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0043] The example computer system 500 includes a processing device 502, a main memory 504 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), etc.), a static memory 506 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 518, which communicate with each other via a bus 530.

[0044] Processing device 502 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, or the like. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, a processor implementing other instruction sets, or a processor implementing a combination of instruction sets. Processing device 502 may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like. Processing device 502 is configured to execute instructions 526 for performing the operations and steps discussed herein. Computer system 500 may further include a network interface device 508 for communicating over a network 520.

[0045] The data storage system 518 may include a machine-readable storage medium 524 (also referred to as a computer-readable medium) having stored thereon one or more instructions 526 or sets of software embodying any one or more of the methodologies or functions described herein. The instructions 526 may also reside, completely or at least partially, within the main memory 504 and / or within the processing device 502 during execution thereof by the computer system 500, with the main memory 504 and the processing device 502 also constituting machine-readable storage media. The machine-readable storage medium 524, the data storage system 518, and / or the main memory 504 may correspond to Figure 1 storage system 110.

[0046] In one embodiment, instructions 526 include instructions for implementing a program corresponding to a programming sequence component (e.g., Figure 1 13). Although the machine-readable storage medium 524 is shown as a single medium in the example embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media (e.g., a centralized or distributed database, and / or associated caches and servers) that store one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium that can store or encode a set of instructions for execution by a machine and cause the machine to perform any one or more of the methods of the present disclosure. Thus, the term "machine-readable storage medium" should be considered to include, but not be limited to, solid-state memory, optical media, and magnetic media.

[0047] Some portions of the previous detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means by which those skilled in the data processing arts most effectively convey the substance of their work to others skilled in the art. An algorithm is herein and generally conceived to be a self-consistent sequence of steps producing a desired result. Operations are those requiring physical manipulation of physical quantities. Typically, but not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise controlled. At times, it has proven convenient, primarily for common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0048] It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless expressly stated otherwise, as is apparent from the foregoing discussion, it should be understood that throughout the description, aspects of the present disclosure may refer to the actions and processes of a computer system or similar electronic computing device that controls and transforms data represented as physical (electronic) quantities within a computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0049] The present disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specially constructed for the desired purpose, or it may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in the computer. This computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any other type of medium suitable for storing electronic instructions and each coupled to a computer system bus.

[0050] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems may be used with the programs according to the teachings herein, or it may prove convenient to construct more specialized devices to perform the methods. The structures of various such systems will become apparent as described below. Additionally, the present disclosure is not described with reference to any particular programming language. It will be appreciated that the teachings of the present disclosure as described herein may be implemented using a variety of programming languages.

[0051] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having stored thereon instructions that can be used to program a computer system (or other electronic device) to perform processes according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). For example, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory device, and the like.

[0052] In the foregoing description, the embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made thereto without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. Accordingly, the description and drawings are to be regarded in an illustrative rather than a restrictive sense.

Claims

1. A system comprising: Memory; and a processing device operatively coupled to the memory to: reading data from a first memory cell of the plurality of memory cells; determining whether the data stored in the first memory unit includes an error; Upon determining that the data stored in the first memory unit includes the error, determining whether an error correction operation on the data stored in the first memory unit is successful; and In response to determining that the error correction operation on the data stored in the first memory unit is unsuccessful, performing the following operations: identifying a second memory cell among the plurality of memory cells; and A two-pass programming operation is performed by a processing device on the second memory cell instead of the first memory cell.

2. The system according to claim 1, wherein the processing device is further configured to: In response to determining that the error correction operation on the data stored in the first memory cell is successful, corrected data is provided to the first memory cell.

3. The system of claim 1 , wherein to perform the two-pass programming operation on the second memory cell, the processing device is further configured to: performing a first programming pass on the second memory cell by providing new data to the second memory cell; and A second programming pass is performed on the second memory cell by providing additional data to the second memory cell.

4. The system according to claim 3, wherein in order to provide the new data to the second memory unit, the processing device is further configured to: The new data is provided to a plurality of pages of the second memory cells.

5. The system of claim 3 , wherein to perform the second programming pass on the second memory cell, the processing device is further configured to: The additional data is provided to a particular page of the second memory cells.

6. The system of claim 1, wherein the first memory cell and the second memory cell of the plurality of memory cells are on a same word line.

7. The system of claim 1 , wherein the processing device is further configured to: determining that the data stored in the first memory unit does not include errors; and In response to determining that the data stored in the first memory cell does not include errors, additional data is provided to refresh the data stored in the first memory cell among the plurality of memory cells.

8. A method comprising: reading data from a first memory cell of the plurality of memory cells; determining whether the data stored in the first memory unit includes an error; Upon determining that the data stored in the first memory unit includes the error, determining whether an error correction operation on the data stored in the first memory unit is successful; and In response to determining that the error correction operation on the data stored in the first memory unit is unsuccessful, performing the following operations: identifying a second memory cell among the plurality of memory cells; and A two-pass programming operation is performed by a processing device on the second memory cell instead of the first memory cell.

9. The method according to claim 8, further comprising: In response to determining that the error correction operation on the data stored in the first memory cell is successful, corrected data is provided to the first memory cell.

10. The method of claim 8, wherein performing the two-pass programming operation on the second memory cell comprises: performing a first programming pass on the second memory cell by providing new data to the second memory cell; and A second programming pass is performed on the second memory cell by providing additional data to the second memory cell.

11. The method of claim 10 , wherein providing the new data to the second memory unit comprises: The new data is provided to a plurality of pages of the second memory cells.

12. The method of claim 10, wherein performing the second programming pass on the second memory cell comprises: The additional data is provided to a particular page of the second memory cells.

13. The method of claim 8, wherein the first and second memory cells of the plurality of memory cells are on a same word line.

14. The method according to claim 8, further comprising: determining that the data stored in the first memory unit does not include errors; and In response to determining that the data stored in the first memory cell does not include errors, additional data is provided to refresh the data stored in the first memory cell among the plurality of memory cells.

15. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to: reading data from a first memory cell of the plurality of memory cells; determining whether the data stored in the first memory unit includes an error; Upon determining that the data stored in the first memory unit includes the error, determining whether an error correction operation on the data stored in the first memory unit is successful; and In response to determining that the error correction operation on the data stored in the first memory unit is unsuccessful, performing the following operations: identifying a second memory cell among the plurality of memory cells; and A two-pass programming operation is performed by a processing device on the second memory cell instead of the first memory cell.

16. The non-transitory computer-readable storage medium of claim 15, the operations further comprising: In response to determining that the error correction operation on the data stored in the first memory cell was unsuccessful, corrected data is provided to the first memory cell.

17. The non-transitory computer-readable storage medium of claim 15, wherein performing the two-pass programming operation on the second memory cell comprises: performing a first programming pass on the second memory cell by providing new data to the second memory cell; and A second programming pass is performed on the second memory cell by providing additional data to the second memory cell.

18. The non-transitory computer-readable storage medium of claim 17, wherein providing the new data to the second memory unit comprises: The new data is provided to a plurality of pages of the second memory cells.

19. The non-transitory computer-readable storage medium of claim 15, wherein the first memory cell and the second memory cell of the plurality of memory cells are on a same word line.

20. The non-transitory computer-readable storage medium of claim 15, the operations further comprising: determining that the data stored in the first memory unit does not include errors; and In response to determining that the data stored in the first memory cell does not include errors, additional data is provided to refresh the data stored in the first memory cell among the plurality of memory cells.

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