Method for manufacturing a semiconductor device and semiconductor device

Abstract

The present disclosure relates to a method for manufacturing a semiconductor device and a semiconductor device. A method for manufacturing a semiconductor device includes: providing a semiconductor substrate in which a trench is formed; irradiating a second portion of the semiconductor substrate adjacent to a first portion of the trench with a femtosecond laser beam such that non-thermal melting occurs in the second portion of the semiconductor substrate; and after completion of the irradiation with the femtosecond laser beam, performing a thermal oxidation process on the semiconductor substrate such that an oxide layer is formed in the second portion of the semiconductor substrate.

Description

Technical Field

[0001] The present disclosure generally relates to the field of semiconductors, and more particularly, to methods for manufacturing semiconductor devices and semiconductor devices. Background Art

[0002] Compared with silicon (Si), silicon carbide (SiC), as a representative of third-generation semiconductor materials, has more superior electrical characteristics such as a large bandgap width, a high critical breakdown electric field, a high thermal conductivity, a high carrier saturation drift rate, and strong radiation resistance. Relying on the electrical characteristics of SiC, semiconductor devices more suitable for application fields such as high voltage, high temperature, high frequency, and strong radiation can be developed. Among them, SiC metal oxide semiconductor field-effect transistors (MOSFETs) have received particular attention.

[0003] SiC MOSFETs commonly used in high-voltage and low-power scenarios are divided into trench-type SiC MOSFETs and planar SiC MOSFETs. Due to the presence of a junction field-effect transistor (JFET) region in the vertical-structured planar SiC MOSFET, the output DC resistance of the semiconductor device is relatively large, which limits the power threshold of the semiconductor device. In addition, the planar SiC MOSFET has a problem of channel mobility degradation caused by channel ion implantation. Compared with the traditional planar SiC MOSFET, the trench-type SiC MOSFET has no JFET region, can avoid the parasitic JFET effect (such as the additional resistance generated by the JFET region), can achieve an increased wafer density, and also has improved electrical properties such as a higher blocking voltage, better switching characteristics, and lower on-resistance. Summary of the Invention

[0004] A brief summary of the present disclosure is given below in order to provide a basic understanding of some aspects of the present disclosure. However, it should be understood that this summary is not an exhaustive summary of the present disclosure. It is not intended to identify the key or important parts of the present disclosure, nor is it intended to limit the scope of the present disclosure. Its purpose is only to present some concepts of the present disclosure in a simplified form as a prelude to the more detailed description given later.

[0005] According to a first aspect of the present disclosure, a method for manufacturing a semiconductor device is provided. The method includes: providing a semiconductor substrate in which a trench is formed; irradiating a second portion of the semiconductor substrate adjacent to a first portion of the trench with a femtosecond laser beam such that non-thermal melting occurs in the second portion of the semiconductor substrate; and after completion of the irradiation with the femtosecond laser beam, performing a thermal oxidation process on the semiconductor substrate such that an oxide layer is formed in the second portion of the semiconductor substrate.

[0006] In some embodiments, in the intact crystal structure of the semiconductor substrate, the oxidation rate of the crystal plane where the first portion of the trench is located is lower than the oxidation rate of the crystal plane where a third portion of the trench, which is different from the first portion, is located.

[0007] In some embodiments, the femtosecond laser beam is a first femtosecond laser beam, and the method further includes: before performing the thermal oxidation process on the semiconductor substrate, irradiating a fourth portion of the semiconductor substrate adjacent to the third portion of the trench with a second femtosecond laser beam such that non-thermal melting occurs in the fourth portion of the semiconductor substrate; after completion of the irradiation with the first femtosecond laser beam and the second femtosecond laser beam, performing a thermal oxidation process on the semiconductor substrate such that an oxide layer is formed in the second portion and the fourth portion of the semiconductor substrate, wherein the irradiation with the first femtosecond laser beam and the irradiation with the second femtosecond laser beam are configured such that the depth of the region where non-thermal melting occurs in the second portion of the semiconductor substrate is greater than the depth of the region where non-thermal melting occurs in the fourth portion of the semiconductor substrate.

[0008] In some embodiments, the method satisfies at least one of the following: the irradiation duration of the first femtosecond laser beam is greater than the irradiation duration of the second femtosecond laser beam; or the intensity of the first femtosecond laser beam is greater than the intensity of the second femtosecond laser beam; or the first femtosecond laser beam and the second femtosecond laser beam are irradiated in pulse form, and the pulse frequency of the first femtosecond laser beam is greater than the pulse frequency of the second femtosecond laser beam.

[0009] In some embodiments, the first portion of the trench is the bottom surface of the trench, and the third portion of the trench is the side surface of the trench.

[0010] In some embodiments, the semiconductor substrate includes silicon carbide.

[0011] In some embodiments, the femtosecond laser beam is provided by a femtosecond laser.

[0012] In some embodiments, during the irradiation with the femtosecond laser beam, the ratio of the energy contribution of the non-thermal melting process in the second portion of the semiconductor substrate to the energy contribution of the thermal melting process in the second portion of the semiconductor substrate exceeds a preset ratio.

[0013] In some embodiments, the preset ratio is determined based on the value at the maximum slope of the variation trend of the ratio of the energy contribution of the non-thermal melting process to the energy contribution of the thermal melting process with respect to the laser parameters of the femtosecond laser beam.

[0014] In some embodiments, the laser parameters of the femtosecond laser beam are configured to be not less than a first laser parameter threshold, at which a second portion of the semiconductor substrate begins to melt.

[0015] In some embodiments, the laser parameters of the femtosecond laser beam are configured to be not greater than a second laser parameter threshold, at which the second portion of the semiconductor substrate is completely melted.

[0016] In some embodiments, the laser parameters of the femtosecond laser beam are configured to maximize the ratio of the energy contribution of the non-thermal melting process to the energy contribution of the thermal melting process.

[0017] In some embodiments, the first laser parameter threshold and the second laser parameter threshold are determined based on the carrier number density balance, the energy conservation of the carrier system, and the energy balance of the lattice system of the semiconductor substrate.

[0018] In some embodiments, the carrier number density balance requirement of the semiconductor substrate The energy conservation requirement of the carrier system of the semiconductor substrate The energy balance requirement of the lattice system of the semiconductor substrate The requirement for the second portion of the semiconductor substrate to begin to melt is ρC L (T m -T 0 ) = ρC L (T Lm -T 0 ) + N C E g ; The requirement for the second portion of the semiconductor substrate to be completely melted is ρC L (T m -T 0 ) + L m = ρC L (T Lm -T 0 ) + N C E g , where N C is the carrier concentration, t is the time, α 1 is the single-photon absorption coefficient, I is the intensity of the femtosecond laser beam, hv is the photon energy corresponding to the wavelength of the femtosecond laser beam, β is the two-photon absorption coefficient, δ is the impact ionization coefficient, γ is the Auger recombination coefficient, U C is the total energy of the carrier system, α FCAis the free carrier absorption coefficient, k B is the Boltzmann constant, τ C is the carrier-lattice relaxation time, T C is the carrier temperature, T L is the lattice temperature, U L is the total energy of the lattice system, z is the spatial coordinate, κ L is the lattice thermal conductivity, ρ is the density of the semiconductor substrate, C L is the lattice heat capacity, T m is the melting point of the semiconductor substrate at room temperature, T 0 is the lattice temperature at room temperature, T Lm is the carrier concentration of N C is the melting point of the semiconductor substrate when g is the bandgap width of the semiconductor substrate, L m is the latent heat of fusion of the semiconductor substrate.

[0019] In some embodiments, the laser parameters of the femtosecond laser beam are set based on the relationship between the desired thickness of the oxide layer formed by the second portion of the semiconductor substrate and the first reference thickness and the second reference thickness. The first reference thickness is the thickness of the oxide layer formed by the second portion of the semiconductor substrate when irradiated with the femtosecond laser beam at the first laser parameter threshold, and the second reference thickness is the thickness of the oxide layer formed by the second portion of the semiconductor substrate when irradiated with the femtosecond laser beam at the second laser parameter threshold.

[0020] In some embodiments, the laser parameters of the femtosecond laser beam include intensity, wavelength, or a combination thereof.

[0021] In some embodiments, irradiating the second portion of the semiconductor substrate with the femtosecond laser beam includes irradiating the second portion of the semiconductor substrate with the femtosecond laser beam in pulse form. In such an embodiment, the femtosecond laser beam can be referred to as a pulsed femtosecond laser beam. In some examples, the laser parameters of the pulsed femtosecond laser beam include pulse width, energy density, wavelength, or a combination thereof. The pulse width and energy density of the pulsed femtosecond laser beam jointly determine the intensity of the pulsed femtosecond laser beam.

[0022] In some embodiments, the pulse width of the femtosecond laser beam is set to be between 50 femtoseconds (fs) and 150 fs.

[0023] In some embodiments, the pulse frequency of the femtosecond laser beam is configured such that non-thermal melting continuously occurs in the second portion of the semiconductor substrate.

[0024] In some embodiments, the pulse frequency of the femtosecond laser beam is set to be greater than 1 megahertz (MHz).

[0025] In some embodiments, the femtosecond laser beam is configured to be irradiated in a direction parallel to the depth direction of the trench, and the irradiation area of the femtosecond laser beam is configured to cover the trench in the width direction of the trench.

[0026] In some embodiments, irradiating the second portion of the semiconductor substrate with the femtosecond laser beam includes scanning the second portion of the semiconductor substrate with a single femtosecond laser beam or multiple femtosecond laser beams in a scanning direction parallel to the length direction of the trench.

[0027] In some embodiments, when scanning the second portion of the semiconductor substrate with a single femtosecond laser beam, the previous irradiation area and the next irradiation area of the single femtosecond laser beam partially overlap each other in the scanning direction; or when scanning the second portion of the semiconductor substrate with multiple femtosecond laser beams, the irradiation areas of every two adjacent femtosecond laser beams among the multiple femtosecond laser beams partially overlap each other in the scanning direction.

[0028] In some embodiments, the method further includes forming a gate over the oxide layer.

[0029] In some embodiments, the method further includes: forming one of a source region and a drain region in a fifth portion of the semiconductor substrate at one side of the top of the trench, and forming the other of the source region and the drain region in a sixth portion of the semiconductor substrate at the other side of the top of the trench; or forming one of the source region and the drain region in one or both of the fifth portion and the sixth portion of the semiconductor substrate, and forming the other of the source region and the drain region in a seventh portion of the semiconductor substrate under the trench.

[0030] In some embodiments, providing the semiconductor substrate in which the trench is formed includes: forming a hard mask layer on the semiconductor substrate; forming a photoresist pattern on the hard mask layer to etch the hard mask layer and the semiconductor substrate to form a trench in the semiconductor substrate.

[0031] In some embodiments, the method further includes: removing the hard mask layer after the irradiation of the femtosecond laser beam is completed and before the semiconductor substrate is thermally oxidized.

[0032] In some embodiments, the femtosecond laser beam is a first femtosecond laser beam, and the method further includes: before performing thermal oxidation treatment on the semiconductor substrate, performing a pull-back treatment on the hard mask layer to expose one or both of a fifth portion and a sixth portion of the semiconductor substrate located on both sides of the top of the trench; irradiating one or both of the fifth portion and the sixth portion of the semiconductor substrate with a third femtosecond laser beam, so that one or both of the fifth portion and the sixth portion of the semiconductor substrate undergo non-thermal melting; and after completing the irradiation of the first femtosecond laser beam and the third femtosecond laser beam, performing thermal oxidation treatment on the semiconductor substrate, so that an oxide layer is formed on the second portion of the semiconductor substrate and the one or both of the fifth portion and the sixth portion.

[0033] In some embodiments, the third femtosecond laser beam is the same as the first femtosecond laser beam.

[0034] In some embodiments, the irradiation of the first femtosecond laser beam and the irradiation of the third femtosecond laser beam are configured such that the depth of the region where non-thermal melting occurs in the second portion of the semiconductor substrate is equal to the depth of the region where non-thermal melting occurs in the one or both of the fifth portion and the sixth portion of the semiconductor substrate.

[0035] In some embodiments, the method further includes forming a gate over the oxide layer, and wherein the method further includes: forming one of a source region and a drain region in an eighth portion of the semiconductor substrate located on a side away from the trench of the fifth portion, and forming the other of the source region and the drain region in a ninth portion of the semiconductor substrate located on a side away from the trench of the sixth portion; or forming one of the source region and the drain region in one or both of the eighth portion and the ninth portion of the semiconductor substrate, and forming the other of the source region and the drain region in a seventh portion of the semiconductor substrate located under the trench.

[0036] According to a second aspect of the present disclosure, there is provided a semiconductor device manufactured by the method according to the first aspect of the present disclosure.

[0037] In some embodiments, the semiconductor device includes a MOSFET, and wherein the oxide layer is configured to provide a gate oxide layer of the MOSFET. Description of the Drawings

[0038] From the following description of the embodiments of the present disclosure shown in conjunction with the drawings, the foregoing and other features and advantages of the present disclosure will become apparent. The drawings are incorporated herein and form a part of the specification, further for explaining the principles of the present disclosure and enabling those skilled in the art to manufacture and use the present disclosure. Among them:

[0039] Figure 1 A schematic cross-section of a conventional trench-type SiC MOSFET is shown;

[0040] Figure 2 FIG. 2 shows a flowchart of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0041] Figures 3A to 3J which respectively show schematic cross-sectional views of semiconductor devices corresponding to respective steps of a non-limiting exemplary process for implementing Figure 2 the method shown;

[0042] Figure 4A FIG. 12 shows a schematic top view of a semiconductor device when scanning a semiconductor substrate with a single femtosecond laser beam according to some embodiments of the present disclosure;

[0043] Figure 4B FIG. 16 shows a schematic top view of a semiconductor device when scanning a semiconductor substrate with a multi-femtosecond laser beam according to some embodiments of the present disclosure;

[0044] Figure 5 which show schematic cross-sectional views of semiconductor devices corresponding to respective steps of a non-limiting exemplary process for implementing a method for manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0045] Figure 6 which show schematic cross-sectional views of semiconductor devices corresponding to respective steps of another non-limiting exemplary process for implementing a method for manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0046] Note that in the embodiments described below, sometimes the same reference numerals are used commonly between different drawings to denote the same parts or parts having the same functions, and their repeated description is omitted. In some cases, similar reference numerals and letters are used to denote similar items, and thus, once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.

[0047] For ease of understanding, the positions, dimensions, ranges, etc. of the respective structures shown in the drawings and the like sometimes do not represent the actual positions, dimensions, ranges, etc. Therefore, the present disclosure is not limited to the positions, dimensions, ranges, etc. disclosed in the drawings and the like. DETAILED DESCRIPTION

[0048] Various exemplary embodiments of the present disclosure will be described in detail below with reference to the drawings. It should be noted that: unless otherwise specifically stated, the relative arrangements, numerical expressions, and numerical values of the components and steps set forth in these embodiments do not limit the scope of the present disclosure.

[0049] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way a limitation on the present disclosure, its application, or its use. That is, the structures and methods herein are shown in an exemplary manner to illustrate different embodiments of the structures and methods in the present disclosure. However, those skilled in the art will understand that they merely illustrate the exemplary ways in which the present disclosure can be implemented, rather than exhaustive ways. In addition, the drawings do not have to be drawn to scale, and some features may be enlarged to show details of specific components.

[0050] In addition, technologies, methods, and devices known to those of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and devices should be regarded as part of the specification.

[0051] In all the examples shown and discussed herein, any specific values should be construed as merely exemplary and not as a limitation. Thus, other examples of the exemplary embodiments may have different values.

[0052] In this document, the same or similar characters may be used to represent the same or similar variables. Therefore, once a variable is defined in a certain embodiment, it does not need to be repeatedly described in subsequent embodiments.

[0053] Since the electric field strength of the gate oxide layer in SiC MOSFET is higher than that of the SiC material, when the SiC material has not been broken down, the gate oxide layer has already been broken down, resulting in premature failure of the semiconductor device. In this case, to fabricate a high-quality SiC MOSFET, the reliability issue of the gate oxide layer of the SiC MOSFET needs to be considered.

[0054] The gate oxide layer of SiC MOSFET is usually prepared by thermally oxidizing SiC to generate silicon dioxide (SiO 2 ). This thermal oxidation process is anisotropic, and the oxidation rates at different crystal planes of SiC vary significantly, which will have an adverse impact on the performance of the semiconductor device. Specifically, in the hexagonal SiC structure, on the (0001) crystal plane, one chemical bond of the tetrahedrally bonded Si atoms is along the C axis (<0001>), and this crystal plane is called the "Si plane". And on the crystal plane, one chemical bond of the tetrahedrally bonded C atoms is along the C axis and this crystal plane is called the "C plane". In addition to the Si plane and the C plane, the crystal plane is called the "A plane", and the

[0055] SiC thermal oxidation can be expressed by the following equation:

[0056]

[0057] It can be seen that the oxidation rate of SiC strongly depends on the crystal orientation of SiC. The fundamental reason is that when the Si atoms on the surface of the SiC substrate are oxidized, one Si-C bond on the C crystal plane needs to be broken, two Si-C bonds on the A crystal plane need to be broken, and three Si-C bonds on the Si crystal plane need to be broken. Since the ratio of the activation energy is the same as the difference in the number of broken Si-C bonds between the crystal plane orientations, the oxidation activation energy in the rate-limiting interfacial reaction should be related to the bond energy of the Si-C bonds broken on the crystal plane. Therefore, the C crystal plane has the fastest oxidation rate, and the Si crystal plane (0001) has the slowest oxidation rate. The A crystal plane and the M crystal plane have oxidation rates between those of the Si crystal plane (0001) and the C crystal plane .

[0058] When preparing a trench in the SiC substrate, the bottom of the trench is usually oriented to the Si crystal plane (0001), and the sidewalls of the trench are usually oriented to the A crystal plane or the M crystal plane That is to say, under the condition of ensuring uniform heating of each crystal plane during the thermal oxidation process, the thickness of the oxide layer formed at the bottom of the trench in the SiC substrate is smaller than the thickness of the oxide layer formed on the sidewalls of the trench. For example, Figure 1 shows a schematic cross-section of the trench-type SiC MOSFET 10 after a conventional thermal oxidation process (components not to be discussed are not shown in Figure 1 ). As Figure 1 shown, the thickness of the gate oxide layer 13 at the bottom of the trench 11 is about one-third of the thickness of the gate oxide layer 12 on the sidewalls of the trench 11. However, in a trench-type SiC MOSFET, the electric field is concentrated at the trench corners, and the oxide layer is prone to breakdown, thereby limiting the blocking voltage of the semiconductor device.

[0059] Although the above is described by taking SiC as an example, it should be understood that if other substrate materials also have different oxidation rates on different crystal planes, resulting in anisotropy in their thermal oxidation processes, there will also be similar reliability problems with the gate oxide layer.

[0060] Therefore, a new manufacturing method for semiconductor devices is desired to optimize the formation of the oxide layer of the semiconductor device to improve the performance of the semiconductor device.

[0061] To this end, the present disclosure provides a method for manufacturing a semiconductor device, which irradiates a portion of a semiconductor substrate adjacent to a specific portion of a trench with a femtosecond laser beam, causing non-thermal melting of this portion of the semiconductor substrate, so that the thickness of the oxide layer formed on this portion of the semiconductor substrate can reach the requirements, increasing the reliability of the oxide layer, improving the blocking voltage and reliability of the semiconductor device. In addition, by changing the laser parameters and irradiation parameters of the femtosecond laser beam, the thickness distribution of the formed oxide layer can be further adjusted to meet various requirements in actual semiconductor manufacturing.

[0062] There are two types of melting, including thermal melting and non-thermal melting. It should be noted that in this article, "occurring non-thermal melting" means that in the melting process, it is completely a non-thermal melting process, or the non-thermal melting process dominates and there is a certain thermal melting process, but the case of completely thermal melting process and the case where the thermal melting process dominates and there is a certain non-thermal melting process are excluded. That is, the form of melting depends on the respective contributions of the non-thermal melting process and the thermal melting process to the energy required for melting. If the non-thermal melting process dominates, it is called "non-thermal melting".

[0063] The method for manufacturing a semiconductor device and the corresponding semiconductor device according to some embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. It can be understood that there may be other steps in the actual method, and there may be other components in the actual semiconductor device. In order to avoid obscuring the key points of the present disclosure, the accompanying drawings do not show and this article does not discuss other steps / other components.

[0064] Figure 2 FIG. 100 shows a flowchart of a method 100 for manufacturing a semiconductor device 200 according to some embodiments of the present disclosure. Figures 3A to 3J FIGS. 12-14 respectively show schematic cross-sectional views of a semiconductor device corresponding to the respective steps of a non-limiting example process implementing the Figure 2 method shown.

[0065] For convenience of description, in the present disclosure, the direction parallel to the thickness direction of the transistor is indicated by z, the direction perpendicular to the thickness direction of the transistor is indicated by x, and the direction perpendicular to x and z is indicated by y. In addition, in this article, for the sake of convenience of description, "high", "low", "upper", "lower", "deep", "shallow", etc. can be used to describe the relative relationship of the transistor in z, "left", "right", etc. can be used to describe the relative relationship of the transistor in x, and "front", "rear", etc. can be used to describe the relative relationship of the transistor in y.

[0066] As Figure 2 shown, method 100 includes: at step S102, providing a semiconductor substrate in which a trench is formed.

[0067] For example, a semiconductor substrate may include a semiconductor material having different oxidation rates on different crystal planes. In some embodiments, the semiconductor substrate includes silicon carbide. For illustrative purposes, in the following description, a semiconductor substrate whose semiconductor material includes silicon carbide (SiC) is taken as a non-limiting example.

[0068] In some embodiments, in the intact crystal structure of the semiconductor substrate (i.e., the crystal structure has not changed), the oxidation rate of the crystal plane where the first part of the trench is located is lower than the oxidation rate of the crystal plane where the third part of the trench, which is different from the first part, is located. For example, in the intact crystal structure of the semiconductor substrate, the number of bonds that need to be broken when the crystal plane where the first part of the trench is located undergoes oxidation may be greater than the number of bonds that need to be broken when the crystal plane where the third part of the trench is located undergoes oxidation. In some examples, the first part of the trench is the bottom surface of the trench, and the third part of the trench is the side surface of the trench. For example, in a SiC semiconductor substrate, the bottom surface of the trench is typically the Si crystal plane (0001), and the side surface is typically the A crystal plane or the M crystal plane The oxidation rate of the Si crystal plane (0001) is lower than that of the A crystal plane and the M crystal plane of the oxidation rate.

[0069] A semiconductor substrate in which trenches have been pre-formed may be provided, or an untreated semiconductor substrate may be provided and then trenches may be formed therein. In some embodiments, providing a semiconductor substrate in which trenches are formed may include: forming a hard mask layer on the semiconductor substrate; forming a photoresist pattern on the hard mask layer to etch the hard mask layer and the semiconductor substrate so as to form trenches in the semiconductor substrate. For example, refer to Figures 3A to 3D 。

[0070] As Figure 3A shown, a semiconductor substrate 201 is provided.

[0071] As Figure 3B shown, a hard mask layer 202 is formed on the semiconductor substrate 201 (for example, it can be formed by deposition (such as but not limited to chemical vapor deposition, etc.) or thermal oxidation growth process, etc.).

[0072] The hard mask layer 202 may include, for example, but not limited to, oxides or nitrides of semiconductor materials or combinations thereof, such as silicon dioxide and / or silicon nitride, etc. In some embodiments, the hard mask layer 202 may be a single-layer or multi-layer structure. For example, it may include a stack of a silicon dioxide layer and a silicon nitride layer. The hard mask layer 202 may have any suitable thickness. For example, its thickness may be between 1 nanometer (nm) and 2 micrometers (μm), or may be between 50 nm and 1 μm, or may be between 100 nm and 500 nm. The hard mask layer 202 can help ensure that while the thin layer (which is not covered by the hard mask layer 202) near the trench surface of the semiconductor substrate 201 is melted by the femtosecond laser beam irradiation during the subsequent laser processing process, the part of the hard mask layer 202 that is also irradiated by the femtosecond laser beam and the thin layer of the semiconductor substrate 201 near the upper surface of the substrate below it will not be melted. Since the unetched part of the upper surface of the semiconductor substrate 201 still maintains a good native interface, the hard mask layer 202 can protect its good native interface.

[0073] As Figure 3C shown, a photoresist pattern 203 is formed on the hard mask layer 202. For example, a photoresist may be first coated on the hard mask layer 202, and then the photoresist pattern 203 is formed by exposure and development. The photoresist pattern 203 can define the position, shape, and size of the trench to be fabricated in the semiconductor substrate 201. Any suitable means such as spin-on coating, spray coating, dip coating, brush coating, or evaporation can be used to form the photoresist pattern 203 on the hard mask layer 202.

[0074] As Figure 3D shown, the hard mask layer 202 and the semiconductor substrate 201 are etched to form a trench 204 in the semiconductor substrate 201. For example, the hard mask layer 202 may be first etched using the photoresist pattern 203, and then after removing the photoresist pattern 203 (any suitable method such as dry and / or wet methods can be used to remove the photoresist pattern 203, which is not particularly limited here), the semiconductor substrate 201 is etched using the etched hard mask layer 202 to form the trench 204. As Figure 3D shown, the trench 204 includes a bottom surface 2041 (the first part) and a side surface 2042 (the third part).

[0075] Returning to reference Figure 2 , method 100 further includes: at step S104, irradiating the second part of the semiconductor substrate adjacent to the first part of the trench with a femtosecond laser beam, such that the second part of the semiconductor substrate undergoes non-thermal melting.

[0076] For example, as Figure 3E shown, the second portion 2011 of the semiconductor substrate 201 adjacent to the bottom surface 2041 of the trench 204 is irradiated with a femtosecond laser beam 205, causing non-thermal melting of the second portion 2011 of the semiconductor substrate 201. At the same time, the fourth portion 2012 of the semiconductor substrate 201 adjacent to the side surface 2042 of the trench 204 is not irradiated with the femtosecond laser beam 205.

[0077] The physical processes caused by laser irradiation of the semiconductor substrate can be described as follows.

[0078] (1) Carrier excitation. The semiconductor substrate absorbs laser energy to cause carrier excitation therein. When the photon energy of the laser is greater than or equal to the bandgap width of the semiconductor substrate, single-photon absorption can occur; when the photon energy of the laser is less than the bandgap width of the semiconductor substrate, multi-photon absorption can occur. Free carrier absorption increases the energy of the carriers but does not change the carrier number density. In addition, when the energy of an electron in a high-energy state exceeds the bandgap energy of the minimum conduction band, it can ionize another electron in the valence band, thereby generating two excited electrons at the minimum of the conduction band in a collision ionization process. These electrons can be heated again by the laser electromagnetic field through free carrier absorption, and once they have enough energy, they will strike more valence band electrons. As long as there is a strong enough laser electromagnetic field, this process will repeat, resulting in so-called electron avalanche.

[0079] (2) Carrier-lattice thermalization. After carrier excitation, electrons and holes are redistributed in the conduction band and valence band through carrier-carrier and carrier-phonon scattering. This takes about several hundred femtoseconds. Carrier-carrier scattering does not change the total energy of the excited carrier system or the number of carriers. In carrier-phonon scattering, free carriers lose or gain energy by emitting or absorbing phonons. Although carrier-phonon scattering does not change the number of carriers, the total energy of the carrier system is reduced because spontaneous phonon emission transfers energy to the lattice. In a semiconductor, carrier-carrier scattering and carrier-phonon scattering occur simultaneously within the first few hundred femtoseconds after excitation. Since the phonons emitted in the carrier-phonon scattering process carry little energy, initially the carrier system and the lattice system are in a non-thermal equilibrium state, and many scattering processes are required to reach a thermal equilibrium state, and these scattering processes take from several picoseconds to dozens of picoseconds.

[0080] (3) Carrier removal. Once the carriers and the lattice reach equilibrium, the material is at a well-defined temperature. Although the carriers have the same temperature as the lattice, there is an excess number of free carriers compared to thermal equilibrium. The excess carriers are removed either by recombination of electrons and holes or by diffusion out of the excited region. The recombination process includes radiative recombination and non-radiative recombination processes. In the radiative recombination process, which is the reverse of the photoexcitation process, the excess carrier energy is released in the form of photons. Non-radiative recombination processes include Auger recombination, defect recombination, and surface recombination. For silicon, germanium, and other indirect bandgap semiconductors, Auger recombination dominates during the recombination process. In Auger recombination, an electron and a hole recombine, and the excess energy excites a higher electron in the conduction band. Like other recombination mechanisms, Auger recombination reduces the carrier density. However, it keeps the total energy of the free carrier system constant while increasing the average energy of the remaining carriers. Carrier diffusion simply removes carriers from the region of the sample where they were initially excited and does not reduce the total number of free carriers in the material.

[0081] (4) Thermal effects and changes in the lattice structure. When the free carriers and the lattice reach the equilibrium temperature and the excess free carriers are removed, the material is essentially the same as a material heated by conventional means. The material can reach the equilibrium temperature within a few picoseconds after laser irradiation, but it takes a longer time to remove the excess carriers. If the lattice temperature exceeds the melting point or boiling point, melting or vaporization may occur, but not on the picosecond time scale. If no phase change occurs, the temperature will return to the ambient value on the microsecond time scale. If melting or vaporization occurs, re-solidification or liquefaction will occur when the temperature is below the melting point or boiling point respectively, but the material may not return to its original structure or phase.

[0082] Therefore, to achieve non-thermal melting, it is desirable that the carriers and the lattice have not reached thermal equilibrium. Since the scattering processes required to reach thermal equilibrium typically take from a few picoseconds to dozens of picoseconds, it can be advantageous to control the laser duration within one picosecond (ps), and more advantageous to control the laser duration in the femtosecond range (less than one picosecond, e.g., from a few femtoseconds to a few hundred femtoseconds). A laser beam with a duration in the femtosecond range is what is referred to as a femtosecond laser beam in this article.

[0083] In some embodiments, the femtosecond laser beam is provided by a femtosecond laser. The femtosecond laser can be configured, for example, to generate extremely short femtosecond-level pulses (pulse widths in the femtosecond order of magnitude, i.e., less than one picosecond, typically between a few femtoseconds and a few hundred femtoseconds). In some embodiments, the second portion of the semiconductor substrate can be irradiated with the femtosecond laser beam in pulse form. Exemplarily, the pulse width of the femtosecond laser beam can be set to be between 50 fs and 150 fs, for example, about 100 fs. In some embodiments, the pulse frequency of the femtosecond laser beam can be configured such that non-thermal melting continuously occurs in the second portion of the semiconductor substrate. That is, before the end of the non-thermal melting process caused by the previous pulse, the next pulse has already irradiated the second portion of the semiconductor, thus ensuring a good non-thermal melting effect. Specifically, the pulse frequency of the femtosecond laser beam can be set to be greater than 1 MHz, for example.

[0084] Taking the SiC semiconductor substrate as an example, when the femtosecond laser beam irradiates the SiC surface, the high-density plasma excited by the intense light can weaken the lattice, increase the atomic mobility, and not significantly increase their thermal energy. When about ten percent of the valence electrons are excited to the conduction band, under the action of the plasma, the bond energy between the lattices is weakened, the ion kinetic energy increases, and the ions will drift significantly from their initial positions, thus causing permanent structural changes. According to observations, SiC shows a molten state within hundreds of femtoseconds after laser irradiation. This non-thermal melting is accompanied by the breaking of some carbon-silicon bonds in the laser-irradiated area, so that the number of carbon-silicon bonds that need to be broken in the subsequent oxidation process in the laser-irradiated area is reduced and thus the oxidation rate is increased. In contrast, if a pulsed laser beam with a pulse width above the picosecond order of magnitude (for example, a picosecond laser beam) is selected, then according to observations, a thermal melting process occurs in the irradiated area of SiC during irradiation, the carbon-silicon bonds do not break, but the bond length of the carbon-silicon bonds elongates by about fifteen percent. During the irradiation of such a laser with a large pulse width, the range of the thermal influence area inside SiC along the laser irradiation direction is large and the modification process of the irradiated area is relatively intense, which is not conducive to the growth of the subsequent oxide layer.

[0085] In addition, the wavelength of the femtosecond laser beam can be determined based on the bandgap width of the semiconductor substrate. In some embodiments, the wavelength of the femtosecond laser beam can be selected such that the semiconductor substrate preferentially undergoes single-photon absorption. For example, for the SiC semiconductor substrate, the wavelength of the femtosecond laser beam can be selected to be 248 nm. Of course, a laser wavelength that causes multi-photon absorption in the semiconductor substrate is also feasible, but a higher laser intensity may be required.

[0086] In some embodiments, step S104 can be carried out in an inert gas (such as but not limited to nitrogen, helium, etc.) atmosphere, or can be carried out in a vacuum environment. This is to avoid water and oxygen and maintain cleanliness, and prevent impurity particles from being incorporated into the molten part of the semiconductor substrate during the laser processing process.

[0087] Still referring to Figure 3E , in some embodiments, the femtosecond laser beam 205 is configured to irradiate in a direction parallel to the depth direction (z-direction) of the trench 204. In other embodiments, the femtosecond laser beam 205 can also be configured to irradiate at an angle with respect to the z-direction. In some examples, such an angle does not exceed 15 degrees, or does not exceed 10 degrees, or does not exceed 5 degrees.

[0088] In some embodiments, the irradiation area of the femtosecond laser beam 205 is configured to cover the trench 204 in the width direction (x-direction) of the trench 204. As previously mentioned, the hard mask layer 202 can protect the thin layer near the upper surface of the semiconductor substrate 201 below it from melting even when it is under the irradiation area of the femtosecond laser beam 205, which can make the requirement for the spot size of the femtosecond laser beam 205 less strict, as long as it is ensured that the trench 204 is covered in the width direction (x-direction) of the trench 204, which can also eliminate the need to scan the femtosecond laser beam or increase the femtosecond laser beam in the x-direction.

[0089] If the irradiation area of the femtosecond laser beam 205 (which can be formed by connecting the irradiation areas of multiple femtosecond laser beams) is large enough to cover the entire second portion 2011 of the semiconductor substrate 201, the second portion 2011 of the semiconductor substrate 201 can be processed simultaneously. However, such an approach is subject to many limitations, such as the second portion 2011 of the applicable semiconductor substrate 201 cannot be too wide and / or too long, and a large number of laser combinations are required. Therefore, the method of scanning the femtosecond laser beam can be adopted. In some embodiments, irradiating the second portion 2011 of the semiconductor substrate 201 with the femtosecond laser beam 205 can include scanning the second portion 2011 of the semiconductor substrate 201 with a single femtosecond laser beam or multiple femtosecond laser beams along a scanning direction parallel to the length direction (y-direction) of the trench 204. A preset dwell time can be set for each scanning position to ensure sufficient non-thermal melting at each position. In some embodiments, the preset dwell time can be on the order of milliseconds, for example, between a few milliseconds and several hundred milliseconds. By scanning the femtosecond laser beam, a relatively wide and / or large second portion of the semiconductor substrate can be effectively applied, and the case where the same semiconductor substrate has multiple second portions that require non-thermal melting treatment (for example, there are multiple trenches 204) can also be applied, and the number of lasers used can be reduced.

[0090] In some embodiments, when a single femtosecond laser beam scans the second portion 2011 of the semiconductor substrate 201 along the scanning direction, the previous irradiation area and the next irradiation area of the single femtosecond laser beam partially overlap with each other in the scanning direction. For example, as Figure 4AAs shown, the femtosecond laser beam 205 is a single femtosecond laser beam, and there is an overlapping region 2500 between the previous irradiation region 250 and the next irradiation region 250' in the scanning direction. By setting the overlapping region, the time that each position undergoes laser treatment can be equivalently extended.

[0091] In some embodiments, when scanning the second part 2011 of the semiconductor substrate 201 with multiple femtosecond laser beams along the scanning direction, the irradiation regions of every two adjacent femtosecond laser beams among the multiple femtosecond laser beams partially overlap with each other in the scanning direction. For example, as Figure 4B shown, the femtosecond laser beam 205 includes a femtosecond laser beam 251 and a femtosecond laser beam 252. When scanning the second part 2011 of the semiconductor substrate 201, there is an overlapping region 2500' between the irradiation regions of the adjacent femtosecond laser beams 251 and 252 in the scanning direction. By setting the overlapping region, the intensity that each position undergoes laser treatment can be equivalently enhanced.

[0092] Furthermore, in order to promote non-thermal melting of the second part of the semiconductor substrate, it can be required that during the irradiation of the femtosecond laser beam, the ratio of the energy contribution of the non-thermal melting process to the energy contribution of the thermal melting process of the second part of the semiconductor substrate exceeds a preset ratio. In some examples, the preset ratio can be determined based on the value at the maximum slope of the variation trend of the ratio of the energy contribution of the non-thermal melting process to the energy contribution of the thermal melting process with respect to the laser parameters of the femtosecond laser beam. For example, when the wavelength of the femtosecond laser beam is constant, the variation trend of the ratio of the energy contribution of the non-thermal melting process to the energy contribution of the thermal melting process with respect to the intensity of the femtosecond laser beam can be determined, and the preset ratio can be determined based on the ratio value at the maximum slope of this variation trend. If the femtosecond laser beam is a pulsed femtosecond laser beam, then when the wavelength and pulse width of the pulsed femtosecond laser beam are constant, the variation trend of the ratio of the energy contribution of the non-thermal melting process to the energy contribution of the thermal melting process with respect to the energy density of the pulsed femtosecond laser beam can be determined, and the preset ratio can be determined based on the ratio value at the maximum slope of this variation trend. Of course, the preset ratio can be the ratio corresponding to the maximum slope, or any ratio within the desired range determined based on this maximum slope.

[0093] The energy contribution of the non-thermal melting process can be determined based on the carrier concentration in the semiconductor substrate and the bandgap width of the semiconductor substrate under the irradiation of the femtosecond laser beam. Specifically, for example, the energy contribution of the non-thermal melting process can be expressed as N C E g , where N C is the carrier concentration, and E g is the bandgap width of the semiconductor substrate. The bandgap width usually varies with the carrier concentration and the lattice temperature. For example, in 4H-SiC, when the carrier concentration is 1×1012 / cm 3 In the case of, the bandgap width E g can be expressed as where T L is the lattice temperature.

[0094] The energy contribution of the thermal melting process can be determined based on the density of the semiconductor substrate, the lattice heat capacity of the semiconductor substrate, and the melting point of the semiconductor substrate associated with the carrier concentration in the semiconductor substrate under the irradiation of the femtosecond laser beam. Specifically, for example, the energy contribution of the thermal melting process can be expressed as ρC L (T Lm -T 0 ), where ρ is the density of the semiconductor substrate, C L is the lattice heat capacity of the semiconductor substrate, T Lm is the melting point of the semiconductor substrate (or the lattice temperature at this time) when the carrier concentration is N C , and T 0 is the lattice temperature at room temperature (usually 300K).

[0095] By controlling the laser parameters of the femtosecond laser beam, the ratio of the energy contribution of the non-thermal melting process to the energy contribution of the thermal melting process can be controlled, thereby controlling the degree of non-thermal melting of the semiconductor substrate. In some embodiments, the laser parameters may include intensity, wavelength, or a combination thereof. When the femtosecond laser beam is a pulsed femtosecond laser beam, the intensity of the femtosecond laser beam can be determined by the pulse width and the energy density.

[0096] Specifically, the attenuation of the femtosecond laser beam along the propagation direction z inside the material can be expressed as

[0097]

[0098] Therefore, the intensity I of the femtosecond laser beam can be expressed as

[0099]

[0100] where α 1 is the single-photon absorption coefficient, β is the two-photon absorption coefficient, α FCA is the free-carrier absorption coefficient, z is the spatial coordinate, and I 0 is the surface (z = 0) laser intensity. If the pulsed femtosecond laser beam is simulated as a Gaussian beam, the temporal and spatial evolution of I 0 can be expressed as

[0101]

[0102] where r is the off-axis radial distance (the distance between a point in the femtosecond laser beam and the central axis), t is the time, R is the reflectivity, J is the energy density, τp is the pulse width, t 0 = 3τ p .

[0103] For example, for an indirect bandgap semiconductor (e.g., silicon carbide), the photon absorption process can only occur with the assistance of phonons. Therefore, the absorption coefficients α 1 , β and α FCA depend on the lattice temperature. In addition, α FCA also depends on the carrier concentration. The greater the concentration, the greater the absorption coefficient. α FCA can be expressed as where N C is the carrier concentration, e is the electron charge, c 0 is the speed of light, λ is the wavelength, m eff is the effective electron mass, ε 0 is the vacuum permittivity, n is the refractive index, and μ(T) is the temperature-dependent electron mobility.

[0104] It should be noted that during laser irradiation, the change in the free carrier concentration not only affects α FCA but also causes a significant change in the reflectivity R. Usually, it is assumed that the reflectivity depends only on the lattice temperature during irradiation simulation. Although this can simplify the calculation process, it may affect the accuracy of the simulation results. Therefore, the Drude model can be used to consider the influence of the instantaneous carrier concentration on the reflectivity. The reflectivity expression under this model framework is

[0105]

[0106]

[0107]

[0108] where k is the extinction coefficient, ε is the dielectric constant of the semiconductor substrate, and Re(ε) is the real part of ε. The carrier concentration N C affects the dielectric constant ε, thereby affecting the extinction coefficient k and the refractive index n, and ultimately affecting the reflectivity R.

[0109] In some embodiments, the laser parameters of the femtosecond laser beam 205 are configured to be not less than a first laser parameter threshold, at which the second portion 2011 of the semiconductor substrate 201 begins to melt. That is, during the irradiation of the femtosecond laser beam 205 at the first laser parameter threshold, the sum of the energy contributions of the non-thermal melting process and the thermal melting process exactly provides the heat that the semiconductor substrate 201 needs to absorb from room temperature to the melting point. Additionally, in some embodiments, the laser parameters of the femtosecond laser beam 205 are further configured to be not greater than a second laser parameter threshold, at which the second portion 2011 of the semiconductor substrate 201 is completely melted. That is, during the irradiation of the femtosecond laser beam 205 at the second laser parameter threshold, the sum of the energy contributions of the non-thermal melting process and the thermal melting process exactly provides the heat that the semiconductor substrate 201 needs to absorb from room temperature to the melting point and the latent heat of fusion of the semiconductor substrate 201. It can be understood that the configuration of the laser parameters of the femtosecond laser beam 205 also applies to other femtosecond laser beams to be described below. Further, in order to enable the semiconductor substrate to undergo non-thermal melting as much as possible to increase the thickness of the oxide layer formed in the subsequent thermal oxidation process, the laser parameters of the femtosecond laser beam are further configured to make the ratio of the energy contribution of the non-thermal melting process to the energy contribution of the thermal melting process as large as possible.

[0110] In some embodiments, the first laser parameter threshold and the second laser parameter threshold are determined based on the carrier number density balance, the energy conservation of the carrier system, and the energy balance of the lattice system of the semiconductor substrate. Specifically, for example, the carrier number density balance of the semiconductor substrate requires

[0111]

[0112] The energy conservation of the carrier system of the semiconductor substrate requires

[0113]

[0114] The energy balance of the lattice system of the semiconductor substrate requires

[0115]

[0116] The requirement for the second portion of the semiconductor substrate to begin to melt is

[0117] ρC L (T m -T 0 )=ρC L (T Lm -T 0 )+N C E g (4)

[0118] The requirement for the second portion of the semiconductor substrate to be completely melted is

[0119] ρC L (T m -T 0 )+L m =ρC L (T Lm -T 0 )+N C E g (5)

[0120] Among them, N C is the carrier concentration, t is the time, α 1 is the single-photon absorption coefficient, I is the intensity of the femtosecond laser beam, hν is the photon energy corresponding to the wavelength of the femtosecond laser beam, β is the two-photon absorption coefficient, δ is the impact ionization coefficient, γ is the Auger recombination coefficient, U C is the total energy of the carrier system, α FCA is the free-carrier absorption coefficient, k B is the Boltzmann constant, τ C is the carrier-lattice relaxation time, T C is the carrier temperature, T L is the lattice temperature, U L is the total energy of the lattice system, z is the spatial coordinate, κ L is the lattice thermal conductivity, ρ is the density of the semiconductor substrate, C L is the lattice heat capacity, T m is the melting point of the semiconductor substrate at room temperature, T 0 is the lattice temperature at room temperature, T Lm is the melting point of the semiconductor substrate when the carrier concentration is N C (or rather, the lattice temperature at this time), E g is the bandgap width of the semiconductor substrate, L m is the latent heat of fusion of the semiconductor substrate.

[0121] The interaction between the laser and the semiconductor results in the generation of non-equilibrium carriers and increases the carrier temperature and the lattice temperature. In Equation (1), the first two terms on the right side of the equal sign describe the single-photon absorption process and the two-photon absorption process, and the third and fourth terms describe the impact ionization process and the Auger recombination process. It can be understood that more photon absorption processes are considered similarly.

[0122] The total energy of the carrier system is regulated by the laser absorption process and the transport process. In Equation (2), the first term on the right side of the equal sign describes the energy source obtained by the carrier system through the single-photon absorption process and the free-carrier absorption process, the second term is the energy source obtained by two-photon absorption, and the third term is the energy transfer between the carrier system and the lattice system.

[0123] The laser pulse energy cannot be directly transferred to the lattice system. The lattice system energy is obtained from the carrier system by the carrier-lattice relaxation process. In equation (3), the first term on the right side of the equal sign is the energy transfer term of the lattice system, and the second term is the energy exchange between the lattice system and the carrier system.

[0124] If it is assumed that the optical phonons and acoustic phonons are in thermodynamic equilibrium, the lattice system can be regarded as a single thermodynamic system. Under the above assumptions, the internal energy of the carrier system and the lattice system can be described as U C =N C E g +C C T C and U L =C L T L , where C C is the carrier heat capacity.

[0125] In equations (4) and (5), the first term on the right side of the equal sign is the energy contribution of the thermal melting process, and the second term on the right side of the equal sign is the energy contribution of the non-thermal melting process.

[0126] For example, when the wavelength of the femtosecond laser beam (corresponding to v) is constant, by combining the above equations (1)-(5), the intensity of the femtosecond laser beam when equation (4) is satisfied is solved as the first laser intensity threshold, and the intensity of the femtosecond laser beam when equation (5) is satisfied is solved as the second laser intensity threshold. Then, the intensity of the femtosecond laser beam can be controlled between the first laser intensity threshold and the second laser intensity threshold. For example, the intensity value that maximizes the ratio of the energy contribution of the non-thermal melting process to the energy contribution of the thermal melting process within this range can be selected as the femtosecond laser beam intensity to be applied.

[0127] For example, for a pulsed femtosecond laser beam, the wavelength of the femtosecond laser beam (corresponding to v) and the pulse width (τ p ) is constant, by combining the above equations (1)-(5), the femtosecond laser beam energy density (corresponding to J) when equation (4) is satisfied is solved as the first laser energy density threshold, and the femtosecond laser beam energy density when equation (5) is solved as the second laser energy density threshold. Then, the energy density of the pulsed femtosecond laser beam can be controlled between the first laser energy density threshold and the second laser intensity energy density. For example, the energy density value that maximizes the ratio of the energy contribution of the non-thermal melting process to the energy contribution of the thermal melting process within this range can be selected as the energy density of the pulsed femtosecond laser beam to be applied.

[0128] Return to reference Figure 2 The method 100 further includes: at step S106, after the irradiation of the femtosecond laser beam is completed, performing a thermal oxidation treatment on the semiconductor substrate so that an oxide layer is formed on the second portion of the semiconductor substrate.

[0129] For example, referring to Figure 3F , the hard mask layer 202 can be removed after the irradiation of the femtosecond laser beam 205 is completed and before the thermal oxidation treatment of the semiconductor substrate 201.

[0130] As Figure 3G shown, after the thermal oxidation treatment of the semiconductor substrate 201, an oxide layer 206 is formed on the surface of the semiconductor substrate 201, including the oxide layer formed by the second part 2011 and the fourth part 2012 of the semiconductor substrate 201. As Figure 3G shown, it can be seen that even in the intact crystal structure of the semiconductor substrate 201, the oxidation rate of the crystal plane where the bottom surface of the trench 204 is located is lower than the oxidation rate of the crystal plane where the side surface of the trench 204 is located. However, since the second part 2011 of the semiconductor substrate 201 has undergone non-thermal melting treatment, the thickness d1 of the formed oxide layer can be close to or even greater than the thickness d2 of the oxide layer formed by other parts (such as the fourth part 2012) that have not undergone non-thermal melting treatment.

[0131] In addition, by controlling the degree of non-thermal melting of the semiconductor substrate, the thickness of the oxide layer formed on the semiconductor substrate can be controlled. For example, the laser parameters of the femtosecond laser beam (such as intensity (or pulse width, energy density, etc. in the case of a pulsed femtosecond laser beam), wavelength, etc.) and the irradiation parameters of the femtosecond laser beam (such as irradiation duration, pulse frequency in the case of a pulsed femtosecond laser beam, preset dwell time during scanning in the case of a scanned femtosecond laser beam, spot overlap area, etc.) can all be used to control the degree of non-thermal melting of the semiconductor substrate.

[0132] In some embodiments, the laser parameters of the femtosecond laser beam can be set based on the relationship between the desired thickness of the oxide layer formed by the second part of the semiconductor substrate relative to the first reference thickness and the second reference thickness, where the first reference thickness is the thickness of the oxide layer formed by the second part of the semiconductor substrate when the femtosecond laser beam is irradiated at the first laser parameter threshold, and the second reference thickness is the thickness of the oxide layer formed by the second part of the semiconductor substrate when the femtosecond laser beam is irradiated at the second laser parameter threshold, so as to flexibly set the thickness of the oxide layer of the semiconductor substrate to meet the different requirements of the actual semiconductor manufacturing process.

[0133] Additionally, in some embodiments, method 100 may further include: forming a gate on the oxide layer. For example, as Figure 3HAs shown, a conductive material layer can be deposited on the oxide layer 206 within the trench 204 as the gate 207. The excess conductive material layer and oxide layer can be removed by means such as, for example but not limited to, chemical mechanical polishing. As a non-limiting example, the conductive material of the gate 207 can include one or more of the following: polysilicon, doped polysilicon (such as polysilicon doped with phosphorus ions, polysilicon doped with arsenic ions, polysilicon doped with antimony ions), metal (such as copper), etc. Here, the oxide layer 206 provides a gate oxide layer for the gate 207.

[0134] In some embodiments, method 100 may further include: forming one of the source region and the drain region in a fifth portion of the semiconductor substrate at one side of the top of the trench, and forming the other of the source region and the drain region in a sixth portion of the semiconductor substrate at the other side of the top of the trench. For example, as Figure 3H and Figure 3I shown, by means such as an ion implantation process, a source region 208 is formed in a fifth portion 2013 of the semiconductor substrate 201 at one side of the top of the trench 204, and a drain region 209 is formed in a sixth portion 2014 of the semiconductor substrate 201 at the other side of the top of the trench 204. Of course, in some other embodiments, a drain region 209 can also be formed in the fifth portion 2013 of the semiconductor substrate 201, and a source region 208 can be formed in the sixth portion 2014 of the semiconductor substrate 201. In the transistor structure as Figure 3I shown (referred to herein as the first type of transistor structure), the channel region is located in the active region of the semiconductor substrate 201 between the source region 208 and the drain region 209 and is at least partially defined by the trench 204. When the transistor is turned on, a conductive channel that at least partially extends along the oxide layer 206 to connect the source region 208 and the drain region 209 will be formed in the channel region. Due to the presence of the trench 204, the length of the conductive channel is increased compared to the lateral (in the x direction) distance between the source region 208 and the drain region 209, which is beneficial for avoiding or improving the short channel effect when the transistor is miniaturized (i.e., the lateral distance between the source region 208 and the drain region 209 is shortened).

[0135] Alternatively, in some embodiments, method 100 may further include: forming one of the source region and the drain region in one or both of the fifth portion and the sixth portion of the semiconductor substrate, and forming the other of the source region and the drain region in a seventh portion of the semiconductor substrate located below the trench. For example, as Figure 3H and Figure 3JAs shown, source regions 208 are formed in the fifth portion 2013 and the sixth portion 2014 of the semiconductor substrate 201 by means such as an ion implantation process, etc., and drain regions 209 are formed in the seventh portion 2015 of the semiconductor substrate 201 that is below the trench 204. Of course, in some other embodiments, drain regions 209 can also be formed in the fifth portion 2013 and the sixth portion 2014 of the semiconductor substrate 201, while source regions 208 are formed in the seventh portion 2015 of the semiconductor substrate 201. In the Figure 3J transistor structure shown (hereinafter referred to as the second type of transistor structure in this article), the channel region is located in the active region of the semiconductor substrate 201 between the source region 208 and the drain region 209 and is at least partially defined by the trench 204. When the transistor is turned on, a conductive channel will be formed in the channel region that at least partially extends along the oxide layer 206 to connect the source region 208 and the drain region 209.

[0136] In addition, according to the thickness requirements of the oxide layer in different regions, the corresponding portions of the semiconductor substrate adjacent to different parts of the trench can be respectively subjected to corresponding femtosecond laser irradiation, and the thickness of the oxide layer formed by the corresponding portions can be controlled by controlling the degree of non-thermal melting of the corresponding portions.

[0137] Assume that the femtosecond laser beam used to irradiate the second portion of the semiconductor substrate in step S104 is the first femtosecond laser beam. In some embodiments, method 100 may further include: before performing the thermal oxidation treatment on the semiconductor substrate, irradiating the fourth portion of the semiconductor substrate adjacent to the third portion (e.g., the side surface) of the trench with the second femtosecond laser beam, so that the fourth portion of the semiconductor substrate undergoes non-thermal melting; after completing the irradiation of the first femtosecond laser beam and the second femtosecond laser beam, performing a thermal oxidation treatment on the semiconductor substrate, so that the second portion and the fourth portion of the semiconductor substrate form an oxide layer.

[0138] Exemplarily, in the case where the oxidation rate of the crystal plane where the first portion of the trench is located is lower than the oxidation rate of the crystal plane where the third portion of the trench is located, the irradiation of the first femtosecond laser beam and the irradiation of the second femtosecond laser beam can be configured such that the depth of the region where non-thermal melting occurs in the second portion of the semiconductor substrate is greater than the depth of the region where non-thermal melting occurs in the fourth portion of the semiconductor substrate. In this way, the thickness of the oxide layer subsequently formed by the second portion of the semiconductor substrate can be close to or even greater than the thickness of the oxide layer formed by the fourth portion of the semiconductor substrate. Specifically, the desired thickness of the oxide layer formed by the second portion and the fourth portion of the semiconductor substrate respectively can be achieved by respectively controlling the laser parameters and irradiation parameters of the first femtosecond laser beam and the second femtosecond laser beam to adjust the degree of non-thermal melting of the second portion and the fourth portion of the semiconductor substrate.

[0139] ReferenceFigure 5 , Figure 5 shows a schematic cross-sectional view of a semiconductor device corresponding to respective steps of a non-limiting example process for implementing a method of manufacturing a semiconductor device. Although Figure 5 the foregoing second type of transistor structure is taken as an example for illustration, its teachings can be similarly applied to various transistor structures such as the foregoing first type of transistor structure or other semiconductor device structures. As Figure 5 shown in (a) to (d) of Figure 5 , trenches are formed in a semiconductor substrate by the method mentioned previously. As Figure 5 shown in (e) of Figure 5 , a second portion of the semiconductor substrate adjacent to the bottom surface of the trench is irradiated with a first femtosecond laser beam 2051 to cause non-thermal melting thereof. As Figure 5 shown in (f) of Figure 5 , a fourth portion of the semiconductor substrate adjacent to the side surface of the trench is irradiated with a second femtosecond laser beam 2052 to cause non-thermal melting thereof. It can be understood that although the irradiation of the first femtosecond laser beam 2051 and the second femtosecond laser beam 2052 are described in (f) and (g) of Figure 5The fourth part of the semiconductor substrate is irradiated by the second femtosecond laser beam 2052. Therefore, at this time, the thickness d3 of the oxide layer formed in the fourth part of the semiconductor substrate is greater than Figure 3G the thickness d2 of the oxide layer formed in the fourth part of the semiconductor substrate that is not irradiated by the femtosecond laser beam as shown. Continuing to refer to Figure 5 , as Figure 5 shown in (h) of

[0140] , a gate, a source region, and a drain region can be further fabricated to form a second type of transistor structure.

[0141] In some embodiments, method 100 further includes: before performing the thermal oxidation treatment on the semiconductor substrate, performing a pull-back treatment on the hard mask layer to expose one or both of the fifth part and the sixth part of the semiconductor substrate that are respectively located on both sides of the top of the trench; irradiating one or both of the fifth part and the sixth part of the semiconductor substrate with a third femtosecond laser beam, such that one or both of the fifth part and the sixth part of the semiconductor substrate undergo non-thermal melting; and after completing the irradiation of the first femtosecond laser beam and the third femtosecond laser beam, performing a thermal oxidation treatment on the semiconductor substrate, such that an oxide layer is formed in the second part of the semiconductor substrate and one or both of the fifth part and the sixth part. Additionally, in some embodiments, the third femtosecond laser beam is the same as the first femtosecond laser beam. The irradiation of the third femtosecond laser beam and the irradiation of the first femtosecond laser beam (and the irradiation of the second femtosecond laser beam, if any) can be at least partially parallel or serial. Exemplarily, the irradiation of the first femtosecond laser beam and the irradiation of the third femtosecond laser beam are configured such that the depth of the region where non-thermal melting occurs in the second part of the semiconductor substrate is equal to the depth of the region where non-thermal melting occurs in one or both of the fifth part and the sixth part of the semiconductor substrate. Of course, the desired thickness of the oxide layer formed respectively in the second part of the semiconductor substrate and one or both of the fifth part and the sixth part can be achieved by respectively controlling the laser parameters and irradiation parameters of the first femtosecond laser beam and the third femtosecond laser beam to adjust the degree of non-thermal melting of the second part of the semiconductor substrate and one or both of the fifth part and the sixth part.

[0141] Referring to Figure 6 , Figure 6 shows a schematic cross-sectional view of a semiconductor device corresponding to the respective steps of a non-limiting example process for implementing a method for manufacturing a semiconductor device. Although Figure 6 the foregoing first type of transistor structure and second type of transistor structure are used as examples for illustration, its teachings can be similarly applied to various other transistor structures or other semiconductor device structures. As Figure 6As shown in (a) to (d) of, trenches 204 are formed in the semiconductor substrate by the method mentioned above, and the second part of the semiconductor substrate adjacent to the bottom surface of the trench is irradiated with the first femtosecond laser beam 2051. As Figure 6 As shown in (e) of, a pull-back process is performed on the hard mask layer to expose the fifth part and the sixth part of the semiconductor substrate respectively located on both sides of the top of the trench. As Figure 6 As shown in (f) of, the fifth part and the sixth part of the semiconductor substrate are irradiated with the third femtosecond laser beam 2053 identical to the first femtosecond laser beam 2051 to cause non-thermal melting thereof. It can be understood that although Figure 6 The irradiation processes of the first femtosecond laser beam 2051 and the third femtosecond laser beam 2053 are respectively described in (d) and (f) of, the irradiation of the third femtosecond laser beam 2053 can be at least partially parallel or serial with the irradiation of the first femtosecond laser beam 2051. As Figure 6 As shown in (g) of, after the irradiation of the first femtosecond laser beam 2051 and the third femtosecond laser beam 2053 is completed, the hard mask layer is removed. Then, as Figure 6 As shown in (h) of, the semiconductor substrate is subjected to a thermal oxidation process such that the thickness d4 of the oxide layer formed in each of the fifth part and the sixth part of the semiconductor substrate is substantially equal to the thickness d1 of the oxide layer formed in the second part 2011 of the semiconductor substrate 201, and is greater than the thickness d5 of the oxide layer formed at the horizontal surface of the semiconductor substrate that was previously under the hard mask layer and not irradiated by the first femtosecond laser beam 2051 and the third femtosecond laser beam 2053, and is also greater than the thickness d3 of the oxide layer formed at the vertical surface of the semiconductor substrate not subjected to femtosecond laser treatment. By providing thick oxide layers at both the top and bottom corners of the trench, the blocking voltage of the semiconductor device can be further increased and the electrical performance can be improved.

[0142] Furthermore, the Figure 6 oxide layer formed in (h) of can be used as a gate oxide layer to form transistor structures such as the aforementioned first type transistor structure and second type transistor structure. For example, as Figure 6 As shown in (i1) of, a gate is formed in the trench of the semiconductor substrate on top of the oxide layer, a source region or a drain region is formed in the eighth part of the semiconductor substrate on the side away from the trench of the fifth part and in the ninth part of the semiconductor substrate on the side away from the trench of the sixth part, and the other of the source region and the drain region is formed in the seventh part of the semiconductor substrate under the trench. Alternatively, as Figure 6 As shown in (i2) of, a gate is formed in the trench of the semiconductor substrate on top of the oxide layer, a source region or a drain region is formed in the eighth part of the semiconductor substrate, and the drain region or the source region and the drain region are formed in the ninth part of the semiconductor substrate. AsFigure 6 The transistor structures shown in (i1) and (i2) respectively can achieve a further extended conductive channel length compared to the transistor structures shown in Figure 3J and Figure 3I shown.

[0143] On the other hand, the present disclosure also provides a semiconductor device manufactured by a method according to any embodiment of the present disclosure. In some embodiments, the semiconductor device includes a MOSFET, wherein the oxide layer is configured to provide the gate oxide layer of the MOSFET. The semiconductor device manufactured according to the teachings of the present disclosure has a highly reliable oxide layer, and thus has improved electrical properties.

[0144] The words "left", "right", "front", "rear", "top", "bottom", "upper", "lower", "higher", "lower", etc. in the specification and claims, if any, are used for descriptive purposes and not necessarily for describing invariant relative positions. It should be understood that such words are interchangeable under appropriate circumstances, so that the embodiments of the present disclosure described herein, for example, can be operated in other orientations different from those shown or otherwise described herein. For example, when the device in the drawings is inverted, a feature originally described as "above" other features can then be described as "below" other features. The device can also be oriented in other ways (rotated 90 degrees or in other orientations), and the relative spatial relationships will be correspondingly interpreted at this time.

[0145] In the specification and claims, when an element is said to be "above", "attached" to, "connected" to, "coupled" to, or "in contact" with another element, etc., the element can be directly above, directly attached to, directly connected to, directly coupled to, or directly in contact with the other element, or there can be one or more intermediate elements. In contrast, when an element is said to be "directly" "above", "directly attached" to, "directly connected" to, "directly coupled" to, or "directly in contact" with another element, there will be no intermediate element. In the specification and claims, a feature arranged "adjacent" to another feature can mean that a feature has a part overlapping with the adjacent feature or a part located above or below the adjacent feature.

[0146] As used herein, the word "exemplary" means "serving as an example, instance, or illustration", rather than as a "model" to be precisely replicated. Any implementation described herein exemplarily is not necessarily to be construed as preferred or advantageous over other implementations. Moreover, the present disclosure is not limited by any theory expressed or implied in the technical field, background art, summary of the invention, or detailed description.

[0147] As used herein, the term "substantially" means including any minor variations caused by defects in design or manufacture, tolerances of devices or components, environmental effects, and / or other factors. The term "substantially" also allows for differences from a perfect or ideal situation due to parasitic effects, noise, and other practical considerations that may exist in an actual implementation.

[0148] In addition, for reference purposes only, terms such as "first", "second", etc. may also be used herein and are not intended to be limiting. For example, unless the context clearly indicates otherwise, the terms "first", "second", and other such numerical terms referring to structures or elements do not imply an order or sequence.

[0149] It should also be understood that when the term "comprising / including" is used herein, it specifies the presence of the stated features, integers, steps, operations, units, and / or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, units, and / or components and / or combinations thereof.

[0150] In this disclosure, the term "provide" is used broadly to cover all ways of obtaining an object, so "providing an object" includes, but is not limited to, "purchasing", "preparing / manufacturing", "arranging / setting", "installing / assembling", and / or "ordering" the object, etc.

[0151] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. The terms used herein are for the purpose of describing particular embodiments only and are not intended to limit this disclosure. As used herein, the singular forms "a", "an", and "the" are also intended to include the plural forms unless the context clearly indicates otherwise.

[0152] Those skilled in the art should realize that the boundaries between the above operations are merely illustrative. Multiple operations can be combined into a single operation, a single operation can be distributed among additional operations, and operations can be performed at least partially overlapped in time. Moreover, alternative embodiments can include multiple instances of a particular operation, and the order of operations can be changed in various other embodiments. However, other modifications, variations, and substitutions are also possible. The aspects and elements of all the embodiments disclosed above can be combined in any way and / or in combination with aspects or elements of other embodiments to provide multiple additional embodiments. Therefore, this specification and the drawings should be regarded as illustrative rather than restrictive.

[0153] Although some specific embodiments of the present disclosure have been described in detail by way of examples, those skilled in the art should understand that the above examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The embodiments disclosed herein can be combined arbitrarily without departing from the spirit and scope of the present disclosure. Those skilled in the art should also understand that various modifications can be made to the embodiments without departing from the scope and spirit of the present disclosure. The scope of the present disclosure is defined by the appended claims.

Claims

1. A method for manufacturing a semiconductor device, the method comprising: providing a semiconductor substrate having a trench formed therein; irradiating a second portion of the semiconductor substrate adjacent to the first portion of the trench with a femtosecond laser beam so that the second portion of the semiconductor substrate is non-thermally melted; as well as After the irradiation of the femtosecond laser beam is completed, the semiconductor substrate is subjected to a thermal oxidation treatment so that an oxide layer is formed on the second portion of the semiconductor substrate.

2. The method according to claim 1, wherein: In a sound crystal structure of the semiconductor substrate, an oxidation rate of a crystal plane where the first portion of the trench is located is lower than an oxidation rate of a crystal plane where a third portion of the trench different from the first portion is located.

3. The method according to claim 2, wherein: The femtosecond laser beam is a first femtosecond laser beam, and the method further comprises: Before performing thermal oxidation treatment on the semiconductor substrate, irradiating a fourth portion of the semiconductor substrate adjacent to the third portion of the trench with a second femtosecond laser beam so that the fourth portion of the semiconductor substrate is non-thermally melted; After the irradiation of the first femtosecond laser beam and the second femtosecond laser beam is completed, the semiconductor substrate is subjected to a thermal oxidation treatment so that the second portion and the fourth portion of the semiconductor substrate form an oxide layer, The irradiation of the first femtosecond laser beam and the irradiation of the second femtosecond laser beam are configured to make the depth of the non-thermal melting region in the second portion of the semiconductor substrate greater than the depth of the non-thermal melting region in the fourth portion of the semiconductor substrate.

4. The method according to claim 3, wherein: Satisfy at least one of the following: The irradiation duration of the first femtosecond laser beam is greater than the irradiation duration of the second femtosecond laser beam; or The intensity of the first femtosecond laser beam is greater than the intensity of the second femtosecond laser beam; or The first femtosecond laser beam and the second femtosecond laser beam are irradiated in a pulse form, and a pulse frequency of the first femtosecond laser beam is greater than a pulse frequency of the second femtosecond laser beam.

5. The method according to claim 2, wherein: The first portion of the trench is a bottom surface of the trench, and the third portion of the trench is a side surface of the trench.

6. The method according to claim 1, wherein: The semiconductor substrate includes silicon carbide.

7. The method according to claim 1, wherein: During the irradiation of the femtosecond laser beam, a ratio of a non-thermal melting process energy contribution of the second portion of the semiconductor substrate to a thermal melting process energy contribution of the second portion of the semiconductor substrate exceeds a preset ratio.

8. The method according to claim 7, wherein: The preset ratio is determined based on a value of the ratio of the non-thermal melting process energy contribution to the thermal melting process energy contribution at a point where the slope of the ratio is the largest as the laser parameter of the femtosecond laser beam changes.

9. The method according to claim 1, wherein: The laser parameter of the femtosecond laser beam is configured to be no less than a first laser parameter threshold at which the second portion of the semiconductor substrate begins to melt.

10. The method according to claim 9, wherein: Laser parameters of the femtosecond laser beam are configured to be no greater than a second laser parameter threshold at which the second portion of the semiconductor substrate is completely melted.

11. The method according to claim 10, wherein: The laser parameters of the femtosecond laser beam are set based on the relationship between the expected thickness of the oxide layer to be formed by the second portion of the semiconductor substrate and a first reference thickness and a second reference thickness, wherein the first reference thickness is the thickness of the oxide layer to be formed by the second portion of the semiconductor substrate when the femtosecond laser beam is irradiated at the first laser parameter threshold, and the second reference thickness is the thickness of the oxide layer to be formed by the second portion of the semiconductor substrate when the femtosecond laser beam is irradiated at the second laser parameter threshold.

12. The method according to any one of claims 8 to 11, wherein: The laser parameters of the femtosecond laser beam include intensity, wavelength or a combination thereof.

13. The method according to claim 1, wherein: Irradiating the second portion of the semiconductor substrate with the femtosecond laser beam includes irradiating the second portion of the semiconductor substrate with the femtosecond laser beam in a pulsed form.

14. The method according to claim 13, wherein: The pulse width of the femtosecond laser beam is set to be between 50 fs and 150 fs.

15. The method according to claim 13, wherein: The pulse frequency of the femtosecond laser beam is configured to cause continuous non-thermal melting of the second portion of the semiconductor substrate.

16. The method according to claim 13, wherein: The pulse frequency of the femtosecond laser beam is set to be greater than 1 MHz.

17. The method according to claim 1, wherein: The femtosecond laser beam is configured to irradiate in a direction parallel to a depth direction of the groove, and an irradiation region of the femtosecond laser beam is configured to cover the groove in a width direction of the groove.

18. The method according to claim 1, wherein: Irradiating the second portion of the semiconductor substrate with the femtosecond laser beam includes scanning the second portion of the semiconductor substrate with a single femtosecond laser beam or a plurality of femtosecond laser beams along a scanning direction parallel to a length direction of the trench.

19. The method according to claim 18, wherein: When the single femtosecond laser beam is scanned along the scanning direction over the second portion of the semiconductor substrate, a previous irradiation region and a next irradiation region of the single femtosecond laser beam partially overlap each other in the scanning direction; or When a plurality of femtosecond laser beams are caused to scan the second portion of the semiconductor substrate along the scanning direction, irradiation regions of each adjacent two of the plurality of femtosecond laser beams partially overlap each other in the scanning direction.

20. The method of claim 1, further comprising forming a gate over the oxide layer.

21. The method according to claim 20, further comprising: forming one of a source region and a drain region in a fifth portion of the semiconductor substrate at one side of the trench top, and forming the other of the source region and the drain region in a sixth portion of the semiconductor substrate at the other side of the trench top; or One of a source region and a drain region is formed in one or both of the fifth and sixth portions of the semiconductor substrate, and the other of the source region and the drain region is formed in a seventh portion of the semiconductor substrate below the trench.

22. The method according to claim 1, wherein: Providing a semiconductor substrate having a trench formed therein includes: forming a hard mask layer on a semiconductor substrate; forming a photoresist pattern on the hard mask layer to etch the hard mask layer and the semiconductor substrate to form a trench in the semiconductor substrate, Wherein, the femtosecond laser beam is a first femtosecond laser beam, and the method further comprises: Before performing a thermal oxidation process on the semiconductor substrate, performing a pull-back process on the hard mask layer to expose one or both of a fifth portion and a sixth portion of the semiconductor substrate respectively located on both sides of the top of the trench; irradiating one or both of the fifth portion and the sixth portion of the semiconductor substrate with a third femtosecond laser beam so that one or both of the fifth portion and the sixth portion of the semiconductor substrate undergo non-thermal melting; and After the irradiation of the first femtosecond laser beam and the third femtosecond laser beam is completed, the semiconductor substrate is subjected to a thermal oxidation treatment so that an oxide layer is formed on the second portion of the semiconductor substrate and one or both of the fifth portion and the sixth portion.

23. The method according to claim 22, wherein: The irradiation of the first femtosecond laser beam and the irradiation of the third femtosecond laser beam are configured so that the depth of the region where non-thermal melting occurs in the second portion of the semiconductor substrate is equal to the depth of the region where non-thermal melting occurs in one or both of the fifth portion and the sixth portion of the semiconductor substrate.

24. The method according to claim 22, wherein: The method further includes forming a gate on the oxide layer, And wherein the method further comprises: forming one of the source region and the drain region in an eighth portion of the semiconductor substrate located at a side of the fifth portion away from the trench, and forming the other of the source region and the drain region in a ninth portion of the semiconductor substrate located at a side of the sixth portion away from the trench; or One of a source region and a drain region is formed in one or both of the eighth and ninth portions of the semiconductor substrate, and the other of the source region and the drain region is formed in a seventh portion of the semiconductor substrate below the trench.

25. A semiconductor device manufactured by the method according to any one of claims 1 to 24.

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