A reconfigurable all-digital in-memory computing macrosystem based on dynamic logic

Abstract

The present invention discloses a reconfigurable all-digital in-memory computing macro system based on dynamic logic, which relates to in-memory computing technology and proposes this solution to solve the problem of single operation in the prior art. It includes: an SRAM storage array, 32 reconfigurable computing units, and a macro controller; the SRAM storage array is 64 rows × 128 columns, which is used to store data required for calculation; the reconfigurable computing unit is used in conjunction with the SRAM storage array, and every 4 columns correspond to a reconfigurable computing unit; the macro controller is used to control the SRAM storage array to select the read and write word lines; and is used to select the calculation mode and calculation bit width for the reconfigurable computing unit. The advantage is that dynamic logic is used, which has a higher operating frequency and throughput than other in-memory computing macros implemented under the same process. The reconfigurable Manchester carry chain allows the system to support more diverse bit precision. The logic computing unit is highly reusable and can realize 7 different computing operations.

Description

Technical Field

[0001] The present invention relates to in-memory computing technology, and in particular to a reconfigurable all-digital in-memory computing macro system based on dynamic logic. Background Art

[0002] As an emerging technology, in-memory computing technology effectively solves the power consumption and bandwidth cost problems caused by large-scale data transmission in large-scale matrix-vector multiplication by tightly coupling the logical computing unit directly with the memory unit. This tightly coupled design allows data to be processed directly in the memory during the calculation process, avoiding frequent data transmission, thereby reducing energy consumption and bandwidth requirements. Especially in edge computing and IoT artificial intelligence applications, energy consumption and cost are often critical considerations. Processors based on in-memory computing can effectively meet the needs of these applications, thus providing an important impetus for their development.

[0003] However, most current digital in-memory computing macro designs focus on optimizing specific operators or specific data formats, but lack comprehensive support for a variety of different operators and multiple data bit widths. Especially in actual IoT artificial intelligence application scenarios, it is necessary not only to accelerate basic operations such as matrix-vector multiplication, but also to support more types of operations. For example, in audio processing tasks, preprocessing operations such as fast Fourier transform are often required to extract feature signals, but most current in-memory computing technologies do not support these complex operations. Therefore, further research and development of in-memory computing technologies that support multiple operators and data bit widths to meet the growing application needs is a technical problem that needs to be solved at present. Summary of the invention

[0004] The object of the present invention is to provide a reconfigurable all-digital in-memory computing macro system based on dynamic logic to solve the problems existing in the above-mentioned prior art.

[0005] The present invention discloses a reconfigurable all-digital in-memory computing macro system based on dynamic logic, comprising: an SRAM storage array, 32 reconfigurable computing units, and a macro controller;

[0006] The SRAM storage array has 64 rows×128 columns and is used to store data required for calculation;

[0007] The reconfigurable computing unit is used in conjunction with the SRAM storage array, and every four columns correspond to one reconfigurable computing unit;

[0008] The macro controller is used to control the SRAM storage array to select the read and write word lines; and is used to select the calculation mode and calculation bit width for the reconfigurable calculation unit.

[0009] A single bit in the SRAM storage array includes 6 positive transistors, 6 reverse transistors and 2 inverters; one pole of the 6 positive transistors is in common with the input end of the first inverter and the output end of the second inverter; one pole of the 6 reverse transistors is in common with the output end of the first inverter and the input end of the second inverter; the other poles of the 6 positive transistors and the 6 reverse transistors away from the inverter are respectively connected to the reconfigurable computing unit as bit lines; the gates of the 6 positive transistors and the 6 reverse transistors are respectively connected to the macro controller as word lines; the 6 positive transistors and the 6 reverse transistors have the same structure and are all NMOS transistors.

[0010] Each reconfigurable computing unit includes a group of half adders implemented with dynamic logic to calculate the intermediate values ​​required for subsequent operations; a group of reconfigurable Manchester carry chains to perform calculations on various data bit widths; and a group of Booth encoders and shifters to perform Booth multiplication operations.

[0011] The specific structure of the half adder:

[0012] One electrode of the first transistor is connected to the first input signal, the other electrode is connected to the XOR logic result, and the gate is connected to the second input signal;

[0013] One electrode of the second transistor is connected to the inverted signal of the first input signal, the other electrode is connected to the XOR logic result SUM, and the gate is connected to the inverted signal of the second input signal;

[0014] One electrode of the third transistor is connected to the first input signal, the other electrode is connected to the logical result, and the gate is connected to the inverse signal of the second input signal;

[0015] One electrode of the fourth transistor is grounded, the other electrode is connected to the XOR logic result, and the gate is connected to the dynamic logic switch;

[0016] One electrode of the fifth transistor is grounded, the other electrode is connected to the logic result, and the gate is connected to the dynamic logic switch;

[0017] Among them, the first transistor, the second transistor and the third transistor are PMOS transistors, and the fourth transistor and the fifth transistor are NMOS transistors.

[0018] The reconfigurable all-digital in-memory computing macro system based on dynamic logic described in the present invention has the advantage that it adopts dynamic logic and has a higher operating frequency and throughput than other in-memory computing macros implemented under the same process. The reconfigurable Manchester carry chain allows the system to support a wider range of bit precision. The logic calculation unit is highly reusable and can implement 7 different calculation operations. Using 40nm CMOS technology for transistor-level post-simulation, an operating frequency of 800MHz is achieved at a power supply voltage of 1.1V. For 8-bit operations, addition reaches 6.4GOPS and multiplication reaches 1.6GOPS. At a power supply voltage of 0.9V, the energy efficiency ratio of 8-bit addition reaches 4.22TOPS / W, and that of 8-bit multiplication reaches 0.76TOPS / W. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a structural schematic diagram of the reconfigurable all-digital in-memory computing macro system described in the present invention.

[0020] Figure 2 It is a schematic diagram of the structure of a single bit in the SRAM storage array described in the present invention.

[0021] Figure 3 It is a schematic diagram of the structure of the half adder described in the present invention.

[0022] Figure 4 It is a schematic diagram of the structure of the Manchester carry chain described in the present invention.

[0023] Figure 5 It is a schematic diagram of the operation principle of the multifunctional calculation circuit in the present invention except for multiplication.

[0024] Figure 6 It is a schematic diagram of the principle of multifunctional computing circuit in the present invention in multiplication operation.

[0025] Figure 7 It is a schematic diagram of the reconfigurable computing flow of the reconfigurable all-digital in-memory computing macro system described in the present invention. DETAILED DESCRIPTION

[0026] like Figure 1 As shown, the reconfigurable all-digital in-memory computing macro system based on dynamic logic described in the present invention includes: an SRAM storage array, 32 reconfigurable computing units, and a macro controller.

[0027] The SRAM storage array has 64 rows×128 columns and is used to store data required for calculation.

[0028] The reconfigurable computing unit is used in conjunction with the SRAM storage array, with one reconfigurable computing unit corresponding to every four columns. Each reconfigurable computing unit includes a group of half adders implemented with dynamic logic for calculating intermediate values ​​required for subsequent operations; a group of reconfigurable Manchester carry chains for performing calculations on various data bit widths; and a group of Booth encoders and shifters for performing Booth multiplication operations.

[0029] The macro controller is used to control the SRAM storage array to select the read and write word lines; and is used to select the calculation mode and calculation bit width for the reconfigurable calculation unit.

[0030] At present, the typical 6-transistor SRAM has only one half-duplex read and write channel. Only one row of data can be read at a time in the same array, and data cannot be written at the same time, which limits the computing efficiency. Figure 2 As shown, the SRAM storage array described in this embodiment is constructed based on multiple read and write channels, and a 6-channel SRAM storage array structure is proposed, which can realize simultaneous reading and writing of multiple rows in the same array, increasing the operation efficiency while supporting more complex reconfigurable operation operations. The single bit structure in the SRAM storage array is shown in FIG. Figure 2 As shown, it includes 6 normal transistors, 6 reverse transistors and 2 inverters; one pole of the 6 normal transistors is in common with the input end of the first inverter and the output end of the second inverter; one pole of the 6 reverse transistors is in common with the output end of the first inverter and the input end of the second inverter; the other poles of the 6 normal transistors and the 6 reverse transistors away from the inverter are connected to the reconfigurable computing unit as bit lines respectively; the gates of the 6 normal transistors and the 6 reverse transistors are connected to the macro controller as word lines respectively. The 6 normal transistors and the 6 reverse transistors have the same structure, and are all NMOS tubes. In this embodiment, the common pole can be either the source or the drain.

[0031] Calculation macros based on dynamic logic:

[0032] Since static logic requires a large number of transistors, the node capacitance is larger than that of dynamic logic, resulting in longer propagation delay. Therefore, the present invention proposes a half adder based on dynamic logic, such as Figure 3 As shown in Figure 1, this unit only needs five transistors to implement AND and XOR operations. This unit calculates the intermediate values ​​commonly used in addition operations, helps to simplify the adder circuit design, and provides support for bit operations.

[0033] The specific structure of the half adder:

[0034] One electrode of the first transistor M0 is connected to the first input signal IN1, the other electrode is connected to the XOR logic result SUM, and the gate is connected to the second input signal IN2;

[0035] One electrode of the second transistor M1 is connected to the inverted signal IN1b of the first input signal, the other electrode is connected to the XOR logic result SUM, and the gate is connected to the inverted signal IN2b of the second input signal;

[0036] One electrode of the third transistor M2 is connected to the first input signal IN1, the other electrode is connected to the logic result C0, and the gate is connected to the inverted signal IN2b of the second input signal;

[0037] One electrode of the fourth transistor M3 is grounded, the other electrode is connected to the XOR logic result SUM, and the gate is connected to the dynamic logic switch F;

[0038] One electrode of the fifth transistor M4 is grounded, the other electrode is connected to the logic result C0, and the gate is connected to the dynamic logic switch F;

[0039] Among them, the first transistor M0 , the second transistor M1 , and the third transistor M2 are PMOS transistors, and the fourth transistor M3 and the fifth transistor M4 are NMOS transistors.

[0040] Working principle of half adder: The result of AND operation of IN1 and IN2 is CO signal, and the result of XOR operation is SUM signal. In each cycle, dynamic logic switch F is first set to Vdd, and CO and SUM are precharged to ground. Then F is set to 0, M3 and M4 are turned on, and the operation starts. When calculating CO, in the precharge stage, when F is 1 and M4 is turned on, CO is set to 0. In the calculation stage, only when IN1 and IN2 are both 1, M2 is turned on, CO is pulled to a high level, thereby generating an AND signal. When calculating SUM, it is also first precharged to 0. In the calculation stage, only when IN1=1 and IN2=0 or IN1=0 and IN2=1, M0 or M1 is turned on, SUM is pulled to a high level, thereby generating an XOR signal. The truth table is as follows:

[0041] IN1 IN1b IN2 IN2b CO SUM 0 1 0 1 0 0 0 1 1 0 0 1 1 0 0 1 0 1 1 0 1 0 1 0

[0042] Since traditional high-performance adder circuits usually adopt an adder tree structure, this design often brings challenges to the flexibility and layout regularity of the adder circuit. Therefore, the present invention adopts a structure with a Manchester carry chain of 4 bits per group, which has the advantage of a regular layout, such as Figure 4 In addition, the connection relationship of the Manchester carry chain can be determined by the macro controller according to the required calculation bit width, and the calculation of any 4 times bit width data can be realized by controlling whether the transmission gates between the Manchester carry chains are turned on or not. The Manchester carry chain using dynamic logic provides higher area efficiency, lower power consumption and faster speed.

[0043] like Figure 4As shown, when BP = 1, G = CO, P = SUM, BP = P0 = P1 = P2 = P3, the carry input is immediately sent to the next module through the bypass transistor. If BP ≠ 1, the carry output is obtained through the normal path. Through the bypass channel, the Manchester carry chain as an adder can significantly reduce the delay introduced by the cascade while maintaining balanced delay and flexibility. Due to the increase in bypass, the increase in area is also small, typically between 10% and 20%.

[0044] Based on the above calculation macro, the reconfigurable all-digital in-memory calculation macro system of the present invention can realize a variety of operation operators including row copy, two logical operations, addition, subtraction, and multiplication, wherein the multiplication includes a shift operation and uses a radix 4 booth multiplication. Since different addresses are used for writing back, operations other than multiplication can be realized in the same cycle.

[0045] Two logical operations and row replication: Figure 5 The structure shown can implement other operations besides multiplication, including AND and XOR Boolean operations. For row copying, the macro controller selects the row to be copied and performs XOR operation with a pre-set all-0 row, and writes it into the target row, so that row copying can be implemented.

[0046] Addition and subtraction operations: Addition operations are implemented based on half adders and Manchester carry chains. When performing subtraction, IN1 must first be converted to its complement and added to IN2. For the negation operation, the SUB signal is set to 1, so IN1 is inverted by the XOR gate; for the addition operation, the SUB signal also provides a carry of 1 to the Manchester carry chain.

[0047] Multiplication: In the past, digital in-memory calculations usually used a bit-serial method to perform multiplication, which required M cycles to input M bits of input and complete the multiplication. In order to perform multiplication more efficiently in the CIM macro, the present invention uses a radix-4 Booth multiplication that is more friendly to in-memory calculations. Using encoding technology, the Booth-4 multiplier reduces the number of partial products, thereby reducing hardware costs while achieving higher computational efficiency. To perform an M-bit multiplication and write the result back to the SRAM, only M / 2 cycles are required.

[0048] In the radix 4-Booth multiplication operation, the encoder generates TWO, ZERO, and NEG signals to generate partial products. In order to avoid interference of these signals with other operations, the encoder will not work when performing other operations. This ensures that the encoded signal will not be incorrectly transmitted to other components when performing other operations, thereby ensuring the stability and correctness of the system. In the accumulation process, the hardware resource utilization is optimized and the area overhead is reduced by reusing the addition circuit. The shift operation is achieved by reusing the shifter in the multiplication. The reuse structure enables the hardware to be dynamically configured, thereby reducing power consumption.

[0049] Figure 6 The principle of radix 4-booth multiplication is demonstrated. Taking 8×8 multiplication as an example, a total of 4 cycles from t0 to t3 are required. In each cycle, SRAM needs to read out 3 data: 1) read the multiplier IN2 to the encoder for Booth encoding to generate signals NEG, ZERO, and TWO; 2) read the multiplicand IN1 to a bit shifter. When the TWO signal is 1, IN1 is shifted left by one bit. When the TWO signal is 0, it is not shifted. When the ZERO signal is 1, IN1 is directly set to 0 to generate partial products; 3) When it is t0 cycle, the accumulated sum is initially set to 0 and output. When it is t1-t3 cycle, the accumulated sum of the previous cycle is read out to the two-bit shifter for left shifting by two bits. In the addition and subtraction unit, the NEG signal replaces the input of the SUB signal and is used to invert and add one. The shifted accumulated sum and partial products are used as the data input of the addition and subtraction unit, and the output result is written back to the SRAM accumulation unit as the new accumulated sum.

[0050] The overall reconfigurable calculation flow chart is as follows Figure 7 shown.

[0051] For those skilled in the art, various other corresponding changes and deformations can be made according to the technical solutions and concepts described above, and all of these changes and deformations should fall within the protection scope of the claims of the present invention.

Claims

1. A reconfigurable all-digital in-memory computing macro system based on dynamic logic, characterized in that: include: An SRAM storage array, 32 reconfigurable computing units, and a macro controller; The SRAM storage array has 64 rows×128 columns and is used to store data required for calculation; The reconfigurable computing unit is used in conjunction with the SRAM storage array, and every four columns correspond to one reconfigurable computing unit; The macro controller is used to control the SRAM storage array to select the read and write word lines; and for selecting a computing mode and a computing bit width for a reconfigurable computing unit; A single bit cell in the SRAM storage array includes 6 positive transistors, 6 negative transistors and 2 inverters; One pole of the six positive transistors is in common with the input end of the first inverter and the output end of the second inverter; one pole of the six reverse transistors is in common with the output end of the first inverter and the input end of the second inverter; the other poles of the six positive transistors and the six reverse transistors away from the inverter are respectively connected to the reconfigurable computing unit as bit lines; the gates of the six positive transistors and the six reverse transistors are respectively connected to the macro controller as word lines; the six positive transistors and the six reverse transistors have the same structure and are all NMOS transistors; Each reconfigurable computing unit includes a set of half adders implemented with dynamic logic to calculate the intermediate values ​​required for subsequent operations; a set of reconfigurable Manchester carry chains to perform calculations on various data bit widths; a set of Booth encoders and shifters to perform Booth multiplication operations; The specific structure of the half adder: One electrode of the first transistor is connected to the first input signal, the other electrode is connected to the XOR logic result, and the gate is connected to the second input signal; One electrode of the second transistor is connected to the inverted signal of the first input signal, the other electrode is connected to the XOR logic result SUM, and the gate is connected to the inverted signal of the second input signal; One electrode of the third transistor is connected to the first input signal, the other electrode is connected to the logical result, and the gate is connected to the inverse signal of the second input signal; One electrode of the fourth transistor is grounded, the other electrode is connected to the XOR logic result, and the gate is connected to the dynamic logic switch; One electrode of the fifth transistor is grounded, the other electrode is connected to the logic result, and the gate is connected to the dynamic logic switch; Among them, the first transistor, the second transistor and the third transistor are PMOS transistors, and the fourth transistor and the fifth transistor are NMOS transistors.

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