A perovskite / silicon tandem solar cell and a method for preparing the same

Abstract

The invention discloses a perovskite / silicon stacked solar cell and a preparation method thereof, the method comprising the following steps: preparing a silicon wafer with asymmetric velvet on both sides; preparing a bottom cell with the prepared silicon wafer with asymmetric velvet on both sides as a substrate; removing the anti-reflection film layer on the front side of the bottom cell by acid, and then preparing a carrier recombination layer on the front side of the bottom cell; preparing a hole transport layer on the carrier recombination layer; preparing a perovskite layer on the hole transport layer; preparing an electron transport layer on the perovskite layer; preparing a transparent conductive layer on the electron transport layer; preparing a front anti-reflection layer and a front metal electrode on the transparent conductive layer; the preparation of the silicon wafer comprises: firstly alkali double-sided velvet, back boron doping, removing the front winding and then polishing, then front laser ablation velvet, and finally cleaning and annealing repair. The perovskite / silicon stacked solar cell of the invention can improve the cell conversion efficiency and avoid the leakage of the cell by preparing the bottom cell silicon wafer with asymmetric velvet on both sides.

Description

Technical Field

[0001] The present invention relates to the field of solar cells, and in particular to a perovskite / silicon stacked solar cell and a preparation method thereof. Background Art

[0002] With the continuous development of the photovoltaic industry, the dominant silicon cells have also ushered in new challenges in their development history. At present, the efficiency of crystalline silicon cells has approached the theoretical efficiency limit of 29.4%, and the mass-produced PERC cells have also exceeded the efficiency of 23%. How to break through the efficiency limit of silicon cells has become a hot research topic in the academic community today. The basic principle of perovskite / crystalline silicon stacking technology is to stack perovskite materials and crystalline silicon materials together to form a heterojunction, and use the wide band gap, high absorption coefficient and high carrier mobility of perovskite materials and the stability and good electron transmission performance of crystalline silicon materials to improve the photoelectric conversion efficiency of solar cells. As a new type of battery, perovskite / silicon stacked solar cells are increasingly receiving widespread attention in the photovoltaic industry. Stacked cells broaden the scope of solar energy spectrum utilization and improve battery efficiency. After just a few years, the efficiency reached 31.3%, and its theoretical limit exceeded 40%. Stacked cells have great commercial application value.

[0003] In silicon heterojunction cells, when the perovskite layer contacts crystalline silicon, the sharp pyramid top and bottom prevent the perovskite layer from evenly covering the crystalline silicon surface, thereby introducing new defects in the perovskite layer and the carrier transport layer, resulting in low photoelectric conversion efficiency of the cell. Therefore, uniformly and conformally covering the perovskite layer on the crystalline silicon surface is an effective way to improve the contact problem between the two, and it is also the technical difficulty faced by the current tandem cells.

[0004] At present, in order to increase the photon absorption of crystalline silicon cells, the plane in contact with the perovskite cell is made into a velvet structure with lower reflectivity, and the cell efficiency has been further improved. The commonly used method is to use the alkali velvet method, but the velvet obtained by this method is large and uneven. The perovskite layer needs to be deposited on the pyramid velvet later. The sharp spire and bottom of the pyramid are prone to defects, which in turn affects the performance of the stacked solar cell. At present, there is only the use of laser ablation to prepare velvet in crystalline silicon cells. This method solves the problems of large and uneven velvet and difficult to control reactions, but the problem that comes with it is that the lattice damage is large, and there is only one velvet process. The expansion during the doping process is difficult to remove, and there are problems such as battery leakage. Summary of the invention

[0005] The present invention aims at the above-mentioned problems, makes up for the deficiencies of the prior art, and provides a method for preparing a perovskite / silicon stacked solar cell to solve the problems arising from the above-mentioned background technology.

[0006] The technical solution of the present invention is: a method for preparing a perovskite / silicon stacked solar cell, comprising the following steps:

[0007] S1 prepares a double-sided asymmetric velvet silicon wafer;

[0008] S2 uses the prepared double-sided asymmetric velvet silicon wafer as a substrate to prepare a bottom cell;

[0009] S3 uses acid to remove the anti-reflection film layer on the front side of the bottom battery, and then prepares a carrier recombination layer on the front side of the bottom battery;

[0010] S4: preparing a hole transport layer on the carrier recombination layer;

[0011] S5 preparing a perovskite layer on the hole transport layer;

[0012] S6 preparing an electron transport layer on the perovskite layer;

[0013] S7: preparing a transparent conductive layer on the electron transport layer;

[0014] S8: preparing a front anti-reflection layer and a front metal electrode on the transparent conductive layer;

[0015] The steps in S1 include: firstly alkali double-sided texturing, back-side boron doping, front-side detangling and polishing, front-side laser ablation texturing, and finally cleaning and annealing repair.

[0016] Preferably, the alkaline double-sided texturing in S1 adopts alkaline solution etching for texturing; the back side boron doping in S1 adopts BCl3 as the doping source for doping; the front side deflection removal and polishing in S1 includes removing the front side deflection with acid solution and then polishing the front side with alkaline solution; the front side laser ablation texturing in S1 includes laser ablation texturing of the polished surface produced on the front side with a laser; the cleaning and annealing repair in S1 includes cleaning with alkaline solution and NH3 / H2O2 cleaning solution and repairing the damage of silicon wafer by annealing under a protective atmosphere.

[0017] Preferably, in the alkaline double-sided texturing, the mass fraction of the alkaline solution is 0.5-2wt%, and the etching time is 400S-600S;

[0018] The boron doping temperature is 800-1000°C, the doping square resistance is 200-300Ω / □, the doping thickness is 0.5-0.9μm, and the doping concentration is 1-5E18cm -3; In the de-twisting and re-polishing of the front surface, the mass fraction of the acid solution is 5-20wt%, and the mass fraction of the alkali solution is 3-8wt%; in the front laser ablation and texturing, the setting parameters of the laser are: output power 10-70W, pulse repetition frequency 5-20kHz, laser spot diameter 5-15Pm and laser beam speed 30-60mm / s; in the cleaning and annealing repair, the cleaning time is 100-300S, the annealing repair temperature is 800℃-1000℃, and the annealing repair time is 20min-40min.

[0019] Preferably, the average height of the back velvet surface obtained by alkali double-sided velvet processing in S1 is 0.9-1.2µm, and the grooved velvet surface is formed by laser ablation on the front side in S1, the average distance between the grooves is 30-150µm, and the average depth of the grooves is 0.5-0.9µm.

[0020] Preferably, the method for preparing the carrier recombination layer in S3 is the same as the method for preparing the transparent conductive layer in S7: using PVD magnetron sputtering equipment, under a pressure of ≤1Pa and an atmosphere with an argon-oxygen ratio of 1:0.02-0.1, the power density is 1-3W / cm 2 ; The S4 method for preparing a hole transport layer: preparing a dense TiO2 layer at a high temperature of 400-550°C by a spray thermal decomposition method; The S5 method for preparing a perovskite layer is the same as the S6 method for preparing an electron transport layer: forming it by a coating method followed by annealing.

[0021] The present invention also provides a perovskite / silicon stacked solar cell, comprising: a silicon bottom cell with a double-sided asymmetric velvet surface, wherein the front side of the silicon bottom cell is provided with a carrier recombination layer, a hole transport layer, a perovskite layer, an electron transport layer, a transparent conductive layer, a front anti-reflection layer, and a front metal electrode in sequence from the inside to the outside;

[0022] The front velvet surface of the double-sided asymmetric velvet silicon bottom battery is a smooth and uniform velvet structure in the shape of gullies, and the back velvet surface of the double-sided asymmetric velvet silicon bottom battery is a pyramid velvet structure with uneven sizes.

[0023] Preferably, the average height of the back suede surface is 0.9-1.2 µm, the average distance between the grooves in the front suede surface is 30-150 µm, and the average depth of the grooves in the front suede surface is 0.5-0.9 µm.

[0024] Preferably, the carrier recombination layer and the transparent conductive layer are both made of ITO, and both have a thickness of 80-100 nm; the hole transport layer is made of TiO2, and has a thickness of 30-100 nm.

[0025] Preferably, the band gap width of the perovskite layer is 1.3-1.8 eV, the perovskite material structure is ABX3, wherein A is any one of methylamine, formamidine, Cs or a mixture of several cations, B is Pb or Sn, X is any one of Cl, Br, I or a mixture of three anions, and its thickness is 800-1200 nm.

[0026] Preferably, the electron transport layer material is SnO2, and its thickness is 15-40nm.

[0027] Compared with the prior art, the present invention has the following beneficial effects:

[0028] (1) In the preparation of silicon wafers, the present invention uses double-sided alkaline texturing to form a pyramid-shaped texture on the back side with uneven sizes, which can increase the PN node area, increase the number of photons absorbed, and increase the current; the front side is dewound and then polished to avoid leakage, and the front polished surface is ablated by laser. Since the ablation of the front polished surface forms a smooth and uniform grooved texture structure, it is beneficial to achieve uniform and conformal coverage of the perovskite layer on the crystalline silicon surface in the stacked battery. Secondly, the groove shape can reduce the reflectivity of the front side of the crystalline silicon bottom battery, increase the carrier concentration, and increase the open circuit voltage and short circuit current. The groove shape is only formed on one side, and only part of the texture is ablated. The silicon wafer thickness loss is small and the lattice damage is small, the damage to the silicon substrate is smaller, and the effect on carrier generation is small; finally, the lattice damage is repaired by cleaning and annealing. The perovskite / silicon stacked solar cell of the present invention can further improve the short circuit current, open circuit voltage, and fill factor through the preparation of double-sided asymmetric texture, thereby improving the battery conversion efficiency and avoiding battery leakage.

[0029] (2) The present invention forms a groove shape by laser etching, with an average distance between the groove shapes of 30-150µm and an average groove depth of 0.5-0.9µm. Within this range, the perovskite film layer can be evenly coated, and the thickness loss of the silicon wafer and the lattice damage can be minimized. The average height of the velvet surface on the back is maintained between 0.9-1.2µm, which can maintain good emitter uniformity. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 The preparation flow chart of perovskite / silicon tandem solar cells;

[0031] Figure 2 Schematic diagram of the structure of a perovskite / silicon tandem solar cell;

[0032] Figure 3 Schematic diagram of the bottom cell structure of a perovskite / silicon tandem solar cell;

[0033] Figure 4 This is the SEM image of the front velvet surface of the silicon wafer;

[0034] Figure 5 This is the SEM image of the velvet surface on the back of the silicon wafer;

[0035] In the figure: 1-bottom cell, 2-carrier recombination layer, 3-hole transport layer, 4-perovskite layer, 5-electron transport layer, 6-transparent conductive layer, 7-front anti-reflection layer, 8-front metal electrode, 11-silicon wafer, 12-boron-doped layer, 13-tunneling oxide layer, 14-phosphorus-doped layer, 15-passivation film layer, 16-back anti-reflection layer, 17-back metal electrode. DETAILED DESCRIPTION

[0036] The following will be combined with the accompanying drawings in the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work belong to the protection scope of the present invention.

[0037] like Figure 1 As shown, a method for preparing a perovskite / silicon tandem solar cell comprises the following steps:

[0038] S1 prepares a silicon wafer 11 with asymmetric texture on both sides;

[0039] S2 prepares a bottom cell 1 using the prepared double-sided asymmetric velvet silicon wafer as a substrate;

[0040] S3 uses acid to remove the anti-reflection film layer on the front side of the bottom battery, and then prepares a carrier recombination layer 2 on the front side of the bottom battery;

[0041] S4: preparing a hole transport layer 3 on the carrier recombination layer;

[0042] S5: preparing a perovskite layer 4 on the hole transport layer;

[0043] S6 preparing an electron transport layer 5 on the perovskite thin layer;

[0044] S7: preparing a transparent conductive layer 6 on the electron transport layer;

[0045] S8: preparing a front anti-reflection film 7 and a front metal electrode 8 on the transparent conductive layer;

[0046] The steps in S1 include: firstly alkali double-sided texturing, back-side boron doping, front-side detangling and polishing, front-side laser ablation texturing, and finally cleaning and annealing repair.

[0047] In the preparation of silicon wafers, the present invention uses double-sided alkaline texturing to form a pyramid-shaped texture with uneven sizes on the back side, which can increase the PN node area, increase the number of photon absorption, and increase the current; the front side is dewound and then polished to avoid leakage, and the front polished surface is ablated by laser. Since the ablation of the front polished surface forms a smooth and uniform grooved texture structure, it is beneficial to achieve uniform and conformal coverage of the perovskite layer on the crystalline silicon surface in the stacked battery. Secondly, the groove shape can reduce the reflectivity of the front side of the crystalline silicon bottom battery, increase the carrier concentration, and increase the open circuit voltage and short circuit current. The groove shape is only formed on one side, and only part of the texture is ablated, so the silicon wafer thickness loss is small and the lattice damage is small, the damage to the silicon substrate is smaller, and the influence on carrier generation is small; finally, the lattice damage is repaired by cleaning and annealing; the perovskite / silicon stacked solar cell of the present invention can further improve the short circuit current, open circuit voltage, and fill factor through the preparation of double-sided asymmetric texture, thereby improving the battery conversion efficiency and avoiding battery leakage.

[0048] As a preferred embodiment, the alkaline double-sided texturing in S1 adopts alkaline solution etching for texturing; the back side boron doping in S1 adopts BCl3 as the doping source for doping; the front side deflection removal and polishing in S1 includes removing the front side deflection with acid solution and then polishing the front side with alkaline solution; the front side laser ablation texturing in S1 includes laser ablation texturing of the polished surface produced on the front side with a laser; the cleaning and annealing repair in S1 includes cleaning with alkaline solution and NH3 / H2O2 cleaning solution and repairing the damage of silicon wafer by annealing under a protective atmosphere.

[0049] As a preferred implementation, the silicon wafer in S1 is an N-type silicon wafer with a resistivity of 1.0-7.0Ωcm and a thickness of 100-200µm.

[0050] As a preferred embodiment, in the alkaline double-sided texturing, the mass fraction of the alkaline solution is 0.5-2wt%, the etching time is 400S-600S; the doping temperature of the boron doping is 800-1000°C, the doping square resistance is 200-300Ω / □, the doping thickness is 0.5-0.9μm, and the doping concentration is 1-5E18cm -3 ; In the de-twisting and re-polishing of the front surface, the mass fraction of the acid solution is 5-20wt%, and the mass fraction of the alkali solution is 3-8wt%; in the front laser ablation and texturing, the setting parameters of the laser are: output power 10-70W, pulse repetition frequency 5-20kHz, laser spot diameter 5-15Pm and laser beam speed 30-60mm / s; in the cleaning and annealing repair, the cleaning time is 100-300S, the annealing repair temperature is 800℃-1000℃, and the annealing repair time is 20min-40min.

[0051] As a preferred embodiment, the average height of the back side velvet produced by double-sided alkali velvet in S1 is 0.9-1.2µm, the front side is laser ablated to form a groove-shaped velvet in S1, the average distance between the grooves is 30-150µm, and the average depth of the grooves is 0.5-0.9µm; specifically, the average height of the back side velvet is 0.9µm, 1.0µm, 1.1µm, 1.2µm or any range composed of the above values, preferably, the average height of the back side velvet is 1.0-1.1µm; for structures with an average height of less than 0.9μm, it cannot be completed by changing the etching concentration and time under the existing experimental conditions; for structures with an average height of less than 1.2μm, relative to 0.9-1.2μm, it is not conducive to better electrical performance. Specifically, the average distance between the grooves is 30µm, 40µm, 50µm, 60µm, 70µm, 80µm, 90µm, 100µm, 110µm, 120µm, 130µm, 140µm, 150µm or any range thereof, preferably, the average distance between the grooves is 50-130µm; specifically, the average depth of the grooves is 0.5µm, 0.6µm, 0.7µm, 0.8µm, 0.9µm or any range thereof, preferably, the average depth of the grooves is 0.6-0.8µm. When the average distance or average depth of the grooves is too small, the lattice damage is large and the electrical properties are relatively weak; when the average distance or average depth of the grooves is too large, it is not conducive to better electrical properties.

[0052] The grooved velvet surface formed by laser etching in the present invention has an average distance between the grooves of 30-150µm and an average depth of 0.5-0.9µm. Within this range, the perovskite film layer can be evenly coated, and the thickness loss of the silicon wafer and the lattice damage can be reduced as much as possible; the average height of the back velvet surface is maintained between 0.9-1.2µm, which can maintain good emitter uniformity.

[0053] As a preferred implementation, S2 includes:

[0054] S2-1 uses LPCVD technology to deposit a tunnel oxide layer 13 with a thickness of 1-3 nm; and continues to deposit an intrinsic polysilicon layer with a thickness of 50-150 nm. POCl3 is used as a doping source to dope the intrinsic polysilicon layer at a doping temperature of 800-900°C and a doping concentration of 1-5E20cm -3 ;

[0055] S2-2 uses high concentration HF to remove the back winding; uses HF / H2O2 and NH3 / H2O2 cleaning solutions to clean the silicon wafer;

[0056] S2-3 A layer of AlO is deposited on the surface of boron-doped 12 by ALD atomic deposition. x A passivation film layer 15 having a thickness of 3-6 nm;

[0057] S2-4 SiN is deposited on both sides by PECVD x The anti-reflection film layer 16 has a thickness of 5nm-10nm;

[0058] S2-5: Printing AgAl paste on the back side of the silicon wafer and forming a back side metal electrode 17 after sintering.

[0059] As a preferred embodiment, the method for preparing the carrier recombination layer 2 in S3 is the same as the method for preparing the transparent conductive layer 6 in S7: using a PVD magnetron sputtering device, at a pressure of ≤1Pa and an atmosphere with an argon-oxygen ratio of 1:0.02-0.1, and a power density of 1-3W / cm 2 .

[0060] As a preferred embodiment, the method for preparing the hole transport layer 3 in S4 is: preparing a dense TiO2 layer at a high temperature of 400-550°C by spray pyrolysis.

[0061] As a preferred embodiment, the S5 method for preparing a perovskite layer includes: dissolving PbI2 and MAI (methylammonium iodide) in a mixed solvent consisting of DMF (N,N-dimethylformamide) and DMSO (dimethyl sulfoxide) (volume ratio 4:1), and stirring the reaction at 40-80°C for 50-70 minutes to form a perovskite precursor. CNT-PAA (carbon nanotube-polyacrylic acid) is added to the perovskite precursor and stirred at 40-80°C overnight. The solution is dripped onto an ITO (indium tin oxide) substrate coated with TiO2 at a speed of 2000-6000rpm / min for 20-60S. After spin coating for 5-15S, chlorobenzene is quickly dripped onto the sample surface, and then annealed at 50°C-90°C for 5-15min.

[0062] As a preferred embodiment, the S6 method for preparing the electron transport layer 5 is as follows: the SnO2 precursor solution is spin-coated on the perovskite layer at a speed of 2000-6000 rpm for 20-40 seconds, the annealing temperature is 130-170°C, and the annealing time is 20-40 minutes. The SnO2 precursor solution is prepared from a 15% SnO2 aqueous solution: deionized water (V\V) = 1:3.

[0063] As a preferred embodiment, the method for preparing the front anti-reflection film 7 in S7 is to deposit SiN on the front surface by PECVD. x The anti-reflection film layer 7 has a thickness of 5nm-10nm.

[0064] As a preferred implementation, AgAl paste is printed on the front side of the silicon wafer and sintered to form the front metal electrode 8 .

[0065] like Figure 2 As shown, this embodiment also provides a perovskite / silicon stacked solar cell, including a silicon bottom cell 1 with a double-sided asymmetric velvet surface, and the front side of the silicon bottom cell is sequentially provided with a carrier recombination layer 2, a hole transport layer 3, a perovskite layer 4, an electron transport layer 5, a transparent conductive layer 6, a front anti-reflection layer 7, and a front metal electrode 8 from the inside to the outside; Figure 3 As shown, the bottom cell 1 includes a silicon wafer 11, and a tunneling oxide layer 13 and a phosphorus-doped layer 14 are sequentially arranged on the front side of the silicon wafer 11 from the inside to the outside, and a boron-doped layer 12, a passivation film layer 15, a back anti-reflection layer 16, and a back metal electrode 17 are sequentially arranged on the back side of the silicon wafer 11 from the inside to the outside.

[0066] like Figure 4 As shown, the front velvet surface of the double-sided asymmetric velvet silicon bottom cell is a smooth and uniform velvet surface structure in the shape of gullies, such as Figure 5 As shown, the back velvet of the silicon bottom cell with double-sided asymmetric velvet is a pyramid velvet structure of uneven size. The present invention prepares a smooth and uniform velvet structure in the shape of a gully on the front of the silicon wafer 11, which is conducive to the uniform and conformal coverage of the perovskite layer on the crystalline silicon surface in the stacked cell. Secondly, the gully shape can reduce the reflectivity of the front of the crystalline silicon bottom cell, increase the carrier concentration, and increase the open circuit voltage and short circuit current. The gully shape is only formed on one side, and only part of the texture is ablated. The silicon wafer thickness loss is small and the lattice damage is small, the damage to the silicon substrate is smaller, and the impact on carrier generation is small; by preparing a pyramid velvet structure of uneven size on the back of the silicon wafer 11, the PN node area can be increased, the number of photon absorption can be increased, and the current can be increased.

[0067] As a preferred embodiment, the average height of the back suede surface is 0.9-1.2µm, the average distance between the grooves in the front suede surface is 30-150µm, and the average depth of the grooves in the front suede surface is 0.5-0.9µm.

[0068] As a preferred implementation, the carrier recombination layer 2 and the transparent conductive layer 6 are both made of ITO, and their thicknesses are both 80-100 nm; the hole transport layer 3 is made of TiO2, and its thickness is 30-100 nm.

[0069] As a preferred embodiment, the band gap width of the perovskite layer 4 is 1.3-1.8 eV, and the material structure of the perovskite layer 4 is ABX3, wherein A is any one of methylamine, formamidine, Cs or a mixture of three cations, B is Pb or Sn, and X is any one of Cl, Br, I or a mixture of three anions, and its thickness is 800-1200 nm.

[0070] As a preferred embodiment, the material of the electron transport layer 5 is SnO2, and its thickness is 15-40nm.

[0071] As a preferred embodiment, the front anti-reflection layer 7 is a composite film composed of one or more of silicon nitride, silicon oxynitride and silicon oxide, and has a thickness of 5-10 nm.

[0072] As a preferred implementation, the front metal electrode 8 is an AgAl gate line electrode.

[0073] The following is a further description of a method for preparing a perovskite / silicon tandem solar cell and a perovskite / silicon tandem solar cell of the present invention through specific embodiments and comparative examples.

[0074] Example 1

[0075] This embodiment provides a perovskite / silicon tandem solar cell, including a silicon bottom cell with a double-sided asymmetric velvet surface, wherein a carrier recombination layer, a hole transport layer, a perovskite layer, an electron transport layer, a transparent conductive layer, a front anti-reflection layer, and a front metal electrode are sequentially arranged on the front side of the silicon bottom cell from the inside to the outside;

[0076] The front velvet surface of the double-sided asymmetric velvet silicon bottom battery is a smooth and uniform velvet structure in the shape of gullies, and the back velvet surface of the double-sided asymmetric velvet silicon bottom battery is a pyramid velvet structure with uneven sizes.

[0077] The average height of the back suede surface is 1.1µm, the average distance between the grooves in the front suede surface is 100µm, and the average depth of the grooves in the front suede surface is 0.7µm.

[0078] The method for preparing the perovskite / silicon tandem solar cell in this embodiment comprises the following steps:

[0079] S1 selects an N-type single crystal silicon wafer with a resistivity of 4Ω cm and a thickness of 150μm. It is etched with a 1.3% NaOH solution for 500S to form an uneven pyramid structure on both sides of the silicon wafer, and the average height of the velvet surface on the back is 1.1μm. BCl3 is used as the doping source, the doping temperature is 900℃, and the doping square resistance is controlled at 250Ω / □ to form a boron doped layer with a thickness of 0.7μm and a doping concentration of 3E18cm-3 ; Use 13wt% HF to remove the front winding, and then use 6wt% NaOH solution to polish the front; use laser ablation to produce the polished surface, producing grooves with an average spacing of 100µm and an average depth of 0.7µm, and the laser parameters are set as follows: output power 40W, pulse repetition frequency 14kHz, laser spot diameter 10Pm and laser beam speed 45mm / s; use 1.3wt% NaOH solution and NH3 / H2O2 to clean the silicon substrate after laser treatment, and the cleaning time is 200S; under a protective atmosphere, the lattice damage of the silicon wafer is repaired by annealing at 900℃, and the annealing repair time is 30min.

[0080] S2 uses LPCVD technology to deposit a tunnel oxide layer with a thickness of 2nm; then deposits intrinsic polysilicon with a thickness of 100nm; uses POCl3 as a doping source, the doping temperature is 850℃, and the doping concentration is 3E20cm -3 , doping thickness 15nm; use 13wt% HF to remove the back winding; use HF / H2O2 and NH3 / H2O2 to clean the silicon wafer; use ALD atomic deposition to deposit a layer of AlO on the boron doped surface x layer with a thickness of 5 nm; SiN is deposited on the front and back surfaces by PECVD x The thickness of the film layer is 7nm; AgAl paste is printed on the back of the silicon wafer and formed into a back metal electrode after sintering.

[0081] S3 uses 13wt% HF to remove the anti-reflection film on the front of the bottom cell, and uses PVD magnetron sputtering equipment. Under a pressure of ≤1Pa and an argon-oxygen ratio of 1:0.06, the power density is 2W / cm 2 , prepare an ITO layer with a thickness of 90nm.

[0082] S4 prepared a TiO2 layer with a thickness of 70nm by spray pyrolysis at a high temperature of 480℃.

[0083] S5 PbI2 and MAI were dissolved in a mixed solvent consisting of DMF and DMSO (volume ratio 4:1) and stirred at 60°C for 60 minutes to form a perovskite precursor. CNT-PAA was added to the perovskite precursor and stirred at 60°C overnight. The solution was dripped onto an ITO substrate coated with TiO2 at a speed of 4000rpm / min for 40S. After spin coating for 10S, chlorobenzene was quickly dripped onto the sample surface, and then annealed at 70°C for 10 minutes to obtain a perovskite layer with a band gap of 1.6eV and a thickness of 1000nm.

[0084] S6 Spin-coat a 15% SnO2 aqueous solution: deionized water (V\V) = 1:3 precursor solution on the clean perovskite layer at a rotation speed of 4000 rpm for 30 seconds, with an annealing temperature of 150° C. and an annealing time of 30 minutes to obtain a SnO2 layer with a thickness of 30 nm.

[0085] S7 uses PVD magnetron sputtering equipment, with a power density of 2W / cm2 at a pressure of ≤1Pa and an argon-oxygen ratio of 1:0.06. 2 , prepare an ITO layer with a thickness of 90nm.

[0086] S8 Deposit 7nm thick SiN on the front side using PECVD x Film layer, AgAl paste is printed on the front side of the silicon wafer, and the front metal electrode is formed after sintering.

[0087] Example 2

[0088] This embodiment provides a perovskite / silicon tandem solar cell, including a silicon bottom cell with a double-sided asymmetric velvet surface, wherein a carrier recombination layer, a hole transport layer, a perovskite layer, an electron transport layer, a transparent conductive layer, a front anti-reflection layer, and a front metal electrode are sequentially arranged on the front side of the silicon bottom cell from the inside to the outside;

[0089] The front velvet surface of the double-sided asymmetric velvet silicon bottom battery is a smooth and uniform velvet structure in the shape of gullies, and the back velvet surface of the double-sided asymmetric velvet silicon bottom battery is a pyramid velvet structure with uneven sizes.

[0090] The average height of the back suede surface is 0.9µm, the average distance between the grooves in the front suede surface is 30µm, and the average depth of the grooves in the front suede surface is 0.5µm.

[0091] The method for preparing the perovskite / silicon tandem solar cell in this embodiment comprises the following steps:

[0092] S1 selects an N-type single crystal silicon wafer with a resistivity of 1Ω cm and a thickness of 100μm. It is etched with a 0.5% NaOH solution for 600S to form a pyramid structure of uneven size on both sides of the silicon wafer, and the average height of the velvet surface on the back is 0.9μm. BCl3 is used as the doping source, the doping temperature is 800℃, and the doping square resistance is controlled at 200Ω / □ to form a boron doped layer with a thickness of 0.5μm and a doping concentration of 1E18cm -3; Use 5wt% HF to remove the front winding, and then use 3wt% NaOH solution to polish the front; use laser ablation to produce the polished surface, and produce grooves with an average spacing of 30µm and an average depth of 0.5µm, where the laser parameters are set as follows: output power 10W, pulse repetition frequency 5kHz, laser spot diameter 5Pm and laser beam speed 30mm / s; use 0.5wt% NaOH solution and NH3 / H2O2 to clean the silicon substrate after laser treatment, and the cleaning time is 300S; under a protective atmosphere, the lattice damage of the silicon wafer is repaired by annealing at 800℃, and the annealing repair time is 40min.

[0093] S2 uses LPCVD technology to deposit a tunnel oxide layer with a thickness of 1nm; then deposits an intrinsic polysilicon layer with a thickness of 50nm; uses POCl3 as a doping source, the doping temperature is 800℃, and the doping concentration is 1E20cm -3 , doping thickness 10nm; use 5wt% HF to remove the back winding; use HF / H2O2 and NH3 / H2O2 to clean the silicon wafer; use ALD atomic deposition method to deposit a layer of AlO on the boron doped surface x layer with a thickness of 3nm; SiN is deposited on the front and back surfaces by PECVD x The thickness of the film layer is 5nm; AgAl paste is printed on the back of the silicon wafer and formed into a back metal electrode after sintering.

[0094] S3 uses 5wt% HF to remove the anti-reflection film on the front of the bottom cell, and uses PVD magnetron sputtering equipment. Under a pressure of ≤1Pa and an argon-oxygen ratio of 1:0.02, the power density is 1W / cm 2 , prepare an ITO layer with a thickness of 80 nm.

[0095] S4 prepared a TiO2 layer with a thickness of 30nm at a high temperature of 400℃ by spray pyrolysis.

[0096] S5 PbI2 and MAI were dissolved in a mixed solvent consisting of DMF and DMSO (volume ratio 4:1) and stirred at 40°C for 50 minutes to form a perovskite precursor. CNT-PAA was added to the perovskite precursor and stirred at 40°C overnight. The solution was dripped onto an ITO substrate coated with TiO2 at a speed of 2000rpm / min for 20S. After spin coating for 5S, chlorobenzene was quickly dripped onto the sample surface, and then annealed at 50°C for 15 minutes to obtain a perovskite layer with a band gap of 1.3eV and a thickness of 800nm.

[0097] S6 Spin coat a 15% SnO2 aqueous solution: deionized water (V\V) = 1:3 precursor solution on the clean perovskite layer at a rotation speed of 2000 rpm for 20 seconds, with an annealing temperature of 130° C. and an annealing time of 40 minutes to obtain a SnO2 layer with a thickness of 15 nm.

[0098] S7 uses PVD magnetron sputtering equipment, with a power density of 1W / cm2 at a pressure of ≤1Pa and an argon-oxygen ratio of 1:0.02. 2 , prepare an ITO layer with a thickness of 80 nm.

[0099] S8 Deposit 5nm thick SiN on the front side using PECVD x Film layer, AgAl paste is printed on the front side of the silicon wafer, and the front metal electrode is formed after sintering.

[0100] Example 3

[0101] This embodiment provides a perovskite / silicon tandem solar cell, including a silicon bottom cell with a double-sided asymmetric velvet surface, wherein a carrier recombination layer, a hole transport layer, a perovskite layer, an electron transport layer, a transparent conductive layer, a front anti-reflection layer, and a front metal electrode are sequentially arranged on the front side of the silicon bottom cell from the inside to the outside;

[0102] The front velvet surface of the double-sided asymmetric velvet silicon bottom battery is a smooth and uniform velvet structure in the shape of gullies, and the back velvet surface of the double-sided asymmetric velvet silicon bottom battery is a pyramid velvet structure with uneven sizes.

[0103] The average height of the back suede surface is 1.2µm, the average distance between the grooves in the front suede surface is 150µm, and the average depth of the grooves in the front suede surface is 0.9µm.

[0104] The method for preparing the perovskite / silicon tandem solar cell in this embodiment comprises the following steps:

[0105] S1 selected an N-type single crystal silicon wafer with a resistivity of 7Ω cm and a thickness of 200μm. It was etched with a 2% NaOH solution for 400S to form an uneven pyramid structure on both sides of the silicon wafer, and the average height of the velvet surface on the back was 1.2μm. BCl3 was used as the doping source, the doping temperature was 1000℃, and the doping square resistance was controlled at 300Ω / □ to form a boron doped layer with a thickness of 0.9μm and a doping concentration of 5E18cm -3; Use 20wt% HF to remove the front winding, and then use 8wt% NaOH solution to polish the front; use laser ablation to produce the polished surface, producing grooves with an average spacing of 150µm and an average depth of 0.9µm, where the laser parameters are set as follows: output power 70W, pulse repetition frequency 20kHz, laser spot diameter 15Pm and laser beam speed 60mm / s; use 2wt% NaOH solution and NH3 / H2O2 to clean the silicon substrate after laser treatment, and the cleaning time is 100S; under a protective atmosphere, the lattice damage of the silicon wafer is repaired by annealing at 1000℃, and the annealing repair time is 20min.

[0106] S2 uses LPCVD technology to deposit a tunnel oxide layer with a thickness of 3nm; then deposits an intrinsic polysilicon layer with a thickness of 150nm; uses POCl3 as a doping source, the doping temperature is 900℃, and the doping concentration is 5E20cm -3 , doping thickness 20nm; use 20wt% HF to remove the back winding; use HF / H2O2 and NH3 / H2O2 to clean the silicon wafer; use ALD atomic deposition method to deposit a layer of AlO on the boron doped surface x The thickness of the layer is 6nm; SiN is deposited on the front and back surfaces by PECVD. x The thickness of the film layer is 10nm; AgAl paste is printed on the back of the silicon wafer and formed into a back metal electrode after sintering.

[0107] S3 uses 20wt% HF to remove the anti-reflection film on the front of the bottom cell, and uses PVD magnetron sputtering equipment. Under a pressure of ≤1Pa and an argon-oxygen ratio of 1:0.1, the power density is 3W / cm 2 , prepare an ITO layer with a thickness of 100 nm.

[0108] S4 prepared a TiO2 layer with a thickness of 70nm by spray pyrolysis at a high temperature of 550℃.

[0109] S5 PbI2 and MAI were dissolved in a mixed solvent consisting of DMF and DMSO (volume ratio 4:1), and stirred at 80°C for 70 minutes to form a perovskite precursor. CNT-PAA was added to the perovskite precursor and stirred at 80°C overnight; the solution was dripped onto an ITO substrate coated with TiO2 at a speed of 6000rpm / min for 60S, and after spin coating for 15S, chlorobenzene was quickly dripped onto the sample surface, and then annealed at 90°C for 5 minutes to obtain a perovskite layer with a band gap of 1.8eV and a thickness of 1200nm.

[0110] S6: Spin-coat a 15% SnO2 aqueous solution: deionized water (V\V) = 1:3 precursor solution on the clean perovskite layer at a speed of 6000 rpm for 40 seconds, with an annealing temperature of 170°C and an annealing time of 20 minutes to obtain a SnO2 layer with a thickness of 40 nm.

[0111] S7 uses PVD magnetron sputtering equipment, with a power density of 3W / cm2 at a pressure of ≤1Pa and an argon-oxygen ratio of 1:0.1. 2 , prepare an ITO layer with a thickness of 100 nm.

[0112] S8 uses PECVD to deposit SiN with a thickness of 10nm on the front side. x Film layer, AgAl paste is printed on the front side of the silicon wafer, and the front metal electrode is formed after sintering.

[0113] Example 4

[0114] Compared with Example 1, the difference is that the average height of the suede on the back side formed in S1 is 1.3μm. Specifically, a NaOH solution with a concentration of 1.3% is used for etching, and the etching time is 590S to form a pyramid structure of uneven size on both sides of the silicon wafer. The average height of the suede on the back side formed is 1.3μm, and the rest are the same.

[0115] Example 5

[0116] Compared with Example 1, the difference is that in S1, a laser is used to perform laser ablation and texturing on the polished surface to produce grooves with an average spacing of 25 μm, and the rest are the same.

[0117] Example 6

[0118] Compared with Example 1, the difference is that in S1, a laser is used to perform laser ablation and texturing on the polished surface to produce grooves with an average spacing of 155 μm, and the rest are the same.

[0119] Example 7

[0120] Compared with Example 1, the difference is that in S1, a laser is used to perform laser ablation and texturing on the polished surface to produce grooves with an average spacing of 100µm and an average depth of 0.4µm, wherein the parameters of the laser are set as follows: output power 8W, pulse repetition frequency 4kHz, laser spot diameter 4Pm and laser beam speed 29mm / s; the rest are the same.

[0121] Example 8

[0122] Compared with Example 1, the difference is that in S1, a laser is used to perform laser ablation and texturing on the polished surface to produce grooves with an average spacing of 100µm and an average depth of 1.0µm, wherein the parameters of the laser are set as follows: output power 72W, pulse repetition frequency 21kHz, laser spot diameter 16Pm and laser beam speed 61mm / s, and the rest are the same.

[0123] Comparative Example 1

[0124] Compared with Example 1, the difference is that S1 does not involve laser texturing, cleaning and annealing repair steps, but only uses alkali texturing steps.

[0125] Specifically, an N-type single crystal silicon wafer with a resistivity of 4Ω cm and a thickness of 150μm was selected, and a NaOH solution with a concentration of 1.3% was used for etching for 500S to form a pyramid structure of uneven size on the back of the silicon wafer, and the average height of the velvet surface on the back was 1.1μm; BCl3 was used as a doping source to dope on the back, the doping temperature was 900℃, the doping square resistance was controlled at 250Ω / □, and a boron doped layer was formed with a thickness of 0.7μm and a doping concentration of 3E18cm -3 ; Use 13wt% HF to remove the front curvature, and then use 6wt% NaOH solution to polish the front, and the rest are the same.

[0126] Comparative Example 2

[0127] Compared with Example 1, the difference is that S1 does not involve the alkaline double-sided texturing step.

[0128] Specifically, an N-type single crystal silicon wafer with a resistivity of 4Ω cm and a thickness of 150μm was selected, and BCl3 was used as a doping source to dope on the back side. The doping temperature was 900°C, and the doping square resistance was controlled at 250Ω / □ to form a boron doped layer with a thickness of 0.7μm and a doping concentration of 3E18cm -3 ; The front side was ablated by laser to produce grooves with an average spacing of 100µm and an average depth of 0.7µm. The parameters of the laser were set as follows: output power 40W, pulse repetition frequency 14kHz, laser spot diameter 10Pm and laser beam speed 45mm / s; the silicon substrate after laser treatment was cleaned with 1.3wt% NaOH solution and NH3 / H2O2 for 200S; under a protective atmosphere, the silicon wafer was annealed at 900℃ to repair lattice damage for 30min, and the rest were the same.

[0129] Comparative Example 3

[0130] Compared with Example 1, the difference is that in S1, laser ablation is first performed for texturing, and then alkali texturing is performed.

[0131] Specifically, an N-type single crystal silicon wafer with a resistivity of 4Ω cm and a thickness of 150μm was taken, and a laser was used to perform laser ablation and texturing on the front side to produce grooves with an average spacing of 100μm and an average depth of 0.7μm, wherein the parameters of the laser were set as follows: output power 40W, pulse repetition frequency 14kHz, laser spot diameter 10Pm and laser beam speed 45mm / s; the silicon substrate after laser treatment was cleaned using a 1.3wt% NaOH solution and NH3 / H2O2 for 200S; the lattice damage of the silicon wafer was repaired by annealing at 900℃ for 30min, and the annealing repair atmosphere was a protective atmosphere; a 1.3% NaOH solution was used for etching for 500S to form pyramid structures of uneven sizes on both sides of the silicon wafer, and the average height of the texturing on the back side was 1.1μm, and the rest were the same.

[0132] Comparative Example 4

[0133] Compared with Example 1, the difference is that in S1, only the front side is alkali-textured and then the front side is laser-ablated.

[0134] Specifically, an N-type single crystal silicon wafer with a resistivity of 4Ω cm and a thickness of 150μm was selected, and a NaOH solution with a concentration of 1.3% was used for etching for 500S to form a pyramid structure of uneven size on the front side of the silicon wafer, and the average height of the velvet surface on the front side was 1.1μm; BCl3 was used as a doping source for back doping, the doping temperature was 900℃, and the doping square resistance was controlled at 250Ω / □ to form a boron doped layer with a thickness of 0.7μm and a doping concentration of 3E18cm -3 ; Use 13wt% HF to remove the front winding, and then use 6wt% NaOH solution to polish the front; use laser ablation to produce the polished surface, producing grooves with an average spacing of 100µm and an average depth of 0.7µm, wherein the laser parameters are set as follows: output power 40W, pulse repetition frequency 14kHz, laser spot diameter 10Pm and laser beam speed 45mm / s; use 1.3wt% NaOH solution and NH3 / H2O2 to clean the silicon substrate after laser treatment, and the cleaning time is 200S; repair the lattice damage of the silicon wafer by annealing at 900℃, and the annealing repair time is 30min. The atmosphere of the annealing repair is a protective atmosphere, and the rest are the same.

[0135] Comparative Example 5

[0136] Compared with Example 1, the difference is that in S1, the front surface is not de-wound and then polished, and the rest is the same.

[0137] The batteries in Examples 1-8 and Comparative Examples 1-5 were tested under the same conditions, and the test results are shown in Table 1.

[0138] Table 1 Test results of battery of embodiment and comparative example

[0139] Grouping Conversion efficiency Eta(%) Open circuit voltage Voc(mV) Short circuit current Jsc(mA / cm2) Filling factor FF(%) Is there leakage? Example 1 28.87 1.736 25.58 76.8 no Example 2 29.51 1.753 25.86 76.91 no Example 3 27.02 1.739 24.69 75.91 no Example 4 25.38 1.718 23.16 75.36 no Example 5 26.55 1.733 24.95 72.56 no Example 6 24.79 1.726 23.14 73.33 no Example 7 25.46 1.724 23.06 75.67 no Example 8 24.60 1.679 23.19 74.69 no Comparative Example 1 24.14 1.685 22.97 73.69 no Comparative Example 2 24.57 1.72 22.9 73.69 no Comparative Example 3 20.86 1.603 21.32 72.11 yes Comparative Example 4 22.06 1.726 20.69 72.99 no Comparative Example 5 21.26 1.613 22.13 70.36 yes

[0140] As can be seen from Table 1, from the comparison of the test experimental data of Examples 1-8 and Comparative Examples 1-5, it can be seen that by preparing a double-sided asymmetric velvet, the short-circuit current, open-circuit voltage, and fill factor can be further improved, thereby improving the battery conversion efficiency and avoiding battery leakage; preferably, as shown in the test experimental data of Example 1 and Examples 4-8, when the average height of the back velvet is 0.9-1.2µm, the average distance between the grooves in the front velvet is 30-150µm, and the average depth of the grooves in the front velvet is 0.5-0.9µm, the battery cell has better photoelectric conversion performance, better stability and less lattice damage; from the comparison of the test experimental data of Example 1 and Comparative Examples 3 and 5, it can be seen that in the preparation process of the double-sided asymmetric velvet, the battery leakage phenomenon is avoided by removing the front winding and then polishing.

[0141] The present invention is further described above with the aid of specific embodiments. However, it should be understood that the specific description here should not be construed as limiting the essence and scope of the present invention. Various modifications made to the above embodiments by ordinary technicians in the field after reading this specification are all within the scope of protection of the present invention.

Claims

1. A method for preparing a perovskite / silicon tandem solar cell, characterized in that: The steps include: S1 prepares a double-sided asymmetric velvet silicon wafer; S2 uses the prepared double-sided asymmetric velvet silicon wafer as a substrate to prepare a bottom cell; S3 uses acid to remove the anti-reflection film layer on the front side of the bottom battery, and then prepares a carrier recombination layer on the front side of the bottom battery; S4: preparing a hole transport layer on the carrier recombination layer; S5 preparing a perovskite layer on the hole transport layer; S6 preparing an electron transport layer on the perovskite layer; S7: preparing a transparent conductive layer on the electron transport layer; S8: preparing a front anti-reflection layer and a front metal electrode on the transparent conductive layer; The steps in S1 include: firstly alkali double-sided texturing, back-side boron doping, front-side winding removal and polishing, front-side laser ablation texturing, and finally cleaning and annealing repair; The alkaline double-sided texturing adopts alkaline solution etching to make texturing, the mass fraction of the alkaline solution is 0.5-2wt%, and the etching time is 400S-600S; The back side boron doping uses BCl3 as a doping source for doping. The doping temperature of the boron doping is 800-1000°C, the doping square resistance is 200-300Ω / □, the doping thickness is 0.5-0.9μm, and the doping concentration is 1-5E18cm -3 ; The front side deflection is removed and then polished, the front side deflection is removed by using an acid solution, and then the front side is polished by using an alkali solution, the mass fraction of the acid solution is 5-20wt%, and the mass fraction of the alkali solution is 3-8wt%; The front laser ablation texturing uses a laser to perform laser ablation texturing on the polished surface produced on the front side, and the setting parameters of the laser are: output power 10-70W, pulse repetition frequency 5-20kHz, laser spot diameter 5-15Pm and laser beam speed 30-60mm / s; The cleaning and annealing repair uses alkaline solution and NH3 / H2O2 cleaning solution for cleaning, and annealing is used to repair silicon wafer damage under a protective atmosphere. The cleaning time is 100-300S, the annealing repair temperature is 800℃-1000℃, and the annealing repair time is 20min-40min.

2. The method for preparing a perovskite / silicon tandem solar cell according to claim 1, characterized in that: The average height of the back velvet surface obtained by double-sided alkali velveting in S1 is 0.9-1.2µm, and the grooved velvet surface is obtained by laser ablation on the front side in S1, the average distance between the grooves is 30-150µm, and the average depth of the grooves is 0.5-0.9µm.

3. The method for preparing a perovskite / silicon tandem solar cell according to claim 1, characterized in that: The method for preparing the carrier recombination layer in S3 is the same as the method for preparing the transparent conductive layer in S7: using PVD magnetron sputtering equipment, under a pressure of ≤1Pa and an atmosphere with an argon-oxygen ratio of 1:0.02-0.1, the power density is 1-3W / cm 2 ; The S4 method for preparing a hole transport layer: preparing a dense TiO2 layer at a high temperature of 400-550°C by spray pyrolysis; The method for preparing the perovskite layer in S5 is the same as the method for preparing the electron transport layer in S6: it is formed by a coating method followed by annealing.

4. A perovskite / silicon tandem solar cell prepared by the preparation method according to any one of claims 1 to 3, characterized in that: It comprises a silicon bottom cell with a double-sided asymmetric velvet surface, wherein the front side of the silicon bottom cell is provided with a carrier recombination layer, a hole transport layer, a perovskite layer, an electron transport layer, a transparent conductive layer, a front anti-reflection layer, and a front metal electrode in sequence from the inside to the outside; The front velvet surface of the double-sided asymmetric velvet silicon bottom battery is a smooth and uniform velvet structure in the shape of gullies, and the back velvet surface of the double-sided asymmetric velvet silicon bottom battery is a pyramid velvet structure with uneven sizes.

5. A perovskite / silicon tandem solar cell according to claim 4, characterized in that: The average height of the back suede surface is 0.9-1.2µm, the average distance between the grooves in the front suede surface is 30-150µm, and the average depth of the grooves in the front suede surface is 0.5-0.9µm.

6. A perovskite / silicon tandem solar cell according to claim 4, characterized in that: The materials of the carrier recombination layer and the transparent conductive layer are both ITO, and the thickness is 80-100nm; the material of the hole transport layer is TiO2, and the thickness is 30-100nm.

7. The perovskite / silicon tandem solar cell according to claim 4, characterized in that: The band gap width of the perovskite layer is 1.3-1.8 eV, and the perovskite material structure is ABX3, wherein A is any one of methylamine, formamidine, Cs or a mixture of several cations, B is Pb or Sn, and X is any one of Cl, Br, I or a mixture of three anions, and its thickness is 800-1200 nm.

8. The perovskite / silicon tandem solar cell according to claim 4, characterized in that: The electron transport layer material is SnO2, and its thickness is 15-40nm.

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