Chip simulation method, device, test terminal and medium based on software and hardware

Abstract

The embodiment of the present application provides a chip simulation method, device, test terminal and medium based on software and hardware. The method includes obtaining a simulation operation through preset simulation software; determining first transaction-level behavior information corresponding to the simulation operation according to the simulation operation; and interacting with a preset hardware simulation platform according to the first transaction-level behavior information, so that the preset hardware simulation platform converts the first transaction-level behavior information to obtain an execution instruction corresponding to the chip to be tested, and simulates the chip to be tested according to the execution instruction. In the embodiment of the present application, by using a combination of hardware and software, the kernel in the chip to be tested is implemented on the preset hardware simulation platform in a physical environment that is closer to the real thing. Compared with chip simulation from the software side, the actual function of the chip to be tested can be simulated more accurately.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a chip simulation method, device, test terminal and medium based on software and hardware. Background Art

[0002] As the scale of digital chips is getting larger and larger, the time spent on chip simulation is getting longer and longer. One of the most important factors is the slow simulation speed. Using the fastest server to simulate some large-scale chips completely may even take more than a month. In the prior art, pure software methods are used on terminal devices to simulate various functions of the chip. However, there is still a difference between the clock of this pure software simulation method and the actual time simulation. Therefore, how to improve the simulation speed of the chip and improve the accuracy of the simulation is an urgent problem to be solved. Summary of the invention

[0003] Some embodiments of the present application aim to provide a chip simulation method, device, test terminal and medium based on software and hardware. Through the technical solution of the embodiments of the present application, a preset simulation software is installed on the test terminal, the test terminal is connected to a preset hardware simulation platform, and the preset hardware simulation platform installs a chip to be tested. The method includes: obtaining a simulation operation through the preset simulation software; determining first transaction-level behavior information corresponding to the simulation operation according to the simulation operation; and interacting with the preset hardware simulation platform according to the first transaction-level behavior information, so that the preset hardware simulation platform converts the first transaction-level behavior information to obtain an execution instruction corresponding to the chip to be tested, and simulates the chip to be tested according to the execution instruction. In the embodiments of the present application, by using a combination of hardware and software, the kernel in the chip to be tested is implemented on the preset hardware simulation platform in a physical environment that is closer to the real environment. Compared with chip simulation from the software side, the actual function of the chip to be tested can be simulated more accurately.

[0004] In a first aspect, some embodiments of the present application provide a chip simulation method based on software and hardware, which is applied to a test terminal, wherein a preset simulation software is installed on the test terminal, and the test terminal is connected to a preset hardware simulation platform, and the preset hardware simulation platform is installed with a chip to be tested, including:

[0005] Acquire simulation operation through the preset simulation software;

[0006] According to the simulation operation, determining first transaction-level behavior information corresponding to the simulation operation;

[0007] According to the first transaction-level behavior information, interactive processing is performed with the preset hardware simulation platform so that the preset hardware simulation platform converts the first transaction-level behavior information, obtains execution instructions corresponding to the chip under test, and simulates the chip under test according to the execution instructions.

[0008] Some embodiments of the present application use a combination of hardware and software to implement a core in the chip under test on a preset hardware simulation platform that is closer to the real physical environment. Compared with chip simulation from the software side, it can more accurately simulate the actual functions of the chip under test.

[0009] Optionally, obtaining the simulation operation through the preset simulation software includes:

[0010] Generate simulation operations through pre-established virtual machines.

[0011] The virtual machine QEMU is used to directly communicate with the external test environment through the TLM model. This process does not require the reconstructing of instructions, data and operation behaviors before generating simulation stimuli, thus avoiding the introduction of unnecessary errors in this link during chip hardware and software co-simulation.

[0012] Some embodiments of the present application use the virtual machine QEMU to implement direct docking of software drivers and simulation environments, thereby omitting the offline dump process commonly used in simulation and debugging. This allows the entire simulation system to perform corresponding simulation operations without having to dump instructions, data, and behaviors in a specific format based on the dump content, thereby eliminating intermediate links such as text dumps and avoiding the introduction of additional errors in this link during chip simulation and troubleshooting.

[0013] Optionally, determining, according to the simulation operation, first transaction-level behavior information corresponding to the simulation operation includes:

[0014] A transaction-level modeling method is adopted to generate first transaction-level behavior information corresponding to the simulation operation according to the simulation operation.

[0015] Some embodiments of the present application adopt a transaction level modeling method, namely a TLM model, with which the virtual machine can directly convert the first transaction level behavior information corresponding to the simulation instruction through interaction, so as to simulate and verify each function of the chip under test.

[0016] Optionally, the preset hardware simulation platform converts the first transaction-level behavior information to obtain an execution instruction corresponding to the chip under test, and simulates the chip under test according to the execution instruction, including:

[0017] The preset hardware simulation platform converts the first transaction-level behavior information into a protocol data format corresponding to the chip under test through a preset protocol conversion method, and corresponds the transaction-level operation in the transaction-level modeling method to the preset bus timing information, so that the preset hardware simulation platform simulates the chip under test according to the preset bus timing information.

[0018] In some embodiments of the present application, after receiving the first transaction-level behavior information through a preset hardware simulation platform, a preset protocol conversion method is used to convert the first transaction-level behavior information into a data format recognizable by the preset hardware simulation platform, and the transaction-level operations in the transaction-level modeling method are matched with the preset bus timing information. The preset hardware simulation platform simulates the chip to be tested according to the preset bus timing information. In this way, the combination of hardware and software can be used, and the core in the chip to be tested can be implemented on the preset hardware simulation platform to be closer to the real physical environment, thereby improving the accuracy of the simulation.

[0019] Optionally, the method further comprises:

[0020] After the preset hardware simulation platform completes the simulation of the chip to be tested, the simulation result is stored in the memory register of the preset hardware simulation platform.

[0021] In some embodiments of the present application, after a preset hardware simulation platform completes simulation of a chip to be tested, the simulation results are saved in a memory register of the preset hardware simulation platform, so that the software can obtain the simulation results for judgment.

[0022] Optionally, the method further comprises:

[0023] A simulation result corresponding to the chip to be tested is obtained from the memory register of the preset hardware simulation platform.

[0024] In some embodiments of the present application, the test terminal may obtain the simulation result corresponding to the chip under test from the memory register of the preset hardware simulation platform, so as to determine whether the chip under test passes the simulation.

[0025] Optionally, the method further comprises:

[0026] Acquiring transactional behavior information corresponding to the chip to be tested in a memory register of the preset hardware simulation platform;

[0027] According to the transaction-level behavior information, executing the transaction-level operation corresponding to the transaction-level behavior information to obtain an execution result;

[0028] The execution result is stored in the memory register.

[0029] Some embodiments of the present application can initiate transaction-level operations from the hardware side, and can also perform simulation more conveniently to improve the accuracy of the simulation.

[0030] In a second aspect, some embodiments of the present application provide a chip simulation device based on software and hardware, which is applied to a test terminal, wherein a preset simulation software is installed on the test terminal, and the test terminal is connected to a preset hardware simulation platform, and the preset hardware simulation platform is installed with a chip to be tested, including:

[0031] An acquisition module, used for acquiring simulation operations through the preset simulation software;

[0032] A determination module, configured to determine first transaction-level behavior information corresponding to the simulation operation according to the simulation operation;

[0033] A test module is used to interact with the preset hardware simulation platform according to the first transaction-level behavior information, so that the preset hardware simulation platform converts the first transaction-level behavior information, obtains execution instructions corresponding to the chip to be tested, and simulates the chip to be tested according to the execution instructions.

[0034] Some embodiments of the present application use a combination of hardware and software to implement a core in the chip under test on a preset hardware simulation platform that is closer to the real physical environment. Compared with chip simulation from the software side, it can more accurately simulate the actual functions of the chip under test.

[0035] Optionally, the acquisition module is used to:

[0036] Generate simulation operations through pre-established virtual machines.

[0037] Some embodiments of the present application use the virtual machine QEMU to implement direct docking of software drivers and simulation environments, thereby omitting the offline dump process commonly used in simulation and debugging. This allows the entire simulation system to perform corresponding simulation operations without having to dump instructions, data, and behaviors in a specific format based on the dump content, thereby eliminating intermediate links such as text dumps and avoiding the introduction of additional errors in this link during chip simulation and troubleshooting.

[0038] Optionally, the determining module is used to:

[0039] A transaction-level modeling method is adopted to generate first transaction-level behavior information corresponding to the simulation operation according to the simulation operation.

[0040] Some embodiments of the present application adopt a transaction level modeling method, namely a TLM model, with which the virtual machine can directly convert the first transaction level behavior information corresponding to the simulation instruction through interaction, so as to simulate and verify each function of the chip under test.

[0041] Optionally, the test module is used to:

[0042] The preset hardware simulation platform converts the first transaction-level behavior information into a protocol data format corresponding to the chip under test through a preset protocol conversion method, and corresponds the transaction-level operation in the transaction-level modeling method to the preset bus timing information, so that the preset hardware simulation platform simulates the chip under test according to the preset bus timing information.

[0043] In some embodiments of the present application, after receiving the first transaction-level behavior information through a preset hardware simulation platform, a preset protocol conversion method is used to convert the first transaction-level behavior information into a data format recognizable by the preset hardware simulation platform, and the transaction-level operations in the transaction-level modeling method are matched with the preset bus timing information. The preset hardware simulation platform simulates the chip to be tested according to the preset bus timing information. In this way, the combination of hardware and software can be used, and the core in the chip to be tested can be implemented on the preset hardware simulation platform to be closer to the real physical environment, thereby improving the accuracy of the simulation.

[0044] Optionally, the test module is used to:

[0045] After the preset hardware simulation platform completes the simulation of the chip to be tested, the simulation result is stored in the memory register of the preset hardware simulation platform.

[0046] In some embodiments of the present application, after a preset hardware simulation platform completes simulation of a chip to be tested, the simulation results are saved in a memory register of the preset hardware simulation platform, so that the software can obtain the simulation results for judgment.

[0047] Optionally, the test module is used to:

[0048] A simulation result corresponding to the chip to be tested is obtained from the memory register of the preset hardware simulation platform.

[0049] In some embodiments of the present application, the test terminal may obtain the simulation result corresponding to the chip under test from the memory register of the preset hardware simulation platform, so as to determine whether the chip under test passes the simulation.

[0050] Optionally, the test module is used to:

[0051] Acquiring transactional behavior information corresponding to the chip to be tested in a memory register of the preset hardware simulation platform;

[0052] According to the transaction-level behavior information, executing the transaction-level operation corresponding to the transaction-level behavior information to obtain an execution result;

[0053] The execution result is stored in the memory register.

[0054] Some embodiments of the present application can initiate transaction-level operations from the hardware side, and can also perform simulation more conveniently to improve the accuracy of the simulation.

[0055] In a third aspect, some embodiments of the present application provide a test terminal comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the software- and hardware-based chip simulation method as described in any embodiment of the first aspect can be implemented.

[0056] In a fourth aspect, some embodiments of the present application provide a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, can implement the software- and hardware-based chip simulation method as described in any embodiment of the first aspect.

[0057] In a fifth aspect, some embodiments of the present application provide a computer program product, comprising a computer program, wherein the computer program, when executed by a processor, can implement the software- and hardware-based chip simulation method as described in any embodiment of the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] In order to more clearly illustrate the technical solutions of some embodiments of the present application, the drawings required for use in some embodiments of the present application will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0059] Figure 1 A schematic diagram of a chip simulation method based on software and hardware provided in an embodiment of the present application;

[0060] Figure 2 A schematic diagram of the structure of a chip simulation system based on software and hardware provided in an embodiment of the present application;

[0061] Figure 3 A flow chart of the FPGA-DUT to TLM model provided in the embodiment of the present application;

[0062] Figure 4 A schematic diagram of the process of TLM model to FPGA-DUT provided in the embodiment of the present application;

[0063] Figure 5 A schematic diagram of the structure of a chip simulation device based on software and hardware provided in an embodiment of the present application;

[0064] Figure 6 A schematic diagram of a test terminal provided in an embodiment of the present application. DETAILED DESCRIPTION

[0065] The technical solutions in some embodiments of the present application will be described below in conjunction with the drawings in some embodiments of the present application.

[0066] It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. At the same time, in the description of this application, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0067] As digital chips become larger and larger, chip simulation takes longer and longer, and one of the most important factors is the slow simulation speed. Using the fastest server, a complete simulation of some large-scale chips may even take more than a month. In the prior art, a pure software method is used on the terminal device to simulate the various functions of the chip. However, there is still a difference between the clock of this pure software simulation method and the actual time simulation. In view of this, some embodiments of the present application provide a chip simulation method based on software and hardware, in which a preset simulation software is installed on a test terminal, the test terminal is connected to a preset hardware simulation platform, and the preset hardware simulation platform is installed with a chip to be tested. The method includes: obtaining a simulation operation through the preset simulation software; determining first transaction-level behavior information corresponding to the simulation operation according to the simulation operation; interacting with the preset hardware simulation platform according to the first transaction-level behavior information, so that the preset hardware simulation platform converts the first transaction-level behavior information, obtains an execution instruction corresponding to the chip to be tested, and simulates the chip to be tested according to the execution instruction. In the embodiments of the present application, by using a combination of hardware and software, the kernel in the chip to be tested is implemented on the preset hardware simulation platform to be closer to the real physical environment, and compared with chip simulation from the software side, the actual function of the chip to be tested can be simulated more accurately.

[0068] like Figure 1 As shown, an embodiment of the present application provides a chip simulation method based on software and hardware, which is applied to a test terminal, on which a preset simulation software is installed, and the test terminal is connected to a preset hardware simulation platform, on which a chip to be tested is installed, and the method includes:

[0069] S101, obtaining simulation operation through preset simulation software;

[0070] Specifically, the embodiment of the present application is applied to a chip simulation system based on software and hardware, including a test terminal and a preset hardware simulation platform. The preset simulation software is installed on the test terminal, and the chip to be tested is installed on the preset hardware simulation platform. The FPGA of the chip to be tested is initially empty. After the program is burned into it, the DUT (Design under Test) to be tested is obtained, wherein the preset hardware simulation platform is a hardware board platform based on FPGA (Field Programmable Gate Array).

[0071] According to a certain function of the chip under test to be simulated, that is, the transaction-level behavior, a simulation stimulus is generated in the preset simulation software on the test terminal, and the test terminal obtains the simulation operation, that is, the simulation operation behavior.

[0072] S102, determining first transaction-level behavior information corresponding to the simulation operation according to the simulation operation;

[0073] Specifically, the test terminal generates first transaction-level behavior information corresponding to the simulation operation through a TLM (Transaction-level modeling) model according to the simulation operation.

[0074] S103. Interact with a preset hardware simulation platform according to the first transaction-level behavior information, so that the preset hardware simulation platform converts the first transaction-level behavior information, obtains execution instructions corresponding to the chip to be tested, and simulates the chip to be tested according to the execution instructions.

[0075] Specifically, the test terminal interacts with the preset hardware simulation platform based on the first transaction-level behavior information, that is, performs data interaction. The preset hardware simulation platform converts the network protocol of the first transaction-level behavior information into a data format recognizable by the preset hardware simulation platform, obtains execution instructions corresponding to the chip to be tested, and then simulates and verifies the chip to be tested based on the execution instructions, so that various functions of the chip can be simulated through a combination of software and hardware, thereby improving the simulation speed and accuracy.

[0076] The core in the DUT to be tested in the embodiment of the present application is implemented in a synthesizable way on the hardware side FPGA chip, which is closer to the real physical environment. In addition, in a multi-core architecture DUT, a core is implemented on the software side and the hardware side respectively. Compared with simply initiating transaction-level operations from the software side through the TLM model, this method can more accurately simulate the actual function of the DUT to be tested.

[0077] Some embodiments of the present application use a combination of hardware and software to implement a core in the chip under test on a preset hardware simulation platform that is closer to the real physical environment. Compared with chip simulation from the software side, it can more accurately simulate the actual functions of the chip under test.

[0078] Another embodiment of the present application further supplements the software and hardware based chip simulation method provided in the above embodiment.

[0079] like Figure 2 As shown, in the embodiment of the present application, the on-chip system bus of the DUT to be tested, the kernel and its corresponding interaction module with the software are implemented on the hardware side FPGA, and the peripheral interface devices of the DUT to be tested are implemented on the software side through the TLM functional model and QEMU (kernel-based virtual machine), as shown in FIG. Figure 2 As shown, the software side is the test terminal, on which QEMU and TLM models are installed. The hardware side is the preset hardware simulation platform, on which protocol transceiver and protocol conversion modules, RTL bridge module and DUT to be tested are installed. The test terminal and the object channel to be tested are used for data transmission, as follows:

[0080] Qemu is a hardware simulator, and the TLM model is a transaction-level simulation model built using SystemC. The two are combined to communicate with the DUT running on the hardware-side FPGA. The interaction between Qemu and the TLM model is carried out through a socket-based communication framework. The TLM model communicates with the hardware-side FPGA chip through PCIe.

[0081] The physical interface of the physical channel is a communication system between software and hardware in the PCIe architecture, in which the hardware side FPGA converts the TLP packet (i.e., the first transaction level behavior information) into the data format of the AXI bus protocol through xDMA (DMA Subsystem for PCI Express). The TLP packet format on the software side is the TLP packet format supported by xDMA.

[0082] The RTL bridge module on the hardware side has a SystemC-based TLM model that provides it with a user space TLM interface (axi2tlm-Bridge and tlm2axi-Bridge).

[0083] The role of the protocol processing part on the hardware side is to communicate with the TLM model on the software side. The data exchange format with the software side is the TLP message data on the PCIe physical interface. The protocol transceiver and conversion module is responsible for converting the received protocol format into the protocol format of the on-chip bus of the DUT to be tested through xDMA, and interacting with the RTL bridge module.

[0084] The RTL bridge module is used to synchronize the transaction interactions between the software and hardware sides, and convert the transaction-level operations in the TLM model with specific bus timing information, thereby enabling data exchange between the TLM model and the DUT to be tested connected to it. Its actual role is reflected in the communication function of a mailbox.

[0085] Optionally, the simulation operation is obtained by using preset simulation software, including:

[0086] Generate simulation operations through pre-established virtual machines.

[0087] Specifically, in the embodiment of the present application, a virtual machine is used to generate simulation operations, that is, simulation stimuli, and a virtual machine is used to replace the simulation stimuli constructed after dumping, thereby reducing the text processing and dumping process and avoiding the introduction of new errors in the text processing script.

[0088] Some embodiments of the present application use the virtual machine QEMU to implement direct docking of software drivers and simulation environments, thereby omitting the offline dump process commonly used in simulation and debugging. This allows the entire simulation system to perform corresponding simulation operations without having to dump instructions, data, and behaviors in a specific format based on the dump content, thereby eliminating intermediate links such as text dumps and avoiding the introduction of additional errors in this link during chip simulation and troubleshooting.

[0089] Optionally, determining, according to the simulation operation, first transaction-level behavior information corresponding to the simulation operation includes:

[0090] A transaction-level modeling method is adopted to generate first transaction-level behavior information corresponding to the simulation operation according to the simulation operation.

[0091] Some embodiments of the present application adopt a transaction level modeling method, namely a TLM model, with which the virtual machine can directly convert the first transaction level behavior information corresponding to the simulation instruction through interaction, so as to simulate and verify each function of the chip under test.

[0092] Optionally, the preset hardware simulation platform converts the first transaction level behavior information to obtain an execution instruction corresponding to the chip to be tested, and simulates the chip to be tested according to the execution instruction, including:

[0093] The preset hardware simulation platform converts the first transaction-level behavior information into a protocol data format corresponding to the chip under test through a preset protocol conversion method, and corresponds the transaction-level operation in the transaction-level modeling method to the preset bus timing information, so that the preset hardware simulation platform simulates the chip under test according to the preset bus timing information.

[0094] In some embodiments of the present application, after receiving the first transaction-level behavior information through a preset hardware simulation platform, a preset protocol conversion method is used to convert the first transaction-level behavior information into a data format recognizable by the preset hardware simulation platform, and the transaction-level operations in the transaction-level modeling method are matched with the preset bus timing information. The preset hardware simulation platform simulates the chip to be tested according to the preset bus timing information. In this way, the combination of hardware and software can be used, and the core in the chip to be tested can be implemented on the preset hardware simulation platform to be closer to the real physical environment, thereby improving the accuracy of the simulation.

[0095] Optionally, the method further comprises:

[0096] After the preset hardware simulation platform completes the simulation of the chip to be tested, the simulation result is stored in the memory register of the preset hardware simulation platform.

[0097] In some embodiments of the present application, after a preset hardware simulation platform completes simulation of a chip to be tested, the simulation results are saved in a memory register of the preset hardware simulation platform, so that the software can obtain the simulation results for judgment.

[0098] Optionally, the method further comprises:

[0099] The simulation results corresponding to the chip under test are obtained from the memory register of the preset hardware simulation platform.

[0100] In some embodiments of the present application, the test terminal may obtain the simulation result corresponding to the chip under test from the memory register of the preset hardware simulation platform, so as to determine whether the chip under test passes the simulation.

[0101] Figure 4 A schematic diagram of the process of the TLM model to FPGA-DUT provided in the embodiment of the present application, such as Figure 4 As shown, the hardware side is controlled from the software side, including:

[0102] The software side sends the transaction-level behavior information after TLM model conversion to the hardware side;

[0103] Send transaction-level behavior information to the FPGA simulation board on the hardware side through the SystemC TLM model interface;

[0104] The FPGA simulation board responds to the DUT under test according to the transaction-level behavior information and saves the response results in the memory registers of the RTL bridge module, thereby achieving a specific response of the DUT under test.

[0105] After the hardware-side simulation is completed, the software-side reads the response results of the DUT under test from the memory register of the RTL bridge module.

[0106] The hardware side returns the achieved response result to the TLM model on the software side, thereby completing the response from the software side to the hardware side.

[0107] Optionally, the method further comprises:

[0108] In a memory register of a preset hardware simulation platform, transactional behavior information corresponding to the chip to be tested is obtained;

[0109] According to the transaction-level behavior information, execute the transaction-level operation corresponding to the transaction-level behavior information to obtain the execution result;

[0110] Store the execution results in memory registers.

[0111] Figure 3 The flow diagram of the FPGA-DUT to TLM model provided in the embodiment of the present application includes:

[0112] 1) Waiting for the transaction-level behavior of TLM converted from bus operation initiated by the hardware side;

[0113] Specifically, the hardware side selects the transaction-level behavior information to be simulated according to the requirements, and the FPGA on the hardware side stores the transaction-level behavior information in the memory register of the RTL bridge module according to different transaction-level behavior information;

[0114] 2) Query the information of the memory mapping register (ie, memory register) of the RTL bridge module, that is, the simulation result.

[0115] 3) The hardware side responds to the corresponding transaction-level operation according to the transaction-level behavior information and obtains a response result;

[0116] 4) The hardware side writes the result back to the memory register of the RTL bridge module, and then returns it to the software side through the TLM model interface.

[0117] In the embodiment of the present application, the software-side TLM model is highly scalable and can meet a large number of different needs without the need to purchase additional dedicated hardware, thereby reducing simulation costs. The hardware-side RTL bridge module can be applied to a multi-core architecture and can flexibly increase or decrease the number of cores.

[0118] Some embodiments of the present application can initiate transaction-level operations from the hardware side, and can also perform simulation more conveniently to improve the accuracy of the simulation.

[0119] It should be noted that each implementable method in this embodiment may be implemented separately, or may be implemented in combination in any combination without conflict, and this application is not limited thereto.

[0120] Another embodiment of the present application provides a chip simulation device based on software and hardware, which is used to execute the chip simulation method based on software and hardware provided in the above embodiment.

[0121] like Figure 5 As shown, it is a schematic diagram of the structure of a chip simulation device based on software and hardware provided in an embodiment of the present application, which is applied to a test terminal, on which a preset simulation software is installed, and the test terminal is connected to a preset hardware simulation platform, on which a chip to be tested is installed, and the chip simulation device based on software and hardware includes an acquisition module 501, a determination module 502 and a test module 503, wherein:

[0122] The acquisition module 501 is used to acquire the simulation operation through the preset simulation software;

[0123] The determination module 502 is used to determine the first transaction level behavior information corresponding to the simulation operation according to the simulation operation;

[0124] The test module 503 is used to interact with the preset hardware simulation platform according to the first transaction level behavior information, so that the preset hardware simulation platform converts the first transaction level behavior information, obtains the execution instructions corresponding to the chip to be tested, and simulates the chip to be tested according to the execution instructions.

[0125] Regarding the device in this embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated here.

[0126] Some embodiments of the present application use a combination of hardware and software to implement a core in the chip under test on a preset hardware simulation platform that is closer to the real physical environment. Compared with chip simulation from the software side, it can more accurately simulate the actual functions of the chip under test.

[0127] Another embodiment of the present application further supplements the software and hardware-based chip simulation device provided in the above embodiment.

[0128] Optionally, the acquisition module is used to:

[0129] Generate simulation operations through pre-established virtual machines.

[0130] Some embodiments of the present application use the virtual machine QEMU to implement direct docking of software drivers and simulation environments, thereby omitting the offline dump process commonly used in simulation and debugging. This allows the entire simulation system to perform corresponding simulation operations without having to dump instructions, data, and behaviors in a specific format based on the dump content, thereby eliminating intermediate links such as text dumps and avoiding the introduction of additional errors in this link during chip simulation and troubleshooting.

[0131] Optionally, the determination module is used to:

[0132] A transaction-level modeling method is adopted to generate first transaction-level behavior information corresponding to the simulation operation according to the simulation operation.

[0133] Some embodiments of the present application adopt a transaction level modeling method, namely a TLM model, with which the virtual machine can directly convert the first transaction level behavior information corresponding to the simulation instruction through interaction, so as to simulate and verify each function of the chip under test.

[0134] Optionally, the test module is used to:

[0135] The preset hardware simulation platform converts the first transaction-level behavior information into a protocol data format corresponding to the chip under test through a preset protocol conversion method, and corresponds the transaction-level operation in the transaction-level modeling method to the preset bus timing information, so that the preset hardware simulation platform simulates the chip under test according to the preset bus timing information.

[0136] In some embodiments of the present application, after receiving the first transaction-level behavior information through a preset hardware simulation platform, a preset protocol conversion method is used to convert the first transaction-level behavior information into a data format recognizable by the preset hardware simulation platform, and the transaction-level operations in the transaction-level modeling method are matched with the preset bus timing information. The preset hardware simulation platform simulates the chip to be tested according to the preset bus timing information. In this way, the combination of hardware and software can be used, and the core in the chip to be tested can be implemented on the preset hardware simulation platform to be closer to the real physical environment, thereby improving the accuracy of the simulation.

[0137] Optionally, the test module is used to:

[0138] After the preset hardware simulation platform completes the simulation of the chip to be tested, the simulation result is stored in the memory register of the preset hardware simulation platform.

[0139] In some embodiments of the present application, after a preset hardware simulation platform completes simulation of a chip to be tested, the simulation results are saved in a memory register of the preset hardware simulation platform, so that the software can obtain the simulation results for judgment.

[0140] Optionally, the test module is used to:

[0141] The simulation results corresponding to the chip under test are obtained from the memory register of the preset hardware simulation platform.

[0142] In some embodiments of the present application, the test terminal may obtain the simulation result corresponding to the chip under test from the memory register of the preset hardware simulation platform, so as to determine whether the chip under test passes the simulation.

[0143] Optionally, the test module is used to:

[0144] In a memory register of a preset hardware simulation platform, transactional behavior information corresponding to the chip to be tested is obtained;

[0145] According to the transaction-level behavior information, execute the transaction-level operation corresponding to the transaction-level behavior information to obtain the execution result;

[0146] Store the execution results in memory registers.

[0147] Some embodiments of the present application can initiate transaction-level operations from the hardware side, and can also perform simulation more conveniently to improve the accuracy of the simulation.

[0148] Regarding the device in this embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated here.

[0149] It should be noted that each implementable method in this embodiment may be implemented separately, or may be implemented in combination in any combination without conflict, and this application is not limited thereto.

[0150] An embodiment of the present application also provides a computer-readable storage medium on which a computer program is stored. When the program is executed by a processor, the operation of the method corresponding to any embodiment of the software and hardware-based chip simulation method provided in the above embodiments can be implemented.

[0151] An embodiment of the present application also provides a computer program product, which includes a computer program, wherein when the computer program is executed by a processor, it can implement the operations corresponding to any embodiment of the software and hardware-based chip simulation method provided in the above embodiments.

[0152] like Figure 6 As shown, some embodiments of the present application provide a test terminal 600, which includes: a memory 610, a processor 620, and a computer program stored in the memory 610 and executable on the processor 620, wherein the processor 620 can implement a method of any embodiment of the above-mentioned software-hardware-based chip simulation method when reading the program from the memory 610 through a bus 630 and executing the program.

[0153] Processor 620 can process digital signals and can include various computing structures, such as complex instruction set computer structure, reduced instruction set computer structure, or a structure that implements a combination of multiple instruction sets. In some examples, processor 620 can be a microprocessor.

[0154] The memory 610 may be used to store instructions executed by the processor 620 or data related to the execution of instructions. These instructions and / or data may include codes for implementing some or all functions of one or more modules described in the embodiments of the present application. The processor 620 of the disclosed embodiment may be used to execute instructions in the memory 610 to implement the method shown above. The memory 610 includes a dynamic random access memory, a static random access memory, a flash memory, an optical memory, or other memory known to those skilled in the art.

[0155] The above are only embodiments of the present application and are not intended to limit the scope of protection of the present application. For those skilled in the art, the present application may have various changes and variations. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application should be included in the scope of protection of the present application. It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in the subsequent drawings.

[0156] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

[0157] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

Claims

1. A chip simulation method based on software and hardware, characterized in that: Applied to a test terminal, the test terminal is installed with preset simulation software, the test terminal is connected to a preset hardware simulation platform, the preset hardware simulation platform is installed with a chip to be tested, the method comprises: Acquire simulation operation through the preset simulation software; According to the simulation operation, determining first transaction-level behavior information corresponding to the simulation operation; According to the first transaction-level behavior information, interactive processing is performed with the preset hardware simulation platform, so that the preset hardware simulation platform converts the first transaction-level behavior information, obtains an execution instruction corresponding to the chip under test, and simulates the chip under test according to the execution instruction; The obtaining of the simulation operation through the preset simulation software includes: Generate simulation operations through pre-established virtual machines; The determining, according to the simulation operation, first transaction-level behavior information corresponding to the simulation operation includes: A transaction-level modeling method is adopted to generate first transaction-level behavior information corresponding to the simulation operation according to the simulation operation.

2. The chip simulation method based on software and hardware according to claim 1, characterized in that: The preset hardware simulation platform converts the first transaction-level behavior information to obtain an execution instruction corresponding to the chip under test, and simulates the chip under test according to the execution instruction, including: The preset hardware simulation platform converts the first transaction-level behavior information into a protocol data format corresponding to the chip under test through a preset protocol conversion method, and corresponds the transaction-level operation in the transaction-level modeling method to the preset bus timing information, so that the preset hardware simulation platform simulates the chip under test according to the preset bus timing information.

3. The chip simulation method based on software and hardware according to claim 1, characterized in that: The method further comprises: After the preset hardware simulation platform completes the simulation of the chip to be tested, the simulation result is stored in the memory register of the preset hardware simulation platform.

4. The chip simulation method based on software and hardware according to claim 1, characterized in that: The method further comprises: A simulation result corresponding to the chip to be tested is obtained from the memory register of the preset hardware simulation platform.

5. The chip simulation method based on software and hardware according to claim 1, characterized in that: The method further comprises: Acquiring transactional behavior information corresponding to the chip to be tested in a memory register of the preset hardware simulation platform; According to the transaction-level behavior information, executing the transaction-level operation corresponding to the transaction-level behavior information to obtain an execution result; The execution result is stored in the memory register.

6. A chip simulation device based on software and hardware, characterized in that: Applied to a test terminal, the test terminal is installed with preset simulation software, the test terminal is connected to a preset hardware simulation platform, the preset hardware simulation platform is installed with a chip to be tested, the device comprises: An acquisition module, used for acquiring simulation operations through the preset simulation software; A determination module, configured to determine first transaction-level behavior information corresponding to the simulation operation according to the simulation operation; A test module, configured to interact with the preset hardware simulation platform according to the first transaction-level behavior information, so that the preset hardware simulation platform converts the first transaction-level behavior information, obtains an execution instruction corresponding to the chip to be tested, and simulates the chip to be tested according to the execution instruction; The acquisition module is used to: Generate simulation operations through pre-established virtual machines; The determining module is used to: A transaction-level modeling method is adopted to generate first transaction-level behavior information corresponding to the simulation operation according to the simulation operation.

7. A test terminal, characterized in that: It comprises a memory, a processor and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the software-hardware-based chip simulation method described in any one of claims 1 to 5 can be implemented.

8. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein the program, when executed by a processor, can implement the software- and hardware-based chip simulation method described in any one of claims 1 to 5.

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