Electrostatic protection circuit and chip

Abstract

The present application provides an electrostatic protection circuit and chip, relating to the field of chip technology. In the present application, a trigger module generates a trigger signal in response to an electrostatic pulse between the first voltage terminal and the ground terminal; a conversion module outputs a control signal in response to the trigger signal to control the bleeder to discharge electrostatic electricity; the bleeder is connected between the first voltage terminal and the ground terminal and discharges static electricity in response to the control signal; the input end of the feedback module is connected to the control end of the bleeder, and upon receiving the control signal, controls the trigger module to continue outputting the trigger signal, causing the conversion module to continue outputting the control signal, thereby causing the bleeder to continue discharging. In this way, the discharge time of the bleeder can be extended through the feedback module, rather than increasing the discharge time by extending the detection time in the trigger module. This does not increase the detection time and reduces the possibility of non-electrostatic discharge (ESD) events falsely triggering the ESD protection.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and in particular to an electrostatic protection circuit and a chip. Background Art

[0002] The electrostatic discharge (ESD) protection circuit of a discharger requires an ESD trigger detection circuit to detect ESD events and turn on the discharger until the static charge is discharged to a level that will not damage the circuit chip. The rise time of the detection signal of an ESD event is generally much shorter than the discharge time required for static charge discharge. To ensure the discharge time, the RC time constant needs to be large enough to ensure that the discharger remains on during the ESD event. However, because ESD detection and discharge share the same RC time constant, an excessively large time constant means that the ESD detection time is unnecessarily increased, which can easily cause non-ESD events, such as hot plugging, to falsely trigger ESD protection. For example, after an HBM chip circuit triggers an ESD event, the time required for the current signal to quickly rise to its peak is 2-10ns, and the discharge time is 130-170ns. However, if the current signal detected in the circuit rises too fast during non-ESD events (such as in a "hot plug" scenario), for example, 120ns, it may be mistaken by the ESD trigger detection circuit as an ESD event.

[0003] Therefore, the current ESD protection circuit must ensure that the discharge device remains turned on during an ESD event, which will extend the detection time of the ESD trigger detection circuit and easily trigger the ESD protection by mistake. Summary of the Invention

[0004] In view of this, embodiments of the present application provide an electrostatic protection circuit and chip, aiming to enable the ESD protection circuit to keep the discharge device turned on during an ESD event while avoiding accidental triggering of the ESD protection by non-ESD events.

[0005] In a first aspect, an embodiment of the present application provides an electrostatic protection circuit connected between a first voltage terminal and a ground terminal, characterized in that it includes: a trigger module, a conversion module, a feedback module, and a bleeder;

[0006] The trigger module is connected between the first voltage terminal and the ground terminal, and is used to generate a trigger signal in response to an electrostatic pulse between the first voltage terminal and the ground terminal;

[0007] The input end of the conversion module is connected to the output end of the trigger module, and is used to output a control signal for controlling the discharger to discharge static electricity in response to the trigger signal;

[0008] The discharger is connected between the first voltage terminal and the ground terminal, and the control terminal of the discharger is connected to the output terminal of the conversion module for discharging static electricity in response to the control signal;

[0009] The input end of the feedback module is connected to the output end of the conversion module, and the output end of the feedback module is connected to the trigger module, and is used to control the trigger module to extend the duration of outputting the trigger signal in response to the control signal.

[0010] Optionally, the feedback module includes a pulse trigger and a control submodule;

[0011] The input end of the pulse trigger is connected to the control end of the bleeder, and the output end of the pulse trigger is connected to the input end of the control submodule;

[0012] The pulse trigger is configured to generate a pulse output signal of a preset width at a rising edge of the control signal in response to the control signal;

[0013] The control submodule is configured to control the trigger module to extend the duration of outputting the trigger signal in response to the pulse output signal.

[0014] Optionally, the trigger module includes a first capacitor, a first end of the first capacitor is connected to the first voltage end via a resistor, a second end of the first capacitor is connected to the ground end, and the first end of the first capacitor is the output end of the trigger module;

[0015] The control submodule includes a first switch, which is connected between the first end of the first capacitor and the second end of the first capacitor. The control end of the first switch is the input end of the control submodule. The first switch is used to control the first end of the first capacitor to be short-circuited to the ground end in response to the pulse output signal.

[0016] Optionally, the pulse trigger includes a delay unit and an AND gate, the input end of the delay unit is connected to the output end of the conversion module and the first input end of the AND gate, the output end of the delay unit is connected to the second input end of the AND gate, and the output end of the AND gate is connected to the input end of the first switch;

[0017] The delay unit is used to increase the width of the rising edge of the control signal.

[0018] Optionally, the delay unit includes a first delay inverter, a first delay capacitor, a first inverter and a second inverter.

[0019] The input end of the first delay inverter is the input end of the delay unit, the output end of the first delay inverter is connected to the first end of the first delay capacitor and the input end of the first inverter, the output end of the first inverter is connected to the input end of the second inverter, the second end of the first delay capacitor is connected to the ground end, and the output end of the second inverter is the output end of the first delay unit; the first delay inverter includes a PMOS tube and multiple N-type inverse ratio tubes connected in series.

[0020] Optionally, the delay unit includes a second delay inverter, a second delay capacitor, a third inverter and a fourth inverter.

[0021] The input end of the third inverter is the input end of the delay unit, the output end of the third inverter is connected to the input end of the second delay inverter, the output end of the second delay inverter is connected to the first end of the second delay capacitor and the input end of the fourth inverter, the output end of the fourth inverter is the output end of the delay unit, and the second end of the second delay capacitor is connected to the ground end; the second delay inverter includes an NMOS transistor and multiple P-type inverse ratio transistors connected in series.

[0022] Optionally, the conversion module includes a conversion inverter, an input end of the conversion inverter is connected to an output end of the trigger module; and an output end of the conversion inverter is connected to a control end of the bleeder.

[0023] Optionally, the conversion module includes a conversion inverter and a pre-driver submodule, the input end of the conversion inverter is connected to the output end of the trigger module, the output end of the conversion inverter is connected to the input end of the pre-driver submodule, the output end of the pre-driver submodule is connected to the control end of the bleeder, and the pre-driver submodule is used to enhance the driving capability of the control signal.

[0024] Optionally, the pre-driver submodule includes a fifth inverter and a sixth inverter, the input end of the fifth inverter is connected to the output end of the conversion inverter, the output end of the fifth inverter is connected to the input end of the sixth inverter, and the output end of the sixth inverter is connected to the bleeder control end.

[0025] In a second aspect, an embodiment of the present application provides a chip that uses any of the above-mentioned electrostatic protection circuits to achieve electrostatic discharge.

[0026] The present invention provides an electrostatic protection circuit and chip. This invention receives a control signal through a feedback module, whose signal output terminal is connected to a trigger module. This module controls the trigger module to continue outputting a trigger signal, causing the conversion module to continue outputting a control signal, thereby causing the bleeder to continue discharging. In this way, the trigger module generates a trigger signal for discharging the generated static electricity in response to an electrostatic discharge phenomenon, and the feedback module extends the discharge time of the bleeder, rather than increasing the discharge time by extending the detection time in the trigger module. This avoids increasing the detection time and reduces the possibility of non-ESD events falsely triggering the ESD protection. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in this embodiment or the prior art, the following briefly introduces the drawings required for use in the embodiment or the prior art description. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0028] Figure 1 A schematic diagram of an electrostatic protection circuit provided in an embodiment of the present application;

[0029] Figure 2 A schematic diagram of another electrostatic protection circuit provided in an embodiment of the present application;

[0030] Figure 3 A schematic diagram of the circuit structure of a delay unit provided in an embodiment of the present application;

[0031] Figure 4 A schematic diagram of the circuit structure of another delay unit provided in an embodiment of the present application;

[0032] Figure 5 A schematic diagram of another electrostatic protection circuit provided in an embodiment of the present application;

[0033] Figure 6 A delay diagram of the pulse trigger provided in an embodiment of the present application.

[0034] Description of the accompanying figures

[0035] 101-first voltage terminal; 102-ground terminal; 103-trigger module; 1031-first capacitor; 1032-resistor; 104-conversion module; 1041-conversion inverter; 1042-fifth inverter; 1043-sixth inverter; 105-bleeder; 106-feedback module; 1061-first switch; 1062-AND gate; 1063-delay unit; 301-first delay inverter; 302-first delay capacitor; 303-first inverter; 304-second inverter; 401-second delay inverter; 402-second delay capacitor; 403-third inverter; 404-fourth inverter. DETAILED DESCRIPTION

[0036] In traditional RC-triggered ESD protection circuits, the ESD event detection circuit and the discharge device's on-time share the same time constant (R*C). To protect the chip from ESD events, the ESD discharge time must be sufficiently long, meaning the RC time constant must be designed to be sufficiently large. A large RC time constant can easily cause false triggering, such as from non-ESD events with fast rise times, because the ESD detection and discharge devices share the same RC time constant. Because the time constant must be large enough to ensure the discharge device remains on during an ESD event, this unnecessarily increases the ESD detection time, making it easy for non-ESD events to falsely trigger the ESD protection circuit.

[0037] To address the above-mentioned issues, the present application proposes an electrostatic protection circuit and chip. Upon receiving a control signal, the feedback module connects its signal output to a trigger module, controlling the trigger module to continue outputting a trigger signal, causing the conversion module to continue outputting a control signal, thereby causing the bleeder to continue discharging. The trigger module generates a trigger signal in response to the electrostatic discharge phenomenon, and extends the discharge time of the bleeder through the feedback module. This invention does not increase the discharge time by extending the detection time in the trigger module. By not increasing the detection time, it also reduces the possibility of non-ESD events falsely triggering the ESD protection.

[0038] Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0039] Figure 1 A schematic diagram of an electrostatic protection circuit provided in an embodiment of the present application is shown in FIG. Figure 1 , connected between the first voltage terminal 101 and the ground terminal 102 , and characterized by comprising: a trigger module 103 , a conversion module 104 , a bleeder 105 and a feedback module 106 .

[0040] The trigger module 103 is connected between the first voltage terminal 101 and the ground terminal 102 , and is configured to generate a trigger signal in response to an electrostatic pulse between the first voltage terminal 101 and the ground terminal 102 .

[0041] When electrostatic discharge occurs at the first voltage terminal 101 relative to the second voltage terminal 102, the voltage at the first voltage terminal will rise rapidly. The trigger module 103 will generate a trigger signal accordingly, so that the generated static electricity can be discharged based on the trigger signal to prevent static electricity from causing safety and usage hazards to the chip circuit.

[0042] In one possible implementation, the trigger module may include a first capacitor 1032, the first end of the first capacitor 1032 is connected to the first voltage end through a resistor 1031, and the second end of the first capacitor 1032 is connected to the ground end 102. The first end of the first capacitor 1032 is the output end of the trigger module 103. When the voltage at the first voltage end 101 rises rapidly, due to the presence of the resistor 1031 and the first capacitor 1032, the trigger signal output from the first end of the first capacitor 1031 is a low level, thereby causing the subsequent conversion module to output a high-level control signal to turn on the bleeder.

[0043] The input end of the conversion module 104 is connected to the output end of the trigger module 103 , and is configured to output a control signal for controlling the discharger 105 to discharge static electricity in response to the trigger signal.

[0044] The conversion module 104 receives the trigger signal generated by the trigger module 103 and generates a control signal capable of controlling the discharger 105 to discharge static electricity. For example, the trigger signal generated by the trigger module 103 is a low-level signal, which can be converted by the conversion module 104 into a high-level control signal required to cause the discharger 105 to discharge static electricity.

[0045] The discharger 105 is connected between the first voltage terminal 101 and the ground terminal 102 , and a control terminal of the discharger is connected to the output terminal of the conversion module 104 , for discharging static electricity in response to the control signal.

[0046] The bleeder 105 is connected to the first voltage terminal 101 and the ground terminal 102 . When the control terminal of the bleeder 105 receives a control signal, the bleeder 105 discharges the static electricity of the first voltage terminal 101 to the ground terminal.

[0047] The input end of the feedback module 106 is connected to the output end of the conversion module 104, and the output end of the feedback module is connected to the trigger module 103, and is used to respond to the control signal to control the trigger module 103 to extend the duration of the trigger signal and delay the inversion of the trigger signal (the level of the trigger signal does not change, for example, the trigger signal is at a low level, and the feedback module 106 still controls the trigger module 103 to output a low level).

[0048] In a possible implementation, the feedback module may control the first end of the first capacitor 1032 to be short-connected to the ground, so that the trigger signal outputted by the first end of the first capacitor 1031 is a low level short-connected to the ground.

[0049] According to the above circuit, the present application first triggers the generation of a trigger signal based on the electrostatic discharge phenomenon sensed by the trigger module, so that the subsequent conversion module outputs a high-level control signal to turn on the bleeder, and then receives the high-level control signal through the feedback module. The feedback module 106 further controls the trigger module to continue to output a low-level trigger signal, so that the conversion module 104 continues to output a high-level control signal, thereby causing the bleeder 105 to delay and continue to discharge. In this way, the trigger module can respond to the electrostatic discharge phenomenon that occurs, generate a trigger signal for discharging the generated static electricity, and ensure the discharge time of the bleeder 105 through the feedback module 106, instead of increasing the discharge time by extending the detection time in the trigger module 103. Not increasing the detection time also reduces the situation where non-ESD events mistakenly trigger ESD protection.

[0050] In a possible implementation, the bleeder may be an N-type MOSFET tube, the source of the bleeder is connected to the ground terminal, the gate of the bleeder is the control terminal of the bleeder, and the drain of the bleeder is connected to the first power supply terminal.

[0051] In the embodiment of the present application, the above Figure 1 The possible implementations of the feedback module in the embodiment are described in detail below. It should be noted that the implementations given in the following description are only exemplary and do not represent all implementations of the embodiments of the present application.

[0052] The feedback module 106 includes a pulse trigger and a control submodule.

[0053] The input end of the pulse trigger is connected to the output end of the conversion module, and the output end of the pulse trigger is connected to the input end of the control submodule.

[0054] The pulse trigger is used to generate a pulse output signal of a preset width at a rising edge of the control signal in response to the control signal.

[0055] The control submodule is configured to control the trigger module to extend the duration of outputting the trigger signal in response to the pulse output signal.

[0056] The control submodule controls the trigger module to output a trigger signal, and the pulse trigger is used to control the duration of the control submodule controlling the trigger module to output the trigger signal.

[0057] See also Figure 2 Another electrostatic protection circuit schematic diagram shown is based on the above-mentioned feedback module 106. In one possible implementation, the trigger module 103 includes a first capacitor 1032, the first end of the first capacitor 1032 is connected to the first voltage end through a resistor 1031, the second end of the first capacitor 1032 is connected to the ground end 102, and the first end of the first capacitor 1031 is the output end of the trigger module 103.

[0058] When electrostatic discharge occurs at the first voltage terminal 101 relative to the second voltage terminal 102, since the duration of the rising edge of the electrostatic pulse is much shorter than the RC delay time of the first capacitor 1032, the potential across the first capacitor 1032 does not have time to change, that is, relative to the high level of the first voltage terminal 101 at this time, the trigger signal output by the trigger module is a low level.

[0059] The control submodule includes a first switch 1061, which is connected between the first end of the first capacitor and the second end of the first capacitor. The control end of the first switch 1061 is the input end of the control submodule. The first switch 1061 controls the first end of the first capacitor 1032 to be short-circuited to the ground end 102 in response to the pulse output signal.

[0060] The first switch may be any switch capable of controlling whether the first capacitor is short-circuited.

[0061] In a possible implementation, the first switch 1061 may be an NMOSFET tube, or may be another type of switch that can control the conduction between the two ends of the first capacitor through a control terminal.

[0062] A first end of the first capacitor 1032 is connected to the drain of the first switch 1061, and a second end of the first capacitor 1032 is connected to the source of the first switch 1061. The control end of the first switch 1061 serves as the gate of the first switch. When the first switch 1061 is turned on, the first end of the first capacitor 1031 is connected to the ground, so that the first end of the first capacitor 1031, i.e., the output end of the trigger module, continues to output a low-level trigger signal.

[0063] In another possible implementation, the pulse trigger includes a delay unit 1063 and an AND gate 1062, the input end of the delay unit 1063 is connected to the output end of the conversion module and the first input end of the AND gate 1062, the output end of the delay unit 1063 is connected to the second input end of the AND gate 1062, and the output end of the AND gate 1062 is connected to the input end of the first switch 1061.

[0064] The delay unit 1063 is used to increase the width of the rising edge of the control signal.

[0065] The delay unit 1063 in the pulse trigger outputs a high level, and the first switch 1061 can remain turned on, thereby controlling the first end of the first capacitor 1032 to be grounded. The output end of the trigger module 103 outputs a trigger signal, and then the conversion module 104 outputs a control signal to keep the bleeder 105 discharging.

[0066] In the electrostatic protection circuit of the above embodiment, when an ESD event occurs, the trigger module 103 detects the ESD event and causes the bleeder 105 to discharge static electricity. Simultaneously, the rising edge of the control signal passes through the feedback module 106, which outputs a high-level pulse with a width of Tpulse. During this period, the first switch 1061 is turned on, the first end of the first capacitor 1032 is shorted to the ground terminal VSS, and the bleeder 105 remains turned on. After Tpulse, the pulse generation circuit outputs a low level, and the first switch 1061 is turned off.

[0067] There are multiple implementations of the delay unit 1063 of the pulse trigger.

[0068] In one possible implementation, see Figure 3 A circuit structure diagram of a delay unit in the embodiment of the present invention, wherein the delay unit includes a first delay inverter 301, a first delay capacitor 302, a first inverter 303 and a second inverter 304;

[0069] The input end of the first delay inverter 301 is the input end of the delay unit 302, the output end of the first delay inverter 301 is connected to the first end of the first delay capacitor 302 and the input end of the first inverter 303, the output end of the first inverter 303 is connected to the input end of the second inverter 304, the second end of the first delay capacitor 302 is connected to the ground end, and the output end of the second inverter 302 is the output end of the delay unit; the first delay inverter 301 includes a PMOS transistor and multiple N-type inverse ratio transistors connected in series.

[0070] In another possible implementation, see Figure 4The circuit structure diagram of another delay unit shown is as follows, wherein the delay unit includes a second delay inverter 401, a second delay capacitor 402, a third inverter 403 and a fourth inverter 404. The input end of the third inverter 403 is the input end of the delay unit, the output end of the third inverter 403 is connected to the input end of the second delay inverter 401, the output end of the second delay inverter 401 is connected to the first end of the second delay capacitor 402 and the input end of the fourth inverter 403, the output end of the fourth inverter 403 is the output end of the delay unit, and the second end of the second delay capacitor 402 is connected to the ground end; the second delay inverter 401 includes an NMOS transistor and multiple P-type inverse ratio transistors connected in series.

[0071] according to Figure 4 The implementation shown is to delay the control signal by combining multiple P-type inverse ratio transistors connected in series with a second delay capacitor. Alternatively, the width of the rising edge of the control signal can be increased by increasing the number of inverse ratio transistors, increasing the size of the inverse ratio transistors, or increasing the second delay capacitor.

[0072] In the embodiment of the present application, the above Figure 1 There are many possible implementations of the conversion module 104, which are described in detail below. It should be noted that the implementations given in the following description are only exemplary and do not represent all implementations of the embodiments of the present application.

[0073] In a possible implementation, the conversion module includes a conversion inverter, an input end of the conversion inverter is connected to an output end of the trigger module; and an output end of the conversion inverter is connected to a control end of the bleeder.

[0074] The conversion inverter in the conversion module converts the trigger signal (low level) output by the trigger module into a control signal (high level) capable of driving the discharger control terminal to discharge static electricity.

[0075] In another possible implementation, see Figure 5 A schematic diagram of another electrostatic protection circuit is shown, in which the conversion module 104 includes a conversion inverter 1041 and a pre-driver submodule. The input end of the conversion inverter 1041 is connected to the output end of the trigger module 103, the output end of the conversion inverter 1041 is connected to the input end of the pre-driver submodule, and the output end of the pre-driver submodule is connected to the control end of the bleeder 105. The pre-driver submodule is used to enhance the driving capability of the control signal.

[0076] Exemplarily, the pre-driver submodule includes a fifth inverter 1042 and a sixth inverter 1043, the input end of the fifth inverter 1042 is connected to the output end of the conversion inverter, the output end of the fifth inverter 1042 is connected to the input end of the sixth inverter 1043, and the output end of the sixth inverter 1043 is connected to the control end of the bleeder 105.

[0077] The conversion inverter 1041 in the conversion module 104 converts the trigger signal (low level) output by the trigger module 103 into a high level. This high level is input to the pre-driver submodule, which enhances the driving capability of the output signal of the conversion inverter. The pre-driver submodule outputs a control signal that can drive the discharger control terminal to discharge static electricity.

[0078] Based on the above embodiments and the above Figure 5 As shown in the schematic diagram of another electrostatic protection circuit, the specific implementation process of the discharge delay of the bleeder in the present application is as follows: when an electrostatic discharge (ESD) event occurs, the trigger module 103 detects the ESD event. Specifically, the voltage of the first voltage terminal 101 rises rapidly. Due to the presence of the resistor 1031 and the first capacitor 1032 in the trigger module 103, the first end of the first capacitor 1031 outputs a low-level voltage, thereby causing the subsequent conversion module to output a high-level control signal, turning on the discharge bleeder, causing VTRI G to become high and thus turning on the discharge NMOS.

[0079] At the same time, the pulse trigger of the feedback circuit 106 outputs a high-level pulse with a width of Tpulse according to the rising edge of the control signal VTRI G, controlling the first switch 1061 to turn on, so that the first end of the first capacitor 1031 is shorted to VSS. As a result, the trigger signal output by the first end of the first capacitor 1031 is a low-level voltage shorted to ground, and the bleeder device continues to remain turned on. In this way, the feedback module extends the duration of the trigger module outputting the low-level trigger signal, thereby achieving a delay in the bleeder discharge.

[0080] See Figure 5 The schematic diagram of another electrostatic protection circuit and Figure 6 The delay diagram of the pulse trigger is shown in FIG. Figure 6 Td ly in Figure 5The delay from the control signal VTRI G to the delay unit output signal VTRI GN_DLY is determined by the N series-connected N-type inverse ratio transistors and the delay capacitor. The rising edge width Tpulse of the delay signal VPULSE output by the pulse trigger is equal to Tdly. Tdly can be adjusted by adjusting the number and size of the series-connected N-type inverse ratio transistors in the delay inverter and the size of the delay capacitor (increasing the width of the rising edge of the control signal by increasing the number of inverse ratio transistors, increasing the size of the inverse ratio transistors, and increasing the delay capacitor). This can adjust Tpulse, thereby independently adjusting the on-time of the discharge device without affecting the ESD detection time. When VPULSE goes low, the first switch 1061 is closed, and the first voltage terminal charges the first capacitor 1032 via resistor 1031. After the voltage at the first terminal of the first capacitor rises from 0 to the conversion inverter flip threshold, a low level is output at the output of the conversion module, turning off the discharge NMOS. The ESD event detection time constant is R*C. When Tpulse is much greater than R*C, the discharge time, the shutdown of the discharge NMOS is primarily determined by Tpulse. Therefore, adjusting the width of Tpulse can adjust the discharge tube conduction time, ensuring that the discharge tube conducts during the entire ESD event without affecting the ESD detection time constant. This expands the range of signal rise speeds during non-ESD events and prevents normal signal changes from falsely triggering ESD discharge protection.

[0081] The embodiment of the present application also provides a corresponding chip for implementing the solution provided by the embodiment of the present application.

[0082] A chip is provided with an electrostatic protection circuit in the above embodiment to achieve electrostatic discharge.

[0083] The "first" and "second" in the names such as "first" and "second" (if any) mentioned in the embodiments of this application are only used as name identifiers and do not represent the first or second in order.

[0084] Through the description of the above embodiments, it can be known that those skilled in the art can clearly understand that all or part of the steps in the above embodiment methods can be implemented by means of software plus a general hardware platform. Based on this understanding, the technical solution of the present application can be embodied in the form of a software product, which can be stored in a storage medium, such as a read-only memory (ROM) / RAM, a magnetic disk, an optical disk, etc., and includes a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network communication device such as a router) to execute the methods described in each embodiment of the present application or certain parts of the embodiments.

[0085] Each embodiment in this specification is described in a progressive manner. The same or similar parts between the embodiments can be referred to each other. Each embodiment focuses on the differences from other embodiments. In particular, for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple. For the relevant parts, refer to the partial description of the method embodiment. Some or all of the modules can be selected according to actual needs to achieve the purpose of the embodiment. Those of ordinary skill in the art can understand and implement it without paying any creative work.

[0086] The above description is merely an exemplary embodiment of the present application and is not intended to limit the scope of protection of the present application.

Claims

1. An electrostatic protection circuit connected between a first voltage terminal and a ground terminal, characterized in that: include: Trigger module, conversion module, feedback module and bleeder; The trigger module is connected between the first voltage terminal and the ground terminal, and is used to generate a trigger signal in response to an electrostatic pulse between the first voltage terminal and the ground terminal; The input end of the conversion module is connected to the output end of the trigger module, and is used to output a control signal for controlling the discharger to discharge static electricity in response to the trigger signal; The discharger is connected between the first voltage terminal and the ground terminal, and the control terminal of the discharger is connected to the output terminal of the conversion module for discharging static electricity in response to the control signal; The input end of the feedback module is connected to the output end of the conversion module, and the output end of the feedback module is connected to the trigger module, and is used to control the trigger module to extend the duration of outputting the trigger signal in response to the control signal; The feedback module includes a pulse trigger, and the pulse trigger is used to generate a pulse output signal of a preset width at a rising edge of the control signal in response to the control signal; The trigger module includes a first capacitor, a first end of the first capacitor is connected to the first voltage end through a resistor, a second end of the first capacitor is connected to the ground end, and the first end of the first capacitor is the output end of the trigger module; The control submodule includes a first switch, the first switch being connected between a first terminal of the first capacitor and a second terminal of the first capacitor, the control terminal of the first switch being an input terminal of the control submodule, and the first switch being configured to control the first terminal of the first capacitor to be short-circuited to the ground terminal in response to the pulse output signal; The pulse trigger includes a delay unit and an AND gate, the input end of the delay unit is connected to the output end of the conversion module and the first input end of the AND gate, the output end of the delay unit is connected to the second input end of the AND gate, and the output end of the AND gate is connected to the input end of the first switch; The delay unit is used to increase the width of the rising edge of the control signal.

2. The circuit according to claim 1, wherein: The feedback module also includes a control submodule; The input end of the pulse trigger is connected to the control end of the bleeder, and the output end of the pulse trigger is connected to the input end of the control submodule; The control submodule is used to control the trigger module to extend the duration of the output trigger signal in response to the pulse output signal.

3. The circuit according to claim 2, characterized in that The delay unit includes a first delay inverter, a first delay capacitor, a first inverter and a second inverter. The input end of the first delay inverter is the input end of the delay unit, the output end of the first delay inverter is connected to the first end of the first delay capacitor and the input end of the first inverter, the output end of the first inverter is connected to the input end of the second inverter, the second end of the first delay capacitor is connected to the ground end, and the output end of the second inverter is the output end of the first delay unit; the first delay inverter includes a PMOS transistor and a plurality of N-type inverse ratio transistors connected in series.

4. The circuit according to claim 2, characterized in that The delay unit includes a second delay inverter, a second delay capacitor, a third inverter and a fourth inverter. The input end of the third inverter is the input end of the delay unit, the output end of the third inverter is connected to the input end of the second delay inverter, the output end of the second delay inverter is connected to the first end of the second delay capacitor and the input end of the fourth inverter, the output end of the fourth inverter is the output end of the delay unit, and the second end of the second delay capacitor is connected to the ground end; the second delay inverter includes an NMOS transistor and multiple P-type inverse ratio transistors connected in series.

5. The circuit according to any one of claims 1 to 4, characterized in that: The conversion module includes a conversion inverter, an input end of the conversion inverter is connected to the output end of the trigger module; and an output end of the conversion inverter is connected to the control end of the bleeder.

6. The circuit according to any one of claims 1 to 4, characterized in that: The conversion module includes a conversion inverter and a pre-driver submodule. The input end of the conversion inverter is connected to the output end of the trigger module, the output end of the conversion inverter is connected to the input end of the pre-driver submodule, and the output end of the pre-driver submodule is connected to the control end of the bleeder. The pre-driver submodule is used to enhance the driving capability of the control signal.

7. The circuit according to claim 6, characterized in that The pre-driver submodule includes a fifth inverter and a sixth inverter, the input end of the fifth inverter is connected to the output end of the conversion inverter, the output end of the fifth inverter is connected to the input end of the sixth inverter, and the output end of the sixth inverter is connected to the bleeder control end.

8. A chip, characterized in that: An electrostatic protection circuit as described in any one of claims 1 to 7 is used to achieve electrostatic discharge.

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