Capacitor array switching method for single-ended input SAR ADC with two-level and stable common mode point

Abstract

The present invention relates to a capacitor array switching method for a SAR ADC, and in particular to a capacitor array switching method for a single-ended input SAR ADC with two levels and a stable common mode point, which is used to solve the problem that the output common mode point of the capacitor array switching method for a single-ended input SAR ADC is unstable and mostly has a three-level structure, resulting in the performance of the SAR ADC being limited. The capacitor array switching method for a single-ended input SAR ADC with two levels and a stable common mode point uses a pseudo-differential structure and a split capacitor array to improve the tolerance of the SAR ADC to capacitor mismatch, so as to improve the accuracy of the SAR ADC.

Description

Technical Field

[0001] The invention relates to a capacitor array switching method of a SAR ADC, and in particular to a capacitor array switching method of a single-ended input SAR ADC with two levels and a stable common mode point. Background Art

[0002] ADC (Analog-to-Digital Converter) is an interface device between analog circuits and digital circuits and an important part of the signal chain. Among the many types of ADCs, SAR ADC (Successive Approximation Analog-to-Digital Converter) has attracted widespread attention due to its low power consumption, small area, few analog modules, and compatibility with advanced CMOS (Complementary Metal Oxide Semiconductor) processes. It is often used in applications such as touch screen interfaces and industrial automation systems. However, with the continuous iteration of equipment, SAR ADC requires higher precision to meet new product requirements. The main modules of SAR ADC include: sampling and holding circuit, comparator, capacitor array and SAR logic circuit. Among them, the capacitor array is the core of SAR ADC and is used to connect the other three modules. The capacitor array and its corresponding switching method determine the degree of compromise of SAR ADC power consumption, area, accuracy, and number of interfaces to a certain extent. According to the input signal mode, SAR ADC can be divided into differential input and single-ended input. Single-ended input SAR ADC refers to using a single input terminal to receive analog signals. It is different from differential input SAR ADC, which uses two input terminals (positive input and negative input) to receive signals. Single-ended input SAR ADCs are more common in simple or cost-sensitive applications because they have a simpler structure, but are usually more affected by circuit nonlinear factors. The output common-mode point of the capacitor array switching method of the single-ended input SAR ADC is unstable and mostly a three-level structure, which limits the performance of the SAR ADC. Summary of the invention

[0003] The purpose of the present invention is to solve the shortcomings of the capacitor array switching method of the single-ended input SAR ADC, that is, the output common mode point is unstable and the structure is mostly three-level, which leads to the performance limitation of the SAR ADC, and to provide a capacitor array switching method of the single-ended input SAR ADC with two levels and stable common mode point.

[0004] In order to solve the deficiencies of the above-mentioned prior art, the present invention provides the following technical solutions:

[0005] A two-level single-ended input SAR ADC with a stable common mode point, which is special in that it includes a comparator, a positive-end split capacitor array, a negative-end split capacitor array and a SAR logic circuit;

[0006] One end of the top plate of the positive terminal split capacitor array is connected to the input voltage V through the positive terminal sampling switch INThe other end is connected to the positive terminal of the comparator. The positive end split capacitor array includes a high-end DAC PH and low-end DAC PL , high-end DAC PH and low-end DAC PL The number and weight of capacitors are the same;

[0007] One end of the top plate of the negative terminal split capacitor array is connected to the reference voltage V through the negative terminal sampling switch. REF The other end is connected to the negative terminal of the comparator, and the negative end split capacitor array includes the high-end DAC NH and low-end DAC NL , high-end DAC NH and low-end DAC NL The number and weight of capacitors are consistent;

[0008] The comparator is used to generate the A-th digital code D according to the comparison result of the voltage at the positive terminal and the voltage at the negative terminal of the comparator. A , A is an integer from 0 to N-1, and N is a positive integer;

[0009] The input end of the SAR logic circuit is connected to the output end of the comparator, and the output end is connected to the high-end DAC PH , low-end DAC PL , high-end DAC NH and low-end DAC NL The SAR logic circuit is used to switch the bottom plate of the A-th digital code D A The value controls the high-segment DAC PH , low-end DAC PL , high-end DAC NH and low-end DAC NL The connection voltage of the bottom plate.

[0010] Furthermore, its working phases are sampling phase, holding phase and conversion phase in sequence;

[0011] During the sampling phase, the high-segment DAC PH and low-end DAC PL The bottom plates are connected to GND, and the top plates are connected to the input voltage V IN , the high-segment DAC NH and low-end DAC NL The bottom plates are connected to the input signal V IN , the top plate is connected to the reference voltage V REF ;

[0012] During the hold phase, the high-segment DAC PH and low-end DAC PL The bottom plates are connected to the reference voltage V REFand GND, the high-segment DAC NH and low-end DAC NL The bottom plate is connected to GND and the reference voltage V REF ;

[0013] In the conversion phase, the A-th digital code D A When the value is 1, the high-segment DAC PH The bottom plate of the corresponding capacitor is connected to GND, the high-end DAC NH The bottom plate of the corresponding capacitor is connected to the reference voltage V REF ; The A-th digit code D A The value is 0, the low-segment DAC PL The bottom plate of the corresponding capacitor is connected to the reference voltage V REF , the low-segment DAC NL The bottom plate of the corresponding capacitor is connected to GND.

[0014] Furthermore, the high-end DAC PH , low-end DAC PL , high-end DAC NH and low-end DAC NL Both include 2 in parallel N-1 A capacitor.

[0015] At the same time, the present invention also provides a capacitor array switching method for the above-mentioned two-level single-ended input SAR ADC with stable common mode point, which is special in that it includes the following steps:

[0016] Step 1: Sampling stage;

[0017] The input signal V IN Connect the positive end split capacitor array to the high-end DAC PH and low-end DAC PL top plate, high-end DAC PH and low-end DAC PL The bottom plates of the IN Connect the negative end of the split capacitor array to the high-end DAC NH and low-end DAC NL bottom plate, high-end DAC NH and low-end DAC NL The top plate is connected to the reference voltage V REF ;

[0018] Step 2: Maintaining stage;

[0019] Disconnect the positive sampling switch and the negative sampling switch, and then turn on the high-end DAC. PH , low-end DAC PL The bottom plates are connected to the reference voltage VREF and GND, high-end DAC NH , low-end DAC NL The bottom plate is connected to GND and the reference voltage V REF ;

[0020] Step 3: Conversion phase;

[0021] The comparator compares the voltage at its positive terminal with the voltage at its negative terminal to generate the A-bit digital code D. A , output to the SAR logic circuit, which is based on the A-th digital code D A The value controls the high-segment DAC PH , low-end DAC PL , high-end DAC NH and low-end DAC NL The connection voltage of the bottom plate.

[0022] Furthermore, the step 3 is specifically as follows:

[0023] Step 3.1, compare the highest bit;

[0024] The comparator compares the voltage at its positive terminal with the voltage at its negative terminal to generate the N-1th digital code D. N-1 SAR logic circuit determines the N-1th digital code D N-1 If the value of D N-1 =1, then execute step 3.1.1. If D N-1 =0, then execute step 3.1.2;

[0025] Step 3.1.1, the SAR logic circuit sets the high-end DAC PH The bottom plate of the highest capacitor is connected to GND, which reduces the output voltage of the positive end split capacitor array The SAR logic circuit converts the high-end DAC NH The bottom plate of the highest capacitor is connected to the reference voltage V REF , so that the output voltage of the negative split capacitor array increases The common mode point remains stable during this process;

[0026] Step 3.1.2: The SAR logic circuit sets the low-end DAC PL The bottom plate of the highest capacitor is connected to the reference voltage V REF , so that the output voltage of the positive split capacitor array increases The SAR logic circuit converts the low-end DAC NL The bottom plate of the highest capacitor is connected to GND, which reduces the output voltage of the negative split capacitor array. The common mode point remains stable during this process;

[0027] Step 3.2, compare the second highest position;

[0028] The comparator compares the voltage at its positive terminal with the voltage at its negative terminal to generate the N-2 digit digital code D. N-2 SAR logic circuit determines the N-2 digit code D N-2 If the value of D N-2 =1, then execute step 3.2.1. If D N-2 =0, then execute step 3.2.2;

[0029] Step 3.2.1: The SAR logic circuit sets the high-end DAC PH The bottom plate of the second highest capacitor is connected to GND, which reduces the output voltage of the positive end split capacitor array. The SAR logic circuit converts the high-end DAC NH The bottom plate of the second highest capacitor is connected to the reference voltage V REF , so that the output voltage of the negative split capacitor array increases The common mode point remains stable during this process;

[0030] Step 3.2.2: The SAR logic circuit sets the low-end DAC PL The bottom plate of the second highest capacitor is connected to the reference voltage V REF , so that the output voltage of the positive split capacitor array increases The SAR logic circuit converts the low-end DAC NL The bottom plate of the second highest capacitor is connected to GND, which reduces the output voltage of the negative split capacitor array. The common mode point remains stable during this process;

[0031] Step 3.3, successive approximation;

[0032] Follow the method of step 3.1 and step 3.2 to perform successive approximation until the output D N-1 D N-2 ...N-digit code of D1D0.

[0033] Compared with the prior art, the present invention has the following beneficial effects:

[0034] (1) The two-level and common-mode-point-stable single-ended input SAR ADC capacitor array of the present invention is used to improve various performance indicators of the SAR ADC; only two levels are used, the tolerance to voltage mismatch is high, and the peripheral auxiliary circuit (LDO (low dropout linear regulator) / reference) of the SAR ADC is simplified.

[0035] (2) The capacitor array switching method of the present invention uses a pseudo-differential structure and a split capacitor array to improve the tolerance of the SAR ADC to capacitor mismatch, thereby improving the accuracy of the SAR ADC.

[0036] (3) The capacitor array switching method of the present invention uses a combination of top plate and bottom plate sampling and a double-end switching method to stabilize the output common mode point of the capacitor array, prevent dynamic offset of the comparator, and make the SAR ADC more linear, thereby improving the accuracy of the SAR ADC. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 It is a structural schematic diagram of an embodiment of a two-level single-ended input SAR ADC with a stable common mode point according to the present invention;

[0038] Figure 1 The reference numerals are explained as follows: 1-SAR logic circuit; 21-positive end sampling switch, 22-negative end sampling switch (1).

[0039] Figure 2 It is a schematic diagram of the principle of an embodiment of a capacitor array switching method for a single-ended input SAR ADC with two levels and a stable common mode point according to the present invention;

[0040] Figure 3 A schematic diagram of an existing capacitor array switching method;

[0041] Figure 4 It is applied to 12-bit SAR ADC with 0.5% voltage mismatch. Figure 3 MATLAB simulation of the effective number of bits distribution of existing capacitor array switching methods;

[0042] Figure 5 It is applied to 12-bit SAR ADC with 1% capacitor mismatch. Figure 3 MATLAB simulation of the effective number of bits distribution of existing capacitor array switching methods;

[0043] Figure 6 The MATLAB simulation effective bit number distribution of the present invention is applied to 12-bit SAR ADC under the condition of 0.5% voltage mismatch;

[0044] Figure 7 The MATLAB simulation effective number of bits distribution of the present invention is applied to 12-bit SAR ADC under the condition of 1% capacitor mismatch. DETAILED DESCRIPTION

[0045] The present invention will be further described below in conjunction with the accompanying drawings and exemplary embodiments.

[0046] Reference Figure 1 The present invention discloses a two-level single-ended input SAR ADC with a stable common mode point, comprising a comparator, a positive-end split capacitor array, a negative-end split capacitor array and a SAR logic circuit 1.

[0047] One end of the top plate of the positive terminal split capacitor array is connected to the input voltage V through the positive terminal sampling switch 21. IN The other end is connected to the positive terminal of the comparator. The positive end split capacitor array includes a high-end DAC PH and low-end DAC PL , high-end DAC PH and low-end DAC PL The number of capacitors and their weights are the same.

[0048] One end of the top plate of the negative split capacitor array is connected to a reference voltage V via a negative sampling switch 22. REF The other end is connected to the negative terminal of the comparator, and the negative end split capacitor array includes the high-end DAC NH and low-end DAC NL , high-end DAC NH and low-end DAC NL The number of capacitors and their weights are the same.

[0049] The high-end DAC PH , low-end DAC PL , high-end DAC NH and low-end DAC NL Both include 2 in parallel N-1 A capacitor.

[0050] The comparator is used to generate the A-th digital code D according to the comparison result of the voltage at the positive terminal and the voltage at the negative terminal of the comparator. A , A is an integer from 0 to N-1, and N is a positive integer.

[0051] The input end of the SAR logic circuit 1 is connected to the output end of the comparator, and the output end is connected to the high-end DAC PH , low-end DAC PL , high-end DAC NH and low-end DAC NL The SAR logic circuit 1 is used to switch the bottom plate of the A-th digital code D A The value controls the high-segment DAC PH , low-end DAC PL , high-end DAC NH and low-end DAC NL The connection voltage of the bottom plate.

[0052] The working phases of the two-level single-ended input SAR ADC with stable common mode point of the present invention are sampling phase, holding phase and conversion phase in sequence.

[0053] During the sampling phase, the high-segment DAC PH and low-end DAC PL The bottom plates are connected to GND, and the top plates are connected to the input voltage VIN , the high-segment DAC NH and low-end DAC NL The bottom plates are connected to the input signal V IN , and its top plate is connected to the reference voltage V REF .

[0054] During the hold phase, the high-segment DAC PH and low-end DAC PL The bottom plates are connected to the reference voltage V REF and GND, the high-segment DAC NH and low-end DAC NL The bottom plate is connected to GND and the reference voltage V REF ;

[0055] In the conversion phase, the A-th digital code D A When the value is 1, the high-segment DAC PH The bottom plate of the corresponding capacitor is connected to GND, the high-end DAC NH The bottom plate of the corresponding capacitor is connected to the reference voltage V REF ; The A-th digit code D A The value is 0, the low-segment DAC PL The bottom plate of the corresponding capacitor is connected to the reference voltage V REF , the low-segment DAC NL The bottom plate of the corresponding capacitor is connected to GND.

[0056] Reference Figure 2 The present invention discloses a capacitor array switching method for a single-ended input SAR ADC with two levels and a stable common mode point, comprising the following steps:

[0057] Step 1: Sampling stage;

[0058] The input signal V IN Connect the positive end split capacitor array to the high-end DAC PH and low-end DAC PL top plate, high-end DAC PH and low-end DAC PL The bottom plates of the IN Connect the negative end of the split capacitor array to the high-end DAC NH and low-end DAC NL bottom plate, high-end DAC NH and low-end DAC NL The top plate is connected to the reference voltage V REF ;

[0059] Step 2: Maintaining stage;

[0060] Disconnect the positive sampling switch 21 and the negative sampling switch 22, and the high-end DAC PH , low-end DAC PL The bottom plates are connected to the reference voltage V REF and GND, high-end DAC NH , low-end DAC NL The bottom plate is connected to GND and the reference voltage V REF ; At this time, the voltage at the positive terminal of the comparator is The voltage at the negative terminal is

[0061] Step 3: Conversion phase;

[0062] The comparator compares the voltage at its positive end with the voltage at its negative end to generate a digital code, which is output to the SAR logic circuit 1. The SAR logic circuit 1 controls the high-end DAC according to the digital code. PH , low-end DAC PL , high-end DAC NH and low-end DAC NL The connection voltage of the bottom plate;

[0063] Specifically,

[0064] Step 3.1, compare the highest bit;

[0065] The comparator compares the voltage at its positive terminal with the voltage at its negative terminal to generate the N-1th digital code D. N-1 SAR logic circuit 1 determines the N-1th digital code D N-1 If the value of D N-1 =1, then execute step 3.1.1. If D N-1 =0, then execute step 3.1.2;

[0066] Step 3.1.1, SAR logic circuit 1 sets the high-end DAC PH The bottom plate of the highest capacitor is connected to GND, which reduces the output voltage of the positive end split capacitor array The SAR logic circuit 1 converts the high-end DAC NH The bottom plate of the highest capacitor is connected to the reference voltage V REF , so that the output voltage of the negative split capacitor array increases The common mode point remains stable during this process;

[0067] Step 3.1.2: SAR logic circuit 1 sets the low-end DAC PL The bottom plate of the highest capacitor is connected to the reference voltage V REF , so that the output voltage of the positive split capacitor array increases The SAR logic circuit 1 sets the low-end DAC NLThe bottom plate of the highest capacitor is connected to GND, which reduces the output voltage of the negative split capacitor array. The common mode point remains stable during this process;

[0068] Step 3.2, compare the second highest position;

[0069] The comparator compares the voltage at its positive terminal with the voltage at its negative terminal to generate the N-2 digit digital code D. N-2 SAR logic circuit 1 determines the N-2 digit code D N-2 If the value of D N-2 =1, then execute step 3.2.1. If D N-2 =0, then execute step 3.2.2;

[0070] Step 3.2.1, SAR logic circuit 1 sets the high-end DAC PH The bottom plate of the second highest capacitor is connected to GND, which reduces the output voltage of the positive end split capacitor array. The SAR logic circuit 1 converts the high-end DAC NH The bottom plate of the second highest capacitor is connected to the reference voltage V REF , so that the output voltage of the negative split capacitor array increases The common mode point remains stable during this process;

[0071] Step 3.2.2: SAR logic circuit 1 sets the low-end DAC PL The bottom plate of the second highest capacitor is connected to the reference voltage V REF , so that the output voltage of the positive split capacitor array increases The SAR logic circuit 1 sets the low-end DAC NL The bottom plate of the second highest capacitor is connected to GND, which reduces the output voltage of the negative split capacitor array. The common mode point remains stable during this process;

[0072] Step 3.3, successive approximation;

[0073] Follow the method of step 3.1 and step 3.2 to perform successive approximation until the output D N-1 D N-2 ...N-digit code of D1D0.

[0074] Figure 3 A conventional capacitor array switching method includes the following steps:

[0075] Step 1: Sampling stage;

[0076] The common mode voltage V' CM Connect the top plate of the capacitor array, and the bottom plate of the capacitor array is connected to the input signal V' IN ;

[0077] Step 2: Maintaining stage;

[0078] The sampling switch is disconnected, and the bottom plate voltage of the highest capacitor in the capacitor array is connected to the reference voltage V' REF , the bottom plates of other capacitors are connected to GND;

[0079] Step 3: Conversion phase;

[0080] The comparator compares the voltage at its positive terminal with the common-mode voltage V' at its negative terminal. CM Generate the N'-1th digit code D N’-1 , output to the SAR logic circuit, which is based on the N'-1 digital code D N’-1 controlling a bottom plate switch of the capacitor array;

[0081] Follow the above steps to perform successive approximation until the output D N’-1 D N’-2 ...N' digit code of D1D0.

[0082] The above existing capacitor array switching method has three undesirable factors:

[0083] (1) Three levels are used, with the common mode voltage V' CM It can be generated by external / internal LDO or reference, which undoubtedly uses additional resources to ensure the common-mode voltage V' CM existence.

[0084] (2) There will be a voltage mismatch between the three references. This mismatch can be regarded as a kind of noise. When the mismatch is large, it will have a great impact on the accuracy of the SAR ADC.

[0085] (3) The negative terminal of the comparator is connected to the common mode voltage V' CM , which means that during the quantization process of the SAR ADC, only the voltage at the positive terminal of the comparator changes. This will cause the common-mode voltage of the comparator input to change all the time, causing dynamic offset of the comparator, which in turn affects the linear characteristics of the SAR ADC, and ultimately makes it difficult to improve the accuracy.

[0086] Figure 4 and Figure 6The MATLAB simulation effective bit distribution of the existing capacitor array switch method and the capacitor array switch method of the present invention are respectively applied to 12-bit SAR ADC under the condition of 0.5% voltage mismatch, and the simulation is performed 500 times respectively. The horizontal axis ENOB represents the effective bit, and the vertical axis count represents the number of times the ENOB value appears in each column of the histogram. For the existing capacitor array switch method, most of the ENOBs are above 11.5-bit, the worst reaches about 7.5-bit, and there are many distributions below 11-bit, with an average of 11.12-bit and a standard deviation of 1.25-bit. For the capacitor array switch method of the present invention, most of the ENOBs are above 11.8-bit, and the poor ENOBs are very few, with an average of 11.9-bit and a standard deviation of 0.27-bit. It can be seen from this that the multi-level capacitor array switch method is very strict to the level accuracy, and often needs to consume additional resources and power consumption (such as high-precision LDO, high-precision benchmark) to achieve a certain accuracy.

[0087] Figure 5 and Figure 7 The MATLAB simulation effective bit distributions of the existing capacitor array switching method and the capacitor array switching method of the present invention are respectively applied to the 12-bit SAR ADC under the condition of 1% capacitor mismatch, and the simulations are respectively performed 500 times. For the existing capacitor array switching method, most of the ENOBs are above 11.5-bit, the worst reaches about 10.8-bit, the mean is 11.7-bit, and the standard deviation is 0.21-bit. For the capacitor array switching method of the present invention, most of the ENOBs are above 11.8-bit, the worst reaches about 11.2-bit, the mean is 11.85-bit, and the standard deviation is 0.13-bit. Among them, the worst value and mean value of ENOB are more advantageous for the capacitor array switching method of the present invention.

Claims

1. A capacitor array switching method for a two-level single-ended input SAR ADC with a stable common mode point, using a two-level single-ended input SAR ADC with a stable common mode point, the two-level single-ended input SAR ADC with a stable common mode point comprising a comparator, a positive end split capacitor array, a negative end split capacitor array and a SAR logic circuit (1); One end of the top plate of the positive terminal split capacitor array is connected to the input voltage V via a positive terminal sampling switch (21). IN The other end is connected to the positive terminal of the comparator. The positive end split capacitor array includes a high-end DAC PH and low-end DAC PL , high-end DAC PH and low-end DAC PL The number and weight of capacitors are consistent; One end of the top plate of the negative-end split capacitor array is connected to a reference voltage V via a negative-end sampling switch (22). REF The other end is connected to the negative terminal of the comparator, and the negative end split capacitor array includes the high-end DAC NH and low-end DAC NL , high-end DAC NH and low-end DAC N The number and weight of capacitors in L are consistent; The comparator is used to generate the A-th digital code D according to the comparison result of the voltage at the positive terminal and the voltage at the negative terminal of the comparator. A , A is an integer from 0 to N-1, and N is an integer greater than 1; The input end of the SAR logic circuit (1) is connected to the output end of the comparator, and the output end is connected to the high-end DAC PH , low-end DAC PL , high-end DAC NH and low-end DAC NL The SAR logic circuit (1) is used to generate a digital code D according to the A-th bit. A The value controls the high-segment DAC PH , low-end DAC PL , high-end DAC NH and low-end DAC NL The connection voltage of the bottom plate; It is characterized in that The steps include: Step 1, sampling stage; The input signal V IN Connect the positive end split capacitor array to the high-end DAC PH and low-end DAC PL top plate, high-end DAC PH and low-end DAC PL The bottom plates of the IN Connect the negative end of the split capacitor array to the high-end DAC NH and low-end DAC NL bottom plate, high-end DAC NH and low-end DAC NL The top plate is connected to the reference voltage V REF ; Step 2: Maintaining stage; The positive sampling switch (21) and the negative sampling switch (22) are disconnected, and the high-end DAC PH , low-end DAC PL The bottom plates are connected to the reference voltage V REF and GND, high-end DAC NH , low-end DAC NL The bottom plate is connected to GND and the reference voltage V REF ; Step 3: Conversion phase; The comparator compares the voltage at its positive terminal with the voltage at its negative terminal to generate the A-bit digital code D. A , output to the SAR logic circuit (1), which then generates the A-th digital code D A The value controls the high-segment DAC PH , low-end DAC PL , high-end DAC NH and low-end DAC NL The connection voltage of the bottom plate.

2. The capacitor array switching method of a single-ended input SAR ADC with two levels and stable common mode point according to claim 1, characterized in that: Its working phases are sampling phase, holding phase and conversion phase in sequence; During the sampling phase, the high-segment DAC PH and low-end DAC PL The bottom plates are connected to GND, and the top plates are connected to the input voltage V IN , the high-segment DAC NH and low-end DAC NL The bottom plates are connected to the input signal V IN , the top plate is connected to the reference voltage V REF ; During the hold phase, the high-segment DAC PH and low-end DAC PL The bottom plates are connected to the reference voltage V REF and GND, the high-segment DAC NH and low-end DAC NL The bottom plate is connected to GND and the reference voltage V REF ; In the conversion phase, the A-th digital code D A When the value is 1, the high-segment DAC PH The bottom plate of the corresponding capacitor is connected to GND, the high-end DAC NH The bottom plate of the corresponding capacitor is connected to the reference voltage V REF ; The A-th digit code D A The value is 0, the low-segment DAC PL The bottom plate of the corresponding capacitor is connected to the reference voltage V REF , the low-segment DAC NL The bottom plate of the corresponding capacitor is connected to GND.

3. The capacitor array switching method of a single-ended input SAR ADC with two levels and stable common mode point according to claim 1 or 2, characterized in that: The high-end DAC PH , low-end DAC PL , high-end DAC NH and low-end DAC NL Both include 2 in parallel N-1 A capacitor.

4. The capacitor array switching method of a single-ended input SAR ADC with two levels and stable common mode point according to claim 1, characterized in that: The step 3 is specifically as follows: Step 3.1, compare the highest bit; The comparator compares the voltage at its positive terminal with the voltage at its negative terminal to generate the N-1th digital code D. N-1 SAR logic circuit (1) determines the N-1th digital code D N-1 If the value of D N-1 =1, then execute step 3.1.

1. If D N-1 =0, then execute step 3.1.2; Step 3.1.1, the SAR logic circuit (1) sets the high-end DAC PH The bottom plate of the highest capacitor is connected to GND, which reduces the output voltage of the positive end split capacitor array The SAR logic circuit (1) converts the high-end DAC NH The bottom plate of the highest capacitor is connected to the reference voltage V REF , so that the output voltage of the negative split capacitor array increases The common mode point remains stable during this process; Step 3.1.2: The SAR logic circuit (1) sets the low-end DAC PL The bottom plate of the highest capacitor is connected to the reference voltage V REF , so that the output voltage of the positive split capacitor array increases The SAR logic circuit (1) converts the low-end DAC NL The bottom plate of the highest capacitor is connected to GND, which reduces the output voltage of the negative split capacitor array. The common mode point remains stable during this process; Step 3.2, compare the second highest position; The comparator compares the voltage at its positive terminal with the voltage at its negative terminal to generate the N-2 digit digital code D. N-2 SAR logic circuit (1) determines the N-2 digit code D N-2 If the value of D N-2 =1, then execute step 3.2.

1. If D N-2 =0, then execute step 3.2.2; Step 3.2.

1. The SAR logic circuit (1) sets the high-end DAC PH The bottom plate of the second highest capacitor is connected to GND, which reduces the output voltage of the positive end split capacitor array. The SAR logic circuit (1) converts the high-end DAC NH The bottom plate of the second highest capacitor is connected to the reference voltage V REF , so that the output voltage of the negative split capacitor array increases The common mode point remains stable during this process; Step 3.2.2: The SAR logic circuit (1) sets the low-end DAC PL The bottom plate of the second highest capacitor is connected to the reference voltage V REF , so that the output voltage of the positive split capacitor array increases The SAR logic circuit (1) converts the low-end DAC NL The bottom plate of the second highest capacitor is connected to GND, which reduces the output voltage of the negative split capacitor array. The common mode point remains stable during this process; Step 3.3, successive approximation; Follow the method of step 3.1 and step 3.2 to perform successive approximation until the output D N-1 D N-2 ...N-digit digital code of D1D0.

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