Display panel, manufacturing method thereof, and display device

Abstract

A display panel and a manufacturing method thereof, and a display device, wherein the display panel includes a first substrate and a second substrate. The first substrate includes a base substrate and a plurality of data lines, a plurality of gate lines and a semiconductor layer located on the base substrate. A plurality of spacers are provided on the side of the second substrate facing the first substrate. The first substrate includes a plurality of transfer structures and a plurality of support structures, at least part of the support structures of the plurality of support structures being configured to contact at least part of the spacers of the plurality of spacers, and the orthographic projections of at least part of the spacers on the base substrate overlap with the orthographic projections of at least part of the support structures on the base substrate and the orthographic projections of at least part of the transfer structures on the base substrate. The transfer structure provided on the same layer as the gate lines on the first substrate can raise the support structure that overlaps with the transfer structure in a direction perpendicular to the first substrate, while ensuring that the raised support structure and the spacers can reliably support the box thickness, and at the same time, try to maintain the flatness of the support structure.

Description

[0001] This application claims priority to Chinese patent application No. 202211485025.6 filed on November 24, 2022, and the contents of the above-mentioned Chinese patent application disclosure are hereby cited in their entirety as part of this application. Technical Field

[0002] At least one embodiment of the present disclosure relates to a display panel, a manufacturing method thereof, and a display device. Background Art

[0003] Liquid crystal displays (LCDs), as one of the most popular display devices, offer advantages such as fast response speed, high integration, and low power consumption. Typically, in an LCD panel, an array substrate and a counter substrate are aligned to form a liquid crystal cell, which is filled with a liquid crystal layer. To ensure uniformity in the cell gap across all locations, a post spacer (PS) is placed between the array substrate and the counter substrate, maintaining a stable cell gap across the LCD panel. Summary of the Invention

[0004] At least one embodiment of the present disclosure provides a display panel, comprising: a first substrate, comprising a base substrate and a plurality of data lines, a plurality of gate lines, and a semiconductor layer located on the base substrate, wherein the plurality of gate lines are located on a side of the plurality of data lines away from the base substrate, the plurality of data lines are arranged along a first direction, the plurality of gate lines are arranged along a second direction, and the second direction intersects the first direction; a second substrate, disposed opposite to the first substrate, wherein a plurality of spacers are disposed on a side of the second substrate facing the first substrate, wherein the semiconductor layer is located between the layer where the plurality of data lines are located and the layer where the plurality of gate lines are located, and the semiconductor layer is located between the layer where the plurality of data lines are located and the layer where the plurality of gate lines are located. The body layer includes a channel region pattern of the transistor, a first doping region pattern, and a second doping region pattern; the first substrate also includes a plurality of transfer structures and a plurality of support structures, the plurality of transfer structures are arranged in the same layer as the plurality of gate lines, and at least one data line is electrically connected to the first doping region pattern through at least one transfer structure; at least part of the support structures of the plurality of support structures are configured to support at least part of the spacers of the plurality of spacers, and the orthographic projection of at least part of the spacers on the base substrate overlaps with the orthographic projection of at least part of the support structure on the base substrate, and the orthographic projection of at least part of the transfer structure on the base substrate. By overlapping the support structure on the first substrate with at least part of the spacers on the second substrate in a direction perpendicular to the first substrate, the support structure can be configured to support at least part of the spacers; at the same time, the transfer structure arranged in the same layer as the gate lines on the first substrate can raise the support structure that overlaps with the transfer structure in a direction perpendicular to the first substrate, thereby ensuring that the raised support structure and spacers can reliably support the box thickness while maintaining the flatness of the support structure as much as possible.

[0005] For example, according to an embodiment of the present disclosure, an orthographic projection of at least part of the spacer on the base substrate overlaps with an orthographic projection of the first doping region pattern on the base substrate.

[0006] For example, according to an embodiment of the present disclosure, an orthographic projection of at least part of the spacer on the base substrate overlaps with at least one of the channel region pattern of the transistor and the second doping region pattern.

[0007] For example, according to an embodiment of the present disclosure, at least one supporting structure extends along the extension direction of the data line, at least one spacer extends along the extension direction of the gate line, and the orthographic projection of the at least one spacer on the base substrate overlaps with the orthographic projection of at least two supporting structures on the base substrate.

[0008] For example, according to an embodiment of the present disclosure, the orthographic projection of at least one supporting structure on the base substrate completely falls within the orthographic projection of the data line on the base substrate.

[0009] For example, according to an embodiment of the present disclosure, the first substrate also includes a plurality of first light-shielding portions, which are arranged in the same layer as the plurality of data lines and overlap with the channel region pattern in a direction perpendicular to the base substrate; wherein the orthographic projection of at least part of the spacer on the base substrate overlaps with at least one first light-shielding portion.

[0010] For example, according to an embodiment of the present disclosure, the first substrate further includes a plurality of sub-pixels, each sub-pixel includes a pixel electrode and a common electrode, and the pixel electrode is electrically connected to the second doping region pattern.

[0011] For example, according to an embodiment of the present disclosure, the multiple spacers include at least one first sub-spacer and at least one second sub-spacer; the size of the at least one first sub-spacer in the first direction is greater than or equal to the pitch of two adjacent sub-pixels in the first direction, and / or the size of the at least one second sub-spacer in the first direction is greater than or equal to the pitch of two adjacent sub-pixels in the first direction.

[0012] For example, according to an embodiment of the present disclosure, the multiple spacers also include at least one second sub-spacer; the at least one second sub-spacer is spaced apart from the at least one first sub-spacer; the ratio of the number of the first sub-spacers to the number of the sub-pixels is a first ratio, the ratio of the number of the second sub-spacers to the number of the sub-pixels is a second ratio, and the sum of the first ratio and the second ratio is less than 1.

[0013] For example, according to an embodiment of the present disclosure, the at least one second sub-spacer includes a plurality of second sub-spacers, the orthographic projections of at least part of the second sub-spacers on the base substrate do not overlap with the orthographic projections of the plurality of supporting structures on the base substrate, and the size of at least part of the second sub-spacers in a direction perpendicular to the base substrate is greater than the size of the at least one first sub-spacer in a direction perpendicular to the base substrate.

[0014] For example, according to an embodiment of the present disclosure, the at least one second sub-spacer includes a plurality of second sub-spacers, the orthographic projections of at least part of the second sub-spacers on the base substrate overlap with the orthographic projections of the plurality of supporting structures on the base substrate, and the size of at least part of the second sub-spacers in a direction perpendicular to the base substrate is smaller than the size of the at least one first sub-spacer in a direction perpendicular to the base substrate.

[0015] For example, according to an embodiment of the present disclosure, the first ratio is 1 / 5 to 2 / 5; and / or the second ratio is 1 / 5 to 2 / 5.

[0016] For example, according to an embodiment of the present disclosure, a plane perpendicular to the second direction is a reference plane, and an orthographic projection of the first sub-spacer on the reference plane and an orthographic projection of the second sub-spacer on the reference plane at least partially do not overlap.

[0017] For example, according to an embodiment of the present disclosure, the at least one first sub-spacer includes a plurality of first sub-spacer rows, each first sub-spacer row includes a plurality of first sub-spacers arranged along the first direction, the at least one second sub-spacer includes a plurality of second sub-spacer rows, each second sub-spacer row includes the plurality of second sub-spacers arranged along the first direction, the plurality of first sub-spacer rows and the plurality of second sub-spacer rows are alternately arranged along the second direction, and the adjacent first sub-spacer rows and the second sub-spacer rows are staggered in the first direction.

[0018] For example, according to an embodiment of the present disclosure, at least one supporting structure includes a supporting portion and a second light-shielding portion that are stacked, and the second light-shielding portion is located between the supporting portion and the base substrate; the orthographic projection of the supporting portion on the base substrate completely falls within the orthographic projection of the second light-shielding portion on the base substrate, and the size of the supporting portion in a direction perpendicular to the base substrate is larger than the size of the second light-shielding portion in a direction perpendicular to the base substrate.

[0019] For example, according to an embodiment of the present disclosure, the second light shielding portion includes a conductive material, and / or the supporting portion and the second light shielding portion both include a conductive material and are electrically connected to each other; the second light shielding portion is electrically connected to the common electrode.

[0020] At least one embodiment of the present disclosure provides a display panel, comprising: a first substrate, comprising a base substrate and a plurality of data lines and a plurality of gate lines located on the base substrate, the plurality of gate lines being located on a side of the plurality of data lines facing the base substrate, the plurality of data lines being arranged along a first direction, the plurality of gate lines being arranged along a second direction, the second direction intersecting with the first direction; a second substrate, arranged opposite to the first substrate, a plurality of spacers being provided on a side of the second substrate facing the first substrate, wherein the first substrate further comprises a plurality of supporting structures, the plurality of supporting structures being configured to support at least part of the plurality of spacers, at least part of the plurality of supporting structures extending along an extension direction of the data lines and being electrically connected to the data lines, and an orthographic projection of at least part of the plurality of supporting structures on the base substrate being completely within an orthographic projection of the data lines on the base substrate. By overlapping the support structure on the first substrate and at least part of the spacer on the second substrate in a direction perpendicular to the first substrate, the support structure can be configured to support at least part of the spacer; the support structure electrically connected to the data line can also reduce the routing resistance of the data line; at the same time, the orthographic projection of at least part of the support structure on the base substrate is completely covered by the orthographic projection of the data line on the base substrate, so that the data line can both raise the support structure and maintain the flatness of the support structure as much as possible, and also shield the support structure from light; in addition, the support structure extends along the extension direction of the data line, which makes it easy to produce a support structure with a smaller size in the first direction, thereby making it easy to reduce the size of other film layer structures and increase the aperture ratio.

[0021] For example, according to an embodiment of the present disclosure, the multiple spacers include a plurality of first sub-spacers and a plurality of second sub-spacers, the orthographic projections of the multiple first sub-spacers on the base substrate overlap with the orthographic projections of the multiple supporting structures on the base substrate, and the orthographic projections of the multiple second sub-spacers on the base substrate overlap with the orthographic projections of the multiple supporting structures on the base substrate, and the size of at least part of the second sub-spacers in the direction perpendicular to the base substrate is smaller than the size of at least one first sub-spacer in the direction perpendicular to the base substrate.

[0022] At least one embodiment of the present disclosure provides a display device including the above-mentioned display panel.

[0023] At least one embodiment of the present disclosure provides a method for forming the aforementioned display panel, comprising: forming the first substrate and the second substrate that are relatively arranged, wherein forming the first substrate comprises: providing the base substrate; sequentially forming the multiple data lines, the semiconductor layer, and the multiple gate lines and the multiple transfer structures arranged on the same layer on the base substrate; forming the multiple support structures on the side of the multiple transfer structures away from the base substrate, each support structure comprising a stacked light-shielding portion and a supporting portion, the orthographic projection of the supporting portion on the base substrate being completely within the orthographic projection of the light-shielding portion on the base substrate, wherein forming the multiple support structures comprises: forming a stacked first material layer and a second material layer, the first material layer being located between the second material layer and the base substrate; forming a mask template on the side of the second material layer away from the first material layer; wet-etching the second material layer using the mask template as a mask to form the supporting portion; and dry-etching the first material layer using the mask template as a mask to form the light-shielding portion. By fabricating the support portion so that its orthographic projection on the base substrate lies completely within the orthographic projection of the light-shielding portion, the support portion is fully shielded, enhancing the light-shielding effect of the light-shielding portion on the support portion and reducing the risk of light leakage. Furthermore, through a single masking process, the support portion is formed by wet etching the second material layer and the light-shielding portion is formed by dry etching the first material layer, reducing the impact of overlap offset during the manufacturing process. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are merely embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without any creative work.

[0025] Figure 1 A schematic structural diagram of a display panel provided in at least one embodiment of the present disclosure.

[0026] Figure 2 A schematic diagram of a partial planar structure of a display panel provided as an example in an embodiment of the present disclosure.

[0027] Figure 3 A schematic diagram of a partially enlarged structure in a display panel provided as an example in an embodiment of the present disclosure.

[0028] Figures 4A to 4H for Figure 3 Schematic diagram of the different film layers in the display panel.

[0029] Figure 5 To include Figures 4A to 4H Structural diagram of the stacked arrangement of the various film layers shown.

[0030] Figure 6 A schematic diagram of a partial planar structure of a display panel provided according to an example of the present disclosure.

[0031] Figure 7 The figure is a schematic structural diagram of a display panel provided according to another example of an embodiment of the present disclosure.

[0032] Figure 8 For the Figure 2 The cross-sectional structure diagram of the display panel taken along line AA' is shown.

[0033] Figure 9 For the Figure 2 The cross-sectional structure diagram of the display panel taken along line BB' is shown.

[0034] Figure 10 For the Figure 2 The cross-sectional structure diagram of the display panel taken along line CC' is shown.

[0035] Figure 11-13 Schematic diagram of a partial planar structure of a display panel provided according to different examples of the embodiments of the present disclosure.

[0036] Figure 14 A structural schematic diagram of a display panel provided as another example of an embodiment of the present disclosure.

[0037] Figure 15 A schematic diagram of a partially enlarged structure in a display panel according to another example provided in an embodiment of the present disclosure.

[0038] Figure 16 A schematic diagram of a partially enlarged structure in a display panel according to another example provided in an embodiment of the present disclosure.

[0039] Figure 17 An electron microscope image of the support structure in the display panel provided in an embodiment of the present disclosure.

[0040] Figure 18 This is an electron microscope image of the spacers in the display panel provided in an embodiment of the present disclosure.

[0041] Figure 19 A schematic structural diagram of a display panel provided in another embodiment of the present disclosure.

[0042] Figures 20A to 20E Schematic cross-sectional view of the steps of making a support structure according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0043] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0044] Unless otherwise defined, technical or scientific terms used in this disclosure should have the ordinary meanings understood by people with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are simply used to distinguish different components. The words "include" or "comprising" and similar terms mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0045] The features such as "perpendicular", "parallel" and "same" used in the embodiments of the present disclosure include the features such as "perpendicular", "parallel" and "same" in the strict sense, as well as the cases where "approximately perpendicular", "approximately parallel" and "approximately the same" contain certain errors, taking into account the errors associated with the measurement and the measurement of specific quantities (that is, the limitations of the measurement system), and are expressed as being within the acceptable deviation range for a specific value determined by a person of ordinary skill in the art. The "center" in the embodiments of the present disclosure can include a position strictly at the geometric center and a position approximately at the center of a small area around the geometric center. For example, "approximately" can mean within one or more standard deviations, or within 10% or 5% of the value.

[0046] When the number of a component is not specifically indicated in the following text of the embodiments of the present disclosure, it means that the component can be one or more, or can be understood as at least one. "At least one" refers to one or more, and "more" refers to at least two. The "same-layer arrangement" referred to in the present disclosure refers to a structure in which two (or more) structures are formed by the same deposition process and patterned by the same composition process, and their materials may be the same or different. The "integrated arrangement structure" in the present disclosure refers to a structure in which two (or more) structures are formed by the same deposition process and patterned by the same composition process to be connected to each other, and their materials may be the same or different.

[0047] With increasing market demand for ultra-high pixel density (PPI) liquid crystal displays (LCDs), the need for color filter substrates (CFs) is growing. This is driving higher resolution requirements for color filter substrates (CFs). In addition to meeting the support requirements for LCD cell assembly, the spacers on CF substrates must also be as small as possible to avoid sacrificing aperture ratio.

[0048] To ensure the LCD's cell thickness, gap strength, and liquid crystal margin (LC Margin), spacers must maintain a specific size and distribution ratio. To prevent abnormal alignment of the liquid crystal molecules around the spacers and to prevent visible light leakage around the spacers due to relative displacement between the two opposing substrates, the black matrix on the color filter substrate needs to be increased around the spacers to compensate.

[0049] During the research, the inventors of this application found that the size of the spacers is difficult to reduce further due to the limitations of the spacer material, process capabilities, and high uniformity. At the same time, the pixel pitch of ultra-high PPI (for example, PPI greater than or equal to 2000) is extremely small, and the impact of the spacer size on the aperture ratio is becoming increasingly prominent. The inventors of this application also found that when trying to make smaller high-precision spacers, the flatness of the spacer surface is difficult to guarantee, making it difficult to maintain the uniformity of the box thickness.

[0050] At least one embodiment of the present disclosure provides a display panel comprising a first substrate and a second substrate disposed opposite the first substrate. The first substrate comprises a base substrate, and a plurality of data lines, a plurality of gate lines, and a semiconductor layer located on the base substrate, the plurality of gate lines being located on a side of the plurality of data lines away from the base substrate, the plurality of data lines being arranged along a first direction, the plurality of gate lines being arranged along a second direction intersecting the first direction; and a plurality of spacers being disposed on a side of the second substrate facing the first substrate. The semiconductor layer is located between the layer where the multiple data lines are located and the layer where the multiple gate lines are located, and the semiconductor layer includes a channel region pattern, a first doping region pattern and a second doping region pattern of the transistor; the first substrate also includes a plurality of transfer structures and a plurality of support structures, the plurality of transfer structures are arranged in the same layer as the multiple gate lines, and at least one data line is electrically connected to the first doping region pattern through at least one transfer structure; at least part of the support structures are configured to support at least part of the multiple spacers, and the orthographic projection of at least part of the spacers on the base substrate overlaps with the orthographic projection of at least part of the support structure on the base substrate and the orthographic projection of at least part of the transfer structure on the base substrate. By overlapping the support structure on the first substrate and at least part of the spacer on the second substrate in a direction perpendicular to the first substrate, the support structure can be configured to support at least part of the spacer; at the same time, the transfer structure arranged on the same layer as the gate line on the first substrate can raise the support structure overlapping with the transfer structure in a direction perpendicular to the first substrate, thereby ensuring that the raised support structure and the spacer can reliably support the box thickness while maintaining the flatness of the support structure as much as possible.

[0051] At least one embodiment of the present disclosure provides a method for forming the above-mentioned display panel, comprising: forming the first substrate and the second substrate that are relatively arranged, wherein forming the first substrate comprises: providing the base substrate; sequentially forming the multiple data lines, the semiconductor layer, and the multiple gate lines and the multiple transfer structures arranged on the same layer on the base substrate; forming the multiple supporting structures on the side of the multiple transfer structures away from the base substrate, each supporting structure comprising a light-shielding portion and a supporting portion that are stacked, the orthographic projection of the supporting portion on the base substrate being completely within the orthographic projection of the light-shielding portion on the base substrate, wherein forming the multiple supporting structures comprises: forming a first material layer and a second material layer that are stacked, the first material layer being located between the second material layer and the base substrate; forming a mask template on the side of the second material layer away from the first material layer; wet-etching the second material layer using the mask template as a mask to form the support portion; and dry-etching the first material layer using the mask template as a mask to form the light-shielding portion. By fabricating the support portion so that its orthographic projection on the substrate lies completely within the orthographic projection of the light-shielding portion, the support portion is fully shielded, enhancing the light-shielding effect of the light-shielding portion on the support portion and reducing the risk of light leakage. Furthermore, through a single mask process, the support portion is wet-etched on the second material layer and the light-shielding portion is dry-etched on the first material layer, reducing the impact of overlap in the manufacturing process.

[0052] At least one embodiment of the present disclosure provides another display panel, comprising: a first substrate, comprising a base substrate and a plurality of data lines and a plurality of gate lines located on the base substrate, the plurality of gate lines being located on a side of the plurality of data lines facing the base substrate, the plurality of data lines being arranged along a first direction, the plurality of gate lines being arranged along a second direction, the second direction intersecting with the first direction; a second substrate, arranged opposite to the first substrate, a plurality of spacers being provided on a side of the second substrate facing the first substrate, wherein the first substrate further comprises a plurality of supporting structures, the plurality of supporting structures being configured to support at least part of the plurality of spacers, at least part of the plurality of supporting structures extending along an extension direction of the data lines and being electrically connected to the data lines, and an orthographic projection of at least part of the plurality of supporting structures on the base substrate being completely within an orthographic projection of the data lines on the base substrate. By overlapping the support structure on the first substrate and at least part of the spacer on the second substrate in a direction perpendicular to the first substrate, the support structure can be configured to support at least part of the spacer; the support structure electrically connected to the data line can also reduce the routing resistance of the data line; at the same time, the orthographic projection of at least part of the support structure on the base substrate is completely covered by the orthographic projection of the data line on the base substrate, so that the data line can both raise the support structure and maintain the flatness of the support structure as much as possible, and also shield the support structure from light; in addition, the support structure extends along the extension direction of the data line, which makes it easy to produce a support structure with a smaller size in the first direction, thereby making it easy to reduce the size of other film layer structures and increase the aperture ratio.

[0053] The display panel, the manufacturing method thereof, and the display device provided by the present disclosure are described below with reference to the accompanying drawings and through some embodiments.

[0054] Figure 1 A schematic structural diagram of a display panel provided in at least one embodiment of the present disclosure.

[0055] like Figure 1 As shown, at least one embodiment of the present disclosure provides a display panel, including a first substrate 100 and a second substrate 200. The first substrate 100 includes a base substrate 110 and a plurality of data lines 120, a plurality of gate lines 130 and a semiconductor layer 140 located on the base substrate 110. For example, the first substrate 100 is an array substrate. For example, the second substrate 200 is an opposing substrate, and the opposing substrate is, for example, a color filter substrate. For example, a liquid crystal layer (not shown in the figure) is sandwiched between the first substrate 100 and the second substrate 200. For example, at least one surface of the first substrate 100 and the second substrate 200 facing each other is further provided with an alignment film (not shown in the figure), and the alignment film aligns the liquid crystals in the liquid crystal layer.

[0056] Figure 2This is a schematic diagram of a partial planar structure of a display panel provided as an example in an embodiment of the present disclosure. Figure 2 , and combined with Figure 1 , multiple gate lines 130 are located on a side of the multiple data lines 120 away from the base substrate 110, the multiple data lines 120 are arranged along a first direction x, and the multiple gate lines 130 are arranged along a second direction y, and the second direction y intersects with the first direction x. For example, the first substrate 100 also includes multiple sub-pixels 180, each sub-pixel 180 includes a pixel electrode 181 and a common electrode 182. For example, the multiple data lines 120 and the multiple gate lines 130 are insulated and cross-arranged to define the multiple sub-pixels 180. For example, the pixel electrodes 181 in different sub-pixels 180 are insulated from each other. For example, the common electrode 182 and the pixel electrode 181 can be made of a transparent conductive material. For example, the material of the common electrode 182 and the pixel electrode 181 can include indium tin oxide (ITO). For example, the common electrode 182 can be located on a side of the pixel electrode 181 away from the base substrate.

[0057] For example, the plurality of sub-pixels 180 are arranged in an array along a first direction x and a second direction y, and the first direction x intersects the second direction y. Figure 2 The first direction is schematically shown as the x-direction and the second direction is the y-direction, but this is not limiting. The first and second directions can be interchangeable. For example, the first direction x is perpendicular to the second direction y. However, the angle between the first and second directions can be 80 to 100 degrees, such as 85 to 95 degrees. For example, the area where the multiple sub-pixels are located is a display area for displaying an image, and the first substrate may also include a peripheral area surrounding the display area.

[0058] Figure 3 This is a schematic diagram of a partially enlarged structure of a display panel provided as an example in an embodiment of the present disclosure. It should be noted that: Figure 3 The display panel shown in FIG can be used with Figure 1 or Figure 2 The display panels shown are display panels of the same example, or they may be display panels of different examples. It is understandable that Figure 1 and Figure 2 The positional relationship between the film layers is only schematically shown and is not intended to limit Figure 3 The display panel shown. Similarly, Figure 3 The positional relationship between the film layers shown can also be applied to Figure 1 or Figure 2 The present disclosure is not limited to the display panel shown.

[0059] Combine Figure 1 and Figure 3As shown, the second substrate 200 is arranged opposite to the first substrate 100, and a plurality of spacers 210 (Photo Spacer, PS) are provided on the side of the second substrate 200 facing the first substrate 100. The semiconductor layer 140 is located between the layer where the plurality of data lines 120 are located and the layer where the plurality of gate lines 130 are located. The semiconductor layer 140 includes a channel region pattern 141 of the transistor, a first doping region pattern 142 and a second doping region pattern 143.

[0060] For example, the transistors used in the embodiments of the present disclosure may all be thin film transistors or field effect transistors or other switching devices with the same characteristics. The embodiments of the present disclosure are all described by taking thin film transistors as an example. A thin film transistor includes a gate, a source, and a drain. The source and drain of the thin film transistor used here may be symmetrical in structure, so the source and drain may be structurally indistinguishable. For example, the gate of the thin film transistor overlaps with the channel region pattern 141 in the semiconductor layer 140. For example, one of the source and drain of the thin film transistor overlaps with the first doping region pattern 142, and the other overlaps with the second doping region pattern 143.

[0061] like Figure 1 and Figure 3 As shown, the first substrate 100 further includes a plurality of transfer structures 150 and a plurality of support structures 160. The plurality of transfer structures 150 are disposed on the same layer as the plurality of gate lines 130, and at least one data line 120 is electrically connected to the first doped region pattern 142 via at least one transfer structure 150. For example, the data line 120 is electrically connected to one of the source and drain electrodes of the thin film transistor via the transfer structure 150.

[0062] For example, the pixel electrode 181 is electrically connected to the second doped region pattern 143. For example, the pixel electrode 181 is electrically connected to the other of the source and drain electrodes of the thin film transistor. For example, the gate line 130 is electrically connected to the gate electrode of the thin film transistor to control the on or off of the thin film transistor, the pixel electrode 181 is electrically connected to one of the source and drain electrodes of the thin film transistor, and the data line 120 is electrically connected to the other of the source and drain electrodes of the thin film transistor. The data line 120 inputs the voltage signal required for displaying the image to the pixel electrode 181 through the thin film transistor to realize the display of the display panel.

[0063] like Figure 1As shown, at least some of the multiple support structures 160 are configured to support at least some of the spacers 210 of the multiple spacers 210, and the orthographic projections of at least some of the spacers 210 on the base substrate 110 overlap with the orthographic projections of at least some of the support structures 160 on the base substrate 110, as well as the orthographic projections of at least some of the transition structures 150 on the base substrate 110. It is understood that the term "at least some" in this disclosure refers to at least some of the structures when there are multiple structures. For example, if there are multiple support structures 160, at least some of the support structures 160 refers to more than one support structure 160, or it may refer to all of the multiple support structures 160.

[0064] By overlapping the support structure 160 on the first substrate 100 and at least part of the spacer 210 on the second substrate 200 in a direction perpendicular to the first substrate 100, the support structure 160 can support at least part of the spacer 210; at the same time, the transfer structure 150 arranged on the same layer as the gate line 130 on the first substrate 100 can raise the support structure 160 overlapping with the transfer structure 150 in a direction perpendicular to the first substrate 100, thereby ensuring that the raised support structure 160 and the spacer 210 can reliably support the box thickness while maintaining the flatness of the support structure 160 as much as possible.

[0065] refer to Figure 1 and Figure 3 For example, the first substrate 100 further includes a plurality of first light shielding portions 170, which are disposed in the same layer as the plurality of data lines 120 and overlap the channel pattern 141 in a direction perpendicular to the base substrate 110. The first light shielding portions 170, which are disposed in the same layer as the data lines 120, can shield the channel pattern 141 from light, thereby reducing the risk of light leakage.

[0066] refer to Figure 3 For example, the orthographic projection of at least a portion of the spacer 210 on the base substrate 110 overlaps with at least one first light shielding portion 170. In this way, the first light shielding portion 170 can shield the spacer 210 from light while shielding the channel region pattern 141. In addition, in conjunction with some examples described later, when the black matrix 220 shields the spacer 210 from light, the shielding of the spacer 210 by the first light shielding portion 170 can reduce the size of the black matrix 220 in the second direction y, thereby increasing the aperture ratio.

[0067] Figures 4A to 4H for Figure 3 Schematic diagram of the different film layers in the display panel. Figure 5 To include Figures 4A to 4H The structure diagram of the stacking arrangement of each film layer is shown. Figure 3 It is understandable that Figures 4A to 5Can also be with Figure 1 or Figure 2 The display panels shown are display panels of the same example or different examples. Figures 4A to 5 The coatings shown can also be applied to Figure 1 or Figure 2 The display panel shown is not limited in this disclosure.

[0068] Figure 4A The film layer where the data line 120 and the first light shielding portion 170 are located is shown. Figure 1 、 Figure 4A and Figure 5 For example, the first substrate 100 further includes a buffer layer 101 (Buffer), and the buffer layer 101 covers the data line 120 and the first light shielding portion 170 .

[0069] Figure 4B The film layer where the semiconductor layer 140 is located is shown. Figure 4C A first via hole 190 a and a second via hole 190 b in the gate insulating layer 190 are shown. Figure 4D The film layer where the gate line 130 is located is shown.

[0070] refer to Figure 1 、 Figure 4B and Figure 5 For example, the first substrate 100 further includes a first insulating layer 102 stacked on the side of the buffer layer 101 away from the base substrate 110. For example, the first insulating layer 102 is a first passivation layer (PVX1). Figure 4D As shown, the semiconductor layer 140 and the transfer structure 150 are formed on the buffer layer 101 , the gate line 130 is formed on the side of the semiconductor layer 140 away from the buffer layer 101 , and the first insulating layer 102 covers the surface of the transfer structure 150 and the gate line 130 away from the buffer layer 101 .

[0071] Combine Figure 1 、 Figure 4C and Figure 5 As shown, for example, a gate insulating layer 190 is further provided between the gate line 130 and the semiconductor layer 140. For example, a gate insulating layer 190 is also provided between the transfer structure 150 and the buffer layer 101. For example, the gate insulating layer 190 includes a first via hole 190a and a second via hole 190b. The transfer structure 150 is electrically connected to the data line 120 through the first via hole 190a, and a portion of the pixel electrode 181 is electrically connected to the semiconductor layer 140 through the second via hole 190b.

[0072] For example, reference Figure 1 The buffer layer 101 includes a third via hole 101 a , and a portion of the transfer structure 150 passes through the third via hole 101 a , thereby achieving electrical connection between the transfer structure 150 and the first doping region pattern 142 .

[0073] Figure 4E The film layer where the second sub-via hole 103 a is located on the planarization layer 103 is shown. Figure 4F The film layer where the fourth via hole 182 a on the common electrode 182 is located is shown. Figure 4G FIG4 shows the film layer where the third sub-via hole 104a is located on the second insulating layer 104. FIG4h shows the film layer where the pixel electrode 181 is located.

[0074] Combine Figure 1 and Figure 5 As shown, for example, in combination with some of the aforementioned examples, the first substrate 100 further includes a planarization layer 103 and a second insulating layer 104, which are sequentially stacked on a side of the first insulating layer 102 away from the buffer layer 101 in a direction perpendicular to the base substrate 110. The second insulating layer 104 is, for example, a second passivation layer (PVX2).

[0075] Combine Figure 1 、 Figure 4F and Figure 5 As shown, for example, the common electrode 182 is formed on the planarization layer 103, the second insulating layer 104 covers the surface of the common electrode 182 on a side away from the planarization layer 103, and the pixel electrode 181 is located on a side of the second insulating layer 104 away from the planarization layer 103. For example, the common electrode 182 includes a fourth via hole 182 a, and the fourth via hole 182 a avoids the pixel electrode 181 so that a portion of the pixel electrode 181 can be electrically connected to the semiconductor layer 140.

[0076] Combine Figure 1 as well as Figures 4D to 5 As shown, for example, the first insulating layer 102 includes a first sub-via 102a, the planarization layer 103 includes a second sub-via 103a, and the second insulating layer 104 includes a third sub-via 104a. The orthographic projections of the first sub-via 102a, the second sub-via 103a, and the third sub-via 104a on the base substrate 110 all overlap with the orthographic projections of the second doping region pattern 143 on the base substrate 110. For example, a straight line perpendicular to the base substrate 110 passes through the first sub-via 102a, the second sub-via 103a, and the third sub-via 104a, thereby forming a trepanation hole by the first sub-via 102a, the second sub-via 103a, and the third sub-via 104a. In this way, a portion of the structure of the pixel electrode 181 is electrically connected to the second doping region pattern 143 through the first sub-via 102a, the second sub-via 103a, and the third sub-via 104a.

[0077] like Figure 4HAs shown, the pixel electrode 181 includes a first domain 1811 and a second domain 1812. The first domain 1811 and the second domain 1812 are axially symmetrical about the area bisector of the pixel electrode 181 in the first direction x, thereby providing the pixel electrode 181 with a high degree of symmetry. For example, the first domain 1811 and the second domain 1812 are sequentially arranged along the second direction y. By arranging the pixel electrode 181 into the first domain 1811 and the second domain 1812, the first substrate 100 can reduce color shift and improve display quality. For example, the pixel electrode 181 includes a plurality of spaced first slits 1813 located in the first domain 1811. For example, the pixel electrode 181 includes a plurality of spaced second slits 1814 located in the second domain 1812.

[0078] refer to Figure 3 For example, at least a portion of the orthographic projection of the spacer 210 on the base substrate 110 overlaps with the orthographic projection of the first doped region pattern 142 on the base substrate 110. In this way, the first doped region pattern 142 and the transfer structure 150 are electrically connected and can both raise the support structure 160, thereby making the surface of the support structure 160 configured to support the spacer 210 more flat.

[0079] For example, the orthographic projection of at least part of the spacer 210 on the base substrate 110 overlaps with at least one of the channel region pattern 141 and the second doping region pattern 143 of the transistor. For example, the orthographic projection of the spacer 210 on the base substrate 110 overlaps with the channel region pattern 141 of the transistor and overlaps with the second doping region pattern 143. In combination with some examples described later, when the spacer 210, the channel region pattern 141 and the second doping region pattern 143 are shielded by the black matrix 220, the orthographic projection of the spacer 210 on the base substrate 110, the channel region pattern 141 and the second doping region pattern 143 are set to overlap, which can reduce the area that the black matrix 220 needs to block. In this way, the size of the black matrix 220 in the second direction y can be reduced, thereby increasing the aperture ratio.

[0080] Combine Figures 1 to 3As shown, for example, at least one support structure 160 extends along the extension direction of the data line 120, and at least one spacer 210 extends along the extension direction of the gate line 130. The extension direction of the support structure 160 intersects with the extension direction of the spacer 210, so that the spacer 210 overlaps with the orthographic projection of the support structure 160 on the base substrate 110. Moreover, the cross-arrangement of the support structure 160 and the spacer 210 can also effectively prevent the spacer 210 from sliding, reducing the risk of scratches and light leakage. The orthographic projection of at least one spacer 210 on the base substrate 110 overlaps with the orthographic projections of at least two support structures 160 on the base substrate 110. When the second substrate 200 slides relative to the first substrate 100 along the extension direction of the gate line 130, since the spacer 210 is supported by at least two support structures 160, it is ensured that the spacer 210 will not slide off the support structure 160.

[0081] For example, the orthographic projection of at least one supporting structure 160 on the base substrate 110 completely falls within the orthographic projection of the data line 120 on the base substrate 110. The orthographic projection of at least one supporting structure 160 on the base substrate 110 is completely covered by the orthographic projection of the data line 120 on the base substrate 110, thereby raising the supporting structure 160 by the data line 120, maintaining the flatness of the supporting structure 160 as much as possible, and also enabling light shielding by the data line 120.

[0082] Figure 6 FIG. 1 is a schematic diagram of a partial planar structure of a display panel provided according to an example of the present disclosure. Figure 6 As shown, for example, the support structure 160 is a continuous structure. For example, the continuous support structure 160 extends uninterruptedly along the extension direction of the data line 120. For example, the at least one support structure 160 includes a plurality of support structures 160, and the plurality of support structures 160 are arranged along the first direction x. For example, the plurality of support structures 160 correspond one-to-one to the plurality of data lines 120.

[0083] refer to Figure 2 For example, the support structure 160 is a discontinuous structure. For example, the support structure 160 extends along the extension direction of the data line 120 and has discontinuous portions. For example, each support structure 160 includes a plurality of support segments 160a spaced apart along the second direction y. The interval between two adjacent support segments 160a is the discontinuous portion of the support structure 160.

[0084] Figure 7 The figure is a schematic structural diagram of a display panel provided according to another example of an embodiment of the present disclosure.

[0085] like Figure 7As shown, for example, the pixel electrode 181 is formed on the planarization layer 103, the second insulating layer 104 covers the surface of the pixel electrode 181 away from the planarization layer 103, and the common electrode 182 is formed on the side of the second insulating layer 104 away from the planarization layer 103. It can be understood that in different examples (for example Figure 1 and Figure 7 ), depending on the location of the common electrode 182, the positional relationship and manufacturing sequence of the support structure 160 and other film layers may also be different accordingly, which will be described in detail in some examples below.

[0086] In conjunction with some of the aforementioned examples, the first insulating layer 102 includes a first sub-via 102a, the planarization layer 103 includes a second sub-via 103a, and a portion of the pixel electrode 181 is electrically connected to the second doping region pattern 143 via the second sub-via 103a and the first sub-via 102a. For example, a straight line perpendicular to the base substrate 110 passes through the first sub-via 102a and the second sub-via 103a, thereby forming a casing hole by the second sub-via 103a and the first sub-via 102a.

[0087] like Figure 1 or Figure 7 As shown, for example, the plurality of spacers 210 include at least one first sub-spacer 211 and at least one second sub-spacer 212. For example, the first sub-spacer 211 is supported by the support structure 160 to jointly support the thickness of the box, forming a main spacer (Main PS) that plays a major supporting role. For example, when subjected to external force, the second sub-spacer 212 supports the first substrate 100, forming a sub-spacer (Sub PS) that plays an auxiliary supporting role. It should be noted that, as Figure 1 and Figure 7 As shown, the orthographic projection of the support structure 160 on the base substrate 110 completely falls within the orthographic projection of the spacer 210 on the base substrate 110. In some examples, the orthographic projection of the support structure completely overlaps with the orthographic projection of the spacer (not shown in the figure). In other examples, the orthographic projection of the spacer completely falls within the orthographic projection of the support structure (not shown in the figure). This is conducive to achieving stable support of the spacer by the support structure, and the present disclosure is not limited to this.

[0088] For example, at least one support structure 160 includes a stacked support portion 161 and a second light shielding portion 162, with the second light shielding portion 162 positioned between the support portion 161 and the base substrate 110. For example, the support portion 161 can support the first sub-spacer 211 to form a main spacer. For example, the orthographic projection of the support portion 161 on the base substrate 110 completely falls within the orthographic projection of the second light shielding portion 162 on the base substrate 110. In this way, the second light shielding portion 162 can shield the support portion 161 from light, thereby reducing the risk of light leakage.

[0089] For example, a dimension d1 of the support portion 161 in a direction perpendicular to the base substrate 110 is greater than a dimension d2 of the second light shielding portion 162 in a direction perpendicular to the base substrate 110. In this way, the second light shielding portion 162 can raise the support portion 161 more evenly, thereby enabling the support portion 161 to better contact and support the spacer 210.

[0090] For example, the outer contours of the orthographic projection of the support portion 161 on the base substrate 110 and the orthographic projection of the second light shielding portion 162 on the base substrate 110 have a spacing of greater than or equal to 0.5 microns in the first direction x. This provides a good light shielding effect while achieving a relatively small size of the support structure in the first direction. It is understood that the spacing between the outer contours can be 0.5 microns, 0.55 microns, 0.6 microns, etc., and the spacing can be adjusted according to actual needs. For example, the spacing between the outer contours can be larger, and this is not limited in this disclosure.

[0091] For example, the support portion 161 and the second light shielding portion 162 are both axisymmetric structures, and their axes of symmetry coincide. Thus, the second light shielding portion 162 can adequately shield the support portion 161 from light on both sides of the axis of symmetry. For example, the axes of symmetry of the support portion 161 and the second light shielding portion 162 both pass through the centerline of the data line 120. In this way, the second light shielding portion 162 and the data line 120 work together to better shield the support portion 161 from light. For example, in a direction perpendicular to the base substrate 110, the orthographic projection of the data line 120 overlaps the orthographic projection of the second light shielding portion 162.

[0092] Combine Figure 2 、 Figure 3 and Figure 6 As shown, for example, the dimension w1 of the data line 120 in the first direction x is greater than or equal to the dimension w2 of the second light shielding portion 162 in the first direction x. In this way, the influence of the second light shielding portion 162 on the aperture ratio can be further reduced.

[0093] In combination with some examples described later, the black matrix 220 covering the data line 120 can shield the support portion 161 together with the data line 120 and the second light shielding portion 162 , while also reducing the impact of optical crosstalk between two adjacent sub-pixels 180 .

[0094] like Figure 1 and Figure 7 As shown, for example, the second light shielding portion 162 includes a conductive material and is electrically connected to the common electrode 182. Thus, the second light shielding portion 162 can reduce the resistive load of the common electrode 182, thereby reducing the resistance of the common electrode 182 and balancing the voltage of the common electrode 182 within the display panel. For example, the second light shielding portion 162 includes a metal material.

[0095] For example, the material of the support portion 161 includes an inorganic material. For example, unlike the support portion made of an organic material, the support portion 161 in the example of the present disclosure uses an inorganic material. Based on the process capability of the etching process of the inorganic material (which can be a dry etching process or a wet etching process), a high-precision support portion 161 can be prepared. For example, the inorganic material includes an inorganic insulating material. For example, the inorganic material includes: at least one of silicon oxide, silicon nitride, and silicon oxynitride. In addition, the support portion 161 extends along the extension direction of the data line 120. Compared with some columnar support portions, the support portion 161 in the present disclosure is also easier to produce a smaller size, thereby achieving high precision.

[0096] For example, the support portion 161 and the second light shielding portion 162 both comprise a conductive material and are electrically connected to each other, and the second light shielding portion 162 is electrically connected to the common electrode 182. In this way, the support portion 161 and the second light shielding portion 162 can jointly reduce the resistive load of the common electrode 182, thereby reducing the resistance of the common electrode 182 and further improving the display quality of the display panel. For example, the support portion 161 and the second light shielding portion 162 both comprise a metal material. For example, the metal material includes at least one of molybdenum, aluminum, titanium, and copper.

[0097] For example, the support portion 161 and the second light shielding portion 162 are made of different materials. For example, the support portion 161 includes molybdenum, and the second light shielding portion 162 includes titanium. For example, the support portion 161 includes molybdenum-aluminum-molybdenum, and the second light shielding portion 162 includes titanium.

[0098] For example, a dimension l1 of the support portion 161 facing the second light shielding portion 162 in the first direction x is less than or equal to 2 microns. For example, the dimension l1 may be, but is not limited to, 2 microns, 1.9 microns, 1.8 microns, 1.7 microns, 1.6 microns, 1.5 microns, etc. For example, a dimension l2 of the support portion 161 facing away from the second light shielding portion 162 in the first direction x is greater than or equal to 0.8 microns. For example, the dimension l2 may be, but is not limited to, 0.8 microns, 0.9 microns, 1.0 microns, etc.

[0099] For example, in the direction perpendicular to the base substrate 110, the dimension d1 of the support portion 161 is less than or equal to 0.4 microns. For example, the dimension d1 can be, but is not limited to, 0.4 microns, 0.3 microns, etc. For example, the slope angle α (Profile) of the support portion 161 is 75° to 85°. Figure 1 As shown, the slope angle α is the angle between the side wall and the bottom surface of the support portion 161. For example, the slope angle α of the support portion 161 can be, but is not limited to, 78°, 80°, 83°, etc.

[0100] For example, in a direction perpendicular to the base substrate 110, the dimension d1 of the support portion 161 is less than or equal to 0.8 microns. For example, the dimension d1 may be, but is not limited to, 0.8 microns, 0.7 microns, 0.6 microns, 0.5 microns, etc. For example, the slope angle α of the support portion 161 is 55° to 65°. For example, the slope angle α of the support portion 161 may be, but is not limited to, 58°, 60°, 63°, etc.

[0101] For example, the dimension w2 of the second light shielding portion 162 in the first direction x is less than or equal to 4 microns. For example, the dimension w2 may be, but is not limited to, 3.9 microns, 3.8 microns, 3.7 microns, 3.6 microns, 3.5 microns, 3 microns, 2.5 microns, 2 microns, etc. For example, in conjunction with some of the aforementioned examples, the dimension w1 of the data line 120 is 2.5 microns, and the dimension w2 of the second light shielding portion 162 is less than or equal to 2.5 microns. For example, the dimension d2 of the second light shielding portion 162 perpendicular to the base substrate 110 is greater than or equal to 0.3 microns. For example, the dimension d2 may be, but is not limited to, 0.3 microns, 0.4 microns, 0.5 microns, etc.

[0102] like Figure 7 As shown, for example, in combination with some of the aforementioned examples, the common electrode 182, the second light shielding portion 162 and the support portion 161 are sequentially stacked on the second insulating layer 104. For example, the second light shielding portion 162 and the support portion 161 in the support structure 160 both include metal materials, and the second insulating layer 104 is a second passivation layer. In this way, the surface of the first substrate 100 facing the second substrate 200 can have good mechanical properties. Figure 7 In the illustrated example, the support portion 161 of the support structure 160 is in direct contact with the first sub-spacer 211 to support the first sub-spacer 211. Figure 1 A second passivation layer 104 may be provided between the support portion 161 of the support structure 160 and the first sub-spacer 211 . The support structure 160 supports the first sub-spacer 211 through the second passivation layer 104 , which is not limited in the present disclosure.

[0103] Figure 8 For the Figure 2 The cross-sectional structure diagram of the display panel taken along line AA' is shown. Figure 9 For the Figure 2 The cross-sectional structure diagram of the display panel taken along line BB' is shown. Figure 10 For the Figure 2 The cross-sectional structure diagram of the display panel cut along line CC' is shown. Figures 8 to 10 The relative positions of the support structure 160, the spacer 210, the data line 120 and the gate line 130 are only schematically shown, and the relative positions of other structures are not strictly limited. Figures 8 to 10 Shows a difference from Figures 3 to 5 The cross-sectional view of the display panel is shown, but Figures 8 to 10 The structure shown in the example can be fully applied to Figure 2 The display panel shown.

[0104] refer to Figures 8 to 10 , and combined with Figure 2 For example, a color filter layer corresponding to the pixel unit and a black matrix 220 (BM) covering structures such as the gate line 130 and the data line 120 located in the non-display area can be provided on the side of the second substrate 200 facing the first substrate 100. For example, the first sub-spacer 211 and the second sub-spacer 212 are both provided on the black matrix 220. For example, the black matrix 220 covering the data line 120 is an axisymmetric structure, which coincides with the axis of symmetry of the support structure 160. In this way, the support structure 160 can be further shielded from light by the black matrix 220 covering the data line 120. For example, the spacer 210 is an axisymmetric structure, and the axis of symmetry of the spacer 210 coincides with the axis of symmetry of the black matrix 220 covering the gate line 130. In this way, the spacer 210 can be shielded from light by the black matrix 220 covering the gate line 130.

[0105] For example, in conjunction with some of the previous examples, refer to Figure 3 In a direction perpendicular to the base substrate 110, the orthographic projection of the second light shielding portion 162 in the direction in which the data line 120 extends partially overlaps with the orthographic projection of the spacer 210, but partially does not overlap. For example, in the direction in which the data line 120 extends, portions of the orthographic projection of the second light shielding portion 162 on the base substrate 110 are located on opposite sides of the orthographic projection of the spacer 210 on the base substrate 110 in the direction in which the spacer 210 extends. For example, on both sides of the spacer 210 along the second direction y, the dimension l3 of the second light shielding portion 162 is greater than 30 microns. It can be understood that the dimension l3 of the second light shielding portion 162 in its extension direction extends 30 microns beyond the two sides of the spacer 210.

[0106] For example, a dimension D2 of at least one first sub-spacer 211 in the first direction x is greater than or equal to a pitch D1 between two adjacent sub-pixels 180 in the first direction x, such that at least one first sub-spacer 211 extending along the extension direction of the gate line 130 can pass through the two sub-pixels 180. For example, a dimension D2 of all first sub-spacers 211 in the first direction x is greater than or equal to the pitch D1 between two adjacent sub-pixels 180 in the first direction x. For example, the pitch D1 between two adjacent sub-pixels 180 in the first direction x is the distance between two center lines of the two sub-pixels 180 extending in the second direction y. For example, a dimension D2 of the first sub-spacer 211 in the first direction x is greater than or equal to 52.32 microns. In conjunction with some of the aforementioned examples, the sub-pixels 180 are defined by the intersection of the gate line 130 and the data line 120, and the first sub-spacer 211 is supported by the support structure 160 extending along the extension direction of the data line 120, such that the first sub-spacer 211 can be supported by both support structures 160. In this way, when the second substrate 200 slides along the extending direction of the gate line 130 , the first sub-spacer 211 will not slide off the supporting structure 160 .

[0107] Figure 11-13 Schematic diagram of a partial planar structure of a display panel provided according to different examples of the embodiment of the present disclosure. Figure 11 and Figure 1 As shown, for example, at least one second sub-spacer 212 is spaced apart from at least one first sub-spacer 211. The second sub-spacer 212 is spaced apart from the first sub-spacer 211, thereby providing a more uniform support between the first substrate 100 and the second substrate 200. Figure 11 As shown, for example, adjacent first sub-spacers 211 and second sub-spacers 212 are spaced apart from each other in the second direction y. For example, adjacent first sub-spacers 211 and second sub-spacers 212 are staggered in the first direction x. Of course, the present disclosure is not limited to this. The first sub-spacers 211 and second sub-spacers 212 may also be arranged in other ways, as long as they can be more evenly distributed on the second substrate 200 and provide more uniform support.

[0108] For example, the spacer 210 may be made of an organic material. For example, if the support structure 160 is made of an inorganic material, the spacer 210, which is made of a relatively elastic organic material, can be combined with the support structure 160 to enhance the elasticity of the area where the spacer 210 is located. This reduces the risk of the support structure 160 scratching the second substrate 200 when a large force is applied to the second substrate 200.

[0109] For example, the minimum width of the spacer 210 can be less than or equal to 3 microns. For example, the minimum width of the spacer 210 can be, but is not limited to, 3.5 microns, 3 microns, 2.5 microns, 2 microns, 1.5 microns or 1 micron, and can be set according to actual needs. At this time, the minimum width of the black matrix 220 portion used to shield the spacer 210 and its surrounding area can also be reduced accordingly, which is conducive to improving the product aperture ratio. Taking the black matrix 220 covering the gate line 130 as an example, the size of the black matrix 220 in the second direction y can be reduced from 17 microns to 9 microns.

[0110] refer to Figure 11 For example, the ratio of the number of first sub-spacers 211 to the number of sub-pixels 180 is a first ratio, the ratio of the number of second sub-spacers 212 to the number of sub-pixels 180 is a second ratio, and the sum of the first ratio and the second ratio is less than 1. The number of the first sub-spacers 211 and the second sub-spacers 212 can be adjusted according to actual needs, thereby adjusting the ratio to the number of sub-pixels 180. By adjusting the density of the first sub-spacers 211 and the second sub-spacers 212, the support force between the first substrate 100 and the second substrate 200 is made more stable.

[0111] For example, the spacing between two adjacent spacers 210 in the first direction x is greater than 5 microns. For example, the spacing between two adjacent first sub-spacers 211 in the first direction x is greater than 5 microns. For example, the spacing between two adjacent second sub-spacers 212 in the first direction x is greater than 5 microns. Of course, the spacing between the spacers 210 can be adjusted according to actual needs and is not limited here.

[0112] For example, the first ratio is 1 / 5 to 2 / 5. Taking 10 sub-pixels 180 as a cycle as an example, the 10 sub-pixels 180 are arranged in 2 rows and 5 columns. In combination with the above examples, the extension length of the first sub-spacer 211 can pass through two sub-pixels 180, and the number of the first sub-spacers 211 can be 2 to 4. Figure 11 As shown, the number of the first sub-spacers 211 is 2. Figure 12 and Figure 13 As shown, four first sub-spacers 211 are provided.

[0113] For example, the second ratio is 1 / 5 to 2 / 5. Taking 10 sub-pixels 180 as a cycle as an example, the 10 sub-pixels 180 are arranged in 2 rows and 5 columns. In combination with the above examples, the extension length of the second sub-spacer 212 can pass through two sub-pixels 180, and the number of the second sub-spacers 212 can be 2 to 4. Figure 11 As shown, the second sub-spacers 212 are provided in two pieces. Figure 12 and Figure 13As shown, the number of the second sub-spacers 212 is set to 4. Of course, the first ratio and the second ratio can also be adjusted according to actual needs, and the present disclosure does not limit this.

[0114] Figure 14 A structural schematic diagram of a display panel provided as another example of an embodiment of the present disclosure.

[0115] refer to Figure 11 and Figure 14 For example, the at least one second sub-spacer 212 includes a plurality of second sub-spacers 212, and the orthographic projections of at least some of the second sub-spacers 212 on the base substrate 110 do not overlap with the orthographic projections of the plurality of support structures 160 on the base substrate 110. In this way, when a force is applied to the second substrate 200, the second sub-spacers 212 can support the side surface of the first substrate 100 facing the second substrate 200, thereby forming auxiliary spacers.

[0116] like Figure 14 As shown, for example, the dimension S2 of at least some of the second sub-spacers 212 in a direction perpendicular to the base substrate 110 is greater than the dimension S1 of at least one first sub-spacer 211 in a direction perpendicular to the base substrate 110. This reduces the distance between the second sub-spacers 212 and the first substrate 100, making it easier to support the first substrate 100 to support the cell thickness when subjected to force. For example, in a direction perpendicular to the base substrate 110, the difference between the dimensions of the second sub-spacers 212 and the first sub-spacers 211 (e.g., the difference between S2 and S1) is 0.4 microns to 1 micron. It is understood that the height difference between the second sub-spacers 212 and the first sub-spacers 211 can be, but is not limited to, 0.4 microns, 0.5 microns, 0.6 microns, 0.7 microns, 0.8 microns, 0.9 microns, or 1.0 microns.

[0117] For example, reference Figure 1 or Figure 7 The at least one second sub-spacer 212 includes a plurality of second sub-spacers 212, the orthographic projections of at least some of the second sub-spacers 212 on the base substrate 110 overlap with the orthographic projections of the plurality of support structures 160 on the base substrate 110, and the dimension S2 of at least some of the second sub-spacers 212 in a direction perpendicular to the base substrate 110 is smaller than the dimension S1 of at least one first sub-spacer 211 in a direction perpendicular to the base substrate 110. Thus, when no force is applied to the second substrate 200, the second sub-spacers 212 are not supported by the support structures 160, and the main spacer formed by the support of the first sub-spacers 211 and the support structures 160 maintains the thickness of the cell. However, when a force is applied to the second substrate 200, the second sub-spacers 212 and the support structures 160 can support the cell, thereby forming auxiliary spacers.

[0118] refer to Figure 11 For example, a plane perpendicular to the second direction y is a reference plane, and the orthographic projection of the first sub-spacer 211 on the reference plane and the orthographic projection of the second sub-spacer 212 on the reference plane at least partially do not overlap. It is understood that on the reference plane, the orthographic projections of the first sub-spacer 211 and the second sub-spacer 212 may overlap and not overlap, or their orthographic projections on the reference plane may not overlap at all. Thus, the first sub-spacers 211 and the second sub-spacers 212 are staggered in the second direction y, thereby providing more stable support between the first substrate 100 and the second substrate 200.

[0119] like Figure 11 As shown, for example, the at least one first sub-spacer 211 includes a plurality of first sub-spacer rows L1, each of which includes a plurality of first sub-spacers 211 arranged along a first direction x. For example, the plurality of first sub-spacers 211 are arranged along the arrangement direction of the data lines 120 to form the first sub-spacer row L1. The at least one second sub-spacer 212 includes a plurality of second sub-spacer rows L2, each of which includes a plurality of second sub-spacers 212 arranged along the first direction x. For example, the plurality of second sub-spacers 212 are arranged along the arrangement direction of the data lines 120 to form the second sub-spacer row L2.

[0120] For example, multiple first sub-spacer rows L1 and multiple second sub-spacer rows L2 are alternately arranged along the second direction y. Thus, in the direction of arrangement of the gate lines 130, the first sub-spacer rows L1 and the second sub-spacer rows L2 can alternately form main spacers and auxiliary spacers, making the supporting force more uniform. For example, adjacent first sub-spacer rows L1 and second sub-spacer rows L2 are staggered in the first direction x, so that the first sub-spacers 211 in the first sub-spacer row L1 and the second sub-spacer 212 in the second sub-spacer row L2 can be staggered in the direction of arrangement of the data lines 120.

[0121] Figure 15 A schematic diagram of a partially enlarged structure in a display panel according to another example provided in an embodiment of the present disclosure. Figure 16 This is a schematic diagram of a partially enlarged structure of another example of a display panel provided in an embodiment of the present disclosure. Figure 15 and Figure 16, for example, the dimension D3 of at least one second sub-spacer 212 in the first direction x is greater than or equal to the pitch D1 of two adjacent sub-pixels 180 in the first direction x, so that at least one second sub-spacer 212 extending in the direction of the gate line 130 can pass through the two sub-pixels 180. For example, the dimension D3 of all second sub-spacers 212 in the first direction x is greater than or equal to the pitch D1 of two adjacent sub-pixels 180 in the first direction x. For example, the dimension D3 of the second sub-spacer 212 in the first direction x is greater than or equal to 52.32 microns. In this way, when the second substrate 200 is subjected to a force, the second sub-spacer 212 can be supported by at least two supporting structures 160 to form a secondary spacer, and when the second substrate 200 slides and displaces along the extension direction of the gate line 130, the second sub-spacer 212 will not slide off the supporting structure 160. It can be understood that the position on the first substrate 100 corresponding to the second sub-spacer 212 can be as follows Figure 15 The support structure 160 is provided as shown, and can also be provided as shown. Figure 16 The support structure 160 is not shown, and the present disclosure is not limited thereto.

[0122] refer to Figure 1 and Figure 3 For example, in a direction perpendicular to the substrate 110, the data line 120 and the gate line 130 do not overlap, and the support structure 160 and the gate line do not overlap. For example, at the overlap of the data line 120 and the gate line 130, the support structure 160 and the gate line 130 also overlap. For example, referring to Figure 3 In a direction perpendicular to the base substrate 110 , the spacers 210 and the gate lines 130 do not overlap. By arranging the spacers 210 and the gate lines 130 to not overlap, the width of the black matrix 220 at the corresponding position of the gate lines 130 is reduced.

[0123] Figure 17 An electron microscope image of the support structure in the display panel provided in an embodiment of the present disclosure. Figure 18 This is an electron microscope image of the spacer in the display panel provided by the embodiment of the present disclosure. Figure 17 As shown, in the support structure 160, the second light shielding portion 162 can well shield the support portion 161 from light, and the surface of the support portion 161 away from the second light shielding portion 162 has good flatness. Figure 18 As shown, the spacer 210 is formed on the black matrix 220, and the side of the spacer 210 away from the black matrix 220 is smaller. Therefore, the support structure 160 can stably support the spacer 210 and realize the refinement of the spacer 160. Figure 1 、 Figure 7 The cross-sectional view schematically shows the cross-sectional shape of the spacer. For example, the cross-sectional shape can be Figure 18 shown.

[0124] It should be noted that Figure 18 The electron microscope image shown is a schematic diagram of the spacer 210 at an oblique viewing angle, rather than a cross-sectional schematic diagram. Figure 18 It can be seen that the spacers 210 on the second substrate 200 in the examples of the present disclosure are not columnar spacers, but rather strip-shaped spacers. When making columnar spacers, due to the limitations of the manufacturing process, it is difficult to reduce the size of the side of the columnar spacer away from the black matrix. However, when making the spacers 210 in the examples of the present disclosure, since the spacers 210 are roughly strip-shaped, the size of the side of the spacers 210 away from the black matrix 220 can be made smaller, thereby improving the refinement of the spacers 210.

[0125] Figure 19 A schematic structural diagram of a display panel provided in another embodiment of the present disclosure.

[0126] like Figure 19 As shown, at least one embodiment of the present disclosure provides a display panel, including a first substrate 300 and a second substrate 400. For example, the first substrate 300 is an array substrate. For example, the second substrate 400 is an opposing substrate, and the opposing substrate is, for example, a color filter substrate. The first substrate 300 includes a base substrate 310 and a plurality of data lines 320 and a plurality of gate lines 330 located on the base substrate 310. The plurality of gate lines 330 are located on a side of the plurality of data lines 320 facing the base substrate 310. The plurality of data lines 320 are arranged along a first direction x, and the plurality of gate lines 330 are arranged along a second direction y, and the second direction y intersects the first direction x. For example, the plurality of data lines 320 and the plurality of gate lines 330 are insulated and cross-arranged to define a plurality of sub-pixels.

[0127] like Figure 19 As shown, the second substrate 400 is disposed opposite the first substrate 300, and a plurality of spacers 410 are disposed on the side of the second substrate 400 facing the first substrate 300. The first substrate 300 further includes a plurality of support structures 340, which are configured to support at least some of the spacers 410. The support structures 340 support the spacers 410, and together they form a main spacer 410, thereby supporting the cell thickness between the first substrate 300 and the second substrate 400.

[0128] like Figure 19 As shown, at least a portion of the plurality of support structures 340 extends along the extension direction of the data lines 320 and is electrically connected to the data lines 320. Thus, the electrical connection between the support structures 340 and the data lines 320 can reduce the resistance of the data lines 320 and improve the charging rate of the first substrate 300.

[0129] like Figure 19As shown, at least a portion of the orthographic projections of the multiple support structures 340 on the base substrate 310 are completely within the orthographic projections of the data lines 320 on the base substrate 310. In this way, the data lines 320 can be reused as a light shielding layer to shield the support structures 340 from light, thereby reducing the risk of light leakage. Furthermore, there is no need to fabricate an additional light shielding layer to shield the support structures 340 from light, which can simplify the manufacturing process.

[0130] For example, the first substrate 300 further includes a gate insulating layer 350. The gate line 330 is formed on the base substrate 310, and the gate insulating layer 350 covers the gate line 330. For example, the first substrate 300 further includes an active layer 360, and a portion of the active layer 360 is disposed on the same layer as the data line 320. For example, the data line 320 and the active layer 360 are directly overlapped, thereby saving a mask process and reducing costs. For example, the data line 320 and the active layer 360 are both formed on the gate insulating layer 350. For example, the support structure 340 is formed on the side of the data line 320 away from the gate insulating layer 350. For example, the first substrate 300 further includes a first insulating layer 370, and the first insulating layer 370 covers the data line 320, the active layer 360, and the side of the support structure 340 away from the gate insulating layer 350. For example, the first substrate 300 further includes a common electrode 380, and the common electrode 380 is formed on the first insulating layer 370. For example, the first substrate 300 further includes a second insulating layer 390 , and the second insulating layer 390 covers a side of the common electrode 380 away from the first insulating layer 370 .

[0131] For example, the support structure 340 comprises a metal material, and the first insulating layer 370 and the second insulating layer 390 are both passivation layers. In this way, the support structure 340 can be protected by the first insulating layer 370 and the second insulating layer 390, and the surface of the first substrate 300 facing the second substrate 400 can also have good mechanical properties. Furthermore, the first insulating layer 370 and the second insulating layer 390 can prevent the metal support structure 340 from affecting the electric field within the liquid crystal cell, thereby reducing the effect of the support structure 340 on the liquid crystal molecules. It is understood that the support structure 340 supports the spacer 410 through the first insulating layer 370 and the second insulating layer 390, without directly contacting the spacer 410.

[0132] For example, the first substrate 300 further includes a pixel electrode 385 located on a surface of the second insulating layer 390 that is away from the first insulating layer 370. The pixel electrode 385 is electrically connected to the data line 320 via a thin film transistor. For example, the first insulating layer 370 includes a first sub-via 371, and the second insulating layer 390 includes a second sub-via 391. A straight line perpendicular to the base substrate 110 passes through the first sub-via 371 and the second sub-via 391, thereby forming a casing hole formed by the first sub-via 371 and the second sub-via 391. Part of the pixel electrode 385 passes through the casing hole formed by the first sub-via 371 and the second sub-via 391 to achieve electrical connection with the data line 320.

[0133] For example, the plurality of spacers 410 includes a plurality of first sub-spacers 411 and a plurality of second sub-spacers 412. The orthographic projections of the plurality of first sub-spacers 411 on the base substrate 310 overlap with the orthographic projections of the plurality of support structures 340 on the base substrate 310. In this way, the first sub-spacers 411 are supported by the support structures 340 to jointly support the thickness of the box, forming main spacers that play a primary supporting role.

[0134] For example, the orthographic projections of the plurality of second sub-spacers on the base substrate may not overlap with the orthographic projections of the plurality of support structures on the base substrate (not shown). For example, there is no support structure at the position on the first substrate corresponding to the second sub-spacers. When a force is applied to the second substrate, the second sub-spacers can support a side surface of the first substrate facing the second substrate, thereby forming auxiliary spacers.

[0135] For example, the orthographic projection of at least a portion of the second sub-spacers 412 on the base substrate 310 overlaps with the orthographic projections of the multiple support structures 340 on the base substrate 310, and the dimension S2 of at least a portion of the second sub-spacers 412 in a direction perpendicular to the base substrate 310 is smaller than the dimension S1 of at least one first sub-spacer 411 in a direction perpendicular to the base substrate 310. In this manner, when no force is applied to the second substrate 400, no supporting force is generated between the second sub-spacers 412 and the support structures 340, and only the main spacers formed by the support of the first sub-spacers 411 and the support structures 340 support the thickness of the box. However, when a force is applied to the second substrate 400, the second sub-spacers 412 and the support structures 340 provide support, thereby forming auxiliary spacers.

[0136] For example, the display panel can be any one of a twisted nematic (TN) type liquid crystal display panel, an in-plane switching (IPS) type liquid crystal display panel, a fringe field switching (FFS) type liquid crystal display panel, an advanced super dimension switch (ADS) type liquid crystal display panel, and a high advanced super dimension switch (HADS) type liquid crystal display panel. When the first substrate is an array substrate in a TN type liquid crystal display panel, a common electrode is not provided on the first substrate; when the first substrate is an array substrate in an IPS type liquid crystal display panel, an FFS type liquid crystal display panel, an ADS type liquid crystal display panel, or a HADS type liquid crystal display panel, a common electrode is provided on the first substrate. The technical solution disclosed herein does not limit the specific type of the display panel.

[0137] At least one embodiment of the present disclosure provides a display device including the above-mentioned display panel. The technical effects of the display device provided by the embodiment of the present disclosure can be referred to the corresponding description of the display panel in the above embodiment, which will not be repeated here.

[0138] The display device in this embodiment can be any product or component with a display function, such as a liquid crystal panel, a liquid crystal television, a monitor, a mobile phone, a tablet computer, a laptop computer, a digital photo frame, a navigator, etc. The display device can also include other conventional components such as a display panel, which is not limited in the embodiments of the present disclosure.

[0139] refer to Figure 1 At least one embodiment of the present disclosure provides a method for forming Figures 1 to 16 The method for manufacturing the display panel in any of the examples shown includes: forming a first substrate 100 and a second substrate 200 that are oppositely disposed.

[0140] Forming the first substrate 100 includes providing a base substrate 110. For example, the base substrate 110 can be prepared on a glass carrier.

[0141] For example, a plurality of data lines 120, a semiconductor layer 140, and a plurality of gate lines 130 and a plurality of transfer structures 150 disposed on the same layer are sequentially formed on a base substrate 110. For example, the data lines 120 are electrically connected to the first doped region pattern 142 of the semiconductor layer 140 via the transfer structures 150. For example, the gate lines 130 are electrically connected to the channel region pattern 141 of the semiconductor layer 140.

[0142] For example, a plurality of support structures 160 are formed on the side of the plurality of adapter structures 150 away from the base substrate 110, and each support structure 160 includes a stacked light shielding portion (which can be called a second light shielding portion 162) and a support portion 161, and the orthographic projection of the support portion 161 on the base substrate 110 is completely located within the orthographic projection of the light shielding portion on the base substrate 110. In this way, by making the orthographic projection of the support portion 161 on the base substrate 110 completely located within the orthographic projection of the light shielding portion on the base substrate 110, the support portion 161 can be fully shielded, the light shielding effect of the light shielding portion on the support portion 161 is improved, and the risk of light leakage is reduced. Moreover, by forming the support structure 160 on the side of the adapter structure 150 away from the base substrate 110, the support structure 160 can be raised by the adapter structure 150, thereby ensuring that the raised support structure 160 and the spacer 210 can reliably support the box thickness while maintaining the flatness of the support structure 160 as much as possible.

[0143] Figures 20A to 20E Schematic cross-sectional views of various steps of manufacturing the support structure 160 provided in an embodiment of the present disclosure.

[0144] like Figure 20A As shown, for example, forming a plurality of support structures 160 includes forming a first material layer 10 and a second material layer 20 that are stacked, wherein the first material layer 10 is located between the second material layer 20 and the substrate. The substrate is, for example, Figure 1 The base substrate 110 is shown. For example, in combination with some of the aforementioned examples, a first material layer 10 is formed on the common electrode 182 of the first substrate 100. The first material layer 10 includes a metal material. A second material layer 20 is formed on the first material layer 10. The second material layer 20 includes an inorganic material. For example, the second material layer 20 includes a metal material.

[0145] like Figure 20B As shown, for example, a mask 30 is formed on the side of the second material layer 20 away from the first material layer 10. For example, a photoresist pattern is formed on the side of the second material layer 20 away from the first material layer 10, and the photoresist pattern serves as the mask 30.

[0146] like Figure 20C As shown, for example, the second material layer 20 is wet-etched using the mask plate 30 as a mask to form the support portion 161. For example, the mask plate 30 is used to block the second material layer 20 at the location where the support portion 161 is to be formed, so that the second material layer 20 at locations other than the location where the support portion 161 is to be formed is etched. For example, both sides of the second material layer 20 are etched using an etching solution to form the support portion 161.

[0147] like Figure 20DAs shown, for example, the first material layer 10 is dry-etched using the mask plate 30 as a mask to form a light shielding portion. For example, the light shielding portion can be Figure 1 The second light shielding portion 162 is shown. For example, the mask plate 30 is used to block the first material layer 10 at the position where the light shielding portion is to be formed, so that the first material layer 10 at positions other than the position where the light shielding portion is to be formed is etched.

[0148] like Figure 20E As shown, for example, the mask plate 30 is removed after the light shielding portion is formed.

[0149] Thus, through one mask process, the second material layer 20 is wet-etched to form the support portion 161, and the first material layer 10 is dry-etched to form the light shielding portion (such as the second light shielding portion 162), thereby reducing the influence of overlapping offset in the manufacturing process.

[0150] There are a few points to note:

[0151] (1) The drawings of the embodiments of the present disclosure only involve structures related to the embodiments of the present disclosure, and other structures can refer to general designs.

[0152] (2) In the absence of conflict, features in the same embodiment and different embodiments of the present disclosure may be combined with each other.

[0153] The foregoing description is merely an exemplary embodiment of the present disclosure and is not intended to limit the scope of protection of the present disclosure. The scope of protection of the present disclosure is determined by the appended claims.

Claims

1. A display panel, comprising: A first substrate comprising a base substrate, and a plurality of data lines, a plurality of gate lines, and a semiconductor layer located on the base substrate, wherein the plurality of gate lines are located on a side of the plurality of data lines away from the base substrate, the plurality of data lines are arranged along a first direction, and the plurality of gate lines are arranged along a second direction, wherein the second direction intersects the first direction; A second substrate is arranged opposite to the first substrate, and a plurality of spacers are arranged on a side of the second substrate facing the first substrate. The semiconductor layer is located between the layer where the plurality of data lines are located and the layer where the plurality of gate lines are located, and the semiconductor layer includes a channel region pattern of a transistor, a first doping region pattern, and a second doping region pattern; The first substrate further includes a plurality of transfer structures and a plurality of support structures, wherein the plurality of transfer structures are disposed on the same layer as the plurality of gate lines, and at least one data line is electrically connected to the first doped region pattern via at least one transfer structure; At least some of the multiple supporting structures are configured to support at least some of the multiple spacers, and the orthographic projections of at least some of the spacers on the base substrate overlap with the orthographic projections of at least some of the supporting structures on the base substrate and the orthographic projections of at least some of the transition structures on the base substrate.

2. The display panel according to claim 1, wherein: The orthographic projection of at least part of the spacer on the base substrate overlaps with the orthographic projection of the first doping region pattern on the base substrate.

3. The display panel according to claim 1 or 2, wherein: An orthographic projection of at least part of the spacer on the base substrate overlaps with at least one of the channel region pattern of the transistor and the second doping region pattern.

4. The display panel according to claim 1 or 2, wherein: At least one supporting structure extends along the extension direction of the data line, at least one spacer extends along the extension direction of the gate line, and the orthographic projection of the at least one spacer on the base substrate overlaps with the orthographic projections of at least two supporting structures on the base substrate.

5. The display panel according to claim 1 or 2, wherein: An orthographic projection of at least one supporting structure on the base substrate completely falls within an orthographic projection of the data line on the base substrate.

6. The display panel according to claim 1 or 2, wherein: The first substrate further includes a plurality of first light shielding portions, which are arranged in the same layer as the plurality of data lines and overlap with the channel region pattern in a direction perpendicular to the base substrate; The orthographic projection of at least part of the spacer on the base substrate overlaps with at least one first light shielding portion.

7. The display panel according to claim 1, wherein: The first substrate further includes a plurality of sub-pixels, each sub-pixel includes a pixel electrode and a common electrode, and the pixel electrode is electrically connected to the second doping region pattern.

8. The display panel according to claim 7, wherein: The plurality of spacers include at least one first sub-spacer and at least one second sub-spacer; The size of the at least one first sub-spacer in the first direction is greater than or equal to the pitch between two adjacent sub-pixels in the first direction, and / or the size of the at least one second sub-spacer in the first direction is greater than or equal to the pitch between two adjacent sub-pixels in the first direction.

9. The display panel according to claim 8, wherein: The at least one second sub-spacer is spaced apart from the at least one first sub-spacer; The ratio of the number of the first sub-spacers to the number of the sub-pixels is a first ratio, the ratio of the number of the second sub-spacers to the number of the sub-pixels is a second ratio, and the sum of the first ratio and the second ratio is less than 1.

10. The display panel according to claim 9, wherein: The at least one second sub-spacer includes a plurality of second sub-spacers, the orthographic projections of at least some of the second sub-spacers on the base substrate do not overlap with the orthographic projections of the plurality of support structures on the base substrate, and the size of at least some of the second sub-spacers in a direction perpendicular to the base substrate is greater than the size of the at least one first sub-spacer in the direction perpendicular to the base substrate.

11. The display panel according to claim 9, wherein: The at least one second sub-spacer includes a plurality of second sub-spacers, the orthographic projections of at least some of the second sub-spacers on the base substrate overlap with the orthographic projections of the plurality of support structures on the base substrate, and the size of at least some of the second sub-spacers in a direction perpendicular to the base substrate is smaller than the size of the at least one first sub-spacer in the direction perpendicular to the base substrate.

12. The display panel according to any one of claims 9 to 11, wherein: The first ratio is 1 / 5 to 2 / 5; and / or The second ratio is 1 / 5 to 2 / 5.

13. The display panel according to any one of claims 9 to 11, wherein: A plane perpendicular to the second direction is a reference plane, and an orthographic projection of the first sub-spacer on the reference plane and an orthographic projection of the second sub-spacer on the reference plane at least partially do not overlap.

14. The display panel according to claim 13, wherein: The at least one first sub-spacer includes a plurality of first sub-spacer rows, each first sub-spacer row includes a plurality of first sub-spacers arranged along the first direction, the at least one second sub-spacer includes a plurality of second sub-spacers rows, each second sub-spacer row includes the plurality of second sub-spacers arranged along the first direction, the plurality of first sub-spacer rows and the plurality of second sub-spacer rows are alternately arranged along the second direction, and adjacent first sub-spacer rows and second sub-spacer rows are staggered in the first direction.

15. The display panel according to any one of claims 7 to 11, wherein: At least one supporting structure includes a supporting portion and a second light shielding portion that are stacked, wherein the second light shielding portion is located between the supporting portion and the base substrate; The orthographic projection of the supporting portion on the base substrate completely falls within the orthographic projection of the second light-shielding portion on the base substrate, and the size of the supporting portion in a direction perpendicular to the base substrate is larger than the size of the second light-shielding portion in a direction perpendicular to the base substrate.

16. The display panel according to claim 15, wherein: The second light shielding portion comprises a conductive material, and / or the support portion and the second light shielding portion both comprise a conductive material and are electrically connected to each other; The second light shielding portion is electrically connected to the common electrode.

17. A display device comprising the display panel according to any one of claims 1 to 16.

18. A method for forming the display panel according to claim 1, comprising: forming the first substrate and the second substrate arranged opposite to each other, Wherein, forming the first substrate includes: Providing the substrate; Sequentially forming the plurality of data lines, the semiconductor layer, the plurality of gate lines and the plurality of transfer structures disposed on the same layer on the base substrate; The plurality of support structures are formed on a side of the plurality of transfer structures away from the base substrate, each support structure comprising a light shielding portion and a support portion that are stacked, and an orthographic projection of the support portion on the base substrate is completely within an orthographic projection of the light shielding portion on the base substrate. Wherein, forming the plurality of support structures comprises: forming a first material layer and a second material layer stacked together, wherein the first material layer is located between the second material layer and the base substrate; forming a mask on a side of the second material layer away from the first material layer; performing wet etching on the second material layer using the mask plate as a mask to form the support portion; The first material layer is dry-etched using the mask plate as a mask to form the light shielding portion.

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