Latch control-based IPM, recovery control method, and control system

Abstract

The application provides an IPM based on latch control, a recovery control method and a control system, and belongs to the technical field of integrated circuits. The IPM comprises a first MOS tube, a high-side drive chip for driving the first MOS tube, a second MOS tube and a low-side drive chip for driving the second MOS tube. The drain electrode of the first MOS tube is connected to a power supply, the source electrode of the second MOS tube is grounded, the source electrode of the first MOS tube is connected to the drain electrode of the second MOS tube, so that the first MOS tube and the second MOS tube are connected in series. The high-side drive chip comprises a signal input circuit, a detection circuit and a latch circuit. The latch circuit comprises a signal control element and a latch. The application can effectively solve the problem that the high-side power switching element cannot be recovered in time, and affect the performance and stability of the whole IPM circuit, by adding the latch circuit. In addition, the application does not need to add an additional terminal to receive an external detection signal or a recovery signal, and meets the small packaging requirement of the IPM.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of integrated circuits. More particularly, to an IPM based on latch control, a recovery control method and a control system. BACKGROUND

[0002] Intelligent Power Module (IPM) is often used in three-phase inverter circuits of household appliances, industrial machines and vehicle products. Since IPM is often used under high voltage and high current, when abnormal state (such as load short circuit) occurs, too much energy (current) will cause damage to the power switch element. Therefore, it is necessary to protect the power switch element in time under abnormal state of the power switch element.

[0003] Considering that when the drive chip (IC) in the IPM is separated at the high side and the low side, the abnormal state detection of the high side usually depends on the external microcomputer control to output corresponding control signals, the delay time from detecting the actual power switch element to stopping the power supply is long, which is easy to cause damage due to exceeding the damage tolerance range of the power switch element. In the related art, a detection circuit is arranged at the high side, the potential change of the output end of the high side power switch element is detected, and the high side power switch element is cut off by using the potential change to realize protection control of the high side power switch element.

[0004] However, the above related technology may cause the high side power switch element to be in the protection state for too long time, and the normal operation of the high side power element of the IPM cannot be recovered in time, which will cause the IPM to be unable to work normally, thereby affecting the performance and stability of the whole system. Therefore, it is urgent to provide a technical solution capable of recovering the operation of the high side power element in time. SUMMARY

[0005] Embodiments of the present application provide an IPM based on latch control, a recovery control method and a control system. By adding a latch circuit in the high side drive chip, the operation of the high side power element of the IPM can be recovered in time after detecting that the high side power switch element is abnormal and enters the protection state.

[0006] In a first aspect, the embodiments of the present application provide an intelligent power module (IPM) based on latch control, comprising a first MOS tube, a high-side drive chip for driving the first MOS tube, a second MOS tube, and a low-side drive chip for driving the second MOS tube; wherein the drain of the first MOS tube is connected to a power supply, the source of the second MOS tube is grounded, the source of the first MOS tube is connected to the drain of the second MOS tube, so that the first MOS tube and the second MOS tube are connected in series, the high-side drive chip comprises a signal input circuit, a detection circuit, and a latch circuit, the latch circuit comprises a signal control element and a latch; one end of the detection circuit is connected to a connecting wire between the first MOS tube and the second MOS tube, and the other end of the detection circuit is connected to the signal control element, for detecting a source potential change of the first MOS tube, and outputting a first protection signal to the signal control element according to the source potential change;

[0007] The other end of the signal control element is connected to the latch, for receiving a first drive signal transmitted by the signal input circuit and the first protection signal of the detection circuit, making the first protection signal effective when the first drive signal is a signal for turning on the first MOS tube, and making the first protection signal ineffective when the first drive signal is a signal for turning off the first MOS tube.

[0008] The other end of the latch is connected to the gate of the first MOS tube, for latching the first protection signal when the first protection signal is effective, and outputting the first protection signal to the first MOS tube, so that the first MOS tube is in a current protection state; and when the first protection signal is ineffective, transmitting the first drive signal to the first MOS tube, to drive the first MOS tube to turn on or turn off based on the first drive signal.

[0009] In an embodiment, the signal control element is an analog switch, which is specifically used for turning on the connection between the detection circuit when the first drive signal is a signal for turning on the first MOS tube, so that the first protection signal output by the detection circuit is effective, and turning off the connection between the detection circuit when the first drive signal is a signal for turning off the first MOS tube, so that the first protection signal output by the detection circuit is ineffective.

[0010] In an embodiment, the latch circuit further comprises a timer, one end of which is connected to the signal control element, and the other end of which is connected to the latch, so that the other end of the signal control element is connected to the latch through the timer.

[0011] The timer is configured to generate a blocking signal about a preset protection time when the first protection signal is received, the blocking signal being configured to place the first MOS transistor in a current protection state within the preset protection time, and when the first protection signal in the latch is disabled and the preset protection time is not reached, the first MOS transistor continues to be placed in the current protection state until the preset protection time is reached.

[0012] In an embodiment, the high-side drive chip further comprises a filter circuit;

[0013] The filter circuit is connected to the signal input circuit at one end and to the latch circuit at the other end, so that the latch circuit receives the filtered first drive signal after the first drive signal is filtered by the filter circuit.

[0014] In an embodiment, the high-side drive chip further comprises a level conversion circuit and a high-side drive module, the level conversion circuit is connected to the latch circuit at one end and to one end of the high-side drive module at the other end; the other end of the high-side drive module is connected to the gate of the first MOS transistor, so that the latch circuit is connected to the gate of the first MOS transistor through the level conversion circuit and the high-side drive module, the level conversion circuit is configured to perform level conversion on the first drive signal transmitted by the latch circuit, and the high-side drive module is configured to drive the first MOS transistor to turn on or turn off according to the level-converted first drive signal.

[0015] In an embodiment, the high-side drive chip further comprises a pull-up resistor, one end of the pull-up resistor is connected to a power supply end of the high-side drive chip, and the other end of the pull-up resistor is connected to the signal input circuit, the latch circuit and the level conversion circuit, the pull-up resistor and the level conversion circuit are configured to maintain the signal state corresponding to the pull-up resistor when the first protection signal is disabled.

[0016] In one embodiment, the IPM further comprises a third MOS tube and a fourth MOS tube; wherein the drain of the third MOS tube is connected to a power supply, the source of the fourth MOS tube is grounded, the source of the third MOS tube is connected to the drain of the fourth MOS tube, so that the third MOS tube and the fourth MOS tube are connected in series; the detection circuit is further connected to the connecting wire between the third MOS tube and the fourth MOS tube at one end, for detecting the source potential change of the third MOS tube, and outputting a second protection signal to the signal control element according to the source potential change; the signal control element is further used for receiving the second drive signal transmitted by the signal input circuit and the second protection signal of the detection circuit, making the second protection signal valid when the second drive signal is a signal for turning on the third MOS tube, making the second protection signal invalid when the second drive signal is a signal for turning off the third MOS tube; the latch is further connected to the gate of the third MOS tube at the other end, for latching the second protection signal when the second protection signal is valid, and outputting to the third MOS tube, so that the third MOS tube is placed in a current protection state; and when the second protection signal is invalid, transmitting the second drive signal to the third MOS tube, so as to drive the third MOS tube to turn on or turn off based on the second drive signal.

[0017] In a second aspect, the embodiments of the present application further provide an IPM recovery control method, the IPM comprising a first MOS tube, a high-side drive chip for driving the first MOS tube, a second MOS tube, and a low-side drive chip for driving the second MOS tube; wherein the drain of the first MOS tube is connected to a power supply, the source of the second MOS tube is grounded, the source of the first MOS tube is connected to the drain of the second MOS tube, so that the first MOS tube and the second MOS tube are connected in series, the high-side drive chip comprises a signal input circuit, a detection circuit, and a latch circuit, and the latch circuit comprises a signal control element and a latch; the method comprises: the detection circuit detects a source potential change of the first MOS tube, and outputs a first protection signal to the signal control element according to the source potential change; the signal control element receives a first drive signal transmitted by the signal input circuit, makes the first protection signal output by the detection circuit valid when the first drive signal is a signal for turning on the first MOS tube, and makes the first protection signal output by the detection circuit invalid when the first drive signal is a signal for turning off the first MOS tube; the latch latches the first protection signal when the first protection signal is valid, and outputs the latched first protection signal to the first MOS tube, so that the first MOS tube is placed in a current protection state; and the latch latches the first drive signal when the first protection signal is invalid, and transmits the latched first drive signal to the first MOS tube, so as to drive the first MOS tube to turn on or turn off based on the first drive signal.

[0018] In a third aspect, the embodiments of the present application further provide a computer readable storage medium, comprising computer execution instructions stored on the computer readable storage medium, when the computer execution instructions are executed by a processor, the IPM recovery control method is realized.

[0019] In a fourth aspect, the embodiments of the present application further provide an IPM control system, comprising the IPM and a load device, and the load device is electrically connected with the first MOS tube.

[0020] The IPM, recovery control method and control system based on latch control provided by the embodiment of the application, the intelligent power module IPM based on latch control, comprising a first MOS tube, a high-side drive chip for driving the first MOS tube, a second MOS tube and a low-side drive chip for driving the second MOS tube; wherein the drain electrode of the first MOS tube is connected to a power supply, the source electrode of the second MOS tube is grounded, the source electrode of the first MOS tube is connected to the drain electrode of the second MOS tube, so that the first MOS tube and the second MOS tube are connected in series, the high-side drive chip comprises a signal input circuit, a detection circuit and a latch circuit, the latch circuit comprises a signal control element and a latch; the detection circuit has one end connected to a connecting wire between the first MOS tube and the second MOS tube and the other end connected to the signal control element, for detecting the source potential change of the first MOS tube and outputting a first protection signal to the signal control element according to the source potential change; the signal control element has one end connected to the detection circuit and the signal input circuit respectively and the other end connected to the latch, for receiving a first drive signal transmitted by the signal input circuit and the first protection signal of the detection circuit, making the first protection signal effective when the first drive signal is a signal for turning on the first MOS tube, and making the first protection signal ineffective when the first drive signal is a signal for turning off the first MOS tube; the latch has one end connected to the signal control element and the signal input circuit respectively and the other end connected to the gate electrode of the first MOS tube, for latching the first protection signal and outputting to the first MOS tube when the first protection signal is effective, so that the first MOS tube is in a current protection state, and for transmitting the first drive signal to the first MOS tube when the first protection signal is ineffective, so as to drive the first MOS tube to turn on or turn off based on the first drive signal. In the technical solution, the latch circuit in the high-side drive chip can realize fast protection of the abnormal state of the high-side IGBT tube, and at the same time, can realize automatic recovery control based on the driving characteristics of the MOS tube, so as to effectively solve the problem that the high-side power switching element cannot be recovered in time, affecting the performance and stability of the entire IPM circuit. In addition, the detection circuit and the latch circuit in the embodiment are integrated in the high-side drive chip, without the need to increase additional terminals to receive external detection signals or recovery signals, while meeting the small packaging requirements of the IPM. BRIEF DESCRIPTION OF DRAWINGS

[0021] In order to more clearly illustrate the embodiments of the present application or the implementation manners in the related art, the accompanying drawings needed to be used in the embodiments or related art description will be briefly introduced. Obviously, the accompanying drawings in the following description are some embodiments of the present application, and other drawings can also be obtained by those skilled in the art based on these drawings.

[0022] Figure 1 is a structure schematic diagram of an IPM provided by an embodiment of the present application based on latch control;

[0023] Figure 2 is Figure 1 a structure schematic diagram of the high-side drive chip 120;

[0024] Figure 3a is Figure 1 one of structure schematic diagrams of the latch circuit 122;

[0025] Figure 3b is Figure 1 one of timing diagrams of the latch circuit 122;

[0026] Figure 3c is Figure 1 the second structure schematic diagram of the latch circuit 122;

[0027] Figure 3d is Figure 1 the second timing diagram of the latch circuit 122;

[0028] Figure 4a is Figure 1 one of structure schematic diagrams of the detection circuit 123;

[0029] Figure 4b is Figure 1 the second structure schematic diagram of the detection circuit 123;

[0030] Figure 5 is a structure schematic diagram of another IPM provided by an embodiment of the present application;

[0031] Figure 6 is a flow schematic diagram of a recovery control method of an IPM provided by an embodiment of the present application;

[0032] Figure 7 is a structure schematic diagram of a control system of an IPM provided by an embodiment of the present application. DETAILED DESCRIPTION

[0033] In order to make the purposes, the embodiments and the advantages of the present application more clear, the following will combine the drawings in the exemplary embodiments of the present application to make a clear and complete description of the exemplary embodiments of the present application. Obviously, the described exemplary embodiments are only a part of the embodiments of the present application, but not all the embodiments of the present application.

[0034] It should be noted that the brief description of the terms in the present application is only for the convenience of understanding the following described embodiments, and is not intended to limit the embodiments of the present application. Unless otherwise specified, these terms should be understood according to their ordinary and general meanings.

[0035] In addition, the terms "include" and "have" and any variations thereof are intended to cover but not exclusive inclusion, for example, a product or device including a series of components does not have to be limited to the clearly listed components, but can include other components that are not clearly listed or inherent to these products or devices.

[0036] In the IPM, MOS tube (MOS tube FET, Metal-Oxide-Semiconductor Field Effect Transistor) tube can be used as a power switch element. The MOS tube includes a source, a drain, a gate and an insulating layer (oxide layer) between the source and the drain, which is based on the voltage control of the conductivity of the channel, by applying a positive voltage to the gate to attract the electrons of the source, forming a conductive channel, and applying a negative voltage will repel the electrons to close the channel. The existing IPM integrates logic, control, detection and protection circuit (set in the low side drive chip) inside, which is convenient to use, not only reduces the size of the system and the development time, but also greatly enhances the reliability of the system, adapts to the development direction of today's power devices-modularization, complexification and power integrated circuit (Power Integrated Circuit, PIC), so it is often used in high current and high voltage circuit structures. When the load is abnormal, such as load short circuit, etc., the MOS tube will flow through the excessive current exceeding the rated value, which may cause damage to the MOS tube.

[0037] In the related art, considering that when the drive IC in the IPM is separated at the high side and the low side, the abnormal state detection of the high side usually relies on the external microcomputer control output corresponding control signal, the delay time of detecting the actual energization stop of the MOS tube of the high side from the (low side protection circuit) is long, and the problem of damage due to exceeding the damage tolerance range of the MOS tube is easily caused. Therefore, a detection circuit is arranged at the high side, the potential change of the output end of the high side MOS tube is detected, and the energization of the high side MOS tube is cut off by using the potential change to realize the rapid protection control of the high side MOS tube. Although the above related technology solves the problem that the high side MOS tube can quickly enter the current protection state and avoids the problem of BJT tube damage, the high side MOS tube will be in the current protection state for a long time. If the abnormal condition disappears (for example, the load short circuit fault has been eliminated), the energization of the high side MOS tube of the IPM cannot be restored in time, which will cause the IPM to be unable to work normally, thereby affecting the performance and stability of the entire circuit.

[0038] In view of this, the embodiment of the present application provides a latch control-based IPM, a recovery control method and a control system. The latch control-based intelligent power module (IPM) comprises a first MOS tube, a high-side drive chip for driving the first MOS tube, a second MOS tube and a low-side drive chip for driving the second MOS tube. The drain of the first MOS tube is connected to a power supply, the source of the second MOS tube is grounded, and the source of the first MOS tube is connected to the drain of the second MOS tube, so that the first MOS tube and the second MOS tube are connected in series. The high-side drive chip comprises a signal input circuit, a detection circuit and a latch circuit. The latch circuit comprises a signal control element and a latch. One end of the detection circuit is connected to a connecting wire between the first MOS tube and the second MOS tube, and the other end is connected to the signal control element, for detecting a source potential change of the first MOS tube and outputting a first protection signal to the signal control element according to the source potential change. One end of the signal control element is connected to the detection circuit and the signal input circuit respectively, and the other end is connected to the latch, for receiving a first drive signal transmitted by the signal input circuit and the first protection signal of the detection circuit. When the first drive signal is a signal for turning on the first MOS tube, the first protection signal is enabled. When the first drive signal is a signal for turning off the first MOS tube, the first protection signal is disabled. One end of the latch is connected to the signal control element and the signal input circuit respectively, and the other end is connected to the gate of the first MOS tube. When the first protection signal is enabled, the latch latches the first protection signal and outputs it to the first MOS tube, so that the first MOS tube is in a current protection state. When the first protection signal is disabled, the first drive signal is transmitted to the first MOS tube, so that the first MOS tube is driven to turn on or turn off based on the first drive signal. In this technical solution, the latch circuit in the high-side drive chip can quickly protect the high-side IGBT tube in an abnormal state, and can automatically recover the control based on the driving characteristics of the MOS tube. Thus, the problem of the high-side power switching element being unable to recover in time and affecting the performance and stability of the entire IPM circuit can be effectively solved. In addition, the detection circuit and the latch circuit in the embodiment are integrated in the high-side drive chip, without the need to increase additional terminals to receive external detection signals or recovery signals, while meeting the small packaging requirements of the IPM.

[0039] The technical solutions of the present application will be described in detail below in combination with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0040] Figure 1An IPM based on latch control is shown in the embodiments of the present application, as shown in Figure 1 The IPM 100 includes a first MOS tube 110 and a high-side drive chip 120 for driving the first MOS tube 110, a second MOS tube 130 and a low-side drive chip 140 for driving the second MOS tube 130. The drain of the first MOS tube 110 is connected to a power supply, the source of the second MOS tube 130 is grounded, and the source of the first MOS tube 110 is connected to the drain of the second MOS tube 130, so that the first MOS tube 110 and the second MOS tube 130 are connected in series. The high-side drive chip 120 includes a signal input circuit 121, a detection circuit 122 and a latch circuit 123. The latch circuit 123 includes a signal control element 1231 and a latch 1232. One end of the detection circuit 122 is connected to a connecting wire between the first MOS tube 110 and the second MOS tube 130, and the other end is connected to the signal control element 1231, for detecting the source potential change of the first MOS tube 110 and outputting a first protection signal to the signal control element 1231 according to the source potential change. One end of the signal control element 1231 is connected to the detection circuit 122 and the signal input circuit 121 respectively, and the other end is connected to the latch 1232, for receiving a first drive signal transmitted by the signal input circuit 121 and the first protection signal of the detection circuit 122. When the first drive signal is a signal for turning on the first MOS tube 110, the first protection signal is enabled. When the first drive signal is a signal for turning off the first MOS tube 110, the first protection signal is disabled. One end of the latch 1232 is connected to the signal control element 1231 and the signal input circuit 121 respectively, and the other end is connected to the gate of the first MOS tube 110. When the first protection signal is enabled, the first protection signal is latched and output to the first MOS tube 110, so that the first MOS tube 110 is in a current protection state. When the first protection signal is disabled, the first drive signal is latched and transmitted to the first MOS tube 110, so that the first MOS tube 110 is turned on or turned off based on the first drive signal.

[0041] A latch is a pulse-level-sensitive bistable circuit with two stable states: 0 and 1. Once a state is determined, it maintains its position until a specific external input pulse level is applied to a certain position in the circuit, at which point it may change state. This embodiment leverages the circuit characteristics of a latch and integrates the corresponding detection circuit and latch circuit into the high-side driver chip to effectively achieve efficient current protection and fast recovery of the first MOS transistor.

[0042] In this embodiment, the high-side driver chip and the first MOS transistor, the low-side driver chip and the second MOS transistor form a half-bridge circuit and are connected to a load. Under normal operating conditions, the first MOS transistor and the second MOS transistor are turned on or off based on the driving action of their respective driver chips, thereby driving the load. When the load connected to the first MOS transistor is abnormal (such as a load short circuit), the Vs potential of the first MOS transistor will change: for example, under normal operating conditions, the Vs potential is a high potential (such as 20V, which can be determined based on the adaptability of the actual application). When the load is short-circuited, the current increases sharply, causing the Vs potential to drop sharply. The detection circuit 123 quickly determines the abnormal state of the first MOS transistor by detecting the Vs potential. The detection circuit 123 sends a first protection signal corresponding to the change in the Vs potential to the latch circuit 122. The signal control element controls the first protection signal (Vsen) output by the detection circuit 123 to be valid when the signal state of the first drive signal (HIN) is the signal state (e.g., a high-level signal that turns on the MOS transistor, or a low-level signal that turns off the MOS transistor) when the signal turns on the MOS transistor. That is, when HIN is the on signal, the detection circuit 123 synchronously receives the Vsen signal (if any) output by the detection circuit, and latches the first protection signal (which can be obtained through a driver corresponding to the first MOS transistor, i.e., the first high-side driver module mentioned later) into the first MOS transistor, thereby placing the first MOS transistor in a protection state (e.g., if the first protection signal is a low-level signal, the signal output from the latch will always keep the first MOS transistor in the off state). Even if the current first drive signal is a signal that turns on the first MOS transistor, the first MOS transistor will still be in the power-off state. Next, after the first MOS transistor is placed in the current protection state, the signal control element monitors the first drive signal and, when the currently input first drive signal is an OFF signal for shutting down the first MOS transistor, invalidates the first protection signal, that is, the latch circuit does not receive the first protection signal, and the latch no longer latches the first protection signal. This allows the first MOS transistor to automatically recover from the high-side MOS transistor when HIN is an OFF signal. In this way, it is possible to effectively avoid the problem that the high-side MOS transistor is in a power-off state for a long time after being placed in the current protection state, thereby affecting the performance and stability of the entire system.

[0043] When the first MOS transistor is turned on by the HIN signal, the Vsen signal (an overcurrent detection signal generated according to the change of Vs, i.e. the first protection signal) is transmitted from the output part of the latch circuit to the first MOS transistor (or the high-side drive part of the first MOS transistor). Since the Vsen signal is transmitted from the latch, the first MOS transistor is turned off regardless of the state of HIN. When the HIN signal is in the OFF state for the first MOS transistor, the Vsen signal is cut off by the analog switch, and then, when the HIN signal becomes in the ON state, the ON signal of the first MOS transistor is transmitted from the output part to the high-side gate drive part due to the latch circuit module, and the first MOS transistor returns to the on state.

[0044] It can be understood that, when the Vsen signal is valid, the signal latched in the latch includes HIN and Vsen, and when the signal is output to the first MOS transistor, the first MOS transistor is turned off based on the Vsen signal, so that the first MOS transistor is in a protection state regardless of the signal state of HIN. When the non-protection signal output by the detection circuit, i.e. the signal when no excessive current is detected, it is always synchronized with the HIN signal, and the latch action of HIN is used to control the turn-on or turn-off of the IGBT. When the first MOS transistor is in the OFF state, the Vsen signal is disabled, the latch only receives the HIN signal, and the latched signal is synchronized with the HIN signal. When HIN is in the on signal, the first MOS transistor can quickly restore the on state. In addition, when the Vsen signal does not detect excessive current, it is always synchronized with the HIN signal, and the latch action of HIN can be used to control the turn-on or turn-off of the first MOS transistor.

[0045] Further as shown in Figure 2 The high-side drive chip 120 can further include a filter circuit 124, one end of the filter circuit 124 being connected to the signal input circuit 121, and the other end of the filter circuit 124 being connected to the latch circuit 122, so that the latch circuit 122 receives the filtered first drive signal after filtering the first drive signal by the filter circuit 124.

[0046] In the embodiment, the filter circuit can include a dead time and a low pass filter (DT&LPF), wherein the dead time is a short delay time set when switching the first MOS tube and the second MOS tube to avoid short circuit caused by the simultaneous conduction of the two MOS tubes. The setting of the dead time can effectively prevent the simultaneous conduction of the two switching devices in the circuit, thereby avoiding transient overcurrent and damaging the circuit; the low pass filter can filter out high-frequency noise or interference signals to ensure the stability and accuracy of the output signal, and allows low-frequency signals to pass while preventing high-frequency signals to pass to achieve the filtering effect. When driving the first MOS tube, the low pass filter can help smooth the output signal, reduce electromagnetic interference, and improve the performance and stability of the system.

[0047] In the embodiment, the signal control element 1231 is an analog switch, which is specifically used to connect the detection circuit 123 when the first drive signal is a signal for turning on the first MOS tube 110, so that the first protection signal output by the detection circuit 123 is valid, and disconnect the detection circuit 123 when the first drive signal is a signal for turning off the first MOS tube 110, so that the first protection signal output by the detection circuit 123 is invalid.

[0048] In the embodiment, the analog switch is connected with the detection circuit to make the first protection signal (Vsen) valid only when the first drive signal (HIN) for driving the first MOS tube makes the first MOS tube ON. In some embodiments, the signal control element can also use a flip-flop or a logic gate circuit element to realize the control signal, and the embodiment does not particularly limit this.

[0049] Further exemplarily, the high-side drive chip 120 can further include a level conversion circuit 125 and a high-side drive module 126, one end of the level conversion circuit 125 is connected to the latch circuit 122, and the other end of the level conversion circuit 125 is connected to one end of the high-side drive module 120; the other end of the high-side drive module 126 is connected to the gate of the first MOS tube 110, so that the latch circuit 122 is connected to the gate of the first MOS tube 110 through the level conversion circuit 125 and the high-side drive module 126, the level conversion circuit 125 is used for performing level conversion on the first drive signal transmitted by the latch circuit 122, and the high-side drive module 126 is used for driving the first MOS tube 110 to turn on or turn off according to the first drive signal after level conversion.

[0050] In the embodiment, the level conversion circuit 125 can include a high level conversion logic module and a high level conversion module connected in sequence. The high level conversion logic module can be a logic gate circuit, which is used to control the level of the output signal according to the logic state (such as logic high or logic low) of the input signal, so that the input driving signal can meet the control logic requirements of the first MOS tube; the high level conversion module can include a level shifter or an amplifier circuit, which converts the logic level signal after the high level conversion logic into a high level signal sufficient to drive the first MOS tube, so that the turn-on and turn-off process of the first MOS tube is stable and reliable, and the misoperation or damage is avoided.

[0051] In the embodiment, the high side drive module 126, i.e. the high side gate drive, can drive the turn-on and turn-off of the MOS tube according to the level state of the driving signal (through signal amplification, buffering, etc.), or turn off the MOS tube according to the first protection signal.

[0052] Further, the high side drive chip 120 can further include a pull-up resistor (Reg) 127, one end of which is connected to the power supply end (VCC) of the high side drive chip 120, and the other end of which is connected to the signal input circuit 121, the latch circuit 122 and the level conversion circuit 125. The pull-up resistor Reg and the level conversion circuit are used to maintain the signal state corresponding to the pull-up resistor when the first protection signal is invalid.

[0053] In the embodiment, the connection mode of the pull-up resistor Reg and the latch circuit can be, for example, as shown in Figure 3a The pull-up resistor Reg is connected between the signal control element (such as an analog switch) 1221 and the latch 1222. When the 4HIN signal opens the signal control element 1221, the first protection signal is transmitted, but when it is closed, the output of the signal control element 1221 is in an open circuit state. By connecting the Reg pull-up resistor in the latch, the state when the switch is closed can be determined. In other words, when the switch is closed, the state of this part becomes the Reg voltage, and the connected circuit is kept at a high level (which can be at a potential state of about 0V (low level) or about 5V (high level)), which can effectively improve the stability of the circuit.

[0054] Alternatively, the power supply VCC can supply the driving power VB to the gate of the first MOS tube through the diode circuit (BSD&R) amplification, and output the first driving signal HO to the high side MOS tube to turn on or turn off the high side MOS tube.

[0055] The timing diagram for current protection and recovery control of the first MOS tube based on the above circuit structure is as shown in Figure 3bAs shown, after the first MOS tube detects the change of Vs potential, the first MOS tube is turned off based on the latching of the first protection signal (Vsen), and automatically resumes control when HIN is in the IGBT OFF state, (although the first MOS tube is turned off, the drive resumes operation) until the IGBT is in the ON state, and turns on.

[0056] In some embodiments, as Figure 3c As shown, the latch circuit 122 can further include a timer 1223, one end of which is connected to the signal control element 1221, and the other end is connected to the latch 1224, so that the other end of the signal control element 1221 is connected to the latch 1224 through the timer 1223; the timer 1223 is used to generate a blocking signal about the preset protection time when receiving the first protection signal, the blocking signal is used to place the first MOS tube 110 in the current protection state within the preset protection time, and when the first protection signal in the latch 1222 is invalid and the preset protection time is not reached, the first MOS tube 110 continues to be placed in the current protection state until the preset protection time is reached.

[0057] In this embodiment, by adding a timer, the first MOS tube is quickly restored to operation when the HIN signal is the OFF signal of the first MOS tube after a certain time of cutting off. Specifically, when the first MOS tube drive signal (HIN) is in MOS ON, the overcurrent detection signal (Vsen) is valid due to the circuit such as analog switch. When the first MOS tube is turned on by the HIN signal, the Vsen signal generates an overcurrent detection signal (OFF) when the timer circuit works, and forms a blocking signal to turn off the first MOS tube within the preset protection time (i.e. OFF time, which can be determined adaptively by those skilled in the art in combination with actual application). The signal is transmitted to the high-side gate drive part through the latch, and no matter the state of HIN, the first MOS tube will be turned off within the preset time. But when the OFF timer cutoff time (OFF time) is over, the first MOS tube is still in the off state due to the working state of the latch (the first protection signal is valid). If the operation of the first MOS tube resumes first after the OFF timer (OFF time) is over, the HIN signal can be transmitted to the high-side gate drive part to turn on the first MOS tube and resume operation by setting the latch circuit or flip-flop circuit when the HIN signal is switched from OFF to ON. The timing diagram of the latch circuit with the added timer can be combined with Figure 3d As shown.

[0058] Optionally, as Figure 4aAs shown, the detection circuit 122 comprises a constant voltage source circuit 311, a current control circuit 312 and a potential detection circuit 313; wherein the current control circuit 312 comprises a current control element 3121 and an operational amplifier 3122 electrically connected to the current control element 3121; one end of the current control circuit 312 is connected to the wire between the first MOS tube 110 and the second IGBT tube 130 (i.e. connected to the source of the first MOS tube 110 in the figure) through the current control element 3121, for detecting the Vs potential of the first MOS tube 110, and the other end is connected to the constant voltage source circuit 311 through the operational amplifier 3122; one end of the potential detection circuit 313 is connected to the current control element 3121, and the other end is connected to the latch circuit 122; when the Vs potential of the first MOS tube changes, the operational amplifier 3122 outputs a corresponding level signal to the current control element 3121 based on the constant voltage source circuit 311, so as to adjust the resistance value of the current control element 3121 and provide a constant current for the current path; the potential detection circuit 313 detects the change of the gate potential of the current control element 3121 after the resistance value is adjusted, and detects the change of the Vs potential of the first MOS tube 110 according to the change of the gate potential.

[0059] The detection circuit in the embodiment can be connected to the wire connected with the first MOS tube and the second MOS tube through the high-side floating power backflow terminal of the high-side drive chip, without the need to add a new terminal in the high-side drive chip to detect the Vs potential of the first BJT.

[0060] Specifically, in combination with Figure 4bAs shown, the current control circuit 312 uses a voltage divider circuit to achieve current control. Specifically, the current control circuit 312 also includes a first resistor R1 and a second resistor R2. The current control element 3121 is a MOS switch tube M1; the constant voltage source circuit 311 includes a first constant voltage source V2; wherein, one end of the first resistor R1 is connected to the wire between the first power switch element 320 and the second power switch element 350, and the other end is connected to the drain of the second MOS tube, so that the MOS switch tube M1 is connected to the wire between the first power element 330 and the second power element 350 through the resistor R1; the second resistor R2, one end of which is connected to the MOS switch The source of the MOS switch tube M1 is connected to the ground terminal, and the other end thereof is connected to the ground terminal; the first input end of the operational amplifier U2 (i.e., the operational amplifier 3122) is connected to the wire between the source of the MOS switch tube M1 and the second resistor R2; the second input end thereof is connected to the first constant voltage source V2; and the output end thereof is connected to the wire between the gate of the MOS switch tube M1 and the potential detection circuit 313; when the gate of the MOS switch tube M1 receives the level signal output by the operational amplifier U2, the potential of the gate of the MOS switch tube M1 is controlled to be turned on by rising potential or to be turned off by falling potential, so as to adjust to the resistance value.

[0061] In this embodiment, R1 (e.g., 5kΩ), M1, and R2 (e.g., 22Ω) form a voltage divider circuit. By controlling the on / off state of the MOS tube, the current in the R1, M1 loop, and R2 is always the same. When the potential of Vs is high enough (normal state), the operational amplifier U2 reduces the gate potential of M1, so that the constant current determined by R2 and V2 is constant. Flowing in this path. Clearly, the current flowing here is also limited by R1. Therefore, when the Vs potential drops (due to an abnormal condition such as a load short circuit) and the current limited by R1 is less than the constant current determined by R2 and V2, operational amplifier U2 controls the rising potential (i.e., the gate potential of M1) to fully turn M1 on (i.e., turn it on), reducing M1's resistance and thus ensuring a constant current throughout the current path.

[0062] Further, the potential detection circuit 313 comprises a third resistor R3 and a fourth resistor R4; one end of the third resistor R3 is connected to the gate of the MOS switch M1, and the other end of the third resistor R3 is connected to the fourth resistor R4; the output end of the operational amplifier U2 is specifically connected to the wire between the gate of the MOS switch M1 and the third resistor R3; and the latch circuit is specifically connected to the wire between the third resistor and the fourth resistor, so that the detection circuit is connected to the latch circuit; wherein the potential change (VR4) of the connection point of the wire between the third resistor and the fourth resistor connected to the latch circuit corresponds to the potential change Vg of the gate, and the potential change Vg of the gate is used to determine the potential change Vs of the second end.

[0063] In this embodiment, the potential detection circuit 313 can adopt a voltage dividing circuit with M1 (gate) to achieve the detection of the potential of M1. Specifically, the potential detection circuit 313 comprises R3 (such as 300Ω) and R4 (such as 200Ω) connected in series with M1 (gate), and the potential point Vg of M1 (gate) and the potential point VR4 of R4 are connected to the wire between the third resistor and the fourth resistor. R4 The voltage dividing circuit utilizes the potential of R4, and according to the principle of the voltage dividing circuit, the current of the Vg point is equal to the current of the VR4 point, that is, Vg / (R3+R4)=VR4 / R4. By detecting the voltage change of the VR4 point, the voltage change of the Vg point can be obtained. R4 The voltage dividing circuit utilizes the potential of R4, and according to the principle of the voltage dividing circuit, the current of the Vg point is equal to the current of the VR4 point, that is, Vg / (R3+R4)=VR4 / R4. By detecting the voltage change of the VR4 point, the voltage change of the Vg point can be obtained.

[0064] In other embodiments, the potential detection circuit can adopt other potential detection structures in addition to the above-mentioned circuit structure, which will not be described here.

[0065] In an optional implementation of one embodiment, the potential detection circuit 313 further comprises an inverter A1; the input end of the inverter A1 is connected to the wire between the third resistor R3 and the fourth resistor R4, and the output end of the inverter A1 is connected to the latch circuit, so that the latch circuit is connected to the wire between the third resistor R3 and the fourth resistor R4 through the inverter, and the inverter A1 is used to invert the potential change Vg of the gate to obtain the first cut-off signal and output the first cut-off signal to the high-side drive chip. Specifically, the inverted potential change (the output signal of the potential detection circuit 313, SEN) corresponds to the Vs potential change, and the SEN signal is output to the latch circuit to achieve current protection of the high-side power element.

[0066] As can be understood, in the above-mentioned embodiments, it has been mentioned that when the Vs potential sharply decreases, the gate potential of M1 needs to be raised by the operational amplifier outputting a high level, that is, when the Vs potential is low, the Vg potential is high, and the two are negatively correlated, while the Vg potential and the Vs potential are positively correlated.R4 The voltage is inversely proportional to the voltage, so the V R4 or its corresponding Vg potential and the final need to detect the Vs potential is opposite, in order to further improve the output efficiency of the cut-off signal, the embodiment increases the inverter A1, by inverting the V R4 potential, get V SEN output, can be directly used as Vs potential corresponding cut-off signal output.

[0067] In other embodiments, the inverter can not be set, by other processing of V R4 potential as the cut-off signal output.

[0068] Further, the detection circuit can also include: a capacitor C1, one end connected to the latch circuit and the third resistor, the second resistor connected to the wire, the other end connected to the ground terminal, for filtering the detected voltage change of the fourth resistor. In this embodiment, the capacitance of the capacitor C1 can be 100p or other values, C1 as a filter capacitor, by filtering can realize the removal or amplification of the signal, so that the output signal is more accurate.

[0069] Further, the constant voltage source circuit 311 also includes a second constant voltage source V1; the operational amplifier U2, the third input end is connected to the second constant voltage source V1, the fourth input end is connected to the ground terminal, so that its output end to the current control element output the second constant voltage or the ground terminal corresponding to the level signal.

[0070] In combination Figure 4b As shown, the operational amplifier U2 includes four input terminals, two signal input terminals (positive input terminal and negative input terminal), two power input terminals (positive power input terminal and negative power input terminal), wherein the positive input terminal (i.e. the second input terminal) and the negative input terminal (i.e. the first input terminal) are connected to the branch of M1 and R2, and the first constant voltage source V2. By comparing the voltage between R2 and the first constant voltage source, when the voltage at R2 point drops to less than V2 (for example, V2 is a constant voltage source of 0.5V, and R2 voltage is less than 0.5V), the second constant voltage source V1 (such as 12V) connected to the positive power input terminal outputs a high level of 12V at the output end, so that the gate voltage of M1 rises, and then the current in the current path is constant. In the example of Figure 4b , a third constant voltage source V3 is also provided, one end of the third constant voltage source V3 is connected to Vs, and the other end is grounded.

[0071] In the above embodiment, the IPM structure corresponding to the half-bridge circuit is shown, and the first MOS tube is overcurrent protected and fast recovery controlled. The embodiments of the present application will be described in combination with the full-bridge circuit.

[0072] Figure 5 Another structure diagram of the IPM provided by the embodiment is shown, and on the basis of the above embodiment, in addition to the above circuit elements, the IPM 100 of the embodiment can further include a third MOS tube 150 and a fourth MOS tube 160; wherein the drain of the third MOS tube 150 is connected to a power supply (VDC), the source of the fourth MOS tube 150 is grounded, the source of the third MOS tube 150 is connected to the drain of the fourth MOS tube 160, so that the third MOS tube 150 and the fourth MOS tube 160 are connected in series; the detection circuit 123 is further connected to the connecting wire between the third MOS tube 150 and the fourth MOS tube 160 at one end, for detecting the source potential change of the third MOS tube 150, and outputting a second protection signal to the signal control element 1221 according to the source potential change; the signal control element 1221 is further used for receiving the second drive signal transmitted by the signal input circuit 121 and the second protection signal of the detection circuit 123, when the second drive signal is a signal for turning on the third MOS tube 150, the second protection signal is enabled; when the second drive signal is a signal for turning off the third MOS tube 150, the second protection signal is disabled; the latch 1222 is further connected to the gate of the third MOS tube 150 at the other end, for latching the second protection signal when the second protection signal is enabled, and outputting to the third MOS tube 150, so that the third MOS tube 150 is placed in a current protection state; and when the second protection signal is disabled, the second drive signal is transmitted to the third MOS tube 150, so as to drive the third MOS tube 150 to turn on or turn off based on the second drive signal.

[0073] Further, the low-side drive chip 140 drives the second MOS tube and the fourth MOS tube to turn on or turn off by receiving the third drive signal and the fourth drive signal, respectively.

[0074] It should be noted that the above full-bridge circuit structure provided by the embodiment has similar principles to the above embodiments, and the related content can be referred to the above embodiments. The circuit structure can realize current protection and fast recovery control for the high-side first MOS tube and the third MOS tube, effectively reduce the time delay of high-side MOS tube protection based on low-side drive chip, and realize fast recovery operation of high-side MOS tube. In some embodiments, the circuit structure provided by the embodiment can also be applied to a three-phase bridge circuit, and the principle is similar, which will not be described here.

[0075] Figure 6A flowchart of an IPM recovery control method provided by an embodiment of the present application is shown. The IPM provided by the embodiment includes a first MOS tube, a high-side drive chip for driving the first MOS tube, a second MOS tube, and a low-side drive chip for driving the second MOS tube. The drain of the first MOS tube is connected to a power supply, the source of the second MOS tube is grounded, the source of the first MOS tube is connected to the drain of the second MOS tube, so that the first MOS tube and the second MOS tube are connected in series. The high-side drive chip includes a signal input circuit, a detection circuit, and a latch circuit. The latch circuit includes a signal control element and a latch. As shown in Figure 6 The method provided by the embodiment can include the following steps:

[0076] In step S601, the detection circuit detects a source potential change of the first MOS tube, and outputs a first protection signal to the signal control element according to the source potential change.

[0077] In step S602, the signal control element receives a first drive signal transmitted by the signal input circuit. When the first drive signal is a signal for turning on the first MOS tube, the signal control element makes the first protection signal output by the detection circuit valid. When the first drive signal is a signal for turning off the first MOS tube, the signal control element makes the first protection signal output by the detection circuit invalid.

[0078] In step S603, the latch latches the first protection signal when the first protection signal is valid, and outputs the latched first protection signal to the first MOS tube, so that the first MOS tube is in a current protection state.

[0079] In step S604, the latch latches the first drive signal when the first protection signal is invalid, and transmits the latched first drive signal to the first MOS tube, so that the first MOS tube is driven to turn on or turn off based on the first drive signal.

[0080] It should be noted that the above method provided by the embodiment of the present application has similar implementation principles and technical effects to the above IPM embodiment, and the related descriptions can be referred to the description of the above IPM embodiment, which will not be repeated here. Figures 1-5

[0081] In a third aspect, the embodiment of the present application further provides a computer readable storage medium, which includes computer execution instructions stored on the computer readable storage medium. When the computer execution instructions are executed by a processor, the IPM recovery control method is implemented.

[0082] ​The computer readable storage medium can include a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various storage medium capable of storing program codes. Specifically, the computer readable storage medium stores program instructions, which are used for recovery control in the above embodiments. For details, please refer to the description of the above embodiments. Figures 1-5 The above description of the system is similar to the description of the above IPM embodiments. For details, please refer to the description of the above embodiments.

[0083] Figure 7 The structure of the IPM control system is shown in the schematic diagram of the control system of the IPM provided by the embodiments of the present application. As shown in the figure, the IPM control system 1000 can include the IPM 100 and a load device 200, and the load device 200 is electrically connected with the first MOS tube. Figure 7

[0084] It should be noted that the above system provided by the embodiments of the present application has similar implementation principles and technical effects to the above IPM embodiments. For details, please refer to the description of the above embodiments. Figures 1-5

[0085] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, but not to limit them; although the above embodiments of the present application have been described in detail, those skilled in the art should understand that: they can still modify the technical solutions recorded in the above embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

[0086] In order to facilitate explanation, the above description has been combined with specific embodiments. However, the above exemplary discussion is not intended to exhaust or limit the embodiments to the specific forms disclosed above. According to the above teaching, various modifications and variations can be obtained. The selection and description of the above embodiments are to better explain the principles and practical applications, so that those skilled in the art can better use the embodiments and various different modified embodiments suitable for specific use considerations.​​

Claims

1. An intelligent power module (IPM) based on latch control, characterized in that: The invention comprises a first MOS transistor and a high-side driver chip for driving the first MOS transistor, a second MOS transistor and a low-side driver chip for driving the second MOS transistor; wherein the drain of the first MOS transistor is connected to a power supply, the source of the second MOS transistor is grounded, the source of the first MOS transistor is connected to the drain of the second MOS transistor, so that the first MOS transistor and the second MOS transistor are connected in series; the high-side driver chip comprises a signal input circuit, a detection circuit and a latch circuit; the latch circuit comprises a signal control element and a latch; The detection circuit has one end connected to the connecting wire between the first MOS transistor and the second MOS transistor, and the other end connected to the signal control element, and is used to detect the source potential change of the first MOS transistor and output a first protection signal to the signal control element according to the source potential change; The signal control element has one end connected to the detection circuit and the signal input circuit respectively, and the other end connected to the latch, and is used to receive the first drive signal transmitted by the signal input circuit and the first protection signal of the detection circuit, and when the first drive signal is a signal for turning on the first MOS transistor, the first protection signal is enabled; when the first drive signal is a signal for turning off the first MOS transistor, the first protection signal is disabled; The latch has one end connected to the signal control element and the signal input circuit respectively, and the other end connected to the gate of the first MOS transistor, and is used to latch the first protection signal when the first protection signal is valid and output it to the first MOS transistor, so that the first MOS transistor is placed in a current protection state; and when the first protection signal is invalid, transmit the first drive signal to the first MOS transistor, so as to drive the first MOS transistor to be turned on or off based on the first drive signal.

2. The IPM according to claim 1, wherein: The signal control element is an analog switch, which is specifically used to connect the connection between the detection circuit and the detection circuit when the first drive signal is a signal for turning on the first MOS transistor, so that the first protection signal output by the detection circuit is valid; and to disconnect the connection between the detection circuit and the detection circuit when the first drive signal is a signal for turning off the first MOS transistor, so that the first protection signal output by the detection circuit is invalid.

3. The IPM according to claim 1 or 2, characterized in that The latch circuit further includes a timer having one end connected to the signal control element and another end connected to the latch, such that the other end of the signal control element is connected to the latch through the timer; The timer is configured to generate a blocking signal for a preset protection time upon receiving the first protection signal, wherein the blocking signal is configured to place the first MOS transistor in a current protection state within the preset protection time; and when the first protection signal in the latch fails and the preset protection time has not been reached, the first MOS transistor continues to be placed in the current protection state until the preset protection time is reached.

4. The IPM according to claim 1 or 2, characterized in that Also included is a filter circuit; One end of the filter circuit is connected to the signal input circuit, and the other end is connected to the latch circuit, so that the latch circuit receives the filtered first drive signal after filtering the first drive signal through the filter circuit.

5. The IPM according to claim 1 or 2, characterized in that: It also includes a level conversion circuit and a high-side driving module, wherein one end of the level conversion circuit is connected to the latch circuit, and the other end is connected to one end of the high-side driving module; the other end of the high-side driving module is connected to the gate of the first MOS tube, so that the latch circuit is connected to the gate of the first MOS tube through the level conversion circuit and the high-side driving module, the level conversion circuit is used to perform level conversion on the first driving signal transmitted by the latch circuit, and the high-side driving module is used to drive the first MOS tube to be turned on or off according to the first driving signal after level conversion.

6. The IPM according to claim 5, wherein: It also includes a pull-up resistor, one end of which is connected to the power supply terminal of the high-side driver chip, and the other end of which is connected to the signal input circuit, the latch circuit and the level conversion circuit. The pull-up resistor and the level conversion circuit are used to maintain the signal state corresponding to the pull-up resistor when the first protection signal fails.

7. The IPM according to claim 1 or 2, characterized in that: The device further includes a third MOS transistor and a fourth MOS transistor; wherein the drain of the third MOS transistor is connected to a power supply, the source of the fourth MOS transistor is grounded, and the source of the third MOS transistor is connected to the drain of the fourth MOS transistor, so that the third MOS transistor and the fourth MOS transistor are connected in series; The detection circuit, one end of which is further connected to the connecting wire between the third MOS transistor and the fourth MOS transistor, is used to detect the source potential change of the third MOS transistor and output a second protection signal to the signal control element according to the source potential change; The signal control element is further configured to receive a second drive signal transmitted by the signal input circuit and a second protection signal of the detection circuit, and to enable the second protection signal when the second drive signal is a signal for turning on the third MOS transistor; and to disable the second protection signal when the second drive signal is a signal for turning off the third MOS transistor; The latch, whose other end is also connected to the gate of the third MOS transistor, is used to latch the second protection signal when the second protection signal is valid and output it to the third MOS transistor, so that the third MOS transistor is placed in a current protection state; and when the second protection signal is invalid, transmit the second drive signal to the third MOS transistor to drive the third MOS transistor to be turned on or off based on the second drive signal.

8. A recovery control method for IPM, characterized in that: The IPM includes a first MOS transistor and a high-side driver chip for driving the first MOS transistor, a second MOS transistor and a low-side driver chip for driving the second MOS transistor; wherein the drain of the first MOS transistor is connected to a power supply, the source of the second MOS transistor is grounded, and the source of the first MOS transistor is connected to the drain of the second MOS transistor, so that the first MOS transistor and the second MOS transistor are connected in series; the high-side driver chip includes a signal input circuit, a detection circuit and a latch circuit; the latch circuit includes a signal control element and a latch; the method includes: The detection circuit detects a change in the source potential of the first MOS transistor and outputs a first protection signal to the signal control element according to the change in the source potential; The signal control element receives a first drive signal transmitted by the signal input circuit, and when the first drive signal is a signal for turning on the first MOS transistor, enables the first protection signal output by the detection circuit; and when the first drive signal is a signal for turning off the first MOS transistor, disables the first protection signal output by the detection circuit; When the first protection signal is valid, the latch latches the first protection signal and outputs the latched first protection signal to the first MOS transistor, so that the first MOS transistor is placed in a current protection state; When the first protection signal is invalid, the latch latches the first drive signal and transmits the latched first drive signal to the first MOS transistor to drive the first MOS transistor to be turned on or off based on the first drive signal.

9. A computer-readable storage medium, characterized in that The computer-readable storage medium stores computer-executable instructions, and when the computer-executable instructions are executed by a processor, the IPM recovery control method according to claim 8 is implemented.

10. An IPM control system, characterized in that: The method comprises the IPM according to any one of claims 1 to 7 and a load device, wherein the load device is electrically connected to the first MOS transistor.

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