Chip packaging structure, electronic device and manufacturing method of chip packaging structure

Abstract

The present application provides a chip packaging structure, an electronic device and a method for manufacturing a chip packaging structure, which relates to the field of packaging technology and is used to solve the problem of how to improve the reliability of the chip packaging structure. The chip packaging structure includes a substrate, at least one first chip, a first plastic package and a metal connection structure. The substrate has a first surface. At least one first chip includes a filter chip, and at least one first chip is arranged on the first surface and has a first gap with the first surface. The first plastic package has a second surface, the second surface faces the first surface, and the second surface has at least one groove. The first plastic package is connected to the substrate through a metal connection structure, and at least one first chip is accommodated in the at least one groove.

Description

Technical Field

[0001] The present application relates to the field of packaging technology, and in particular to a chip packaging structure, an electronic device, and a method for manufacturing the chip packaging structure. Background Art

[0002] Electronic devices usually have a radio frequency transceiver system composed of multiple electronic components to receive and transmit wireless signals. The electronic components that make up the radio frequency transceiver system need to be packaged on a substrate to protect the electronic components. The radio frequency transceiver system usually has a filter chip for selecting preset frequency band signals.

[0003] In the related art, the filter chip is flipped on the substrate. Before the filter is encapsulated on the substrate by injection molding, a layer of organic film is covered on the substrate and the filter chip to form a cavity between the encapsulated filter chip and the substrate to prevent excessive signal loss during transmission. However, due to the large difference in thermal expansion coefficient between the organic film and the filter chip, when the temperature changes, the organic film will exert a large stress on the filter chip, causing the connection structure between the filter chip and the substrate to crack and fail easily, which in turn leads to low reliability of the overall packaging structure. Summary of the invention

[0004] The embodiments of the present application provide a chip packaging structure, an electronic device and a method for manufacturing the chip packaging structure, which are used to solve the problem of how to improve the reliability of the chip packaging structure.

[0005] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0006] In a first aspect, an embodiment of the present application provides a chip packaging structure, which includes a substrate, at least one first chip, a first plastic package, and a metal connection structure. The substrate has a first surface. At least one first chip includes a filter chip, and at least one first chip is arranged on the first surface and has a first gap with the first surface. The first plastic package has a second surface, the second surface faces the first surface, and the second surface has at least one groove. The first plastic package is connected to the substrate through a metal connection structure, and at least one first chip is provided in a groove.

[0007] The chip packaging structure provided by the embodiment of the present application is that the second surface of the first plastic package has at least one groove, the first plastic package is connected to the substrate through a metal connection structure, and at least one first chip is accommodated in the at least one groove, which is conducive to first making the first plastic package through a mold, and then connecting the first plastic package to the substrate through the metal connection structure. It is not necessary to cover the first chip with an organic film to realize that the first chip is packaged on the substrate through the first plastic package, and at the same time, there is a first gap between the filter chip and the substrate to ensure the performance of the filter chip. Therefore, when the temperature changes, the first chip will not be subjected to the stress applied by the organic film, so the risk of failure of the connection structure between the first chip and the substrate is reduced. In addition, when the first chip is not in contact with the first plastic package and the temperature changes, the first chip will not be subjected to the stress applied by the first plastic package, so the risk of failure of the connection structure between the first chip and the substrate is further reduced, and the reliability of the chip packaging structure is improved.

[0008] In addition, packaging the first chip with the first plastic packaging body is conducive to mass production of the first plastic packaging body through injection molding using the same mold. There is no need to etch individual sheet blanks one by one to form a packaging body. The process complexity is low, the processing efficiency is high, and the cost is low.

[0009] In some possible implementations of the first aspect, the metal connection structure includes a first metal connection member and a second metal connection member. The first metal connection member is disposed on the first plastic package. The second metal connection member is located on the substrate, and the second metal connection member is bonded or welded to the first metal connection member. In this way, the strength of the formed metal connection structure is relatively high, and the reliability of the connection between the first plastic package and the substrate is relatively good, further improving the reliability of the chip packaging structure. In addition, the metal connection structure also has a certain electromagnetic shielding effect, reducing the risk of electromagnetic interference between the first chips and between the first chip and the electronic components outside the chip packaging structure.

[0010] In some possible implementations of the first aspect, the second surface includes a first area and a second area connected to each other, the first metal connector covers the first area, and the groove wall of at least one groove forms at least a part of the second area. The chip packaging structure also includes a first metal layer, which is arranged on the second surface; the first metal layer includes a first part, and the first part covers the second area. In this way, the first part of the first metal layer and the first metal connector can form an electromagnetic shielding structure, which can not only prevent the first chips in different grooves from causing electromagnetic interference to each other, but also prevent the first chip in the chip packaging structure from causing electromagnetic interference to other electronic components outside the chip packaging structure. Therefore, while the first plastic package is connected to the substrate to encapsulate and protect the first chip, an electromagnetic shielding structure is formed, which simplifies the difficulty of making the electromagnetic shielding structure and improves the manufacturing efficiency of the chip packaging structure.

[0011] In some possible implementations of the first aspect, the first metal layer further includes a second portion, the second portion forms a first metal connector, and the first metal layer is an integrally formed structure. In this way, a continuous first metal layer covering the entire area of ​​the second surface can be formed by a process such as electroplating or deposition (such as physical vapor deposition), and the manufacturing process is simple, the manufacturing efficiency is high, and the manufacturing cost is low.

[0012] In some possible implementations of the first aspect, the chip packaging structure further includes a metal insert, which is embedded in the first plastic package, and the end face of the metal insert facing the first surface is exposed on the second surface; the first metal layer also covers the metal insert. In this way, when the first plastic package is connected to the substrate, the high temperature of bonding or welding can be prevented from causing the first plastic package to warp and deform, thereby squeezing the first chip, resulting in reduced connection reliability between the first chip and the substrate. In addition, the metal insert can also play a certain role in electromagnetic shielding, further reducing the risk of electromagnetic interference between the first chips.

[0013] In some possible implementations of the first aspect, the chip packaging structure further includes a metal insert, which is embedded in the first plastic package body, and the end face of the metal insert facing the first surface is exposed on the second surface, and the metal insert forms a first metal connector. In this way, when the first plastic package body is connected to the substrate, the high temperature of bonding or welding can be prevented from causing the first plastic package body to warp and deform, thereby squeezing the first chip, resulting in reduced connection reliability between the first chip and the substrate. In addition, the metal insert can also be reused as the first metal connector, simplifying the overall design and processing difficulty of the chip packaging structure. Finally, the metal insert can also play a certain role in electromagnetic shielding, further reducing the risk of electromagnetic interference between the first chips.

[0014] In some possible implementations of the first aspect, the first plastic package body further has a third surface opposite to the second surface, and a peripheral side surface connected between the third surface and the second surface, and a portion of the surface of the metal insert is exposed on the third surface and / or the peripheral side surface. The chip packaging structure also includes a second metal layer, and the second metal layer covers the third surface, the peripheral side surface and a portion of the surface of the metal insert. In this way, the second metal layer forms an electromagnetic shielding structure connected to the reference ground of the substrate through the metal insert outside the chip packaging structure, further reducing the risk of electromagnetic interference between the first chip and other electronic components, and ensuring the reliability of the chip packaging structure. In addition, by exposing a portion of the surface of the metal insert to the third surface and / or the peripheral side surface, the grounding path between the second metal layer and the substrate is shorter, and the electromagnetic shielding effect of the second metal layer is better.

[0015] In some possible implementations of the first aspect, the material of the metal insert includes at least one of lead, copper, silver, gold, nickel, palladium, and tin. In this way, the metal insert has good solderability and can ensure the connection reliability between the metal insert and the solder.

[0016] In some possible implementations of the first aspect, the first metal layer includes a first layer and a second layer stacked and bonded in sequence, the first layer is located on a side of the second layer away from the first plastic package body and facing the first surface; the first layer is one of a tin layer, a stainless steel layer, a nickel layer, a silver layer, a gold layer, and a lead layer, and the second layer is a copper layer. In this way, the first metal layer has good corrosion resistance or solderability, and also has good electromagnetic shielding effect.

[0017] In some possible implementations of the first aspect, the first metal layer further includes a third layer laminated and bonded between the second layer and the second surface, and the third layer is a stainless steel layer. In this way, the bonding force between the first metal layer and the first plastic package is relatively large, thereby ensuring the overall reliability of the chip packaging structure.

[0018] In some possible implementations of the first aspect, there are multiple first chips, and the multiple first chips include a non-filter chip. The chip packaging structure also includes at least one first filling body, and a first filling body fills a first gap between a non-filter chip and the first surface. In this way, the first filling body can not only support the non-filter chip, but also wrap the connection structure between the non-filter chip and the substrate to protect the connection structure, thereby improving the reliability of the structural connection and electrical connection between the non-filter chip and the substrate.

[0019] In some possible implementations of the first aspect, the metal connection structure includes a sealing section, which is arranged around at least one groove. In this way, the sealing section, the first surface of the substrate, and the second surface of the first plastic package body are arranged to form a sealed cavity, which can prevent water vapor from entering the cavity from the gap between the first plastic package body and the first surface to damage the first chip. In addition, the metal connection structure has a better water vapor isolation effect than the plastic forming the first plastic package body, thereby ensuring the reliability of the chip packaging structure.

[0020] In some possible implementations of the first aspect, the number of grooves is multiple, and the area on the second surface surrounded by the sealing section is the third area. The metal connection structure also includes a blocking section, which is located on the inner peripheral side of the sealing section. The blocking section cooperates with the sealing section to separate the third area into multiple sub-areas, and the groove wall of a groove forms at least a part of a sub-area. In this way, while increasing the connection reliability between the first plastic package body and the substrate, the peripheral side of each groove and the inner wall of the groove have a continuous electromagnetic shielding structure, which can prevent multiple first chips from causing electromagnetic interference to each other, and can also prevent the first chip from causing electromagnetic interference to the electronic components outside the chip packaging structure.

[0021] In some possible implementations of the first aspect, the packaging structure further includes a second chip and a second plastic package. The second chip is a non-filter chip, the second chip is arranged on the first surface and is located on the peripheral side of the first plastic package, and a second gap is provided between the second chip and the first surface. The second plastic package is injection-molded and connected to the first surface, and the second plastic package covers the second chip and the first plastic package and fills the second gap. The material of the first plastic package includes thermosetting plastic.

[0022] In this way, it is beneficial for the second plastic package to be directly formed on the first surface through the injection molding process to encapsulate the second chip in the substrate, and during the injection molding process, the material can fill the second gap to wrap the connection structure between the second chip and the substrate, which can reduce the risk of the second plastic package applying stress to the second chip due to temperature changes, resulting in cracking and failure of the connection structure between the second chip and the substrate, thereby ensuring the reliability of the chip packaging structure. In addition, by directly forming the second plastic package by injection molding on the first surface, the packaging process is simple, the efficiency is high, and the cost is low. Finally, by making the second plastic package cover the first plastic package, the second plastic package is simultaneously connected to the first surface and the first plastic package by injection molding, thereby improving the reliability of the second plastic package fixed to the substrate, thereby improving the overall reliability of the chip packaging structure while improving the appearance consistency of the chip packaging structure.

[0023] In some possible implementations of the first aspect, the chip packaging structure is a radio frequency module.

[0024] In some possible implementations of the first aspect, the substrate is a printed circuit board PCB or a redistribution layer RDL.

[0025] In a second aspect, an embodiment of the present application provides an electronic device, the electronic device comprising a first circuit board and a chip packaging structure. The chip packaging structure is the chip packaging structure described in any of the aforementioned implementations, and at least one first chip is electrically connected to the first circuit board.

[0026] Since the electronic device provided in the embodiment of the present application includes the chip packaging structure described in the above implementation method, the two can solve the same problem and achieve the same effect, which will not be repeated here.

[0027] In a third aspect, an embodiment of the present application provides a method for manufacturing a chip packaging structure, comprising: providing a chip structure to be packaged and a first plastic package structure respectively; wherein the chip structure to be packaged comprises a substrate and at least one first chip, the substrate has a first surface, the at least one first chip comprises a filter chip, the at least one first chip is arranged on the first surface and has a first gap with the first surface; the first plastic package structure comprises a first plastic package, the first plastic package has a second surface, and the second surface has at least one groove. The first surface of the chip structure to be packaged is faced to the second surface of the first plastic package structure, and the first plastic package is connected to the substrate through a metal connection structure; wherein the at least one first chip is accommodated in the at least one groove.

[0028] Since the manufacturing method of the chip packaging structure provided in the embodiment of the present application forms the chip packaging structure as described in the above implementation method, the two can solve the same problem and achieve the same effect, which will not be repeated here.

[0029] In some possible implementations of the third aspect, a first plastic package structure is provided, including: providing a mold, the mold cavity having a fourth surface, and the fourth surface having at least one first protrusion. Injecting material into the mold cavity through an injection molding process to form a first plastic package; wherein the fourth surface is used to mold at least a portion of the second surface, and the first protrusion is used to mold a groove. Forming a first metal layer on the second surface, the first metal layer includes a second part, the second part covers the peripheral area of ​​the groove on the second surface, and the second part forms a first metal connector. In this way, pre-fabricating the first plastic package through the mold is conducive to mass production of the first plastic package through the injection molding process using the same mold, and the package can be formed without etching a single sheet blank one by one, and the process complexity is low, the processing efficiency is high, and the cost is low. In addition, by forming a first metal layer on the second surface of the first plastic package to form a first metal connector, the manufacturing method of the first metal connector is simple and easy to implement.

[0030] In some possible implementations of the third aspect, the first metal layer further includes a first portion, and the first portion covers an area on the second surface that is not covered by the first metal connector. In this way, while forming the first metal connector for connecting the substrate, an electromagnetic shielding structure is also formed at the same time, which simplifies the difficulty of manufacturing the electromagnetic shielding structure and improves the manufacturing efficiency of the chip packaging structure.

[0031] In some possible implementations of the third aspect, before injecting material into the cavity of the first mold to form the first plastic package body through the injection molding process, providing the first plastic package body structure also includes: pre-setting a metal insert on the fourth surface. Forming the first plastic package body in the cavity of the mold through the injection molding process includes: forming the first plastic package body connected to the metal insert in the cavity of the mold through the injection molding process. Among them, the end face of the metal insert facing the first surface is exposed to the second surface of the first plastic package body, and the first metal layer also covers the metal insert. In this way, while the first plastic package body is formed by injection molding, the first plastic package body and the metal insert can form an integrated structure with good bonding strength, which can prevent the first plastic package body from warping and deforming and squeezing the first chip during the process of connecting the first plastic package body to the substrate, resulting in a reduction in the connection reliability between the first chip and the substrate. In addition, the metal insert can also play a certain role in electromagnetic shielding, further reducing the risk of electromagnetic interference between the first chips.

[0032] In some possible implementations of the third aspect, a first plastic package structure is provided, including: providing a first mold, the mold cavity of the first mold having a fourth surface, and the fourth surface having at least one first protrusion. A metal insert is pre-arranged on the fourth surface; the fourth surface is used to mold a partial area of ​​the second surface, and the first protrusion is used to mold a groove. A material is injected into the mold cavity of the first mold through an injection molding process to form a first plastic package connected to the metal insert; wherein the end surface of the metal insert facing the first surface is exposed to the second surface, and the metal insert forms a first metal connector. In this way, while the first plastic package is formed by injection molding, the first plastic package and the metal insert can form an integrated structure with good bonding strength, which can prevent the first plastic package from warping and deforming and squeezing the first chip during the process of connecting the first plastic package to the substrate, resulting in a reduction in the connection reliability between the first chip and the substrate. In addition, the metal insert can also play a certain role in electromagnetic shielding, further reducing the risk of electromagnetic interference between the first chips. Finally, the metal insert can also be reused as a first metal connector for connecting to the substrate, simplifying the overall design and manufacturing difficulty of the chip packaging structure.

[0033] In some possible implementations of the third aspect, providing the first plastic package structure further includes: forming a first metal layer on the second surface, the first metal layer covering an area on the second surface that is not covered by the first metal connector. In this way, before the first plastic package is connected to the substrate to package and protect the first chip, an electromagnetic shielding structure is formed in a one-step process, which simplifies the difficulty of manufacturing the electromagnetic shielding structure and improves the manufacturing efficiency of the chip packaging structure.

[0034] In some possible implementations of the third aspect, before pre-arranging the metal insert on the fourth surface, providing the first plastic sealing body structure also includes: forming a first release film on the fourth surface. Pre-arranging the metal insert on the fourth surface includes: attaching the metal insert to the first release film. After injecting material into the cavity of the first mold through an injection molding process to form a first plastic sealing body connected to the metal insert, providing the first plastic sealing body structure also includes: removing the mold and the first release film. In this way, by attaching the first release film on the fourth surface, it is easy to detach the first plastic sealing body and the metal insert from the mold. In addition, the metal insert can be fixed to the first release film by the adhesion of the first release film itself, which simplifies the setting method of the metal insert.

[0035] In some possible implementations of the third aspect, the substrate has a second metal connector. The first surface of the chip structure to be packaged faces the second surface of the first plastic package structure, and the first plastic package is connected to the substrate through the metal connection structure, including: solder is provided on the second metal connector and / or the first metal connector. The solder is melted to connect the solder to the first metal connector and the second metal connector to form a metal connection structure. In this way, the first plastic package is connected to the substrate through the metal connection structure formed by welding, which is easier to implement in terms of process and has higher connection reliability.

[0036] In some possible implementations of the third aspect, after forming the first plastic package in the cavity of the first mold by an injection molding process, providing the first plastic package structure also includes: providing a first jig, and supporting the surface of the first plastic package facing away from the second surface on the first supporting surface of the first jig. After the first surface of the chip structure to be packaged faces the second surface of the first plastic package structure, and the first plastic package is connected to the substrate by a metal connection structure, the method also includes: removing the first jig. In this way, the first jig can provide support for the first plastic package, which can prevent the first plastic package from deforming in subsequent process steps and affecting the yield rate of the chip packaging structure.

[0037] In some possible implementations of the third aspect, after forming the first plastic package body in the mold cavity by an injection molding process, the method further includes: thinning the first plastic package body to form a third surface facing away from the first surface, and exposing the end face of the metal insert away from the first surface to the third surface; wherein the first plastic package body also has a peripheral side surface connected between the third surface and the second surface. A second metal layer covering the third surface, the peripheral side surface and the metal insert is formed on the first plastic package body. In this way, the second metal layer forms an electromagnetic shielding structure connected to the substrate reference ground through the metal insert outside the chip packaging structure, further reducing the risk of electromagnetic interference between the first chip and other electronic components, and ensuring the reliability of the chip packaging structure.

[0038] In some possible implementations of the third aspect, there are multiple first chips, and the multiple first chips also include a non-filter chip. Before the first surface of the chip structure to be packaged faces the second surface of the first plastic package structure, and before the first plastic package is connected to the substrate through the metal connection structure, the method also includes: filling a first gap between the non-filter chip and the first surface with a medium to form a first filling body.

[0039] In this way, the first filling body can not only support the non-filter chip, but also wrap the connection structure between the non-filter chip and the substrate to protect the connection structure, thereby improving the reliability of the structural connection and electrical connection between the non-filter chip and the substrate.

[0040] In some possible implementations of the third aspect, the chip structure to be packaged further includes a second chip, the second chip is a non-filter chip, and the second chip is disposed on the first surface and has a second gap with the first surface. The method further includes: forming a second plastic package on the first surface by an injection molding process, and making the second plastic package cover the second chip, the first plastic package, and fill the second gap; wherein the material of the first plastic package includes thermosetting plastic.

[0041] In this way, the second plastic package can wrap the connection structure between the second chip and the substrate, which can reduce the risk of the second plastic package applying stress to the second chip due to temperature changes, resulting in cracking and failure of the connection structure between the second chip and the substrate, thereby ensuring the reliability of the chip packaging structure. In addition, by directly forming the second plastic package by injection molding on the first surface, the packaging process is simple, the efficiency is high, and the cost is low. Finally, by making the second plastic package cover the first plastic package, the second plastic package is simultaneously connected to the first surface and the first plastic package by injection molding, which improves the reliability of the second plastic package fixed to the substrate, thereby improving the overall reliability of the chip packaging structure while improving the appearance consistency of the chip packaging structure.

[0042] In some possible implementations of the third aspect, providing a chip structure to be packaged includes: providing a second jig, the second jig having a second supporting surface. Forming a redistribution layer RDL on the second supporting surface to obtain a substrate; wherein the substrate has a first surface facing away from the second supporting surface. Disposing at least one first chip on the first surface, and providing a first gap between the first chip and the first surface. After the first surface of the chip structure to be packaged faces the second surface of the first plastic package structure, and the first plastic package is connected to the substrate through a metal connection structure, the method further includes: removing the second jig.

[0043] In this way, the thickness of the substrate formed by RDL is relatively small, which is beneficial to reducing the overall thickness of the chip packaging structure, and further beneficial to reducing the thickness of the entire electronic device. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 A schematic diagram of the structure of an electronic device provided in some embodiments of the present application;

[0045] Figure 2 for Figure 1 A schematic structural diagram of a chip packaging structure of the electronic device shown;

[0046] Figure 3 for Figure 2 A cross-sectional structural diagram of the chip packaging structure at line AA shown;

[0047] Figure 4 for Figure 3 A schematic diagram of failure of a welding structure between a first chip and a substrate of the chip packaging structure shown;

[0048] Figure 5 for Figure 2 Another cross-sectional structure diagram of the chip package structure at line AA;

[0049] Figure 6 for Figure 1 Another structural schematic diagram of a chip packaging structure of the electronic device shown;

[0050] Figure 7 for Figure 6 A cross-sectional structural diagram of the chip packaging structure at line BB shown;

[0051] Figure 8 for Figure 1 Another structural schematic diagram of a chip packaging structure of the electronic device shown;

[0052] Fig. 9 for Figure 8 The cross-sectional structure diagram of the chip packaging structure at the CC line is shown;

[0053] Fig.10 for Figure 7 A schematic diagram of a stacked structure of the first metal layer of the chip packaging structure shown;

[0054] Fig.11 for Figure 7 A schematic diagram of another stacked structure of the first metal layer of the chip packaging structure shown;

[0055] Fig.12 for Figure 6 Another cross-sectional structure diagram of the chip packaging structure at line BB;

[0056] Fig.13 for Figure 6 Another cross-sectional structure diagram of the chip packaging structure at line BB;

[0057] Fig.14 for Figure 6 Another cross-sectional structure diagram of the chip packaging structure at line BB;

[0058] Fig.15 for Figure 6 Another cross-sectional structure diagram of the chip packaging structure at line BB;

[0059] Fig.16 for Figure 1 Another structural schematic diagram of a chip packaging structure of the electronic device shown;

[0060] Fig.17 for Fig.16 The cross-sectional structure diagram of the chip packaging structure at line DD is shown;

[0061] Fig.18 A schematic diagram of a method for manufacturing a chip packaging structure provided in some embodiments of the present application;

[0062] Fig.19 for Fig.14 One of the structural schematic diagrams of the manufacturing process of the chip packaging structure shown;

[0063] Fig. 20 for Fig.14 A second structural schematic diagram of a manufacturing process of the chip packaging structure shown;

[0064] Fig.21 for Fig.14 Another structural schematic diagram of the manufacturing process of the chip packaging structure shown;

[0065] Fig. 22 for Fig.14 Another structural schematic diagram of the manufacturing process of the chip packaging structure shown in the second;

[0066] Fig.23 for Fig.13 One of the structural schematic diagrams of the manufacturing process of the chip packaging structure shown;

[0067] Fig.24 for Fig.13 The second structural schematic diagram of the manufacturing process of the chip packaging structure shown;

[0068] Fig.25 for Figure 7 One of the structural schematic diagrams of the manufacturing process of the chip packaging structure shown;

[0069] Fig.26 for Figure 7 The second structural schematic diagram of the manufacturing process of the chip packaging structure shown;

[0070] Fig. 27 for Fig.15 One of the structural schematic diagrams of the manufacturing process of the chip packaging structure shown;

[0071] Fig.28 for Fig.15 The second structural schematic diagram of the manufacturing process of the chip packaging structure shown;

[0072] Fig.29 for Fig.17 One of the structural schematic diagrams of the manufacturing process of the chip packaging structure shown;

[0073] Fig.30 for Fig.17 The second structural schematic diagram of the manufacturing process of the chip packaging structure shown.

[0074] Reference numerals:

[0075] 100- electronic equipment;

[0076] 10- housing;

[0077] 20- a first circuit board;

[0078] 30-chip packaging structure; 30A-chip structure to be packaged; 31-substrate; 31A-welding structure; 31a-first surface; 31b-fifth surface; 311-first pad; 312-second metal connector; 313-second solder layer; 32-first chip; 32A-filter chip; 32B-non-filter chip; 32a-first cavity; 32b-second cavity; 32c-first gap; 321-second pad; 322-first support layer; 323-second support layer; 324-first metal column; 33-organic film; 34-plastic layer; 30B-first plastic body structure; 35-first plastic body; 35a-second surface; 35a1-groove; 35a2-first area; 35a3-second area; 35a4-third area; 35a41-sub-area; 35b-third surface; 35c-side surface; 36-first metal layer; 36a-first layer; 36b-second layer; 36c-third layer; 361-first part; 362-second part; 37-metal connection structure; 371-first solder layer; 372-sealing section; 373-blocking section; 38-metal inlay; 39-second metal layer; 41-first filling body; 42-second chip; 42a-second gap; 43-second plastic package;

[0079] 200-mold; 200a-fourth surface; 200a1-first protrusion; 200b-accommodating cavity; 201-first mold; 202-second mold; 203-carrier; 204-first release film;

[0080] 300 - first fixture; 300a - first supporting surface; 301 - second release film;

[0081] 400-the second fixture; 400a-the second supporting surface. DETAILED DESCRIPTION

[0082] In the embodiments of the present application, it should be noted that, unless otherwise clearly specified and limited, the terms "installation" and "connection" should be understood in a broad sense. For example, "connection" can be a detachable connection or a non-detachable connection; it can be a direct connection or an indirect connection through an intermediate medium.

[0083] In the embodiments of the present application, it should be understood that the directional terms mentioned, such as "up", "down", "left", "right", "inside", "outside", etc., are only references to the directions of the drawings. Therefore, the directional terms used are for better and clearer explanation and understanding of the embodiments of the present application, rather than indicating or implying that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the embodiments of the present application.

[0084] In the embodiments of the present application, the terms "first", "second", "third", "fourth", and "fifth" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first", "second", "third", "fourth", and "fifth" may explicitly or implicitly include one or more of the features.

[0085] In the embodiments of the present application, the terms "include", "comprises" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device including the element.

[0086] In the embodiments of the present application, "and / or" is only a description of the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0087] In the embodiments of the present application, it should be noted that the descriptions "vertical" and "parallel" respectively represent approximately vertical and approximately parallel within a certain error range, and the error range may be a range in which the deviation angle is less than or equal to 5°, 8° or 10° relative to absolute vertical and absolute parallel, respectively, and no specific limitation is made here.

[0088] The present application provides an electronic device, which includes but is not limited to a mobile phone, a tablet personal computer, a laptop computer, a personal digital assistant (PDA), a personal computer, a notebook computer, a vehicle-mounted device, a wearable device, a server, a base station, etc. Among them, the wearable device includes but is not limited to a smart bracelet, a smart watch, a smart head-mounted display, smart glasses, etc. The embodiments of the present application do not impose any special restrictions on the specific form of the electronic device.

[0089] See also Figure 1 , Figure 1 The present invention provides a schematic diagram of the structure of an electronic device 100 provided in some embodiments of the present application. The electronic device 100 may include a housing 10, a first circuit board 20 and a chip packaging structure 30. The first circuit board 20 and the chip packaging structure 30 are arranged in the housing 10, and the housing 10 is used to protect the first circuit board 20, the chip packaging structure 30 and other components of the electronic device 100.

[0090] The first circuit board 20 can be fixed in the housing 10 by means of snap connection, thread connection, bonding, etc. The first circuit board 20 can be the main circuit board of the electronic device 100. The first circuit board 20 is used to set electronic components, and the electronic components include but are not limited to system on a chip (System on a Chip, SoC), dynamic random access memory, power management chip (PowerManagement IC, PMIC), radio frequency module, audio module, etc. The first circuit board 20 can be a hard circuit board, a flexible circuit board, or a hard-soft combination circuit board, which is not limited in this application. In some other embodiments, the first circuit board 20 can also be other circuit boards of the electronic device 100.

[0091] See also Figure 1-Figure 3 , Figure 2 for Figure 1A schematic structural diagram of a chip packaging structure 30 of an electronic device 100 is shown. Figure 3 for Figure 2 The chip packaging structure 30 is a cross-sectional structure diagram at line AA. The chip packaging structure 30 includes a substrate 31, a plurality of first chips 32, an organic film 33 and a plastic sealing layer 34. It should be noted that: Figure 2 The present invention only schematically illustrates a possible combination of the plurality of first chips 32 in the chip package structure 30. The actual functions, shapes, sizes, positions and quantities of the first chips 32 are not subject to any restriction. Figure 2 and the accompanying drawings below.

[0092] In some examples, the substrate 31 may be a printed circuit board (PCB), and the substrate 31 may include insulating dielectric layers (not shown in the figure) and metal circuit layers (not shown in the figure) stacked and alternately arranged, and adjacent insulating dielectric layers and metal circuit layers are bonded. Specifically, polypropylene (PP) layers and copper clad layers may be stacked and alternately arranged and pressed, the PP layer forms the insulating dielectric layer of the PCB, and the copper clad layer is etched to form a metal circuit layer, thereby obtaining a printed circuit board PCB. Among them, the number of insulating dielectric layers may be one or more, and the number of metal circuit layers may be one or more, which is not limited in the present application. In other examples, the substrate 31 may also be a redistribution layer (RDL). Specifically, the redistribution layer RDL may be obtained by forming a dielectric layer on the support surface of the fixture by deposition or other processes, and then forming a metal circuit in the dielectric layer by etching, deposition or other processes. The substrate 31 has a first surface 31a and a fifth surface 31b that are opposite to each other. Based on this, a first pad 311 may be disposed on the first surface 31 a of the substrate 31 , and the first pad 311 is electrically connected to the metal circuit layer in the substrate 31 .

[0093] Please continue reading Figure 2 and Figure 3 The multiple first chips 32 can be unpackaged bare chips, and the surface of the chip 32 facing the first surface 31a is provided with a second pad 321. The second pad 321 and the aforementioned first pad 311 can be welded through a second solder layer 313 to form a welding structure 31A, and the welding structure 31A realizes the structural connection and electrical connection between the first chip 32 and the substrate 31.

[0094] The aforementioned multiple first chips 32 include multiple filter chips 32A. In some examples, the filter chip 32A may include a piezoelectric layer, which may be a lithium niobate layer or a lithium tantalate layer, and the two opposite surfaces of the piezoelectric layer may form the two opposite surfaces of the filter chip 32A. In other examples, the filter chip 32A may also include a substrate layer stacked and adjacent to the piezoelectric layer, and the substrate layer may be a silicon layer, or a stacked silicon dioxide layer and a silicon layer, and the silicon dioxide layer is located between the piezoelectric layer and the silicon layer to improve the temperature drift characteristics of the filter chip 32A. The surface of the piezoelectric layer facing away from the substrate layer forms the surface of the filter chip 32A facing the first surface 31a, and the surface of the substrate layer facing away from the piezoelectric layer forms the other surface of the filter chip 32A.

[0095] Please continue reading Figure 2 , the multiple first chips 32 may also include multiple non-filter chips 32B, and the multiple non-filter chips 32B may include one or more of a switch, a power amplifier (PA), and a low noise amplifier (LNA), so that the chip packaging structure 30 forms a radio frequency module capable of receiving or transmitting radio frequency signals, and the radio frequency module forms at least a part of the radio frequency transceiver system of the electronic device 100. Among them, the number of filter chips 32A may account for more than 60% of the total number of first chips 32. With the application and popularization of 5G, radio frequency modules need to support more and more frequency bands, and the number of filter chips 32A in radio frequency modules will also increase. Therefore, the performance of the filter chip 32A and the reliability of the connection with the substrate 31 determine the performance and reliability of the chip packaging structure 30.

[0096] Please continue reading Figure 2 and Figure 3 , the organic film 33 can be covered on the first surface 31a and the filter chip 32A through a coating process, and a first cavity 32a is formed with a filter chip 32A and the first surface 31a. On this basis, the plastic encapsulation layer 34 is injection-molded and connected to the first surface 31a and / or the organic film 33 and covers the organic film 33, so as to realize the plastic encapsulation of the filter chip 32A on the substrate 31 to protect the filter chip 32A. In this way, in the process of injection molding to form the plastic encapsulation layer 34, the organic film 33 can block the plastic material from filling the gap between the filter chip 32A and the first surface 31a, and can make the acoustic impedance difference between the medium (air) adjacent to the piezoelectric layer and the piezoelectric layer larger, thereby reducing the energy loss of the signal when it is transmitted in the filter chip 32A, thereby ensuring the performance of the filter chip 32A, and then ensuring the performance of the RF module formed by the chip packaging structure 30.

[0097] However, see Figure 3 and Figure 4 , Figure 4 for Figure 3 The schematic diagram of the failure of the welding structure 31A between the first chip 32 and the substrate 31 of the chip packaging structure 30 is shown. Since the organic film 33 covers the filter chip 32A, the portion of the filter chip 32A in contact with the organic film 33 has a relatively small coefficient of thermal expansion (CTE). For example, the CTE of the lithium niobate layer or the lithium tantalate layer is about 7, the CTE of the silicon layer is about 3, and the CTE of the organic film 33 is generally about 80-120. Therefore, the CTE difference between the filter chip 32A and the organic film 33 is relatively large. Therefore, when the temperature changes, the deformation difference between the two is relatively large, resulting in a large deformation mismatch between the interface of the organic film 33 and the filter chip 32A. The filter chip 32A will be subjected to the comprehensive stress in the X-axis direction, the Y-axis direction and the Z-axis direction, and thus the welding structure 31A is subjected to a relatively large stress. Since the welding structure 31A is surrounded by air and is not protected by the plastic layer 34, the welding structure 31A gradually develops fatigue cracks and fails under the periodic stress caused by periodic temperature cycles, thereby reducing the reliability of the chip packaging structure 30 and causing the overall reliability of the electronic device 100 to be low.

[0098] To resolve this issue, see Figure 5 , Figure 5 for Figure 2 Another cross-sectional structural diagram of the chip package structure 30 is shown at line AA. Figure 5 The embodiment shown is Figure 3 The difference of the embodiment shown is that: a first support layer 322 is formed on the piezoelectric layer of the filter chip 32A, a second support layer 323 is formed on the side of the first support layer 322 away from the filter chip 32A, and one or more second cavities 32b are formed on the surface of the first support layer 322, the second support layer 323 and the filter chip 32A. A first metal column 324 is connected to the second pad 321 of the filter chip 32A, the first metal column 324 penetrates the first support layer 322 and the second support layer 323, and is welded to the first pad 311 on the substrate 31 through the second solder layer 313, that is, the second pad 321, the first metal column 324, the second solder layer 313 and the first pad 311 form a welding structure 31A.

[0099] Specifically, an organic material may be formed on the piezoelectric layer of the filter chip 32A first, and a portion of the organic material may be removed by a patterning process to form a first support layer 322 that exposes the piezoelectric layer; next, a second support layer 323 may be formed on the first support layer 322 to form a second cavity 32b, and the first support layer 322 and the second support layer 323 may be formed of the same organic material or different organic materials. Next, a portion of the first support layer 322 and the second support layer 323 may be removed by a patterning process to expose the second pad 321, and then a first metal column 324 may be formed by an electroplating or deposition process, and the first metal column 324 and the first pad 311 may be welded by a second solder layer 313. On this basis, a plastic layer 34 may be formed by an injection molding process, and the plastic layer 34 may cover the filter chip 32A and fill the gap between the filter chip 32A and the substrate 31 and wrap the welding structure 31A, thereby completing the packaging of the filter chip 32A.

[0100] In this way, the plastic layer 34 can protect the welding structure 31A, and can reduce the risk of the welding structure 31A gradually generating fatigue cracks and failing under the periodic cyclic stress caused by periodic temperature cycles, thereby improving the reliability of the chip packaging structure 30 and further improving the reliability of the entire electronic device 100.

[0101] However, this method of first forming the second cavity 32b and then performing plastic sealing increases the material cost and patterning cost of the first support layer 322 and the second support layer 323, and also increases the material cost of the first metal column 324. In addition, the production of the first metal column 324 requires process steps such as patterning, electroplating or deposition, and etching. Therefore, this packaging method has high process complexity and cost. In addition, since the second cavity 32b is formed by the first support layer 322, the second support layer 323 and the filter chip 32A, it is necessary to reserve an area for forming the first metal column 324. Therefore, when the projection areas of the first cavity 32a and the second cavity 32b in the XY plane are the same, the area of ​​the filter chip 32A required for this packaging method is large, which is not conducive to the miniaturization of the chip packaging structure 30.

[0102] Furthermore, in the process of forming the plastic sealing layer 34 through the injection molding process, the second support layer 323 is easily collapsed and contacts the filter chip 32A due to the effect of molding. Therefore, this packaging method has many restrictions on the material strength, structural strength and manufacturing process of the second support layer 323. Finally, when the thickness of the chip packaging structure 30 as a whole in the Z-axis direction is constant, the thickness of the filter chip 32A in this packaging method is relatively small. Since the CTE of the filter chip 32A is significantly different from the CTE of the first support layer 322 and the second support layer 323, when the temperature changes, the first support layer 322 and the second support layer 323 exert a relatively large stress on the filter chip 32A, which easily causes the filter chip 32A to deform and warp, and the yield rate is relatively low.

[0103] To solve the above problems, see Figure 6 and Figure 7 , Figure 6 for Figure 1 Another structural schematic diagram of the chip packaging structure 30 of the electronic device 100 is shown. Figure 7 for Figure 6 The chip package structure 30 is a cross-sectional view at line BB. The chip package structure 30 includes a substrate 31, at least one first chip 32, a first plastic package body 35 and a first metal layer 36. Figure 6 and Figure 7 The embodiment shown is Figure 2 and Figure 3 The difference of the illustrated embodiment is that the substrate 31 has a second metal connector 312, and the surface of the second metal connector 312 forms a partial area of ​​the first surface 31a of the substrate 31, that is, the second metal connector 312 is located on the substrate 31. In some examples, part of the metal circuit of the substrate 31 can be exposed to form the second metal connector 312. In other examples, a metal pad connected to the metal circuit can be formed on the side of the metal circuit facing the first chip 32 through an electroplating or deposition process, and the metal pad is the second metal connector 312. The specific formation method of the second metal connector 312 is not limited in this application. Based on this, the second metal connector 312 can be electrically connected to the reference ground in the substrate 31.

[0104] Figure 6 and Figure 7In the illustrated embodiment, the number of the first chips 32 is multiple, and the first chip 32 may include a filter chip 32A. The number of the filter chips 32A may be multiple or one, and the present application does not limit this. The first chip 32 also includes a non-filter chip 32B. The number of the non-filter chips 32B may be one or multiple, and the present application does not limit this. Among them, the type of the non-filter chip 32B may be as described above, and will not be repeated here. The first chip 32 may be arranged on the first surface 31a of the substrate 31, and a first gap 32c is formed between the first surface 31a. The connection method between the first chip 32 and the substrate 31 may refer to the above, and will not be repeated here.

[0105] Please continue reading Figure 7 The first plastic package body 35 has a second surface 35a and a third surface 35b facing each other, and a peripheral side surface 35c connected between the second surface 35a and the third surface 35b. The second surface 35a faces the first surface 31a, and the second surface 35a has at least one groove 35a1. The shape of the groove 35a1 in the cross section parallel to the XY plane can be rectangular, square, trapezoidal, etc., and the groove 35a1 is used to accommodate the first chip 32. The second surface 35a includes a first area 35a2 and a second area 35a3 connected to each other, and the groove wall of the groove 35a1 forms at least a part of the second area 35a3.

[0106] The first metal layer 36 is disposed on the second surface 35a, and the first metal layer 36 includes a first portion 361 and a second portion 362. The first portion 361 covers the second area 35a3 of the second surface 35a, and the second portion 362 covers the first area 35a2 of the second surface 35a. The second portion 362 forms a first metal connector, that is, the first metal connector is disposed on the first plastic package 35 and covers the first area 35a2 of the second surface 35a of the first plastic package 35. On this basis, the second portion 362 is connected to the second metal connector 312. In some examples, the second portion 362 is bonded to the second metal connector 312, that is, the first metal connector is bonded to the second metal connector 312. In other examples, a first solder layer 371 is disposed between the second portion 362 and the second metal connector 312, and the second portion 362 and the second metal connector 312 are welded through the first solder layer 371. The first metal connector and the second metal connector 312 form at least a portion of the metal connection structure 37. That is, the first plastic package body 35 is connected to the substrate 31 through the metal connecting structure 37, the part where the first metal layer 36 is connected to the first solder layer 371 or the second metal connector 312 is the second part 362 (the first metal connector), and the area on the second surface 35a covered by the first metal connector is the first area 35a2.

[0107] On this basis, the grooves 35a1 correspond to the first chips 32 one by one, and one groove 35a1 contains one first chip 32. Figure 8 and Fig. 9 , Figure 8 for Figure 1 Another structural schematic diagram of the chip packaging structure 30 of the electronic device 100 is shown. Fig. 9 for Figure 8 The cross-sectional structure diagram of the chip packaging structure 30 at the CC line is shown. The number of grooves 35a1 can also be less than the number of first chips 32. There can be one first chip 32 in each groove 35a1 in a part of the grooves 35a1, and there can be multiple first chips 32 in each groove 35a1 in another part of the grooves 35a1. It can be set according to the function of the first chip 32 in the RF module. For example, when the number of filter chips 32A is multiple, two filter chips 32A can be accommodated in one groove 35a1; when the first chip 32 includes PA and / or LNA, PA and LNA are each separately located in a groove 35a1 to prevent the high-power signal transmitted in the PA from interfering with the LNA or the filter chip 32A. That is, at least one first chip 32 is accommodated in at least one groove 35a1, and there is at least one first chip 32 in one groove 35a1. In other embodiments, there can also be multiple first chips 32 in each groove 35a1. In this way, the area of ​​the chip packaging structure 30 in the direction perpendicular to the Z axis can be reduced, which is conducive to the miniaturization of the chip packaging structure 30.

[0108] In this way, compared with injection molding the first plastic package 35 to connect to the first surface 31a, the chip packaging structure 30 provided in this embodiment, by making the second surface 35a of the first plastic package 35 have at least one groove 35a1, the first plastic package 35 is connected to the substrate 31 through a metal connection structure 37, and a groove 35a1 has at least one first chip 32, which is conducive to first making the first plastic package 35 through a mold, and then connecting the first plastic package 35 to the substrate 31 through the metal connection structure 37. There is no need to cover the first chip 32 with an organic film to achieve the first chip 32 is encapsulated on the substrate 31 through the first plastic package 35, while having a first gap 32c between the filter chip 32A and the substrate to ensure the performance of the filter chip 32A, therefore, when the temperature changes, the first chip 32 will not be subjected to the stress applied by the organic film, thereby reducing the risk of failure of the welding structure 31A between the first chip 32 and the substrate 31. Moreover, when the first chip 32 is not in contact with the first plastic package 35 and the temperature changes, the first chip 32 will not be subjected to the stress applied by the first plastic package 35, thereby further reducing the risk of failure of the welding structure 31A between the first chip 32 and the substrate 31, thereby improving the reliability of the chip packaging structure 30.

[0109] In addition, the first plastic package body 35 is connected to the substrate 31 through a metal connection structure 37 formed by bonding or welding a first metal connection member arranged on the first plastic package body 35 and a second metal connection member 312 located on the substrate 31. The strength of the metal connection structure 37 is relatively high, and the reliability of the connection between the first plastic package body 35 and the substrate 31 is relatively good, thereby further improving the reliability of the chip packaging structure 30.

[0110] In addition, packaging the first chip 32 with the first plastic package 35 is conducive to mass production of the first plastic package 35 through an injection molding process using the same mold. There is no need to etch individual sheet blanks one by one to form a package, which reduces process complexity, increases processing efficiency, and reduces cost.

[0111] Finally, by forming the first metal layer 36 on the second surface 35a of the first plastic package 35, the second part 362 of the first metal layer 36 forms the first metal connector of the metal connection structure 37, and the first part 361 can form an electromagnetic shielding structure, which can prevent the first chips 32 in different grooves 35a1 from causing electromagnetic interference to each other, and can also prevent the first chip 32 in the chip packaging structure 30 from causing electromagnetic interference to other electronic components. Therefore, while the first plastic package 35 is connected to the substrate 31 to package and protect the first chip 32, an electromagnetic shielding structure is formed, which simplifies the difficulty of manufacturing the electromagnetic shielding structure and improves the manufacturing efficiency of the chip packaging structure 30.

[0112] See also Figure 7 and Fig. 9 , the first part 361 and the second part 362 of the first metal layer 36 are connected, and the first metal layer 36 is an integrally formed structure. In this way, a continuous first metal layer 36 covering the entire area of ​​the second surface 35a can be formed by electroplating or deposition (such as physical vapor deposition) and other processes, and the manufacturing process is simple, the manufacturing efficiency is high, and the manufacturing cost is low. In some other embodiments, the first metal layer 36 may not include the first part 361, and other electromagnetic shielding structures are used to prevent electromagnetic interference between the first chips 32 and between the first chip 32 and other electronic components.

[0113] See also Fig.10 , Fig.10 for Figure 7A schematic diagram of a stacked structure of the first metal layer 36 of the chip packaging structure 30 is shown. The first metal layer 36 includes a first layer 36a, a second layer 36b and a third layer 36c which are stacked and bonded in sequence. The first layer 36a is located on the side of the second layer 36b away from the first plastic package 35, the first layer 36a faces the first surface 31a of the substrate 31, and the third layer 36c is bonded between the second layer 36b and the second surface 35a of the first plastic package 35. Among them, the third layer 36c can be a stainless steel layer to ensure the bonding force between the first metal layer 36 and the first plastic package 35; the second layer 36b can be a copper layer to ensure the electromagnetic shielding effect of the first metal layer 36; the first layer 36a can be a stainless steel layer to protect the second layer 36b from being oxidized, and further ensure the electromagnetic shielding effect of the first metal layer 36. In some other embodiments, the first layer 36a can also be one of a tin layer, a nickel layer, a silver layer, a gold layer, and a lead layer, so that when the first layer 36a and the second metal connector 312 are welded through the first solder layer 371, the connection reliability between the first metal layer 36 and the first solder layer 371 is guaranteed, and then the reliability of the connection between the first plastic package body 35 and the substrate 31 is guaranteed, so as to ensure the overall reliability of the chip packaging structure 30.

[0114] In some other embodiments, see Fig.11 , Fig.11 for Figure 7 Another schematic diagram of the stacked structure of the first metal layer 36 of the chip packaging structure 30 is shown. In the case where the first layer 36a is a stainless steel layer, the first layer 36a may not be provided in the area corresponding to the second layer 36b and the first solder layer 371, and this part of the first metal layer 36 only includes the second layer 36b and the third layer 36c, that is, the first solder layer 371 is connected between the second layer 36b and the second metal connector 312. While ensuring the connection reliability between the first metal layer 36 and the first solder layer 371, the first solder layer 371 can also cover the area of ​​the second layer 36b not covered by the first layer 36a to protect the second layer 36b from oxidation. In some other embodiments, the first metal layer 36 may also not include the first layer 36a and / or the third layer 36c.

[0115] The thickness of the first metal layer 36 may be greater than or equal to 5um and less than or equal to 15um. For example, the thickness of the first metal layer 36 may be 5um, 7um, 9um, 11um, 13um, 15um, etc. Among them, the ratio of the thickness of the second layer 36b to the thickness of the first metal layer 36 may be greater than or equal to 0.7 to ensure the electromagnetic shielding effect of the first metal layer 36 as a whole. For example, the ratio of the thickness of the second layer 36b to the thickness of the first metal layer 36 may be 0.7, 0.75, 0.8, 0.85, 0.9, 0.95, 0.98, etc.

[0116] Please return to Figure 6 and Figure 8 At least a portion of the metal connection structure 37 is disposed around the entire first chip 32 along a direction parallel to the first surface 31 a . Figure 6 and Figure 8 In the illustrated embodiment, the metal connection structure 37 includes a sealing section 372 and a blocking section 373, and the sealing section 372 is arranged around the entire first chip 32 and the groove 35a1. In this way, the sealing section 372, the first surface 31a of the substrate 31, and the second surface 35a of the first plastic package 35 are arranged to form a sealed cavity, which can prevent water vapor from entering the cavity from the gap between the first plastic package 35 and the first surface 31a to damage the first chip 32. In addition, the metal connection structure 37 has a better water vapor isolation effect than the plastic forming the first plastic package 35, thereby ensuring the reliability of the chip packaging structure 30.

[0117] Based on this, the area on the second surface 35a surrounded by the sealing section 372 is the third area 35a4, the blocking section 373 is located on the inner peripheral side of the sealing section 372 and is connected to the sealing section 372, the blocking section 373 cooperates with the sealing section 372 to separate the third area 35a4 into a plurality of sub-areas 35a41, and the groove wall of a groove 35a1 forms at least a part of a sub-area 35a41. The blocking section 373 can extend in a straight line along a direction perpendicular to the Z axis, or can extend in a curve along a direction perpendicular to the Z axis, and the present application does not limit this. In this way, the peripheral side of each groove 35a1 and the inner wall of the groove 35a1 have a continuous electromagnetic shielding structure, which can prevent multiple first chips 32 from causing electromagnetic interference to each other, and can also prevent the first chip 32 from causing electromagnetic interference to other electronic components. In some other embodiments, the metal connection structure 37 may also not include the blocking section 373.

[0118] See also Fig.12 , Fig.12 for Figure 6 Another cross-sectional structural diagram of the chip package structure 30 at line BB is shown. Fig.12 The embodiment shown is Figure 7The difference of the embodiment shown is that the chip packaging structure 30 also includes a metal insert 38, which is embedded in the first plastic package 35. The number of metal inserts 38 can be multiple, and multiple metal inserts 38 are arranged at intervals in the first plastic package 35. The number of metal inserts 38 can also be one, and one metal insert 38 extends continuously in the first plastic package 35 in a direction perpendicular to the Z axis. In this way, when the first plastic package 35 is connected to the substrate 31, the high temperature of bonding or welding can be prevented from causing the first plastic package 35 to warp and deform, thereby squeezing the first chip 32, resulting in a reduction in the connection reliability between the first chip 32 and the substrate 31. In addition, the metal insert can also play a certain role in electromagnetic shielding, further reducing the risk of electromagnetic interference between the first chips 32.

[0119] Based on this, the end face of the metal insert 38 facing the first surface 31a is exposed to the second surface 35a of the first plastic package 35, and the first metal layer 36 also covers the metal insert 38. Specifically, the first part 361 of the first metal layer 36 may cover the metal insert 38, or the second part 362 of the first metal layer 36 may cover the metal insert 38, or the first part 361 and the second part 362 may cover the metal insert 38 together. It should be noted that, in the case where one end of the metal insert 38 facing the first surface 31a is exposed to the first plastic package 35, and the second part 362 covers at least a part of the metal insert 38, the surface area where the first plastic package 35 and the metal insert 38 are combined forms at least a part of the first area 35a2, and the first metal connector formed by the second part 362 indirectly covers the first area 35a2 by covering the metal insert 38.

[0120] In this way, it is advantageous to allow the first plastic package body 35 to wrap the metal insert 38 while the first plastic package body 35 is formed by injection molding, so that the first plastic package body 35 and the metal insert 38 form an integral structure with good strength, which can ensure the bonding force between the metal insert 38 and the first plastic package body 35, and simplify the process steps of connecting the first plastic package body 35 and the metal insert 38. In addition, the first metal layer 36 also covers the metal insert 38, which enhances the bonding strength between the integral structure formed by the first plastic package body 35 and the metal insert 38 and the first metal layer 36, and there is no need to avoid the metal insert 38 when forming the first metal layer 36, which simplifies the process steps.

[0121] See also Fig.13 , Fig.13 for Figure 6 The chip package structure 30 is shown in another cross-sectional view along line BB. Fig.13 The embodiment shown is Fig.12The embodiment shown is different in that the first metal layer 36 does not include the second portion 362 and the metal insert 38 forms the first metal connector. Fig.13 In the illustrated embodiment, the surface area where the first plastic package 35 is joined to the metal insert 38 is the first area 35a2. The material of the metal insert 38 may include at least one of lead, copper, silver, gold, nickel, palladium, and tin. In this way, while preventing the first plastic package 35 from warping and deforming, the metal insert 38 has good solderability, and can ensure the connection reliability between the metal insert 38 and the first solder layer 371. In this case, the first layer 36a of the first metal layer 36 can be a stainless steel layer with slightly poor solderability but good corrosion resistance, thereby ensuring the reliability of connecting the first plastic package 35 to the substrate 31 through the metal connection structure 37, and ensuring the reliability of the electromagnetic shielding structure formed by the first metal layer 36, thereby ensuring the overall reliability of the chip packaging structure 30.

[0122] Fig.13 In the illustrated embodiment, the end surface of the metal insert 38 facing the first surface 31a is flush with the partial surface area of ​​the first metal layer 36 facing away from the first surface 31a, that is, at least a portion of the first solder layer 371 is embedded in the first portion 361 of the first metal layer 36 and connected to the metal insert 38. In this way, the first portion 361 covered on the second area 35a3 outside the groove wall of the groove 35a1 can be roughly aligned with the first surface 31a. In this case, it is not necessary to extend the metal connection structure 37 between the two grooves 35a1 continuously in the direction perpendicular to the Z axis. The first metal layer 36 is aligned with the first surface 31a to prevent electromagnetic interference between the first chips 32 and electromagnetic interference between the first chip 32 and other electronic components. In addition, the metal connection structure 37 between the two grooves 35a1 can be intermittently arranged, saving costs.

[0123] In some other embodiments, the end surface of the metal insert 38 facing the first surface 31a may also be flush with the surface of the first metal layer 36 facing the first surface 31a, that is, the metal insert 38 protrudes from the first plastic package 35. In this way, there is no need to accurately control the thickness of the first solder layer 371, which reduces the process difficulty of connecting the first plastic package 35 to the substrate 31 through the metal connection structure 37.

[0124] Based on the above, please refer to Fig.14 , Fig.14 for Figure 6 The chip package structure 30 is shown in another cross-sectional view along line BB. Fig.14 The embodiment shown is Fig.12The difference of the embodiment shown is that part of the surface of the metal insert 38 is exposed on the third surface 35b of the first plastic package 35. On this basis, the chip packaging structure 30 also includes a second metal layer 39, which covers the third surface 35b of the first plastic package 35, the peripheral side surface 35c and the part of the surface of the metal insert 38. The material and structure of the second metal layer 39 can refer to the material and structure of the first metal layer 36, which will not be repeated here. In this way, the second metal layer 39 can form an electromagnetic shielding structure connected to the reference ground of the substrate 31 through the metal insert 38 outside the chip packaging structure 30, further reducing the risk of electromagnetic interference between the first chip 32 and other electronic components, and ensuring the reliability of the chip packaging structure 30. In addition, by exposing part of the surface of the metal insert 38 to the third surface 35b, the grounding path between the second metal layer 39 and the substrate 31 is shorter, and the electromagnetic shielding effect of the second metal layer 39 is better.

[0125] In some other embodiments, part of the surface of the metal insert 38 may also be exposed on the peripheral side surface 35c of the first plastic package body 35, and connected to the second metal layer 39. In some other embodiments, part of the surface of the metal insert 38 may also be exposed on the third surface 35b and the peripheral side surface 35c of the first plastic package body 35 at the same time, and connected to the second metal layer 39, and both of them can make the second metal layer 39 connected to the reference ground of the substrate 31 through the metal insert 38, and the present application does not make specific limitations on this.

[0126] It should be noted that, when the chip packaging structure 30 includes a second metal layer 39, the first metal layer 36 may not include the first part 361, and the metal insert 38 between the grooves 35a1 extends continuously in a direction perpendicular to the Z-axis, which can also ensure that the first chips 32 will not cause electromagnetic interference to each other, and can also ensure that the first chip 32 and other electronic components will not cause electromagnetic interference to each other.

[0127] See also Fig.15 , Fig.15 for Figure 6 The chip package structure 30 is shown in another cross-sectional view along line BB. Fig.15The embodiment shown is different from the aforementioned embodiment in that: when the plurality of first chips 32 also include a non-filter chip 32B, the chip packaging structure 30 also includes a first filler 41, and the first filler 41 fills the first gap 32c between the non-filter chip 32B and the first surface 31a of the substrate 31. Specifically, the first filler 41 can be formed by curing the spot-coated insulating glue. In this way, the first filler 41 can not only support the non-filter chip 32B, but also wrap the welding structure 31A between the non-filter chip 32B and the substrate 31 to protect the welding structure 31A, thereby improving the reliability of the structural connection and electrical connection between the non-filter chip 32B and the substrate 31.

[0128] See also Fig.16 and Fig.17 , Fig.16 for Figure 1 Another structural schematic diagram of the chip packaging structure 30 of the electronic device 100 is shown. Fig.17 for Fig.16 The chip package structure 30 is shown as a cross-sectional view at line DD. Fig.16 and Fig.17 The embodiment shown is Figure 6 and Figure 7 The difference of the embodiment shown is that the chip packaging structure 30 also includes a second chip 42 and a second plastic package 43. The second chip 42 is a non-filter chip, and the second chip 42 is arranged on the first surface 31a and is located on the peripheral side of the first plastic package 35, and there is a second gap 42a between the second chip 42 and the first surface 31a. The number of the second chip 42 can be one or more, and this application does not limit this. The connection method between the second chip 42 and the substrate 31 can refer to the connection method between the first chip 32 and the substrate 31 described above, and will not be repeated here. Based on this, the second plastic package 43 is injection-molded and connected to the first surface 31a of the substrate 31, and the second plastic package 43 covers the second chip 42, the first plastic package 35 and fills the second gap 42a between the second chip 42 and the first surface 31a.

[0129] Fig.16 and Fig.17 In the illustrated embodiment, the second plastic encapsulation body 43 covers the third surface 35b of the first plastic encapsulation body 35 and the surface facing the second plastic encapsulation body 43. In some other embodiments, the second plastic encapsulation body 43 may cover the entire outer surface of the first plastic encapsulation body 35, or may only cover the surface of the first plastic encapsulation body 35 facing the second plastic encapsulation body 43. In some other embodiments, the second plastic encapsulation body 43 may not cover the first plastic encapsulation body 35.

[0130] The material of the first plastic package 35 includes thermosetting plastic. For thermosetting materials, they have the properties of producing chemical changes after heating, gradually hardening and forming, and not softening or dissolving when heated again. Specifically, the material of the first plastic package 35 may include at least one of epoxy resin, unsaturated polyester and phenolic resin. In this way, in the process of injection molding the second plastic package 43 and making the second plastic package 43 cover the first plastic package 35, the first plastic package 35 will not soften and deform under the action of high-temperature materials, thereby ensuring the packaging reliability of the first plastic package 35 to the first chip 32. On this basis, the material of the second plastic package 43 may include thermosetting plastic, and the material of the second plastic package 43 may be the same as or different from the material of the first plastic package 35. In some other embodiments, the material of the second plastic package 43 may also include thermoplastic plastic, specifically, the material of the second plastic package 43 may include at least one of polycarbonate, thermoplastic polyurethane elastomer and polyethylene terephthalate.

[0131] In this way, the second plastic package 43 can be directly formed on the first surface 31a by the process of injection molding to encapsulate the second chip 42 in the substrate 31, and the material can be filled in the second gap 42a during the injection molding process to wrap the connection structure between the second chip 42 and the substrate 31, which can reduce the risk of the second plastic package 43 applying stress to the second chip 42 due to temperature changes, resulting in cracking and failure of the connection structure between the second chip 42 and the substrate 31, thereby ensuring the reliability of the chip packaging structure 30. In addition, by directly forming the second plastic package 43 by injection molding on the first surface 31a, the packaging process is simple, the efficiency is high, and the cost is low. Finally, by making the second plastic package 43 cover the first plastic package 35, the second plastic package 43 is simultaneously connected to the first surface 31a and the first plastic package 35 by injection molding, thereby improving the reliability of the second plastic package 43 fixed to the substrate 31, thereby improving the overall reliability of the chip packaging structure 30, and improving the appearance consistency of the chip packaging structure 30.

[0132] When the chip packaging structure 30 shown in the above embodiment is arranged in the housing 10 of the electronic device 100, in the case where the substrate 31 is a PCB, the substrate 31 can be stacked on one side of the first circuit board 20, and the substrate 31 can be connected to the first circuit board 20 through a frame circuit board (not shown in the figure) to form a three-dimensional stacking structure, and the first chip 32 and the second chip 42 can be electrically connected to the first circuit board 20 through the substrate 31 and the frame circuit board. The substrate 31 can also be laid flat with the first circuit board 20 and electrically connected to the first circuit board 20 through a conductive wire, which is not limited in this application. In the case where the substrate 31 is an RDL, the substrate 31 can be stacked on one side of the first circuit board 20 and soldered to the first circuit board 20 through solder balls, and the first chip 32 can be electrically connected to the first circuit board 20 through the substrate 31 and the solder balls.

[0133] The above embodiment takes the chip packaging structure 30 including a plurality of first chips 32 to form a radio frequency module for transmitting and receiving radio frequency signals as an example to introduce the chip packaging structure 30 in detail. In some other embodiments, the chip packaging structure 30 may also form an audio module for performing denoising and equalization on audio signals to improve audio quality. In some other embodiments, the number of first chips 32 in the chip packaging structure 30 may also be one, that is, the chip packaging structure 30 is a discrete device, which is connected to the first circuit board 20 after packaging. That is, the chip packaging structure 30 includes at least one first chip 32.

[0134] See also Fig.18 , Fig.18 The schematic diagram of the structure of the chip packaging structure 30 provided in some embodiments of the present application is a method for manufacturing the chip packaging structure 30. The method for manufacturing the chip packaging structure 30 includes steps S10-S20.

[0135] S10: Provide a chip structure 30A to be packaged and a first plastic package structure 30B respectively. The chip structure 30A to be packaged includes a substrate 31 and at least one first chip 32. The substrate 31 has a first surface 31a, and the substrate 31 has a second metal connector 312. The formation method of the second metal connector 312 can refer to the above, and will not be repeated here. Figure 18-Figure 20 In the illustrated embodiment, the number of the first chips 32 is multiple, and the multiple first chips 32 include a filter chip 32A and a non-filter chip 32B. The first chip 32 is disposed on the first surface 31a and has a first gap 32c between the first surface 31a. The first plastic package structure 30B includes a first plastic package 35, and the first plastic package 35 has a second surface 35a, and the second surface 35a has at least one groove 35a1. In some other embodiments, the chip structure 30A to be packaged may also include a first chip 32, that is, the chip structure 30A to be packaged includes at least one first chip 32. In some other embodiments, the multiple first chips 32 may also not include the non-filter chip 32B.

[0136] S20: The first surface 31a of the chip structure 30A to be packaged faces the second surface 35a of the first plastic package structure 30B, and the first plastic package 35 is connected to the substrate 31 through the metal connection structure 37; wherein, at least one first chip 32 is accommodated in at least one groove 35a1, and one groove 35a1 has at least one first chip 32.

[0137] Specifically, see Fig.19 , Fig.19 for Fig.14One of the structural schematic diagrams of the manufacturing process of the chip packaging structure 30 is shown. In step S10, providing a first plastic package structure 30B includes steps S11a-S17a.

[0138] S11a: Provide a mold 200, the mold cavity of the mold 200 has a fourth surface 200a, and the fourth surface 200a has at least one first protrusion 200a1. Specifically, the mold 200 includes a first mold 201, a second mold 202, and a carrier plate 203. The first mold 201 and the second mold 202 are arranged to form a receiving cavity 200b. The carrier plate 203 is arranged in the first mold 201 or the second mold 202 and is located in the receiving cavity 200b. The carrier plate 203 and the area on the inner wall of the receiving cavity 200b that is not covered by the carrier plate 203 are arranged to form a mold cavity, and one surface of the carrier plate 203 forms the fourth surface 200a. In some other embodiments, the mold 200 may not include the carrier plate 203, the receiving cavity 200b is the mold cavity of the mold 200, and part of the inner wall surface of the receiving cavity 200b forms the fourth surface 200a.

[0139] S12a: forming a first release film 204 on the fourth surface. Specifically, the first release film 204 may be a PET release film having certain adhesiveness on both sides.

[0140] S13a: pre-arrange a metal insert 38 on the fourth surface 200a, the metal insert 38 is used to form another partial area of ​​the second surface 35a. Specifically, step S13a includes step S13a1.

[0141] S13a1: attaching the metal insert 38 to the first release film 204. Specifically, the metal insert 38 can be fixed to the first release film 204 by the adhesion of the first release film 204 itself. In some other embodiments, the metal insert 38 can also be attached to the first release film 204 by an adhesive layer (such as an adhesive layer whose peel strength is negatively correlated with the ambient temperature), which is not limited in the present application.

[0142] S14a: injecting material into the cavity of the mold 200 through an injection molding process to form a first plastic package 35. The fourth surface 200a is used to mold a portion of the second surface 35a, and the first protrusion 200a1 is used to mold the groove 35a1. Specifically, step S14a includes step S14a1.

[0143] S14a1: A first plastic package body 35 connected to the metal insert 38 is formed in the mold cavity of the mold 200 by an injection molding process. One end surface of the metal insert 38 is exposed on the second surface 35a of the first plastic package body 35, that is, the metal insert 38 is used to mold another part of the second surface 35a. In this way, the metal insert 38 can be embedded in the first plastic package body 35 and form an integrated structural component with good strength with the first plastic package body 35.

[0144] S15a: removing the mold 200 and the first release film 204, that is, separating the first plastic package body 35, the metal insert 38 from the first release film 204 to form a part of the first plastic package body 35 structure 30B. Specifically, the first plastic package body 35, the metal insert 38 and the carrier 203 can be separated from the first mold 201 and the second mold 202, and then the first plastic package body 35 and the metal insert 38 are separated from the carrier 203 and the first release film 204.

[0145] S16a: Provide a first jig 300, and support the surface of the first plastic package 35 facing away from the second surface 35a on the first support surface 300a of the first jig 300. Specifically, a second release film 301 is attached to the first support surface 300a, and the surface of the first plastic package 35 facing away from the second surface 35a is attached to the second release film 301. In this way, the first jig 300 can provide support for the first plastic package 35, and can prevent the first plastic package 35 from deforming in subsequent process steps and affecting the yield rate of the chip packaging structure 30. In addition, by attaching the second release film 301, the first plastic package 35 can be prevented from being bonded to the first jig 300 and not easily separated from the first jig 300. In some other embodiments, step S10 may not include step S16a. It should be noted that step S15a can be performed before step S16a or after step S16a, and this application does not limit this.

[0146] S17a: A first metal layer 36 is formed on the second surface 35a, wherein the first metal layer 36 includes a second portion 362 covering the area around the groove 35a1 on the second surface 35a, and the second portion 362 forms a first metal connector. On this basis, the first metal layer 36 also includes a first portion 361 covering the area on the second surface 35a that is not covered by the second portion 362. Based on this, the first metal layer 36 also covers the metal insert 38. It should be noted that the first metal layer 36 indirectly covers the area on the second surface 35a that is bonded to the metal insert 38 by covering the metal insert 38. The laminated structure of the first metal layer 36 can be referred to Fig.10 and Fig.11 In some other embodiments, the first metal layer 36 may not include the first portion 361 .

[0147] Based on the above, please refer to Fig. 20 , Fig. 20 for Fig.14 The second structural schematic diagram of the manufacturing process of the chip packaging structure 30 is shown. In step S10, providing a chip structure 30A to be packaged includes steps S11b-S13b.

[0148] S11b: Provide a second fixture 400 , wherein the second fixture 400 has a second supporting surface 400a .

[0149] S12b: A redistribution layer is formed on the second support surface 400a to obtain the substrate 31, that is, the substrate 31 is an RDL. The substrate 31 has a first surface 31a facing away from the second support surface 400a. In some examples, a material such as silicon dioxide can be first deposited on the second support surface 400a by plasma enhanced chemical vapor deposition to form a dielectric layer; then a metal pattern layer is formed in the dielectric layer by deposition and etching processes to form a metal line to obtain the RDL, and a portion of the metal line can form a second metal connector 312.

[0150] S13b: at least one first chip 32 is disposed on the first surface 31a, and a first gap 32c is formed between the first chip 32 and the first surface 31a. The method of connecting the first chip 32 to the first surface 31a can be referred to above and will not be described here. Fig. 20 , step S20 includes steps S21-S22.

[0151] S21: Solder is provided on the second metal connector 312 and / or the first metal connector formed by the second part 362 of the first metal layer 36. That is, solder is provided on the second metal connector 312 and / or the first metal connector. Specifically, the solder may be provided only on the second metal connector 312, or only on the second part 362, or partly on the second metal connector 312 and another partly on the second part 362. The material of the solder may include tin (Sn) and / or indium (In), and may also include one or more of Ag (silver), gold (Au), copper, Bi (bismuth), nickel, and lead. In some examples, the solder may be a solder ball, which may be provided by electroplating, chemical plating, printing, ball planting, or deposition. In other examples, the solder may be a solder paste, which may be provided by coating or spraying, etc., and the present application does not limit this.

[0152] S22 : melting the solder to form a first solder layer 371 , so that the first solder layer 371 is connected with the first metal connector and the second metal connector 312 to form a metal connection structure 37 .

[0153] On the basis of the above, please continue to refer to Fig. 20The manufacturing method of the chip packaging structure 30 also includes steps S30-S60.

[0154] S30: removing the first fixture 300. It should be noted that, when step S10 does not include step S16a, the manufacturing method of the chip packaging structure 30 does not include step S30.

[0155] S40: removing the second fixture 400. It should be noted that step S30 and step S40 can be performed simultaneously, or step S30 can be performed first and then step S40, or step S40 can be performed first and then step S30.

[0156] S50: Thinning the first plastic package body 35 to form a third surface 35b facing away from the first surface 31a, and exposing the end surface of the metal insert 38 away from the first surface 31a to the third surface 35b; wherein the first plastic package body 35 also has a peripheral side surface 35c connected between the third surface 35b and the second surface 35a.

[0157] S60: forming a second metal layer 39 covering the third surface 35b, the peripheral side surface 35c and the metal insert 38 on the first plastic package body 35. The structure, material and formation method of the second metal layer 39 can refer to the structure, material and formation method of the first metal layer 36, which will not be described in detail here. In some other embodiments, the manufacturing method of the chip packaging structure 30 may also not include steps S50-S60.

[0158] It should be noted that Figure 18-Figure 20 In the illustrated embodiment, in step S10, the chip structure 30A to be packaged and the first plastic package structure 30B are both one. In some other embodiments, in step S10, the chip structure 30A to be packaged and the first plastic package structure 30B can also be multiple, the substrate 31 in the multiple chip structures 30A to be packaged is an integrally formed part, and the first plastic package 35 in the multiple first plastic package structures 30B is an integrally formed part. After step S20, an initial chip packaging structure group is obtained. After step S50 and before step S60, the initial chip packaging structure group needs to be cut to obtain multiple initial chip packaging structures, and then the initial chip packaging structure is processed in step S60 to obtain the chip packaging structure 30; or, after step S20 and before step S50, the initial chip packaging structure group needs to be cut to obtain multiple initial chip packaging structures, and then the initial chip packaging structure is processed in steps S50-S60 to obtain the chip packaging structure 30.

[0159] See also Fig.21 and Fig. 22 , Fig.21 for Fig.14Another structural schematic diagram of the manufacturing process of the chip packaging structure 30 is shown. Fig. 22 for Fig.14 Another structural schematic diagram of the manufacturing process of the chip packaging structure 30 is shown in FIG. 2 . Fig.21 and Fig. 22 The embodiment shown is Fig.19 and Fig. 20 The difference of the illustrated embodiment is that in step S10 , providing a chip structure 30A to be packaged includes steps S11 c - S12 c.

[0160] S11c: providing a substrate 31, wherein the substrate 31 has a first surface 31a and a fifth surface 31b opposite to each other; wherein the substrate 31 is a PCB.

[0161] S12c: at least one first chip 32 is disposed on the first surface 31a, and a first gap 32c is provided between the first chip 32 and the first surface 31a. The method of connecting the first chip 32 to the first surface 31a can be referred to above and will not be repeated here.

[0162] On this basis, the manufacturing method of the chip packaging structure 30 does not include step S40, and the remaining steps can refer to Fig.19 and Fig. 20 In some other embodiments, the manufacturing method of the chip packaging structure 30 may not include steps S50 - S60 .

[0163] See also Fig.23 and Fig.24 , Fig.23 for Fig.13 One of the structural schematic diagrams of the manufacturing process of the chip packaging structure 30 is shown, Fig.24 for Fig.13 The second structural schematic diagram of the manufacturing process of the chip packaging structure 30 is shown. Fig.23 and Fig.24 The embodiment shown is Fig.21 and Fig. 22 The embodiment shown differs in that:

[0164] S14a1: A first plastic package body 35 connected to the metal insert 38 is formed in the mold cavity of the mold 200 by injection molding. The end surface of the metal insert 38 facing the first surface 31a is exposed on the second surface 35a of the first plastic package body 35, and the metal insert 38 forms a first metal connector.

[0165] S17a: forming a first metal layer 36 on the second surface 35a, wherein the first metal layer 36 only includes a first portion 361 covering an area on the second surface 35a that is not covered by the first metal connector.

[0166] S21: Solder is placed on the second metal connector 312 and / or the first metal connector formed by the metal insert 38. The specific placement and composition of the solder can be referred to in Fig.21 and Fig. 22 The embodiments shown are not described in detail here.

[0167] On this basis, the manufacturing method of the chip packaging structure 30 does not include steps S50-S60, and the remaining steps can refer to Fig.21 and Fig. 22 The illustrated embodiment will not be described in detail here. In some other embodiments, the method for manufacturing the chip package structure 30 may also include steps S50 - S60 .

[0168] See also Fig.25 and Fig.26 , Fig.25 for Figure 7 One of the structural schematic diagrams of the manufacturing process of the chip packaging structure 30 is shown, Fig.26 for Figure 7 The second structural schematic diagram of the manufacturing process of the chip packaging structure 30 is shown. Fig.25 and Fig.26 The embodiment shown is Fig.21 and Fig. 22 The embodiment shown differs in that:

[0169] Step S10 does not include step S13a, and step S14a does not include step S14a1. In step S17a, the first metal layer 36 directly covers the entire area of ​​the second surface 35a.

[0170] On this basis, the manufacturing method of the chip packaging structure 30 does not include steps S50-S60, and the remaining steps can refer to Fig.21 and Fig. 22 The illustrated embodiment will not be described in detail here. In some other embodiments, the manufacturing method of the chip packaging structure 30 may also include steps S50-S60.

[0171] See also Fig. 27 and Fig.28 , Fig. 27 for Fig.15 One of the structural schematic diagrams of the manufacturing process of the chip packaging structure 30 is shown, Fig.28 for Fig.15 The second structural schematic diagram of the manufacturing process of the chip packaging structure 30 is shown. Fig. 27 and Fig.28 The embodiment shown is Fig.25 and Fig.26The difference of the illustrated embodiment is that, when the plurality of first chips 32 include a non-filter chip 32B, after step S12c of providing a chip structure 30A to be packaged, step S10 further includes step S13c.

[0172] S13c: Fill the first gap 32c between the non-filter chip 32B and the first surface 31a with a medium to form a first filling body 41. That is, before step S20, the manufacturing method of the chip packaging structure 30 also includes step S13c. The formation method and function of the first filling body 41 can be referred to above and will not be repeated here. The remaining steps can be referred to Fig.25 and Fig.26 The embodiments shown are not described in detail here.

[0173] See also Fig.29 and Fig.30 , Fig.29 for Fig.17 One of the structural schematic diagrams of the manufacturing process of the chip packaging structure 30 is shown, Fig.30 for Fig.17 The second structural schematic diagram of the manufacturing process of the chip packaging structure 30 is shown. Fig.29 and Fig.30 The embodiment shown is Fig.25 and Fig.26 The difference of the embodiment shown is that the chip structure 30A to be packaged further includes a second chip 42, the second chip 42 is a non-filter chip, and the second chip 42 is disposed on the first surface 31a and has a second gap 42a between the second chip 42 and the first surface 31a. Specifically, step S12c is:

[0174] S12c: at least one first chip 32 is disposed on the first surface 31a, and a first gap 32c is provided between the first chip 32 and the first surface 31a, and a second chip 42 is disposed on the first surface 31a, and a second gap 42a is provided between the second chip 42 and the first surface 31a. The manner in which the first chip 32 and the second chip 42 are disposed on the first surface 31a can be referred to above, and will not be repeated here. It should be noted that the second chip 42 is located on the peripheral side of the first plastic package 35 formed after step S20 and is spaced apart from the first plastic package 35.

[0175] On the basis of the above, after step S30 , the method for manufacturing the chip packaging structure 30 further includes step S70 .

[0176] S70: forming a second plastic package 43 on the first surface 31 a by injection molding, and making the second plastic package 43 cover the second chip 42 and fill the second gap 42 a. On this basis, the second plastic package 43 also covers the first plastic package 35 .

[0177] When there are multiple second chips 42, after step S30 and before step S70, metal ribs (not shown in the figure) can be formed on the substrate 31 by welding, and the metal ribs separate the second chips 42 to prevent the second chips 42 from causing electromagnetic interference to each other. Next, referring to the aforementioned steps S50-S60, a third metal layer (not shown in the figure) can be formed on the surface of the second plastic package 43 facing away from the first plastic package 35, and the third metal layer also covers the metal ribs to prevent the chip packaging structure 30 as a whole from causing electromagnetic interference to each other with the electronic components outside the chip packaging structure 30. In this way, the chip area in the chip packaging structure 30 can be packaged, the size of the first plastic package 35 can be made smaller, the strength and precision of the first plastic package 35 can be higher, and the second plastic package 43 can protect the connection structure between the second chip 42 and the substrate 31 while encapsulating and protecting the second chip 42, thereby ensuring the reliability of the chip packaging structure 30 as a whole.

[0178] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0179] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A chip packaging structure, characterized in that: include: a substrate having a first surface; At least one first chip, the at least one first chip comprising a filter chip, the first chip being disposed on the first surface and having a first gap between the first chip and the first surface; A first plastic package body, wherein the first plastic package body has a second surface, the second surface faces the first surface, and the second surface has at least one groove; the second surface includes a first area and a second area connected, and a groove wall of the at least one groove forms at least a part of the second area; A metal connection structure, wherein the first plastic package body is connected to the substrate through the metal connection structure, and the at least one first chip is accommodated in the at least one groove; The metal connection structure comprises: A first metal connector, which is disposed on the first plastic package body and covers the first area; a second metal connector, the second metal connector is located on the substrate, and the second metal connector is bonded or welded to the first metal connector; The chip packaging structure further includes a first metal layer, which is disposed on the second surface; the first metal layer includes a first portion, which covers the second area; The chip packaging structure further includes a metal insert, which is embedded in the first plastic package body, with an end surface of the metal insert facing the first surface exposed on the second surface, and the metal insert forms the first metal connector; or, The first metal layer also includes a second portion, and the second portion forms the first metal connector.

2. The chip packaging structure according to claim 1, characterized in that: The first metal layer includes a first part and a second part, and the first metal layer is an integrally formed structure.

3. The chip packaging structure according to claim 2, characterized in that: The chip packaging structure further includes a metal insert, which is embedded in the first plastic package body, and an end surface of the metal insert facing the first surface is exposed on the second surface; the first metal layer also covers the metal insert.

4. The chip packaging structure according to claim 1 or 3, characterized in that: The first plastic package body further comprises a third surface opposite to the second surface, and a peripheral side surface connected between the third surface and the second surface, and a part of the surface of the metal insert is exposed on the third surface and / or the peripheral side surface; The chip packaging structure further includes a second metal layer, and the second metal layer covers the third surface, the peripheral side surface and the partial surface of the metal insert.

5. The chip packaging structure according to claim 1 or 3, characterized in that: The material of the metal insert includes at least one of lead, copper, silver, gold, nickel, palladium and tin.

6. The chip packaging structure according to any one of claims 1 to 3, characterized in that: The first metal layer includes a first layer and a second layer stacked and bonded in sequence, the first layer is located on a side of the second layer away from the first plastic package body and facing the first surface; the first layer is one of a tin layer, a stainless steel layer, a nickel layer, a silver layer, a gold layer, and a lead layer, and the second layer is a copper layer.

7. The chip packaging structure according to claim 6, characterized in that: The first metal layer further includes a third layer laminated and bonded between the second layer and the second surface, and the third layer is a stainless steel layer.

8. The chip packaging structure according to any one of claims 1 to 3, characterized in that: The number of the first chips is multiple, and the multiple first chips include non-filter chips; The chip packaging structure further includes at least one first filling body, wherein the first filling body fills the first gap between the non-filter chip and the first surface.

9. The chip packaging structure according to any one of claims 1 to 3, characterized in that: The metal connection structure comprises a sealing section, and the sealing section is arranged around the at least one groove.

10. The chip packaging structure according to claim 9, characterized in that: The number of the grooves is multiple; the area on the second surface surrounded by the sealing segment is the third area; The metal connection structure also includes a blocking segment, which is located on the inner peripheral side of the sealing segment. The blocking segment cooperates with the sealing segment to separate the third area into a plurality of sub-areas, and the groove wall of one of the grooves forms at least a part of one of the sub-areas.

11. The chip packaging structure according to any one of claims 1 to 3, characterized in that: The packaging structure further includes: A second chip, the second chip is a non-filter chip, the second chip is arranged on the first surface and is located on the peripheral side of the first plastic package body, and a second gap is formed between the second chip and the first surface; A second plastic package body, the second plastic package body is injection-molded and connected to the first surface, the second plastic package body covers the second chip and the first plastic package body and fills the second gap; Wherein, the material of the first plastic package body includes thermosetting plastic.

12. The chip packaging structure according to any one of claims 1 to 3, characterized in that: The substrate is a printed circuit board or a redistribution layer.

13. The chip packaging structure according to any one of claims 1 to 3, characterized in that: The chip packaging structure is a radio frequency module.

14. An electronic device, characterized in that: include: a first circuit board; A chip packaging structure, wherein the chip packaging structure is the chip packaging structure according to any one of claims 1 to 13, and the at least one first chip is electrically connected to the first circuit board.

15. A method for manufacturing a chip packaging structure, characterized in that: include: A chip structure to be packaged and a first plastic package structure are provided respectively; wherein the chip structure to be packaged comprises a substrate and at least one first chip, the substrate has a first surface, the at least one first chip comprises a filter chip, the at least one first chip is arranged on the first surface and has a first gap with the first surface, and the substrate has a second metal connector; the first plastic package structure comprises a first plastic package, the first plastic package has a second surface, and the second surface has at least one groove; The first surface of the chip structure to be packaged faces the second surface of the first plastic package structure, and the first plastic package is connected to the substrate through a metal connection structure; wherein the at least one first chip is accommodated in the at least one groove; A first plastic package structure is provided, comprising: Providing a mold, wherein the mold cavity has a fourth surface, and the fourth surface has at least one first protrusion; Injecting material into the mold cavity of the mold through an injection molding process to form a first plastic package body; wherein the fourth surface is used to mold at least a portion of the second surface; and the first protrusion is used to mold the groove; forming a first metal layer on the second surface, the first metal layer comprising a second portion, the second portion covering the peripheral area of ​​the groove on the second surface, the second portion forming a first metal connector; the first metal layer further comprising a first portion, the first portion covering an area on the second surface not covered by the first metal connector; Or, providing a first plastic package structure, including: Providing a mold, wherein the mold cavity has a fourth surface, and the fourth surface has at least one first protrusion; Pre-arranging a metal insert on the fourth surface; Injecting material into the mold cavity of the mold through an injection molding process to form a first plastic package body connected to the metal insert; wherein the fourth surface is used to mold a partial area of ​​the second surface, and the first protrusion is used to mold the groove; the end surface of the metal insert facing the first surface is exposed on the second surface, and the metal insert forms a first metal connector; forming a first metal layer on the second surface, wherein the first metal layer covers an area on the second surface that is not covered by the first metal connector; The first surface of the chip structure to be packaged is placed facing the second surface of the first plastic package structure, and the first plastic package is connected to the substrate through a metal connection structure, including: Disposing solder on the second metal connector and / or the first metal connector; The solder is melted to connect the solder with the first metal connector and the second metal connector to form the metal connection structure.

16. The method according to claim 15, characterized in that In the case where the first metal layer includes a first portion and a second portion, Before injecting material into the mold cavity of the mold by an injection molding process to form the first plastic package body, providing the first plastic package body structure further includes: pre-arranging a metal insert on the fourth surface; The forming of the first plastic package body in the mold cavity by the injection molding process comprises: forming the first plastic package body connected to the metal insert in the mold cavity by the injection molding process; The end surface of the metal insert facing the first surface is exposed on the second surface of the first plastic package body, and the first metal layer also covers the metal insert.

17. The method according to claim 15 or 16, characterized in that Before pre-arranging the metal insert on the fourth surface, providing the first plastic package structure further includes: forming a first release film on the fourth surface; Pre-arranging a metal insert on the fourth surface includes: attaching the metal insert to the first release film; After injecting material into the mold cavity of the mold through an injection molding process to form a first plastic package body connected to the metal insert, providing the first plastic package body structure further includes: removing the mold and the first release film.

18. The method according to claim 15 or 16, characterized in that After forming the first plastic package body in the mold cavity by the injection molding process, providing the first plastic package body structure further includes: Providing a first jig, and supporting the surface of the first plastic package body facing away from the second surface on a first supporting surface of the first jig; After the first surface of the chip structure to be packaged is placed facing the second surface of the first plastic package structure, and the first plastic package is connected to the substrate through a metal connection structure, the method further includes: Remove the first fixture.

19. The method according to claim 15 or 16, characterized in that After forming the first plastic package body in the mold cavity by an injection molding process, the method further includes: The first plastic package body is thinned to form a third surface facing away from the first surface, and the end surface of the metal insert away from the first surface is exposed on the third surface; wherein the first plastic package body further comprises a peripheral side surface connected between the third surface and the second surface; A second metal layer is formed on the first plastic package body, covering the third surface, the peripheral side surface and the metal insert.

20. The method according to claim 15 or 16, characterized in that The number of the first chips is multiple, and the multiple first chips also include non-filter chips; Before the first surface of the chip structure to be packaged faces the second surface of the first plastic package structure and the first plastic package is connected to the substrate through a metal connection structure, the method further includes: The first gap between the non-filter chip and the first surface is filled with a dielectric to form a first filling body.

21. The method according to claim 15 or 16, characterized in that The chip structure to be packaged further includes a second chip, the second chip is a non-filter chip, and the second chip is disposed on the first surface and has a second gap with the first surface; The method further comprises: A second plastic package is formed on the first surface by an injection molding process, and the second plastic package covers the second chip, the first plastic package and fills the second gap; wherein the material of the first plastic package includes thermosetting plastic.

22. The method according to claim 15 or 16, characterized in that The chip structure to be packaged includes: Providing a second fixture, wherein the second fixture has a second support surface; forming a redistribution layer on the second supporting surface to obtain a substrate; wherein the substrate has a first surface facing away from the second supporting surface; Disposing at least one first chip on a first surface, and allowing a first gap to exist between the first chip and the first surface; After the first surface of the chip structure to be packaged is placed facing the second surface of the first plastic package structure, and the first plastic package is connected to the substrate through a metal connection structure, the method further includes: Remove the second fixture.

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