A super junction MOSFET device and preparation method thereof

Abstract

The embodiment of the present application provides a super junction MOSFET device and a preparation method, which belongs to the technical field of semiconductor devices. A second type of semiconductor substrate is provided on the upper surface of the drain of the super junction MOSFET device, and a second type of variable doping semiconductor epitaxial region is provided on the upper surface of the second type of semiconductor substrate; a first type of variable doping semiconductor column region is provided in the second type of variable doping semiconductor epitaxial region, and the first type of variable doping semiconductor column region includes a plurality of first type doping regions, and each first type doping region has a different doping concentration, and the second type of variable doping semiconductor epitaxial region includes a plurality of second type doping regions, and each second type doping region has a different doping concentration. The embodiment of the present application can improve the reverse recovery performance of the super junction MOSFET body diode, avoid causing circuit oscillation, and thus avoid thermal burnout and failure of the super junction MOSFET.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor devices, and in particular to a super junction MOSFET device and a preparation method thereof. Background Art

[0002] A superjunction metal oxide field effect transistor (Metal-Oxide-Semiconductor Field-EffectTransistor, superjunction MOSFET) refers to a MOSFET device in which a plurality of vertical PN junctions are arranged alternately in a drift region. There is a contradictory relationship between the breakdown voltage and the on-resistance in the MOSFET device prepared by the prior art. In high-voltage application scenarios, the on-resistance of the MOSFET device increases significantly with the increase of the breakdown voltage, and the power consumption also increases accordingly, resulting in a decrease in the power conversion efficiency of the power electronic system, thereby limiting the application of the MOSFET device in the high-voltage range. Therefore, compared with the MOSFET device prepared by the prior art at the same withstand voltage level, it can be seen that the drift region of the superjunction MOSFET device has a higher doping concentration and can have a lower on-resistance, thereby improving the contradictory relationship between the breakdown voltage and the on-resistance.

[0003] However, the super junction MOSFET of the related art is usually composed of highly doped P columns and N columns arranged alternately, so that the junction area of ​​the PN junction body diode formed by the two is larger. Due to the presence of a PN junction body diode with a large junction area, when the PN junction body diode is forward-conducted, the reverse recovery charge Qrr and the reverse recovery peak current Irrm of the super junction MOSFET body diode will also increase, which can easily cause thermal burnout of the device. At the same time, in the sweep-out stage of the unbalanced carriers in the drift region, the faster the sweep-out speed of the unbalanced carriers stored in the super junction MOSFET, the higher the reverse recovery current rate (i.e., dir / dt, dir represents the reverse recovery current, and dt represents the reverse current recovery time), which makes the reverse recovery softness factor (which can be recorded as S) of the body diode of the super junction MOSFET smaller, making the reverse recovery approach to hard recovery. Due to the presence of stray inductance in the power system, hard recovery can easily cause voltage spikes or circuit oscillations in the body diode, and may induce the opening of the parasitic transistor of the super junction MOSFET, ultimately leading to device failure. It can be seen that the super junction MOSFET prepared by the related technology is prone to circuit oscillation, which leads to thermal burnout and failure of the super junction MOSFET. Therefore, how to improve the reverse recovery performance of the super junction MOSFET body diode to avoid circuit oscillation, thereby avoiding thermal burnout and failure of the super junction MOSFET, has become a technical problem that needs to be solved urgently. Summary of the invention

[0004] The main purpose of the embodiments of the present application is to propose a super junction MOSFET device and a preparation method, aiming to improve the reverse recovery performance of the super junction MOSFET body diode, avoid causing circuit oscillation, and thus avoid thermal burnout and failure of the super junction MOSFET.

[0005] To achieve the above-mentioned object, a first aspect of an embodiment of the present application provides a super junction MOSFET device, wherein the super junction MOSFET device includes a source, an insulating dielectric layer, a gate, a first type semiconductor base region, a second type highly doped semiconductor region, a first type highly doped semiconductor region, a second type variable doped semiconductor epitaxial region, a second type semiconductor substrate and a drain;

[0006] The upper surface of the drain is provided with the second type semiconductor substrate, and the upper surface of the second type semiconductor substrate is provided with the second type variable doping semiconductor epitaxial region; the second type variable doping semiconductor epitaxial region is provided with the first type variable doping semiconductor column region, wherein the second type variable doping semiconductor epitaxial region and the first type variable doping semiconductor column region are regions constructed based on column structures of semiconductor regions of different conductivity types, the first type variable doping semiconductor column region includes a plurality of first type doping regions, and each of the first type doping regions has a different doping concentration, and the second type variable doping semiconductor epitaxial region includes a plurality of second type doping regions, and each of the second type doping regions has a different doping concentration;

[0007] The first type of semiconductor base region is in contact with the upper surface of the first type of variable-doped semiconductor column region, the first type of highly doped semiconductor region and the second type of highly doped semiconductor region are arranged inside the first type of semiconductor base region, and the first type of highly doped semiconductor region and the second type of highly doped semiconductor region are in contact with the source respectively; the gate is located on the upper surfaces of the first type of semiconductor base region and the second type of variable-doped semiconductor epitaxial region, and the gate is isolated from the source by the insulating medium layer.

[0008] A super junction MOSFET device according to an embodiment of the present application has at least the following beneficial effects: the present application can change the electric field distribution and reduce the electric field peak in the drift region by setting a first type of variable doping semiconductor column region inside a second type of variable doping semiconductor epitaxial region, thereby slowing down the speed of carriers and reducing the injection of reverse recovery charge Qrr. A plurality of doping regions are set in the first type of variable doping semiconductor column region and the second type of variable doping semiconductor epitaxial region, and each doping region has a different doping concentration, which can achieve a more refined doping gradient, help improve the performance and stability of the device, help improve the reverse recovery performance of the super junction MOSFET body diode, avoid causing circuit oscillation, and thus avoid thermal burnout and failure of the super junction MOSFET.

[0009] In some embodiments, the first type of variable doped semiconductor column region includes at least three first type of doped regions, and the doping concentration of the first type of doped regions gradually increases from top to bottom.

[0010] In some embodiments, the thickness of the first-type semiconductor base region is greater than the thickness of the first-type highly-doped semiconductor region; the thickness of the first-type highly-doped semiconductor region is greater than the thickness of the second-type highly-doped semiconductor region.

[0011] In some embodiments, the second type of semiconductor substrate and the second type of highly doped semiconductor region have the same doping concentration; and the second type of semiconductor substrate and the second type of highly doped semiconductor region have different thicknesses.

[0012] In some embodiments, the doping concentration of the first type semiconductor base region is less than the doping concentration of the first type highly doped semiconductor region; and the doping concentration of the first type highly doped semiconductor region is less than the doping concentration of the second type highly doped semiconductor region.

[0013] In some embodiments, materials of the second type of variable doped semiconductor epitaxial region and the second type of semiconductor substrate include silicon, silicon carbide, and gallium nitride semiconductor materials.

[0014] In some embodiments, the super junction MOSFET device also includes a gate oxide dielectric layer, the gate oxide dielectric layer is located on the upper surface of the first type semiconductor base region and the second type variable doped semiconductor epitaxial region, and the gate refers to a structure obtained by deposition processing on the upper surface of the gate oxide dielectric layer.

[0015] To achieve the above-mentioned purpose, a second aspect of an embodiment of the present application provides a method for preparing a super junction MOSFET device, the method comprising:

[0016] providing a second type of semiconductor substrate;

[0017] Constructing a column structure based on the second-type semiconductor substrate to obtain a first-type semiconductor after thermal diffusion, wherein the first-type semiconductor after thermal diffusion includes a second-type variable doping semiconductor epitaxial region and a first-type variable doping semiconductor column region filled in the second-type variable doping semiconductor epitaxial region;

[0018] Performing thermal oxidation treatment on the thermally diffused first type semiconductor to obtain the thermally oxidized first type semiconductor, wherein the thermally oxidized first type semiconductor is used to characterize a semiconductor device having a gate oxide dielectric layer structure on the upper surface of the second type variable doped semiconductor epitaxial region;

[0019] Performing ion implantation on the thermally oxidized first-type semiconductor to obtain the ion-implanted first-type semiconductor, wherein the ion-implanted first-type semiconductor includes a first-type semiconductor base region, a second-type highly doped semiconductor region, and a first-type highly doped semiconductor region;

[0020] Performing a deposition process on the first type semiconductor after ion implantation to obtain a deposited first type semiconductor, wherein the deposited first type semiconductor includes a gate;

[0021] Performing a deposition process on the deposited first-type semiconductor to obtain a re-deposited first-type semiconductor, wherein the re-deposited first-type semiconductor includes an insulating dielectric layer;

[0022] A super junction MOSFET device is generated based on the re-deposited first type semiconductor, and the super junction MOSFET device includes a source and a drain.

[0023] According to a method for preparing a super junction MOSFET device in an embodiment of the present application, at least the following beneficial effects are achieved: by setting a second type of semiconductor substrate, constructing a column structure and performing thermal diffusion, fine doping control of the first type of variable doping semiconductor column region and the second type of variable doping semiconductor epitaxial region can be achieved, which helps to improve the performance and stability of the device. After thermal oxidation treatment, the first type of semiconductor after thermal oxidation is obtained, and a gate oxide dielectric layer structure can be formed. After ion implantation treatment, the first type of semiconductor after ion implantation is obtained, and different doping regions can be formed, which optimizes the structural design of the device and helps to improve the performance and reliability of the device. The first type of semiconductor after deposition is obtained by deposition treatment to form a gate; the first type of semiconductor after deposition is obtained again by deposition treatment to form an insulating dielectric layer, which helps to reduce the contact resistance between the gate and the source and improve the conduction performance of the device. According to the super junction MOSFET device including the source and the drain, the whole preparation method can realize the vertical variable doping structure of the PN column of the device, and realize the high integration and micron-level manufacturing of the device.

[0024] In some embodiments, generating a super junction MOSFET device based on the re-deposited first type semiconductor includes: performing physical vapor deposition on the re-deposited first type semiconductor to obtain the super junction MOSFET device.

[0025] In some embodiments, the step of constructing a column structure based on the second type semiconductor substrate to obtain the first type semiconductor after thermal diffusion includes:

[0026] Performing epitaxial processing and ion implantation processing on the second-type semiconductor substrate according to a preset number of times to obtain an initial semiconductor device, wherein the initial semiconductor device includes a second-type variable doped semiconductor epitaxial region having a first-type variable doped semiconductor implantation region; wherein the second-type variable doped semiconductor epitaxial region is in contact with the upper surface of the second-type semiconductor substrate, and the second-type variable doped semiconductor epitaxial region has the first-type variable doped semiconductor implantation region;

[0027] The initial semiconductor device is subjected to thermal diffusion treatment to obtain a first type of semiconductor after thermal diffusion, wherein the first type of semiconductor after thermal diffusion is used to characterize a semiconductor device in which the first type of variable doping semiconductor implantation region in the second type of variable doping semiconductor epitaxial region is changed into the first type of variable doping semiconductor column region.

[0028] In some embodiments, the step of constructing a column structure based on the second type semiconductor substrate to obtain the first type semiconductor after thermal diffusion includes:

[0029] Performing a deposition process on the second-type semiconductor substrate to obtain an initial semiconductor epitaxial region;

[0030] Etching the initial semiconductor epitaxial region to obtain an etched semiconductor epitaxial region;

[0031] The semiconductor epitaxial region after etching is filled based on the preset second type of variable doping semiconductor to obtain the first type of semiconductor after thermal diffusion. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 is a structural schematic diagram of a super junction MOSFET device provided in an embodiment of the present application;

[0033] Figure 2 is a flow chart of a method for preparing a super junction MOSFET device provided in an embodiment of the present application;

[0034] Figure 3 yes Figure 2 A flow chart of step S202 in FIG.

[0035] Figure 4 yes Figure 2 Another flow chart of step S202 in ;

[0036] Figure 5 This is an application flow chart of a method for preparing a super junction MOSFET device provided in an embodiment of the present application;

[0037] Figure 6 This is another flow chart of a method for preparing a super junction MOSFET device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0038] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0039] It should be noted that, although the functional modules are divided in the device schematic diagram and the logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in a different order than the module division in the device or the order in the flowchart. The terms "first", "second", etc. in the specification, claims and the above drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0041] First, some nouns involved in this application are analyzed:

[0042] Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET): refers to a structure consisting of a metal gate, an oxide insulating layer, and a semiconductor material, and can also be called a MOS tube. In practical applications, the current flow in the channel is controlled by applying a voltage to the gate of the MOS tube, thereby realizing functions such as signal amplification and switch control.

[0043] Body diode: In N-type MOSFET devices, the body diode refers to the diode structure composed of the N-type drift region and the P-type base region of the MOSFET. The body diode is mainly used to withstand reverse voltage and conduct reverse current in MOSFET devices.

[0044] Superjunction MOSFET device: Superjunction refers to a structure in which multiple vertical PN junctions are arranged between the drain and the source. In a superjunction MOSFET, the N layer and the P layer are arranged in a vertical trench in the drift layer. When voltage is applied, the depletion layer expands horizontally and quickly merges to form a depletion layer equal to the depth of the trench. This superjunction structure has greatly broken through the theoretical limit of silicon, and the higher the rated voltage, the more obvious the decrease in on-resistance. However, the superjunction structure itself also has some problems and defects, such as increased difficulty in manufacturing process and deterioration of the reverse recovery characteristics of the device.

[0045] Non-equilibrium carriers: refers to excess carriers generated in semiconductors due to external excitation (such as light injection, electrical injection, etc.). In the equilibrium state, the concentration of electrons and holes in the semiconductor is equal, reaching a stable state. However, when the semiconductor is externally excited, excess electrons and holes will be generated. These excess carriers are non-equilibrium carriers.

[0046] In the MOSFET devices prepared by the related technology, there is a contradictory relationship between the breakdown voltage and the on-resistance. There is a 2.5-power functional relationship between the on-resistance and the breakdown voltage of the MOSFT devices prepared by the related technology, and this relationship is called the "silicon limit". In high-voltage application scenarios, the on-resistance of the MOSFT devices prepared by the related technology increases significantly with the increase of the breakdown voltage, and the power consumption also increases accordingly, resulting in a decrease in the power conversion efficiency of the power electronic system. Therefore, the "silicon limit" severely limits the application of MOSFET devices in high-voltage application scenarios.

[0047] In order to break through the "silicon limit" of MOSFET devices prepared by related technologies, the superjunction charge balance theory came into being. The on-resistance of the superjunction MOSFET device designed based on this theory is proportional to the breakdown voltage, that is, at the same withstand voltage level, the superjunction MOSFET has a lower on-resistance, which is due to the higher doping concentration in the drift region. When the superjunction MOSFET device is turned on, a highly doped N region can be formed as a current path for conduction; when the device is turned off, the carriers in the highly doped N region can be removed through the depletion effect of the PN junction to ensure the required withstand voltage level.

[0048] However, superjunction MOSFET devices have poor body diode reverse recovery characteristics. In general, there are two main reasons for the poor reverse recovery characteristics of superjunction MOSFET body diodes: one is that the parasitic large junction body diode (i.e., the body diode with a large junction area) will increase the storage of reverse recovery charge Qrr during the forward conduction phase; the other is that during the carrier sweep phase, the excessively fast carrier sweep speed leads to higher dir / dt (reverse recovery current rate) and dv / dt (instantaneous voltage change rate), which can easily cause circuit oscillation and lead to thermal damage to the device.

[0049] Specifically, the drift region of the super junction MOSFET prepared by the related technology is composed of highly doped P columns and N columns arranged alternately, so that the junction area of ​​the PN junction body diode formed by the two is larger. Due to the presence of a PN junction body diode with a larger junction area, when the PN junction body diode is forward-conducted, the hole carrier injection efficiency is enhanced, and the hole carriers stored in the drift region are much higher than the MOSFET device prepared by the related technology, and the minority carrier storage effect is more obvious. At the same time, the reverse recovery charge Qrr and the reverse recovery peak current Irrm of the super junction MOSFET body diode will also increase, which can easily cause thermal burnout of the device. At the same time, in the sweep-out stage of the unbalanced carriers in the drift region, the faster the sweep-out speed of the unbalanced carriers stored in the super junction MOSFET, the higher the reverse recovery current rate (ie, dir / dt, dir represents the reverse recovery current, and dt represents the reverse current recovery time), which makes the reverse recovery softness factor (which can be recorded as S) of the body diode of the super junction MOSFET smaller, so that the reverse recovery approaches hard recovery. Due to the existence of stray inductance in the power system, hard recovery can easily cause voltage spikes or circuit oscillations in the body diode, and may induce the opening of the parasitic transistor of the superjunction MOSFET, ultimately leading to device failure. It can be seen that the superjunction MOSFET prepared by the related technology is prone to circuit oscillation, which leads to thermal burnout and failure of the superjunction MOSFET.

[0050] However, in many high-voltage switching applications such as switching power supplies, white appliances, and new energy, MOSFET devices with good body diode characteristics and strong durability are required. The reverse recovery characteristics of the body diode directly affect the turn-on loss of the MOSFET device. In addition, for superjunction MOSFETs, the body diode should be able to withstand higher di / dt (instantaneous rate of change of current) and dv / dt. This is because in high-voltage and high-current applications, the switching speed of the MOSFET is faster, and the rate of change of current and voltage is larger. If the body diode cannot withstand higher di / dt and dv / dt, it is easy to cause damage or failure of the device.

[0051] In addition, in order to solve the above technical problems, the related art also proposes a method of using carrier lifetime control technology and new structural design to improve the reverse recovery performance of super junction MOSFET, improve the working efficiency of the circuit and reduce the risk of device failure. Specifically, under thermal equilibrium conditions, the electrons and holes in the drift region of the super junction MOSFET can be continuously balanced between generation and recombination. During the reverse recovery process of the body diode, the external excitation of the super junction MOSFET gradually disappears during the circuit conversion process, and the unbalanced minority carriers stored in the drift region will gradually return to the equilibrium value due to the recombination effect. The smaller the carrier lifetime, the higher its recombination rate, and the smaller the number of carriers stored in the drift region. Therefore, in order to increase the recombination rate of carriers, most of the related technologies use minority carrier lifetime control technology to change the carrier lifetime, thereby reducing the number of unbalanced minority carriers in the drift region, so as to achieve the purpose of reducing the reverse recovery time of the body diode.

[0052] At present, there are two main methods for carrier lifetime control technology. One method is to diffuse deep energy level heavy metals, such as gold and platinum, in the drift region to increase the carrier recombination center, so that the conduction band electrons and valence band holes recombine at the central recombination energy level in the bandgap, thereby achieving the purpose of reducing the carrier lifetime. Another method is to use electron irradiation technology to cause the crystal atoms to shift, form deep energy level recombination centers, and achieve local carrier lifetime control, thereby reducing the storage of non-equilibrium carriers in the drift region. Reducing the carrier lifetime can significantly increase the recombination rate of non-equilibrium carriers, accelerate the disappearance rate of the stored charge Qrr, and reduce the reverse recovery time trr and reverse recovery peak current Irrm. However, the carrier lifetime control technology also has obvious disadvantages. The heavy metal doping process is not only difficult and costly, but also increases the leakage current of the device. Electron irradiation technology also causes problems such as reduced device threshold voltage, reducing the robustness and practicality of the device.

[0053] Therefore, how to improve the reverse recovery performance of the super junction MOSFET body diode to avoid causing circuit oscillation, thereby avoiding thermal burnout and failure of the super junction MOSFET, has become a technical problem that needs to be solved urgently.

[0054] Based on this, the embodiments of the present application provide a super junction MOSFET device and a preparation method, which aim to improve the reverse recovery performance of the super junction MOSFET body diode, avoid causing circuit oscillation, and thus avoid thermal burnout and failure of the super junction MOSFET.

[0055] Please refer to Figure 1, the embodiment of the present application provides a super junction MOSFET device. Among them, the super junction MOSFET device provided by the present application may include a source 110, an insulating dielectric layer 120, a gate 130, a first type semiconductor base region 140, a second type highly doped semiconductor region 141, a first type highly doped semiconductor region 142, a second type of variable doped semiconductor epitaxial region 150, a first type of variable doped semiconductor column region 160, a second type of semiconductor substrate 170 and a drain 180. And the source 110, the insulating dielectric layer 120, the gate 130, the first type semiconductor base region 140, the second type of variable doped semiconductor epitaxial region 150, the second type of semiconductor substrate 170 and the drain 180 are arranged in sequence from top to bottom.

[0056] In one embodiment, if Figure 1 As shown, the upper surface of the drain 180 of the present application may be provided with a second type of semiconductor substrate 170, and the upper surface of the second type of semiconductor substrate 170 may be provided with a second type of variable doping semiconductor epitaxial region 150. A first type of variable doping semiconductor column region 160 may be provided in the second type of variable doping semiconductor epitaxial region 150, wherein the second type of variable doping semiconductor epitaxial region 150 and the first type of variable doping semiconductor column region 160 are regions constructed based on column structures of semiconductor regions of different conductivity types, the first type of variable doping semiconductor column region 160 includes a plurality of first type doping regions, and each first type doping region corresponds to a different doping concentration, and the second type of variable doping semiconductor epitaxial region 150 includes a plurality of second type doping regions, and each second type doping region corresponds to a different doping concentration. Because of this, a super junction MOSFET device provided in an embodiment of the present application can also be described as a super junction MOSFET device based on a P / N column vertical variable doping structure.

[0057] It should be noted that the first type semiconductor base region 140 contacts the upper surface of the first type variable doped semiconductor column region 160, and the lower surface of the first type variable doped semiconductor column region 160 does not contact the second type semiconductor substrate 170. The doping concentration of the second type semiconductor substrate is heavily doped.

[0058] In some embodiments, the material of the second type of variable doped semiconductor epitaxial region and the second type of semiconductor substrate may be any one of semiconductor materials such as silicon, silicon carbide, and gallium nitride.

[0059] In some embodiments, the second type semiconductor substrate 170 and the second type highly doped semiconductor region 141 have the same doping concentration; the second type semiconductor substrate 170 and the second type highly doped semiconductor region 141 have different thicknesses. For example, the doping concentration of the second type highly doped semiconductor region 141 may be 1×10 20 cm -3 The doping concentration of the second type semiconductor substrate 170 may be 1×10 20 cm -3The thickness of the second type highly doped semiconductor region 141 may be 0.25 μm, and the thickness of the second type semiconductor substrate 170 may be 10 μm.

[0060] It should be noted that in MOS tubes, two semiconductor materials of different conductivity types are usually included: N-type semiconductors and P-type semiconductors. N-type semiconductors are formed by doping pure silicon with impurities (such as phosphorus or arsenic). Doping with impurities (such as phosphorus or arsenic) provides additional free electrons, so that the N-type semiconductor has electron-dominated conductivity. P-type semiconductors are formed by doping pure silicon with other impurities (such as boron or aluminum). Doping with other impurities (such as boron or aluminum) forms holes, so that the P-type semiconductor has hole-dominated conductivity. Therefore, the first and second categories mentioned in this application can refer to either P-type or N-type, that is, if the first category refers to P-type, the second category refers to N-type; or the first category refers to N-type, and the second category refers to P-type.

[0061] It should be noted that for a P-type channel super junction MOSFET device, which can also be referred to as a super junction MOSFET device of an N-column structure, the doping type of its drift region is P-type. Specifically, in the prepared P-type channel super junction MOSFET device, the first type refers to N-type, and the second type refers to P-type, that is, the second type of variable doped semiconductor epitaxial region represents a P-type drift region, the first type of variable doped semiconductor column region represents an N-type variable doped semiconductor column region, and the first type of semiconductor base region represents an N-type semiconductor base region. For an N-type channel super junction MOSFET device, which can also be referred to as a super junction MOSFET device of a P-column structure, the doping type of its drift region is N-type. Similarly, in the prepared N-type channel super junction MOSFET device, the first type refers to P-type, and the second type refers to N-type. The embodiment of the present application takes an N-type channel super junction MOSFET as an example to describe how to improve the reverse recovery performance of the super junction MOSFET body diode.

[0062] In some embodiments, the first type of variable doped semiconductor column region includes at least three first type doped regions, and the doping concentration of the first type doped regions increases gradually from top to bottom. For example, the doping concentration of the first type doped regions can be 1.49×10 16 cm -3 , 2.29×10 16 cm -3 , 3.09×10 16 cm -3 . Among them, cm -3It represents the unit of doping concentration per cubic centimeter. The thickness of the first type of variable doping semiconductor column region 160 can be 45μm. It can be seen from this that, compared with the super junction MOSFET device constructed by the related art, the first type of variable doping semiconductor column region constructed by the present application is a structure constructed by doping regions of multiple different doping concentrations. It is precisely because of this structure that it is beneficial to suppress the injection of reverse recovery charge Qrr into the drift region of the super junction MOSFET and slow down the sweeping speed of carriers, so that the reverse recovery characteristics of the super junction MOSFET are improved, avoiding circuit oscillation, thereby avoiding thermal burnout and failure of the super junction MOSFET. Since the highly doped P column and N column internal doping concentration of the drift region of the super junction MOSFET prepared by the related art are always consistent, the "vertical variable doping structure" of the embodiment of the present application is not realized, so that the local resistance of the P column is larger than the local resistance of the P column of the embodiment of the present application, resulting in too strong reverse recovery characteristics. The specific reasons have been explained in the above background technology and will not be repeated here.

[0063] In some embodiments, the second type of variable doped semiconductor epitaxial region includes at least three second type doped regions, and the doping concentration of the second type doped regions increases gradually from top to bottom. For example, the doping concentration of the second type doped regions can be 1.49×10 16 cm -3 , 2.29×10 16 cm -3 , 3.09×10 16 cm -3 The thickness of the second type variable doped semiconductor epitaxial region 150 may be 53 micrometers (ie, μm).

[0064] In a specific embodiment, the first type of variable doping semiconductor column region 160 includes three first type doping regions, and each first type doping region has a different doping concentration. For example, the three first type doping regions in the first type of variable doping semiconductor column region 160 can be respectively recorded as a first type of medium-low doping region 161, a first type of medium doping region 162, and a first type of medium-high doping region 163 from top to bottom. For example, the doping concentration of the first type of medium-low doping region 161 can be 1.49×10 16 cm -3 The doping concentration of the first type medium doping region 162 may be 2.29×10 16 cm -3 The doping concentration of the first type of high doping region 163 may be 3.09×10 16 cm -3The second type of variable doped semiconductor epitaxial region 150 includes three second type doped regions, and each second type doped region has a different doping concentration. Similarly, the three second type doped regions in the second type of variable doped semiconductor epitaxial region 150 can be respectively recorded as the second type medium-low doped region 151, the second type medium doped region 152, and the second type medium-high doped region 153 from top to bottom. For example, the doping concentration of the second type medium-low doped region 151 can be 1.49×10 16 cm -3 The doping concentration of the second medium doping region 152 may be 2.29×10 16 cm -3 The doping concentration of the second type medium and high doping region 153 can be 3.09×10 16 cm -3 .

[0065] It can be seen that the doping concentration of the second type of low doping region 151 can be the same as the doping concentration of the first type of low doping region 161, the doping concentration of the second type of medium doping region 152 can be the same as the doping concentration of the first type of medium doping region 162, and the doping concentration of the second type of high doping region 153 can be the same as the doping concentration of the first type of high doping region 163.

[0066] It should be noted that the heavy doping, high doping, medium-high doping, medium doping and medium-low doping described in the embodiments of the present application are used to characterize the state of the impurity concentration of semiconductor doping, and are all based on the impurity concentration of doping. Moreover, the comparison relationship between the concentration values ​​corresponding to heavy doping, high doping, medium-high doping, medium doping and medium-low doping is: the impurity concentration of heavy doping > the impurity concentration of high doping > the impurity concentration of medium-high doping > the impurity concentration of medium doping > the impurity concentration of medium-low doping.

[0067] It should be noted that, in one embodiment, the heavily doped impurity concentration may be greater than the highly doped impurity concentration. In another embodiment, the heavily doped impurity concentration may be equal to the highly doped impurity concentration. For example, the doping concentration of the heavily doped second type semiconductor substrate is the same as the doping concentration of the second type highly doped semiconductor region, both of which are 1×10 20 cm -3 .

[0068] In one embodiment, the boundaries of different first-type doping regions in the first-type variable doping semiconductor column region 160 are uniform, that is, the boundary line of different first-type doping regions can be a horizontal line. Similarly, the boundaries of different second-type doping regions in the second-type variable doping semiconductor epitaxial region 150 are uniform, and the boundary line of different second-type doping regions can be a horizontal line. Therefore, by uniformly arranging three first-type doping regions with horizontal boundaries in the first-type variable doping semiconductor column region, a multi-level doping structure of the device can be realized, which helps to improve the performance of the semiconductor device, such as increasing the charge carrying capacity, reducing the resistance, and improving the breakdown voltage. The embodiment of the present application can optimize the performance of the device and meet specific application requirements by reasonably designing a multi-level doping structure.

[0069] Based on this, in a specific embodiment, in order to achieve charge balance between the P column and the N column, the number of first-type doped regions included in the first-type variable-doped semiconductor column region is the same as the number of second-type doped regions included in the second-type variable-doped semiconductor epitaxial region, so that one second-type doped region can correspond to one first-type doped region.

[0070] At the same time, in order to achieve the expected effect of charge balance between the P column and the N column, thereby achieving the expected effect of improving the "silicon limit", the concentration can be adjusted so that each second-type doping region is at the same horizontal position as the corresponding first-type doping region, so that the boundary line of different first-type doping regions in the first-type variable doping semiconductor column region and the boundary line of different second-type doping regions in the second-type variable doping semiconductor epitaxial region can be at the same horizontal line. And the doping concentration of a first-type doping region corresponding to a second-type doping region can be the same.

[0071] Specifically, the boundary line between the second type of medium-low doping region 151 and the second type of medium-doping region 152 and the boundary line between the first type of medium-low doping region 161 and the first type of medium-doping region 162 can be on the same horizontal line, and the boundary line between the second type of medium-doping region 152 and the second type of medium-high doping region 153 and the boundary line between the first type of medium-doping region 162 and the first type of medium-high doping region 163 can be on the same horizontal line, that is, the impurity concentration of the doping region between any two boundary lines is also the same. In other words, if the above boundary lines are not on the same horizontal line, the charge between the first type of variable doping semiconductor column region 160 and the second type of variable doping semiconductor epitaxial region 150 cannot reach the expected equilibrium state, thereby failing to achieve the expected effect of improving the "silicon limit", and may also cause degradation of other parameters of the device, such as reduced device withstand voltage performance, increased on-resistance, etc.

[0072] It should be noted that the first type of semiconductor base region 140 is in contact with the upper surface of the first type of variable-doped semiconductor column region 160, the first type of highly doped semiconductor region 142 and the second type of highly doped semiconductor region 141 are arranged inside the first type of semiconductor base region 140, and the first type of highly doped semiconductor region 142 and the second type of highly doped semiconductor region 141 are in contact with the source 110 respectively; the gate 130 is located on the upper surface of the first type of semiconductor base region 140 and the second type of variable-doped semiconductor epitaxial region 150, and the gate 130 and the source 110 are isolated by an insulating dielectric layer 120.

[0073] It should be noted that the contacts between the first type highly doped semiconductor region 142 and the second type highly doped semiconductor region 141 and the source are both ohmic contacts, which can effectively reduce the contact resistance and improve the conduction performance and efficiency of the device.

[0074] In some embodiments, the thickness of the first type semiconductor base region 140 is greater than the thickness of the first type highly doped semiconductor region 142; the thickness of the first type highly doped semiconductor region 142 is greater than the thickness of the second type highly doped semiconductor region 141. For example, the thickness of the first type semiconductor base region 140 may be 1.5 μm, the thickness of the first type highly doped semiconductor region 142 may be 0.45 μm, and the thickness of the second type highly doped semiconductor region 141 may be 0.25 μm.

[0075] In some embodiments, the doping concentration of the first type semiconductor base region 140 is less than the doping concentration of the first type highly doped semiconductor region 142; the doping concentration of the first type highly doped semiconductor region 142 is less than the doping concentration of the second type highly doped semiconductor region 141. For example, the doping concentration of the first type semiconductor base region 140 is 1×10 17 cm -3 The doping concentration of the first type highly doped semiconductor region 142 is 3×10 19 cm -3 The doping concentration of the second type highly doped semiconductor region 141 is 1×10 20 cm -3 .

[0076] In some embodiments, the super junction MOSFET device further includes a gate oxide dielectric layer, the gate oxide dielectric layer is located on the upper surface of the first type semiconductor base region 140 and the second type variable doped semiconductor epitaxial region 150, and the gate 130 refers to a structure obtained by deposition on the upper surface of the gate oxide dielectric layer. For example, the thickness of the gate oxide dielectric layer can be 0.1 μm, 0.05 μm, which is not specifically limited here. The gate oxide dielectric layer is deposited by a thermal oxidation process.

[0077] In a specific embodiment, the gate 130 is a polysilicon gate, and the thickness and doping concentration of the gate can be flexibly adjusted according to actual needs, and are not specifically limited here. For example, the thickness of the gate can be 4 μm, and the doping concentration can be 1×10 20 cm -3 The gate 130 is formed on the upper surface of the gate oxide dielectric layer by a deposition process.

[0078] The embodiment of the present application provides a super junction MOSFET device based on a P / N column vertical variable doping structure. Specifically, by designing the P / N column structure (i.e., the first type variable doping semiconductor column region 160 and the second type variable doping semiconductor epitaxial region 150), the electric field distribution can be changed, and the electric field peak in the drift region can be reduced, thereby slowing down the speed of carriers and reducing the injection of reverse recovery charge Qrr. The P / N column structure can optimize the electric field distribution, reduce the electric field concentration effect, and help slow down the drift speed of carriers.

[0079] It should be noted that the vertical variable doping super junction MOSFET is a metal oxide semiconductor field effect transistor with a special structure. In the vertical variable doping super junction MOSFET structure, multiple PN junctions are formed by introducing multiple vertical doping regions of N-type semiconductors and P-type semiconductors in the drift region, thereby forming a super junction structure. In the embodiment of the present application, the reverse recovery characteristics of the device are effectively improved and the robustness of the device is improved by introducing a vertical variable doping P column structure (i.e., the first type of variable doping semiconductor column region 160) in the vertical variable doping N-type drift region (i.e., the second type of variable doping semiconductor epitaxial region 150). Compared with the P-column structure super junction MOSFET prepared by the related technology, the reverse recovery peak current Irrm of a super junction MOSFET device in the embodiment of the present application is reduced by 2.8%, and the softness factor S is increased by 55%.

[0080] In a specific experiment, compared with the performance of super junction MOSFET prepared by related technology, the reverse recovery peak current Irrm of a super junction MOSFET device provided by the embodiment of the present application is reduced by 2.8%, the reverse recovery storage charge Qrr is reduced by 2.0%, the reverse recovery current rate dir / dt is reduced by 32%, and the softness factor S is increased by 55%. Compared with the super junction MOSFET prepared by related technology with the same specifications, there is no significant change in static parameters. This is precisely because the embodiment of the present application sets three first-class doping regions with doping concentrations gradually increasing from top to bottom in the first-class variable doping semiconductor column region, and sets three second-class doping regions with doping concentrations gradually increasing from top to bottom in the second-class variable doping semiconductor epitaxial region, and the boundary line of a first-class doping region corresponding to a second-class doping region can be on the same horizontal line, and the doping concentration of a first-class doping region corresponding to a second-class doping region can be the same.

[0081] It can be seen from this that a super junction MOSFET device based on a vertical variable doping structure of a P / N column provided in an embodiment of the present application is conducive to suppressing the injection of reverse recovery charge Qrr into the drift region of the super junction MOSFET and slowing down the sweeping speed of carriers, thereby improving the reverse recovery characteristics of the super junction MOSFET. The P / N column vertical variable doping super junction MOSFET structure can achieve an improvement in the local resistance of the drift region P column (i.e., the first type of variable doping semiconductor column region 160) by adjusting the concentration of P-type semiconductor ion implantation. Therefore, a super junction MOSFET device provided in an embodiment of the present application helps to improve the reverse recovery performance of the super junction MOSFET body diode, avoid causing circuit oscillation, and thus avoid thermal burnout and failure of the super junction MOSFET.

[0082] Please refer to Figure 2 , Figure 2 is an optional flow chart of a method for preparing a super junction MOSFET device provided in an embodiment of the present application, Figure 2 The method may include but is not limited to steps S201 to S207.

[0083] Step S201, providing a second type of semiconductor substrate;

[0084] Step S202, constructing a column structure based on the second type semiconductor substrate to obtain the first type semiconductor after thermal diffusion, wherein the first type semiconductor after thermal diffusion includes the second type variable doping semiconductor epitaxial region and the first type variable doping semiconductor column region filled in the second type variable doping semiconductor epitaxial region;

[0085] Step S203, performing thermal oxidation treatment on the first type semiconductor after thermal diffusion to obtain the first type semiconductor after thermal oxidation, wherein the first type semiconductor after thermal oxidation is used to characterize a semiconductor device having a gate oxide dielectric layer structure on the upper surface of the second type variable doped semiconductor epitaxial region;

[0086] Step S204, performing ion implantation on the thermally oxidized first type semiconductor to obtain the ion implanted first type semiconductor, wherein the ion implanted first type semiconductor includes the first type semiconductor base region, the second type highly doped semiconductor region and the first type highly doped semiconductor region;

[0087] Step S205, performing a deposition process on the first type semiconductor after ion implantation to obtain a deposited first type semiconductor, wherein the deposited first type semiconductor includes a gate;

[0088] Step S206, performing a deposition process on the deposited first type semiconductor to obtain a re-deposited first type semiconductor, wherein the re-deposited first type semiconductor includes an insulating dielectric layer;

[0089] Step S207 , generating a super junction MOSFET device based on the re-deposited first type semiconductor, the super junction MOSFET device comprising a source and a drain.

[0090] In the steps S201 to S207 shown in the embodiment of the present application, by setting a second type of semiconductor substrate, constructing a column structure and performing thermal diffusion, fine doping control of the first type of variable doping semiconductor column area and the second type of variable doping semiconductor epitaxial area can be achieved, which helps to improve the performance and stability of the device. After the thermal oxidation treatment, the first type of semiconductor after thermal oxidation is obtained, and a gate oxide dielectric layer structure can be formed. After the ion implantation treatment, the first type of semiconductor after ion implantation is obtained, and different doping regions can be formed, which optimizes the structural design of the device and helps to improve the performance and reliability of the device. The first type of semiconductor after deposition is obtained by deposition treatment to form a gate; the first type of semiconductor after deposition is obtained again by deposition treatment to form an insulating dielectric layer, which helps to reduce the contact resistance between the gate and the source and improve the conduction performance of the device. According to the super junction MOSFET device including the source and the drain, the whole preparation method can realize the vertical variable doping structure of the PN column of the device, and realize the high integration and micron-level manufacturing of the device.

[0091] In step S201 of some embodiments, the thickness and doping concentration of the second type of semiconductor substrate can be set according to actual needs, and are not specifically limited. In a specific embodiment, the second type of semiconductor substrate is an N-type substrate, and the doping concentration of the N-type substrate can be 1×10 20 cm -3 , the thickness of the N-type substrate can be 10μm.

[0092] See also Figure 3 In some embodiments, step S202 may include but is not limited to steps S301 to S302:

[0093] Step S301, performing epitaxial processing and ion implantation processing on the second type semiconductor substrate according to a preset number of times to obtain an initial semiconductor device, wherein the initial semiconductor device includes a second type variable doped semiconductor epitaxial region having a first type variable doped semiconductor implantation region; wherein the second type variable doped semiconductor epitaxial region is in contact with an upper surface of the second type semiconductor substrate, and the second type variable doped semiconductor epitaxial region has a first type variable doped semiconductor implantation region;

[0094] Step S302, performing thermal diffusion treatment on the initial semiconductor device to obtain a first type semiconductor after thermal diffusion, wherein the first type semiconductor after thermal diffusion is used to characterize a semiconductor device in which a first type variable doped semiconductor implantation region in a second type variable doped semiconductor epitaxial region is changed into a first type variable doped semiconductor column region.

[0095] In step S301 of some embodiments, the initial semiconductor device refers to a device having a second type of variable doped semiconductor epitaxial region having a first type of variable doped semiconductor injection region after the second type of semiconductor substrate is subjected to epitaxial treatment and ion implantation treatment. The second type of semiconductor substrate is subjected to epitaxial treatment, that is, a layer of the second type of variable doped semiconductor is deposited on the upper surface of the second type of semiconductor substrate to form a second type of variable doped semiconductor epitaxial region. The epitaxial treatment can be achieved by techniques such as chemical vapor deposition (CVD) or molecular beam epitaxy (MBE). The second type of variable doped semiconductor epitaxial region is subjected to ion implantation treatment, that is, the first type of variable doped semiconductor is implanted into the second type of variable doped semiconductor epitaxial region by ion implantation technology to form a first type of variable doped semiconductor injection region. Ion implantation can regulate the doping concentration and depth of semiconductor materials, and the device performance can be optimized by regulating the doping concentration and depth of semiconductor materials. The preset number of times refers to the number of repetitions of epitaxial growth and ion implantation on the second type semiconductor substrate. Through multiple epitaxial growth and multiple ion implantation processes and setting the concentration of each ion implantation, a second type of variable doping semiconductor epitaxial region having a vertically variable doped first type of variable doping semiconductor implantation region can be formed on the heavily doped second type semiconductor substrate.

[0096] In step S302 of some embodiments, the first type semiconductor after thermal diffusion refers to a semiconductor device having a second type of variable doped semiconductor epitaxial region and a first type of variable doped semiconductor column region disposed therein after thermal diffusion of the initial semiconductor device. Thermal diffusion can achieve fine doping control of the first type of variable doped semiconductor column region and the second type of variable doped semiconductor epitaxial region, which helps to improve the performance and stability of the device.

[0097] See also Figure 4 In some embodiments, step S202 may include but is not limited to steps S401 to S403:

[0098] Step S401, performing a deposition process on the second type semiconductor substrate to obtain an initial semiconductor epitaxial region;

[0099] Step S402, etching the initial semiconductor epitaxial region to obtain an etched semiconductor epitaxial region;

[0100] Step S403, filling the etched semiconductor epitaxial region based on the preset second type of variable doping semiconductor to obtain the first type of semiconductor after thermal diffusion.

[0101] In step S401 of some embodiments, the surface of the second type semiconductor substrate needs to be cleaned first to ensure that there are no impurities and contaminants on the surface to provide a good deposition base. Deposition is performed on the clean surface of the second type semiconductor substrate, that is, a layer of semiconductor material is deposited on the surface by chemical vapor deposition (CVD) or molecular beam epitaxy (MBE) and other techniques to form an initial semiconductor epitaxial region. The deposited semiconductor material can be the first type of variable doped semiconductor or other required materials.

[0102] In step S402 of some embodiments, the etched semiconductor epitaxial region refers to a semiconductor device after the initial semiconductor epitaxial region is etched. The etching process can achieve precise control of the morphology and thickness of the semiconductor epitaxial region.

[0103] In step S403 of some embodiments, firstly, it is necessary to prepare a filling material of the first type semiconductor after thermal diffusion, and the filling material is usually a preset first type semiconductor. The filling material is placed in the etched semiconductor epitaxial region to obtain the first type variable doping semiconductor column region inside the second type variable doping semiconductor epitaxial region.

[0104] In step S203 of some embodiments, the thermally oxidized first type semiconductor is a semiconductor device having a gate oxide dielectric layer structure on the upper surface of the second type variable doped semiconductor epitaxial region obtained by thermally oxidizing the thermally diffused first type semiconductor.

[0105] In step S204 of some embodiments, the first type semiconductor after ion implantation refers to a semiconductor device including a first type semiconductor base region, a second type highly doped semiconductor region and a first type highly doped semiconductor region obtained after ion implantation of the first type semiconductor after thermal oxidation.

[0106] In step S205 of some embodiments, the deposited first type semiconductor refers to a semiconductor device including a gate obtained after a deposition process is performed on the first type semiconductor after ion implantation.

[0107] In step S206 of some embodiments, the re-deposited first-type semiconductor refers to a semiconductor device including an insulating dielectric layer obtained after a deposition process is performed on the deposited first-type semiconductor.

[0108] In step S207 of some embodiments, the super junction MOSFET device refers to a semiconductor device including a source and a drain generated based on the first type semiconductor after re-deposition. Physical vapor deposition (PVD) generally includes two main technologies: sputtering deposition and chemical vapor deposition.

[0109] It should be noted that the first type of semiconductor after re-deposition can be subjected to physical vapor deposition to prepare the source and drain to obtain a super junction MOSFET device. The source and drain can also be prepared by other methods, such as using Ti / Ni / Ag or Ni / Pd / Au processes, but are not limited thereto.

[0110] The embodiment of the present application can achieve fine doping control of the first type of variable doped semiconductor column region and the second type of variable doped semiconductor epitaxial region by setting a second type of semiconductor substrate, constructing a column structure and performing thermal diffusion, which helps to improve the performance and stability of the device. After thermal oxidation treatment, the first type of semiconductor after thermal oxidation is obtained, and a gate oxide dielectric layer structure can be formed. After ion implantation treatment, the first type of semiconductor after ion implantation is obtained, and different doping regions can be formed. The first type of semiconductor after deposition is obtained by deposition treatment to form a gate; the first type of semiconductor after re-deposition is obtained by deposition treatment again to form an insulating dielectric layer, which helps to reduce the contact resistance between the gate and the source and improve the conduction performance of the device. According to the super junction MOSFET device including the source and the drain, the whole preparation method can realize the vertical variable doping structure of the PN column of the device, and realize the high integration and micron-level manufacturing of the device.

[0111] The specific implementation of the method for preparing a super junction MOSFET device is basically the same as the specific embodiment of the above-mentioned super junction MOSFET device, and will not be repeated here.

[0112] See also Figure 5In some application embodiments, step (1) is to provide a second type semiconductor substrate 510; the second type semiconductor substrate 510 is subjected to epitaxial treatment and ion implantation treatment; a photoresist 511 is placed on the second type semiconductor substrate 510. During the ion implantation treatment, the photoresist can effectively protect and position the substrate, thereby helping to ensure the accuracy and stability of the ion implantation treatment process. Steps (2) to (6) are to perform epitaxial treatment and ion implantation treatment on the second type semiconductor substrate 510 for multiple times to obtain an initial semiconductor device, wherein the initial semiconductor device comprises a second type variable doped semiconductor epitaxial region having a first type variable doped semiconductor implantation region; wherein the second type variable doped semiconductor epitaxial region is in contact with the upper surface of the second type semiconductor substrate, and the second type variable doped semiconductor epitaxial region has a first type variable doped semiconductor implantation region. Step (7) is to perform thermal diffusion treatment on the initial semiconductor device to obtain a first type semiconductor after thermal diffusion, wherein the first type semiconductor after thermal diffusion is used to characterize a semiconductor device in which the first type variable doped semiconductor implantation region in the second type variable doped semiconductor epitaxial region 550 is changed into a first type variable doped semiconductor column region 560. The three first-type doping regions in the first-type variable doping semiconductor column region 560 are respectively recorded as the first-type medium-low doping region 561, the first-type medium doping region 562, and the first-type medium-high doping region 563 from top to bottom. The three first-type doping regions in the second-type variable doping semiconductor epitaxial region 550 are respectively recorded as the second-type medium-low doping region 551, the second-type medium doping region 552, and the second-type medium-high doping region 553 from top to bottom. Step (8), ion implantation treatment is performed on the first-type semiconductor after thermal diffusion to obtain the ion-implanted first-type semiconductor having the first-type semiconductor base region 540, the second-type highly doped semiconductor region 541 and the first-type highly doped semiconductor region 542; the ion-implanted first-type semiconductor is deposited to obtain the deposited first-type semiconductor including the gate 530; the deposited first-type semiconductor is deposited to obtain the re-deposited first-type semiconductor including the insulating dielectric layer 520; the source 570 and the drain 580 are prepared based on the re-deposited first-type semiconductor to generate a super junction MOSFET device.

[0113] It should be noted that, when performing step (7), the photoresist 511 has been removed.

[0114] See also Figure 6 In a specific embodiment, in order to prepare a super junction MOSFET device with a vertical variable doping P column structure, that is, the first type represents P type and the second type represents N type. At this time, the process of preparing the super junction MOSFET device is shown in the following steps:

[0115] Step S601, providing a heavily doped N-type substrate; in step S601, this step is substantially the same as the specific embodiment of the above-mentioned step S201, and will not be described in detail herein.

[0116] Step S602, through multiple epitaxial growth and multiple ion implantation processes, the concentration of each ion implantation is set to form a vertically doped N-type epitaxial region with a vertically doped P-type implantation region on a heavily doped N-type substrate; in step S602, this step is basically the same as the specific embodiment of the above-mentioned step S301, and will not be repeated here.

[0117] Step S603, through a thermal diffusion process, the vertical variable doping P type injection region forms a vertical variable doping P column structure in the vertical variable doping N type epitaxial region; in step S603, this step is basically the same as the specific embodiment of the above step S302, and will not be repeated here.

[0118] Step S604, forming a gate oxide dielectric layer on the upper surface of the vertical variable-doped N-type epitaxial region by thermal oxidation process; in step S604, this step is basically the same as the specific embodiment of the above-mentioned step S203, and will not be repeated here.

[0119] Step S605, through the ion implantation process, a P base region (i.e., the first type of semiconductor base region), an N plus region (i.e., the second type of highly doped semiconductor region) and a P plus region (i.e., the first type of highly doped semiconductor region) are formed on the top of the vertically variable-doped N-type epitaxial region; in step S605, this step is basically the same as the specific embodiment of the above-mentioned step S204, and will not be repeated here.

[0120] Step S606, forming a polysilicon gate on the upper surface of the gate oxide dielectric layer through a deposition process; in step S606, this step is basically the same as the specific embodiment of the above-mentioned step S205, and will not be repeated here.

[0121] Step S607, obtaining an insulating dielectric layer through a deposition process; in step S607, this step is substantially the same as the specific embodiment of the above-mentioned step S206, and will not be described again.

[0122] Step S608, preparing a source electrode and a drain electrode. In step S608, this step is substantially the same as the specific embodiment of the above step S207, and will not be described in detail here.

[0123] The embodiments described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. Those skilled in the art will appreciate that with the evolution of technology and the emergence of new application scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0124] Those skilled in the art will appreciate that the technical solutions shown in the figures do not constitute a limitation on the embodiments of the present application, and may include more or fewer steps than shown in the figures, or a combination of certain steps, or different steps.

[0125] The terms "first", "second", "third", "fourth", etc. (if any) in the specification of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0126] It should be understood that in the present application, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0127] The preferred embodiments of the present invention are described above with reference to the accompanying drawings, but the scope of the rights of the present invention is not limited thereto. Any modification, equivalent substitution and improvement made by a person skilled in the art without departing from the scope and essence of the present invention should be within the scope of the rights of the present invention.

Claims

1. A super junction MOSFET device, characterized in that: The super junction MOSFET device comprises a source, an insulating dielectric layer, a gate, a first type semiconductor base region, a second type highly doped semiconductor region, a first type highly doped semiconductor region, a second type variable doped semiconductor epitaxial region, a second type semiconductor substrate and a drain; The upper surface of the drain is provided with the second type semiconductor substrate, and the upper surface of the second type semiconductor substrate is provided with the second type variable doping semiconductor epitaxial region; the second type variable doping semiconductor epitaxial region is provided with the first type variable doping semiconductor column region, wherein the second type variable doping semiconductor epitaxial region and the first type variable doping semiconductor column region are regions constructed based on column structures of semiconductor regions of different conductivity types, the first type variable doping semiconductor column region includes at least three first type doping regions, and the doping concentration of the first type doping region gradually increases from top to bottom, and the second type variable doping semiconductor epitaxial region includes at least three second type doping regions, and the doping concentration of the second type doping region gradually increases from top to bottom; The first type of semiconductor base region is in contact with the upper surface of the first type of variable-doped semiconductor column region, the first type of highly doped semiconductor region and the second type of highly doped semiconductor region are arranged inside the first type of semiconductor base region, and the first type of highly doped semiconductor region and the second type of highly doped semiconductor region are in contact with the source respectively; the gate is located on the upper surfaces of the first type of semiconductor base region and the second type of variable-doped semiconductor epitaxial region, and the gate is isolated from the source by the insulating medium layer.

2. A super junction MOSFET device according to claim 1, characterized in that: The thickness of the first-type semiconductor base region is greater than the thickness of the first-type highly-doped semiconductor region; the thickness of the first-type highly-doped semiconductor region is greater than the thickness of the second-type highly-doped semiconductor region.

3. A super junction MOSFET device according to claim 2, characterized in that: The second type of semiconductor substrate and the second type of highly doped semiconductor region have the same doping concentration; the second type of semiconductor substrate and the second type of highly doped semiconductor region have different thicknesses.

4. A super junction MOSFET device according to claim 2, characterized in that: The doping concentration of the first-type semiconductor base region is less than the doping concentration of the first-type highly-doped semiconductor region; and the doping concentration of the first-type highly-doped semiconductor region is less than the doping concentration of the second-type highly-doped semiconductor region.

5. A super junction MOSFET device according to claim 1, characterized in that: The materials of the second type of variable doped semiconductor epitaxial region and the second type of semiconductor substrate include silicon, silicon carbide, and gallium nitride semiconductor materials.

6. A super junction MOSFET device according to claim 1, characterized in that: The super junction MOSFET device also includes a gate oxide dielectric layer, which is located on the upper surface of the first type semiconductor base region and the second type variable doped semiconductor epitaxial region, and the gate refers to a structure obtained by deposition processing on the upper surface of the gate oxide dielectric layer.

7. A method for preparing a super junction MOSFET device, characterized in that: include: providing a second type of semiconductor substrate; A column structure is constructed based on the second-type semiconductor substrate to obtain a first-type semiconductor after thermal diffusion, wherein the first-type semiconductor after thermal diffusion includes a second-type variable doping semiconductor epitaxial region and a first-type variable doping semiconductor column region filled in the second-type variable doping semiconductor epitaxial region; the first-type variable doping semiconductor column region includes at least three first-type doping regions, and the doping concentration of the first-type doping region gradually increases from top to bottom; the second-type variable doping semiconductor epitaxial region includes at least three second-type doping regions, and the doping concentration of the second-type doping region gradually increases from top to bottom; Performing thermal oxidation treatment on the thermally diffused first type semiconductor to obtain the thermally oxidized first type semiconductor, wherein the thermally oxidized first type semiconductor is used to characterize a semiconductor device having a gate oxide dielectric layer structure on the upper surface of the second type variable doped semiconductor epitaxial region; Performing ion implantation on the thermally oxidized first-type semiconductor to obtain the ion-implanted first-type semiconductor, wherein the ion-implanted first-type semiconductor includes a first-type semiconductor base region, a second-type highly doped semiconductor region, and a first-type highly doped semiconductor region; Performing a deposition process on the first type semiconductor after ion implantation to obtain a deposited first type semiconductor, wherein the deposited first type semiconductor includes a gate; Performing a deposition process on the deposited first-type semiconductor to obtain a re-deposited first-type semiconductor, wherein the re-deposited first-type semiconductor includes an insulating dielectric layer; A super junction MOSFET device is generated based on the re-deposited first type semiconductor, and the super junction MOSFET device includes a source and a drain.

8. The preparation method according to claim 7, characterized in that: The column structure is constructed based on the second type of semiconductor substrate to obtain the first type of semiconductor after thermal diffusion, including: Performing epitaxial processing and ion implantation processing on the second-type semiconductor substrate according to a preset number of times to obtain an initial semiconductor device, wherein the initial semiconductor device includes a second-type variable doped semiconductor epitaxial region having a first-type variable doped semiconductor implantation region; wherein the second-type variable doped semiconductor epitaxial region is in contact with the upper surface of the second-type semiconductor substrate, and the second-type variable doped semiconductor epitaxial region has the first-type variable doped semiconductor implantation region; The initial semiconductor device is subjected to thermal diffusion treatment to obtain a first type of semiconductor after thermal diffusion, wherein the first type of semiconductor after thermal diffusion is used to characterize a semiconductor device in which the first type of variable doping semiconductor implantation region in the second type of variable doping semiconductor epitaxial region is changed into the first type of variable doping semiconductor column region.

9. The preparation method according to claim 7, characterized in that: The method of generating a super junction MOSFET device based on the re-deposited first type semiconductor comprises: performing physical vapor deposition on the re-deposited first type semiconductor to obtain the super junction MOSFET device.

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