Buffer amplifier, driver chip and electronic equipment

Abstract

The present disclosure relates to a buffer amplifier, a driver chip and an electronic device. The buffer amplifier includes: an operational amplifier and a voltage regulating module. The voltage regulating module is configured to work with a target duration as a cycle. During a first period, the voltage at the voltage output terminal of the voltage regulating module is established from an initial voltage to an intermediate voltage; during a second period, the voltage at the voltage output terminal is established to a target voltage, the difference between the target voltage and the input voltage is smaller than the difference between the intermediate voltage and the input voltage, and the voltage at the output terminal of the operational amplifier is established to a preset voltage that is independent of the input voltage. The embodiment of the present disclosure realizes the decoupling of the output voltage of the output terminal of the operational amplifier inside the buffer amplifier from the target output voltage of the entire buffer amplifier output terminal, realizes the true rail-to-rail input and output characteristics of the buffer amplifier, and has lower circuit complexity, area and power consumption.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular to a buffer amplifier, a driver chip and an electronic device. Background Art

[0002] Buffer amplifier (BUF AMP) is widely used in analog integrated circuit design, usually as an interface between two circuits with different impedance levels, to ensure that the signal integrity is maintained when it is transmitted from one circuit to another. Figure 1 As shown in the figure, in a signal chain, the input end of the subsequent circuit is a load for the previous circuit. When the driving capability of the previous circuit is too weak to drive the input end of the subsequent circuit, a voltage buffer amplifier needs to be inserted between the previous circuit and the subsequent circuit. The voltage buffer amplifier has high input impedance and strong output driving capability, which ensures that the previous circuit can drive the buffer amplifier sufficiently and the buffer amplifier can drive the subsequent circuit sufficiently, thereby ensuring the signal integrity of the entire signal chain.

[0003] The basic structure of a buffer amplifier is as follows: Figure 2 As shown in the figure, it includes an operational amplifier (AMP) with dual-end input and single-end output. The positive input terminal (+) of the operational amplifier serves as the input port (Input) of the buffer amplifier, and the negative input terminal (-) is connected to the output terminal of the AMP to form a unit gain negative feedback structure. Therefore, the gain of the buffer amplifier is 1, that is, when the AMP is working normally, the output is equal to the input voltage. The output of the buffer amplifier can be connected to a variety of load types. Figure 2 The figure shows an equivalent model of a typical switched capacitor load. The actual load may also be a resistor, capacitor, etc.

[0004] In some applications, the buffer amplifier is not only required to have high input impedance and high driving capability, but also has certain requirements for its input and output range. For example, in some analog-to-digital converter (ADC) circuits, the reference voltage (VREF) buffer amplifier often needs to have full rail-to-rail input and output capabilities, that is, the input and output range can be as low as ground (or VSS) and as high as the power supply voltage (VDD).

[0005] However, for a conventional amplifier, its output range is usually not completely rail-to-rail. Figure 3As shown, it is the output stage of a conventional amplifier, which is usually composed of two MOS tubes, namely Mp and Mn. If the drain-source voltage (Vds) of Mp and Mn is too small, the MOS tube will be pressed into the linear region. At this time, the amplifier gain becomes significantly smaller, and the output settling speed becomes slower, resulting in a large error near the output power supply or ground. In order to ensure that Mp and Mn are not pressed into the linear region, it is usually necessary to ensure that their |Vds| is greater than the overdrive voltage |Vdsat|, so the effective output range of the op amp is VDD-|Vdsatp|-Vdsatn. Vdsat usually requires at least tens or hundreds of mV, so when a conventional amplifier is used as a buffer amplifier, it is usually impossible to achieve a completely rail-to-rail output range.

[0006] A common method of making an amplifier have a full rail-to-rail output range is as follows Figure 4 As shown, two charge pumps are used to generate a voltage higher than VDD, VDD+VCP, and a voltage lower than VSS, VSS-VCN, respectively, and these two voltages are used as the power supply ground of the amplifier to supply power. Then when VCP>|Vdsatp|, VCN>Vdsatn, the effective output range of the amplifier can reach rail-to-rail, that is, VSS to VDD.

[0007] However, this method will not only significantly increase the complexity, area, and power consumption of the circuit, but the high-frequency ripple generated when the charge pump is working will also deteriorate the output signal quality of the amplifier. Summary of the invention

[0008] According to one aspect of the present disclosure, a buffer amplifier is provided, the buffer amplifier is used to buffer an input voltage, the buffer amplifier comprises: an operational amplifier and a voltage regulating module, wherein:

[0009] The positive input terminal of the operational amplifier is used to receive the input voltage, and the negative input terminal of the operational amplifier is connected to the voltage output terminal of the voltage regulating module.

[0010] The first voltage input terminal of the voltage regulating module is connected to the output terminal of the operational amplifier, and the second voltage input terminal of the voltage regulating module is used to receive a preset voltage. The voltage regulating module is configured to work with a target duration as a cycle, and the target duration includes a first time period, a second time period and a third time period that are sequentially connected, wherein:

[0011] During a first period starting from the start time of the cycle, the voltage at the voltage output terminal of the voltage regulating module is built up from an initial voltage to an intermediate voltage;

[0012] During the second period, the voltage at the voltage output terminal of the voltage regulating module is established to a target voltage, the difference between the target voltage and the input voltage is smaller than the difference between the intermediate voltage and the input voltage, and the voltage at the output terminal of the operational amplifier is established to a preset voltage independent of the input voltage.

[0013] In a possible implementation, the voltage regulating module includes a first switch, a second switch, a third switch and a first capacitor, wherein:

[0014] The first end of the first switch is connected to the first end of the third switch as the first voltage input end of the voltage regulating module,

[0015] The second end of the first switch is connected to the first end of the first capacitor as a voltage output end of the voltage regulating module,

[0016] The second end of the third switch and the first end of the second switch are connected to the second end of the first capacitor.

[0017] The second end of the second switch serves as a second voltage input end of the voltage regulating module.

[0018] In a possible implementation manner, during the first time period, the first switch and the second switch are both turned on, and the third switch is turned off;

[0019] In a possible implementation manner, during the second time period and the third time period, the first switch and the second switch are both turned off, and the third switch is turned on.

[0020] In a possible implementation manner, the output end of the voltage regulating module is also connected to a load.

[0021] The voltage regulating module is further configured to output a voltage to the load during the first period and the second stage.

[0022] In a possible implementation manner, the preset voltage is greater than a ground voltage and less than a power supply voltage, and the buffer amplifier is implemented as a rail-to-rail buffer amplifier.

[0023] In a possible implementation, the load includes at least one of a capacitive load, a resistive load, and a composite load.

[0024] In a possible implementation manner, the operational amplifier is implemented using a rail-to-rail input amplifier.

[0025] According to one aspect of the present disclosure, a driver chip is provided, the driver chip comprising the buffer amplifier.

[0026] According to one aspect of the present disclosure, an analog-to-digital converter is provided, the analog-to-digital converter comprising the buffer amplifier

[0027] According to one aspect of the present disclosure, an electronic device is provided, comprising the driving chip or the analog-to-digital converter.

[0028] In the buffer amplifier of the disclosed embodiment, during the first period starting from the start time of the cycle, the voltage at the voltage output terminal of the voltage regulating module is established from the initial voltage to the intermediate voltage; during the second period, the voltage at the voltage output terminal of the voltage regulating module is established to the target voltage, the difference between the target voltage and the input voltage is smaller than the difference between the intermediate voltage and the input voltage, and the voltage at the output terminal of the operational amplifier is established to a preset voltage that is independent of the input voltage. The disclosed embodiment achieves the decoupling of the output voltage of the output terminal of the operational amplifier inside the buffer amplifier from the target output voltage of the entire buffer amplifier output terminal, achieves the true rail-to-rail input and output characteristics of the buffer amplifier, and has low circuit complexity, area and power consumption, and does not cause the output signal quality to deteriorate.

[0029] It should be understood that the above general description and the following detailed description are exemplary and explanatory only and do not limit the present disclosure. Other features and aspects of the present disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The drawings herein are incorporated into the specification and constitute a part of the specification. These drawings illustrate embodiments consistent with the present disclosure and are used to illustrate the technical solutions of the present disclosure together with the specification.

[0031] Figure 1 A schematic diagram of a signal chain with a buffer amplifier is shown.

[0032] Figure 2 The basic structural diagram of the buffer amplifier is shown.

[0033] Figure 3 A schematic diagram showing the output stage of a conventional amplifier.

[0034] Figure 4 A schematic diagram showing the use of a charge pump to achieve a full rail-to-rail output range for the amplifier.

[0035] Figure 5 A schematic diagram of a buffer amplifier according to an embodiment of the present disclosure is shown.

[0036] Figure 6 A schematic diagram of the circuit structure of a buffer amplifier according to an embodiment of the present disclosure is shown.

[0037] Figure 7 A schematic diagram of the working timing of the voltage regulating module according to an embodiment of the present disclosure is shown.

[0038] Figure 8 A schematic diagram of the working state of a buffer amplifier according to an embodiment of the present disclosure is shown.

[0039] Fig. 9 A schematic diagram of an output waveform of a buffer amplifier according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0040] Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

[0041] In the description of the present disclosure, it should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0042] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present disclosure, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0043] In the present disclosure, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0044] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0045] The term "and / or" herein is only a description of the association relationship of the associated objects, indicating that there may be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the term "at least one" herein represents any combination of at least two of any one or more of a plurality of. For example, including at least one of A, B, and C can represent including any one or more elements selected from the set consisting of A, B, and C.

[0046] In addition, in order to better illustrate the present disclosure, numerous specific details are given in the following specific embodiments. It should be understood by those skilled in the art that the present disclosure can also be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present disclosure.

[0047] See also Figure 5 , Figure 5 A schematic diagram of a buffer amplifier according to an embodiment of the present disclosure is shown.

[0048] like Figure 5 As shown, the buffer amplifier is used to buffer the input voltage Vin, and the buffer amplifier includes: an operational amplifier AMP and a voltage regulating module 10, wherein:

[0049] The positive input terminal (+) of the operational amplifier AMP is used to receive the input voltage Vin, and the negative input terminal (-) of the operational amplifier AMP is connected to the voltage output terminal Nod3 of the voltage regulating module 10.

[0050] The first voltage input terminal Nod1 of the voltage regulating module 10 is connected to the output terminal of the operational amplifier AMP, and the second voltage input terminal Nod2 of the voltage regulating module 10 is used to receive the preset voltage Vref1. The voltage regulating module 10 is configured to work with a target duration as a cycle, and the target duration includes a first time period, a second time period and a third time period that are sequentially connected, wherein:

[0051] During the first period starting from the start time of the cycle, the voltage of the voltage output terminal Nod3 of the voltage regulating module 10 is established from the initial voltage to the intermediate voltage;

[0052] During the second period, the voltage of the voltage output terminal Nod3 of the voltage regulating module 10 is established to the target voltage Vout, the difference between the target voltage Vout and the input voltage Vin is smaller than the difference between the intermediate voltage and the input voltage Vin, and the voltage of the output terminal of the operational amplifier is established to a preset voltage Vref1 that is independent of the input voltage Vin.

[0053] In the buffer amplifier of the disclosed embodiment, during the first period starting from the start time of the cycle, the voltage of the voltage output terminal Nod3 of the voltage regulating module 10 is established from the initial voltage to the intermediate voltage; during the second period, the voltage of the voltage output terminal Nod3 of the voltage regulating module 10 is established to the target voltage Vout, the difference between the target voltage Vout and the input voltage Vin is smaller than the difference between the intermediate voltage and the input voltage Vin, and the voltage of the output terminal of the operational amplifier is established to a preset voltage that is independent of the input voltage Vin; the sum of the durations of the first period, the second period, and the third period is the target duration. The disclosed embodiment realizes the decoupling of the output voltage of the output terminal of the operational amplifier inside the buffer amplifier from the target output voltage of the output terminal of the entire buffer amplifier, realizes the true rail-to-rail input and output characteristics of the buffer amplifier, and has low circuit complexity, area, and power consumption, and does not cause the output signal quality to deteriorate.

[0054] The buffer amplifier of the disclosed embodiment is suitable for application in the design of signal chain circuits with high integration, high precision and low power consumption. Of course, the disclosed embodiment does not limit the specific application environment of the buffer amplifier, and those skilled in the art can set it according to actual conditions and needs.

[0055] The embodiments of the present disclosure do not limit the specific implementation of the operational amplifier AMP and the voltage regulating module 10. Those skilled in the art may adopt appropriate technical solutions according to actual conditions and needs, as long as the adopted technical solutions can achieve the functions claimed in the embodiments of the present disclosure.

[0056] The embodiments of the present disclosure do not limit the specific sizes of the initial voltage and the preset voltage Vref1, and those skilled in the art can set them according to actual conditions and needs. For example, the initial voltage is, for example, 0, and the preset voltage Vref1 is, for example, VDD / 2, wherein VDD is the power supply voltage, and the difference between the target voltage Vout and the input voltage Vin can be within a preset range, which can be a smaller range, that is, the voltage at the output end of the operational amplifier AMP has a smaller fluctuation. Ideally, the voltage at the output end of the operational amplifier AMP is equal to the preset voltage Vref1, for example, VDD / 2. In this way, the embodiments of the present disclosure achieve the decoupling of the output voltage at the output end of the operational amplifier AMP inside the buffer amplifier and the target output voltage at the output end of the entire buffer amplifier.

[0057] The disclosed embodiment does not limit the number of cycles of the period, nor does it limit the specific size of the target duration, and those skilled in the art can set it according to actual conditions and needs.

[0058] The embodiments of the present disclosure do not limit the type of load, and those skilled in the art may set the load according to actual conditions and needs. In one possible implementation, the load includes at least one of a capacitive load, a resistive load, a composite load, and the like.

[0059] The following is an exemplary introduction to possible implementations of the buffer amplifier.

[0060] See also Figure 6 , Figure 6 A schematic diagram of the circuit structure of a buffer amplifier according to an embodiment of the present disclosure is shown.

[0061] In a possible implementation, Figure 6 As shown, the voltage regulating module 10 may include a first switch S1, a second switch S2, a third switch S3 and a first capacitor C S ,in,

[0062] The first end of the first switch S1 is connected to the first end of the third switch S3 as the first voltage input end Nod1 of the voltage regulating module 10.

[0063] The second end of the first switch S1 is connected to the first capacitor C S The first end of the voltage regulator module 10 is connected to the voltage output end Nod3.

[0064] The second end of the third switch S3, the first end of the second switch S2 and the first capacitor C S The second end is connected to

[0065] The second end of the second switch S2 serves as the second voltage input end Nod2 of the voltage regulating module 10 .

[0066] The embodiments of the present disclosure do not limit the specific types of the first switch S1, the second switch S2, and the third switch S3. Those skilled in the art may select appropriate switching devices to implement the first switch S1, the second switch S2, and the third switch S3 according to actual conditions and needs. By way of example, the switch includes any one of a relay, a reed switch, a thyristor, a switching transistor, an electronic bidirectional switch, a photocoupler, a transistor, etc. The transistor may be a metal-oxide-semiconductor field-effect transistor (MOSFET) or an insulated gate bipolar transistor (IGBT), wherein the transistor may be implemented based on silicon carbide SiC or gallium nitride GaN to improve performance.

[0067] Of course, each switch may include a control terminal for controlling the conduction state of the first terminal and the second terminal. As an example, the embodiment of the present disclosure may also set a control module connected to the control terminal of each switch to output a corresponding switch control signal to control the conduction state of each switch. The embodiment of the present disclosure does not limit the specific implementation of the control module. Those skilled in the art may select a suitable implementation method according to actual conditions and needs. In one example, the control module may include a processing component. Exemplarily, the processing component includes but is not limited to a separate processor, or a discrete component, or a combination of a processor and a discrete component. The processor may include a controller having an execution instruction function in an electronic device. The processor may be implemented in any appropriate manner, for example, by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors or other electronic components. Inside the processor, the executable instructions may be executed by hardware circuits such as logic gates, switches, application-specific integrated circuits (ASICs), programmable logic controllers, and embedded microcontrollers.

[0068] Of course, the embodiment of the present disclosure can also configure the switch control signals of each switch and store them in the storage module, and configure the storage module to actively output the switch control signals to each switch. In one example, the storage module may include a computer-readable storage medium, and the computer-readable storage medium may be a tangible device that can hold and store instructions used by the instruction execution device. The computer-readable storage medium may be, for example, - but not limited to - an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the above. More specific examples of computer-readable storage media (a non-exhaustive list) include: portable computer disks, hard disks, random access memories (RAM), read-only memories (ROM), erasable programmable read-only memories (EPROM or flash memory), static random access memories (SRAM), programmable read-only memories (PROM), portable compact disk read-only memories (CD-ROM), digital versatile disks (DVD), memory sticks, floppy disks, mechanical encoding devices, such as punch cards or protruding structures in grooves on which instructions are stored, and any suitable combination of the above. The computer-readable storage medium used herein is not to be construed as a transient signal per se, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., light pulses through a fiber optic cable), or an electrical signal transmitted through wires.

[0069] In a possible implementation manner, during the first time period, the first switch S1 and the second switch S2 are both turned on, and the third switch S3 is turned off;

[0070] In a possible implementation manner, during the second time period and the third time period, the first switch S1 and the second switch S2 are both turned off, and the third switch S3 is turned on.

[0071] See also Figure 7 , Figure 7 A schematic diagram of the working timing of the voltage regulating module 10 according to an embodiment of the present disclosure is shown.

[0072] For example, Figure 7 As shown, assuming that the switch control signal is high (1), it represents that the corresponding switch is closed, and the switch control signal is low (0), it represents that the corresponding switch is open, Phase1 represents the first time period, Phase2 represents the second time period, Phase3 represents the third time period, T0 represents the starting time of the first time period (that is, the starting time of the cycle), T1 represents the starting time of the second time period (that is, the ending time of the first time period), T2 represents the ending time of the second time period (that is, the starting time of the third time period), T3 represents the ending time of the third time period (that is, the ending time of the cycle), and Phase1+Phase2+Phase3 is the target duration.

[0073] Please refer to Figure 8 and Fig. 9 , Figure 8 FIG. 4 shows a schematic diagram of the working state of the buffer amplifier according to an embodiment of the present disclosure, Fig. 9 A schematic diagram of an output waveform of a buffer amplifier according to an embodiment of the present disclosure is shown.

[0074] For example, Figure 7 As shown, the first switch S1 and the second switch S2 are controlled by the same switch control signal, and the switch control signals of the first switch S1, the second switch S2 and the third switch S3 are divided into two working phases, the first phase corresponds to the first period Phase1, and the second phase corresponds to the second period Phase2 and the third period Phase3. In Phase1, the first switch S1 and the second switch S2 are closed, and the third switch S3 is opened; in Phase2 and Phase3, the first switch S1 and the second switch S2 are opened, and the third switch S3 is closed.

[0075] For example, in Phase 1, the first switch S1 and the second switch S2 are closed, and the third switch S3 is open. Therefore, the first capacitor C S Connected between the output terminal of the operational amplifier AMP and a preset voltage Vref1 (eg, VDD / 2) (eg, Figure 8As shown), for the buffer amplifier, it is equivalent to adding a capacitive load. During this period, the operational amplifier AMP is connected to the first capacitor C S and load capacitance C L Charge and discharge (This example assumes that the load is a capacitive load, including a load capacitor C L ), to roughly establish the signal, such as Fig. 9 As shown, at the end of Phase 1, the output voltage is established to Vout', at which time the first capacitor C S The voltage stored on is VS=Vout'-VDD / 2.

[0076] For example, in Phase 2 and Phase 3, the first switch S1 and the second switch S2 are opened, and the third switch S3 is closed. Therefore, the first capacitor C S Connected between the output terminal of the operational amplifier AMP and the voltage output terminal of the voltage regulator module 10 (such as Figure 8 As shown), during this period the first capacitor C S Included in the buffer loop, the operational amplifier AMP and the first capacitor C S The buffer to the load capacitance C L Continue to fine-tune the establishment. At the end of Phase 2, the output voltage is established to Vout", which is the final output voltage (target voltage). At this time, due to the first capacitor C S The voltage VS stored on the capacitor is determined by Phase 1 and does not change in Phase 2. S The output voltage of the operational amplifier AMP is level-shifted compared to Vout'', and its value is Voamp=Vout''-VS=Vout''-Vout''+VDD / 2.

[0077] For example, Fig. 9As shown, ideally, it is hoped that the target value established at the output terminal is equal to the input voltage Vin. At the end of Phase1 and Phase2, the errors of the output voltages Vout' and Vout" compared to the input voltage Vin are Ve1 and Ve2 respectively, and the difference Ve2 between the target voltage Vout and the input voltage Vin is smaller than the difference Ve1 between the intermediate voltage and the input voltage Vin. When the gain of the operational amplifier AMP is high enough and the loop bandwidth is large enough, the errors Ve1 and Ve2 can be made small enough, that is, Vout' and Vout" are approximately equal, then at the end of Phase2, the output voltage Voamp of the operational amplifier AMP is Vout"-Vout'+VDD / 2≈VDD / 2. Therefore, when the buffer amplifier obtains the final output voltage (that is, the end of Phase2), the output voltage of the operational amplifier AMP is approximately equal to VDD / 2, and does not have to be equal to the input voltage Vin, that is, the buffer amplifier decouples the output voltage Voamp of the operational amplifier AMP at Phase2 from the input voltage Vin.

[0078] By utilizing this characteristic, compared with the traditional buffer amplifier, the buffer amplifier of the embodiment of the present disclosure decouples the output voltage Voamp of the operational amplifier AMP at Phase 2 from the input voltage Vin, and makes the output voltage Voamp of the operational amplifier AMP always near VDD / 2, thereby preventing the MOS tube of the output stage of the operational amplifier AMP from entering the linear region. For the case where the input voltage Vin is equal to VSS or VDD, in Phase 1, the error Ve1 is large due to the MOS tube of the output stage entering the linear region, but Ve1 will not exceed the overdrive voltage |Vdsat| of the MOS tube even in the worst case, for example, 100mV, then at the end of Phase 2, the output voltage Voamp of the operational amplifier AMP is within the range of VDD / 2±100mV, and when the power supply voltage and the operating point of the operational amplifier AMP are reasonably set, the MOS tube of the output stage of the operational amplifier AMP at the end of Phase 2 can also be guaranteed to work in the saturation region. Therefore, the buffer amplifier proposed in the embodiment of the present disclosure solves the problem that the output stage MOS tube is pressed into the linear region when the rail-to-rail voltage is input, so that the buffer amplifier has the ability of true rail-to-rail output.

[0079] In a possible implementation manner, the output end of the voltage regulating module 10 is also connected to a load, and the load may be various types of loads, which is not limited in the embodiment of the present disclosure.

[0080] In a possible implementation manner, the voltage regulating module 10 is further configured to output a target voltage Vout to the load during the first time period and the second time period.

[0081] For example, Figure 6 As shown, a capacitive load is used as an example for introduction. The load includes a load capacitor C L .

[0082] In a possible implementation, Figure 6 As shown, the load end may also include:

[0083] The output control switch S4 is arranged between the output end of the voltage regulating module 10 and the load. The output control switch S4 is configured to be turned on in the first period and the second period, and turned off in the third period. The third period is a period during which the load capacitor C L The process of discharging or flipping with the subsequent circuit.

[0084] like Figure 6 As shown, a load switch S5 may be further provided at the load end, and the switch control signal of the load switch S5 may be opposite to the switch control signal of the output control switch S4 ( Figure 7 ).

[0085] For example, in the first period Phase1 and the second period Phase2, when the switch control signal of the output control switch S4 is at a high level, the output control switch S4 is closed. At this time, the buffer amplifier and the load capacitor C L At this time, the load switch S5 is disconnected, which means that the buffer amplifier needs to drive the load capacitor CL and establish its top plate voltage to the required target voltage (ie, Vin).

[0086] In a possible implementation, the preset voltage Vref1 is greater than the ground voltage and less than the power supply voltage, and the buffer amplifier is implemented as a rail-to-rail buffer amplifier. The input and output range of the buffer amplifier in the embodiment of the present disclosure can reach the ground (or VSS) at the lowest and the power supply voltage (VDD) at the highest, and has a large swing.

[0087] In a possible implementation, the operational amplifier AMP is implemented using a rail-to-rail input amplifier. The rail-to-rail input amplifier has many common implementation forms in the industry. The buffer amplifier of the embodiment of the present disclosure is not limited to a specific implementation form of the rail-to-rail input amplifier, so the specific structure of the operational amplifier AMP is not repeated here.

[0088] The buffer amplifier of the disclosed embodiment uses the first capacitor C SThe level shifting characteristic decouples the output voltage of the operational amplifier AMP in the buffer amplifier from the input voltage Vin, and ensures that the output voltage of the operational amplifier AMP operates near the intermediate level, thus solving the problem that the output stage MOS tube of the traditional buffer amplifier is easily pressed into the linear region, thereby making the buffer amplifier have the characteristic of true rail-to-rail input and output.

[0089] Compared with some common methods of using charge pumps to realize true rail-to-rail output amplifiers, the embodiments of the present disclosure do not significantly increase circuit complexity, area, and power consumption, and do not cause the output signal quality to deteriorate. The buffer amplifier of the embodiments of the present disclosure is more suitable for application in high-integration, high-precision, and low-power signal chain circuit design.

[0090] According to one aspect of the present disclosure, a driver chip is provided, the driver chip comprising the buffer amplifier.

[0091] According to one aspect of the present disclosure, an electronic device is provided, and the electronic device includes the driving chip.

[0092] The embodiments of the present disclosure have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or improvements to the technology in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A buffer amplifier, characterized in that: The buffer amplifier is used to buffer the input voltage, and the buffer amplifier includes: an operational amplifier and a voltage regulation module, wherein: The positive input terminal of the operational amplifier is used to receive the input voltage, and the negative input terminal of the operational amplifier is connected to the voltage output terminal of the voltage regulating module. The first voltage input terminal of the voltage regulating module is connected to the output terminal of the operational amplifier, and the second voltage input terminal of the voltage regulating module is used to receive a preset voltage. The voltage regulating module is configured to work with a target duration as a cycle, and the target duration includes a first time period, a second time period and a third time period that are sequentially connected, wherein: During a first period starting from the start time of the cycle, the voltage at the voltage output terminal of the voltage regulating module is built up from an initial voltage to an intermediate voltage; During the second period, the voltage at the voltage output terminal of the voltage regulating module is established to a target voltage, the difference between the target voltage and the input voltage is smaller than the difference between the intermediate voltage and the input voltage, and the voltage at the output terminal of the operational amplifier is established to a preset voltage independent of the input voltage.

2. The buffer amplifier according to claim 1, wherein: The voltage regulating module includes a first switch, a second switch, a third switch and a first capacitor, wherein: The first end of the first switch is connected to the first end of the third switch as the first voltage input end of the voltage regulating module, The second end of the first switch is connected to the first end of the first capacitor as a voltage output end of the voltage regulating module, The second end of the third switch and the first end of the second switch are connected to the second end of the first capacitor. The second end of the second switch serves as a second voltage input end of the voltage regulating module.

3. The buffer amplifier according to claim 2, wherein: During the first period, the first switch and the second switch are both turned on, and the third switch is turned off; During the second period and the third period, the first switch and the second switch are both turned off, and the third switch is turned on.

4. The buffer amplifier according to any one of claims 1 to 3, characterized in that: The output end of the voltage regulating module is also connected to the load. The voltage regulation module is further configured to output the target voltage to the load during the first time period and the second time period.

5. The buffer amplifier according to claim 4, wherein: The preset voltage is greater than a ground voltage and less than a power supply voltage, and the buffer amplifier is implemented as a rail-to-rail buffer amplifier.

6. The buffer amplifier according to claim 4, wherein: The load includes at least one of a capacitive load, a resistive load, and a composite load.

7. The buffer amplifier according to claim 1, wherein: The operational amplifier is implemented using a rail-to-rail input amplifier.

8. A driver chip, characterized in that: The driving chip comprises the buffer amplifier according to any one of claims 1 to 7.

9. An analog-to-digital converter, characterized in that: The analog-to-digital converter comprises a buffer amplifier as claimed in any one of claims 1-7.

10. An electronic device, characterized in that: The electronic device comprises the driving chip according to claim 8 or the analog-to-digital converter according to claim 9.

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