Reconfigurable ferroelectric transistor memory and method of making the same

Abstract

The application provides a reconfigurable ferroelectric transistor memory, which comprises a storage end electrode, a storage end medium layer, a programming end electrode, a medium layer, a source end electrode, a drain end electrode, an ultrathin channel layer, a silicon dioxide layer and a silicon substrate; by applying a pulse signal to the storage end electrode, the threshold voltage of the channel is regulated, so that the storage state is changed, and the transistor has an information storage function; the channel carriers are controlled through a plurality of gates of the programming end and the storage end, and the bipolarity of the Schottky barrier is utilized to realize the dynamic switching of the N type and the P type of the FeFET on the same device, so that the FeFET memory has a reconfigurable characteristic. The application utilizes the nonvolatile storage characteristic of the storage end medium layer, regulates the stored charge in the ultrathin channel layer by a pulse signal, regulates the type and concentration of the conduction charge in the ultrathin channel layer by a direct current signal, so that a single transistor has an information storage function, and the application also has stable endurance characteristics, retention characteristics and synaptic characteristics, and has a reconfigurable advantage.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, in particular to a reconfigurable ferroelectric transistor memory and a preparation method thereof. BACKGROUND

[0002] The traditional Von Neumann architecture faces a bottleneck due to the physical separation of storage units and computing units, and a higher energy-efficient non-Von Neumann architecture has become a new circuit paradigm. The integrated circuit of the non-Von Neumann architecture urgently needs an embedded storage and computing integrated memory unit as a basic building unit. The current RFET has the potential to become a standardized module of future reconfigurable and multifunctional circuits in terms of CMOS logic devices. On the other hand, the ferroelectric field effect transistor (FeFET) as a new type of non-volatile memory is compatible with CMOS circuits in terms of read-write mechanism and driving voltage, and is compatible with advanced CMOS processes. However, due to the fact that the hole mobility in silicon is usually 2-3 times lower than the electron mobility, most researches are focused on N-type FeFET, and the contradiction between the urgent need for P-type FeFET and the less research on P-type FeFET needs to be solved, and the demand for complementary FeFET for CMOS in-memory computing circuits is increasingly urgent.

[0003] By combining FeFET with RFET, the reconfigurable ferroelectric transistor memory formed thereby has the characteristics of composite reconfigurable multifunction, can be used as a reconfigurable module of a multifunctional chip in a non-Von Neumann architecture, realizes the upgrade of the functional density and energy efficiency of a CMOS in-memory computing circuit, develops a high-functional-density and high-energy-efficiency "non-Von" storage and computing integrated architecture, and is expected to become a basic unit of an in-memory computing integrated circuit in the post-Moore era. SUMMARY

[0004] The purpose of the present application is to meet the demand for ferroelectric transistor (FeFET) memory for CMOS in-memory computing, and a reconfigurable ferroelectric transistor memory and a preparation method thereof are proposed. The channel carriers are controlled by multiple gates, and the bipolarity of the Schottky barrier is fully utilized to realize the dynamic switching of N-type and P-type FeFET on the same device, so that the FeFET memory has the reconfigurable characteristic.

[0005] In order to achieve the above purpose, the technical scheme adopted by the present application is:

[0006] A reconfigurable ferroelectric transistor memory, comprising a storage end electrode, a storage end dielectric layer, a programming end electrode, a programming end dielectric layer, a source end electrode, a drain end electrode, an ultrathin channel layer, a silicon dioxide layer and a silicon substrate.

[0007] The silicon substrate, the silicon dioxide layer and the ultra-thin channel layer are sequentially arranged, and the storage end medium layer, the programming end medium layer, the source end electrode and the drain end electrode are arranged on the side of the ultra-thin channel layer away from the silicon dioxide layer.

[0008] The storage end electrode is arranged on the side of the storage end medium layer away from the ultra-thin channel layer, and the programming end electrode is arranged on the side of the programming end medium layer away from the ultra-thin channel layer.

[0009] The storage end medium layer separates the source end electrode, the drain end electrode and the programming end electrode.

[0010] In one embodiment, the programming end electrode is located between the source end electrode and the drain end electrode, and the storage end electrode and the storage end medium layer are arranged on both sides of the programming end electrode.

[0011] In one embodiment, the reconfigurable ferroelectric transistor memory further comprises a passivation layer, and the passivation layer is arranged on the side of the ultra-thin channel layer away from the silicon dioxide layer, and the storage end medium layer and the programming end medium layer are arranged on the side of the passivation layer away from the ultra-thin channel layer.

[0012] In one embodiment, the material of the passivation layer is any one of Al2O3, SiO2, SiON, HfON, TiON and ZrON.

[0013] In one embodiment, the opening voltage of the reconfigurable ferroelectric transistor memory represents the charge storage state of the transistor.

[0014] The storage end electrode controls the threshold voltage of the ultra-thin channel layer and the switching of the device through charge storage, and the programming end electrode is responsible for regulating the type and concentration of the on-charges in the ultra-thin channel layer.

[0015] The polarization state of the storage end medium layer stores the information of the storage end electrode and continuously regulates the working state of the device after the pulse ends.

[0016] The work functions of the metals and semiconductors of the source end electrode and the drain end electrode are similar, which provides similar electron and hole tunneling barriers for the Schottky contact.

[0017] In one embodiment, the ultra-thin channel layer is a lightly doped or undoped semiconductor.

[0018] When the source end electrode is grounded and the drain end electrode is connected to a positive voltage, the working state of the device is adjusted to N-FeFET: a positive voltage is applied to the programming end electrode, the channel region presents a low resistance state, and under the joint action of the positive voltage on the storage end electrode, the device is turned on, thereby realizing the N-type working mode of the reconfigurable ferroelectric transistor memory.

[0019] When the source electrode is grounded and the drain electrode is connected to the reverse voltage, the device operating state is adjusted to P-FeFET: a reverse voltage is applied to the programming electrode, the channel region presents a low resistance state, and under the joint action of the reverse voltage on the storage electrode, the device is turned on, thereby realizing the P-type working mode of the reconfigurable ferroelectric transistor memory.

[0020] In one embodiment, when the N-FeFET is written, a positive pulse is applied to the storage electrode, the storage medium layer is polarized towards the inside of the vertical channel, the electrons in the ultra-thin channel layer respond to the polarization charges in the storage medium layer, the accumulation of electrons in the ultra-thin channel layer increases, the threshold voltage of the device opening decreases, and the device storage state is 1; when the erase operation is performed, a negative pulse is applied to the storage electrode, the polarization charges in the storage medium layer are flipped, part of the electrons in the ultra-thin channel layer are repelled, the threshold voltage of the device opening increases, and the device storage state is 0.

[0021] In one embodiment, when the N-FeFET is written, a positive pulse is applied to the storage electrode, the storage medium layer is polarized towards the inside of the vertical channel, the electrons in the ultra-thin channel layer respond to the polarization charges in the storage medium layer, the accumulation of electrons in the ultra-thin channel layer increases, the threshold voltage of the device opening decreases, and the device storage state is 1; when the erase operation is performed, a negative pulse is applied to the storage electrode, the polarization charges in the storage medium layer are flipped, part of the electrons in the ultra-thin channel layer are repelled, the threshold voltage of the device opening increases, and the device storage state is 0.

[0022] In one embodiment, the materials of the storage electrode, the programming electrode, the source electrode and the drain electrode are any one of tungsten, titanium, copper, aluminum, platinum, iridium, ruthenium, molybdenum, tungsten nitride, titanium nitride, tantalum nitride, iridium oxide, ruthenium oxide, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide and tantalum silicide; the ultra-thin channel layer is any one of Si, Ge, SiGe, GaN, GaAs and SiC; the material of the storage medium layer is any one of AlScN, HYO, HZO, HSO, HAO, BFO, PZT, BST, ZrO2, Al2O3 and ZnSnO3; and the material of the programming medium layer is any one of HfO2, SiO2, SiON, Si3N4, TiO2, HYO, HZO, HSO, HAO, BFO, PZT, BST, ZrO2, Al2O3 and ZnSnO3.

[0023] The application further provides a preparation method of the reconfigurable ferroelectric transistor memory, comprising the following steps:

[0024] Step 1, select a substrate composed of an ultrathin channel layer, a silicon dioxide layer and a silicon substrate in sequence, and etch the ultrathin channel layer into an active region;

[0025] Step 2, deposit a programming end medium layer on the side of the ultrathin channel layer away from the silicon dioxide layer, and use a sputtering process to deposit a metal material on the side of the programming end medium layer away from the ultrathin channel layer and etch to form a programming end electrode;

[0026] Step 3, use an etching process to remove the medium material of the source region and the drain region, use a sputtering process to deposit a thin layer of electrode material on both ends of the active region, and use a stripping process to form a source end electrode and a drain end electrode;

[0027] Step 4, deposit a ferroelectric material to generate a storage end medium layer, grow a layer of metal electrode material on the side of the storage end medium layer away from the ultrathin channel layer, and etch the layer of metal electrode material and the storage end medium layer to form a programming end electrode, thereby completing the preparation of the reconfigurable ferroelectric transistor memory.

[0028] In one embodiment, the storage end electrode fills the gap position between the programming end electrode and the source end electrode and the drain end electrode in a self-aligned manner on the basis of the programming end electrode, the source end electrode and the drain end electrode.

[0029] Compared with the prior art, the present application fully utilizes the non-volatile storage characteristics of the storage end medium layer, adjusts the storage state of the ultrathin channel layer by changing the pulse signal applied to the storage end electrode, thereby changing the threshold voltage, so that the transistor has information storage function; the channel carriers are controlled through the multiple gates of the programming end and the storage end, and the bipolarity of the Schottky barrier is utilized, so that the FeFET structure realizes the dynamic switching of N-type and P-type on the same device, and the FeFET memory has reconfigurable characteristics; secondly, the present application has stable endurance characteristics, retention characteristics and synaptic characteristics, and can be used to develop high-function density and high-energy efficiency "non-von" storage and computing integrated architecture, and is expected to become a basic unit of post-moore's law in-memory computing integrated circuit. BRIEF DESCRIPTION OF DRAWINGS

[0030] Figure 1 Fig. 1 is a structural schematic diagram of the reconfigurable ferroelectric transistor memory of the present application.

[0031] Figure 2 Fig. 2 is a structural schematic diagram of the reconfigurable ferroelectric transistor memory of the present application. Figure 1 Fig. 3 is a cross-sectional view of A-A' in Fig. 2.

[0032] Figure 3 Fig. 4 is a schematic diagram of the storage state of the reconfigurable ferroelectric transistor memory under different pulses and the corresponding energy band diagram, and the working state is N-FeFET and the storage state is 1.

[0033] Figure 4Fig. 1 is a schematic diagram of a storage state of a reconfigurable ferroelectric transistor memory under different pulses, and a corresponding energy band diagram, wherein a working state is N-FeFET, and a storage state is 0.

[0034] Figure 5 Fig. 2 is a schematic diagram of a storage state of a reconfigurable ferroelectric transistor memory under different pulses, and a corresponding energy band diagram, wherein a working state is P-FeFET, and a storage state is 1.

[0035] Figure 6 Fig. 3 is a schematic diagram of a storage state of a reconfigurable ferroelectric transistor memory under different pulses, and a corresponding energy band diagram, wherein a working state is P-FeFET, and a storage state is 0.

[0036] Figure 7 Fig. 4 is a schematic diagram of a preparation process of a reconfigurable ferroelectric transistor memory.

[0037] In the figure, 1 is a storage end electrode, 2 is a storage end medium layer, 3 is a programming end electrode, 4 is a programming end medium layer, 5 is a source end electrode, 6 is a drain end electrode, 7 is an ultrathin channel layer, 8 is a silicon dioxide layer, 9 is a silicon substrate, and 10 is a passivation layer. DETAILED DESCRIPTION

[0038] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by those skilled in the art based on the embodiments in the present application belong to the scope of protection of the present application.

[0039] As shown in Figure 1 and Figure 2 , a structure schematic diagram of a reconfigurable ferroelectric transistor memory is shown, which mainly comprises a storage end electrode 1, a storage end medium layer 2, a programming end electrode 3, a programming end medium layer 4, a source end electrode 5, a drain end electrode 6, an ultrathin channel layer 7, a silicon dioxide layer 8, and a silicon substrate 9.

[0040] In the present application, the silicon substrate 9, the silicon dioxide layer 8, and the ultrathin channel layer 7 are sequentially arranged. For the convenience of description, in the structure shown in Figure 1 and Figure 2 , it is considered that the three are sequentially arranged from bottom to top. The storage end medium layer 2, the programming end medium layer 4, the source end electrode 5, and the drain end electrode 6 are arranged on a side of the ultrathin channel layer 7 away from the silicon dioxide layer 8, that is, the upper surface thereof.

[0041] The storage electrode 1 is disposed on the side of the storage dielectric layer 2 away from the ultrathin channel layer 7, i.e., its upper surface. The programming electrode 3 is disposed on the side of the programming dielectric layer 4 away from the ultrathin channel layer 7, i.e., its upper surface. Furthermore, the storage dielectric layer 2 isolates the source electrode 5, the drain electrode 6, and the programming electrode 3. For example, the programming electrode 3 is located between the source electrode 5 and the drain electrode 6. In this case, the storage electrode 1 and the storage dielectric layer 2 are two separate locations, situated between the programming electrode 3 and the source electrode 5, and between the programming electrode 3 and the drain electrode 6, respectively.

[0042] In a further embodiment of the present invention, the reconfigurable ferroelectric transistor memory further includes a passivation layer 10, which is disposed on the side of the ultrathin channel layer 7 away from the silicon dioxide layer 8, i.e., the upper surface. The storage dielectric layer 2 and the programming dielectric layer 4 are disposed on the passivation layer 10, rather than on the ultrathin channel layer 7.

[0043] In this invention, the ultrathin channel layer 7 refers to a channel layer with a relatively thin thickness, typically around 10 nm.

[0044] In embodiments of the present invention, the storage electrode 1, programming electrode 3, source electrode 5, and drain electrode 6 are all made of metallic materials. Specifically, the materials for the storage electrode 1, programming electrode 3, source electrode 5, and drain electrode 6 can be any one of tungsten, titanium, copper, aluminum, platinum, iridium, ruthenium, molybdenum, tungsten nitride, titanium nitride, tantalum nitride, iridium oxide, ruthenium oxide, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, and tantalum silicide.

[0045] The ultrathin channel layer 7 can be made of intrinsic semiconductor, lightly doped P-type semiconductor or lightly doped N-type semiconductor. Specifically, the material of the ultrathin channel layer 7 can be any one of Si, Ge, SiGe, GaN, GaAs and SiC.

[0046] The material of the storage medium layer 2 can be any one of AlScN, HYO, HZO, HSO, HAO, BFO, PZT, BST, ZrO2, Al2O3, and ZnSnO3.

[0047] The material of the programming end dielectric layer 4 can be any one of HfO2, SiO2, SiON, Si3N4, TiO2, HYO, HZO, HSO, HAO, BFO, PZT, BST, ZrO2, Al2O3, and ZnSnO3.

[0048] The material of the passivation layer 10 can be any one of Al2O3, SiO2, SiON, HfON, TiON, and ZrON.

[0049] The threshold voltage of the reconfigurable ferroelectric transistor memory device opened by the application represents the charge storage state in the ultra-thin channel layer 7; the storage electrode 1 controls the threshold voltage of the ultra-thin channel layer 7 and the switching of the device by charge storage; the programming electrode 3 is responsible for regulating the type and concentration of the on-chip charge in the ultra-thin channel layer 7; the polarization state of the storage medium layer 2 stores the information of the storage electrode 1 and continuously regulates the charge concentration of the channel and the resistance state of the series resistor after the pulse ends, that is, continuously regulates the working state of the device. The source electrode 5 and the drain electrode 6 provide similar electron and hole tunneling barriers.

[0050] Figure 3 、 Figure 4 、 Figure 5 and Figure 6 The principle diagram of the reconfigurable ferroelectric transistor memory under the regulation of different pulses and direct current inputs is shown in the figure, taking the ultra-thin channel layer 7 as an example of lightly doped semiconductor: 1) when the drain electrode 6 is connected to the power supply voltage and the source electrode 5 is grounded, the main carriers in the ultra-thin channel layer 7 are electrons. When performing the "write" operation, a positive pulse is applied to the storage electrode 1, the storage medium layer 2 is polarized towards the inside of the vertical channel, electrons are attracted and gathered, and the electrons are bound to the surface of the channel under the action of polarization, at this time the storage state of the reconfigurable ferroelectric transistor memory is "1"; when performing the "erase" operation, a negative pulse is applied to the storage electrode 1 when the programming electrode 3 is not connected to the voltage, the polarization charge in the storage medium layer 4 is flipped, and the storage state of the device is "0"; (2) when the source electrode 5 is connected to the power supply voltage and the drain electrode 6 is grounded, the main carriers in the ultra-thin channel layer 7 are holes. When performing the "write" operation, a negative pulse is applied to the storage electrode 1, the storage medium layer 2 is polarized towards the outside of the vertical channel, holes are attracted and gathered, and the holes are bound to the surface of the channel under the action of polarization, at this time the storage state of the reconfigurable ferroelectric transistor memory is "1"; when performing the "erase" operation, a positive pulse is applied to the storage electrode 1 when the programming electrode 3 is not connected to the voltage, the polarization charge in the storage medium layer 4 is flipped, and the storage state of the device is "0". When the ultra-thin channel layer 7 is intrinsic semiconductor, the principle is the same as above.

[0051] According to the above structure and working mechanism, the reconfigurable ferroelectric transistor memory of the application can have the advantages of large window voltage, stable endurance characteristics, retention characteristics and synaptic characteristics.

[0052] In summary, by applying a pulse signal to the storage end electrode 1, the threshold voltage of the ultra-thin channel layer 7 and the switching state of the device can be controlled, the type and concentration of the conduction charge in the ultra-thin channel layer 7 are regulated by a direct current signal, and the charge storage state of the single transistor is characterized by the turn-on voltage characteristics of the device, so that the single transistor has information storage function, and the single device can realize a larger storage window, and has a significant advantage of reconfigurability.

[0053] The present application utilizes the non-volatile storage characteristics of the storage end medium layer, and by applying a pulse signal to the storage end electrode, the threshold voltage of the ultra-thin channel layer and the switching state of the device can be controlled, the type and concentration of the conduction charge in the ultra-thin channel layer are regulated by a direct current signal, and the charge storage state of the single transistor is characterized by the turn-on voltage characteristics of the device, so that the single transistor has information storage function; by programming the channel carriers of the multiple gates of the storage end and using the bipolarity of the Schottky barrier, the dynamic switching of the N-type and P-type of the FeFET structure on the same device is realized, so that the FeFET memory has reconfigurable characteristics. Specifically:

[0054] When the source electrode 5 is grounded and the drain electrode 6 is connected to a positive voltage, the device operating state is adjusted to N-FeFET: a positive voltage is applied to the programming end electrode 3, the channel region presents a low resistance state, and under the joint action of the positive voltage on the storage end electrode 1, the device is turned on, thereby realizing the N-type working mode of the reconfigurable ferroelectric transistor memory. When writing operation is performed on the N-FeFET, a positive pulse is applied to the storage end electrode 1, the storage end medium layer 2 is polarized towards the inside of the vertical channel, the electrons in the ultra-thin channel layer 7 respond to the polarization charge in the storage end medium layer 2, so that the accumulation of electrons in the ultra-thin channel layer 7 increases, the threshold voltage of the device for turning on decreases, and the device storage state is 1; when erasing operation is performed, a negative pulse is applied to the storage end electrode 1, so that the polarization charge in the storage end medium layer 2 is flipped, part of the electrons in the ultra-thin channel layer 7 are repelled, the threshold voltage of the device for turning on is increased, and the device storage state is 0.

[0055] When the source electrode 5 is grounded and the drain electrode 6 is connected to the reverse voltage, the working state of the device is adjusted to P-FeFET: a reverse voltage is applied to the programming end electrode 3, and the channel region presents a low resistance state; under the joint action of the reverse voltage on the storage end electrode 1, the device is turned on, thereby realizing the P-type working mode of the reconfigurable ferroelectric transistor memory. When the P-FeFET is written, a negative pulse is applied to the storage end electrode 1, the storage end medium layer 2 is polarized towards the inside of the vertical channel, the holes in the ultra-thin channel layer 7 respond to the polarization charge in the storage end medium layer 2, the accumulation of holes in the ultra-thin channel layer 7 increases, the threshold voltage of the device that turns on decreases, and the storage state of the device is 1; when the erase operation is performed, a positive pulse is applied to the storage end electrode 1, the polarization charge in the storage end medium layer 2 is flipped, part of the holes in the ultra-thin channel layer 7 are repelled, the threshold voltage of the device that turns on increases, and the storage state of the device is 0.

[0056] Secondly, the application has stable endurance characteristics, retention characteristics and synaptic characteristics, can be used for developing high-function density and high-energy efficiency "non-Fon" storage and computing integrated architecture, and is expected to become a basic unit of a post-moore era storage-in-memory computing integrated circuit.

[0057] Referring to Figure 7 The application also includes a preparation method of the reconfigurable ferroelectric transistor memory, comprising the following specific steps:

[0058] 1) selecting a substrate composed of an ultra-thin channel layer 7, a silicon dioxide layer 8 and a silicon substrate 9 in sequence, and etching the ultra-thin channel layer 7 into an active region;

[0059] 2) depositing a passivation layer 10 (if any) and a medium material as a programming end medium layer 4 on the ultra-thin channel layer 7 in sequence, depositing a metal material as a metal electrode on the upper surface of the programming end medium layer 4 by using a sputtering process, and etching the metal layer to form a programming end electrode 3;

[0060] 3) removing the medium layer of the source region and the drain region by using an etching process, depositing a thin layer of electrode material on both ends of the active region by using a sputtering process, and forming a source electrode 5 and a drain electrode 6 by using a stripping process;

[0061] 4) depositing a ferroelectric material to generate a storage end medium layer 2, growing a layer of metal electrode material above the storage end medium layer 2, etching the layer and the storage end medium layer 2 to form a storage end electrode 1, and completing the preparation of the reconfigurable ferroelectric transistor memory. Specifically, in this step, the storage end electrode 1 is formed in a self-aligned manner in the gap position between the programming end electrode 3, the source electrode 5 and the drain electrode 6.

[0062] The following gives specific embodiments of preparation methods of three reconfigurable ferroelectric transistor memories based on different materials.

[0063] Embodiment 1:

[0064] The storage end medium layer 2 is made of HZO, the ultra-thin channel layer is made of P-type lightly doped Si, and the materials of the storage end electrode 1, the programming end electrode 3, the source end electrode 5 and the drain end electrode 6 are metal tungsten, and the specific preparation method is as follows:

[0065] Step one: select a substrate composed of an ultra-thin channel layer 7, a silicon dioxide layer 8 and a silicon substrate 9 in sequence, and etch an active region on the P-type lightly doped Si ultra-thin channel layer 7.

[0066] Step two: use atomic layer deposition technology to deposit a passivation layer above the ultra-thin channel layer 7, and immediately deposit a medium material to form a programming end medium layer 4, and sputter and grow a metal electrode above the programming end medium layer 4, and etch the metal layer to form a programming end electrode 3;

[0067] In this step, a reaction sputtering process is used. First, a molecular pump or a cold pump is used to pump the reaction chamber to a vacuum pressure of 0.02 Torr, and then under the conditions of a power of 350 W and an Ar pressure of 5 mTorr, metal W is selected as the target material to uniformly sputter the upper surface of the programming end medium layer 4, depositing a layer of metal W on the surface, as shown in FIG. 4, to form the programming end electrode 3. Figure 3

[0068] Step three: use etching process to remove the medium layer of the source and drain regions, use sputtering process to deposit a thin layer of metal on both ends of the active region, and form the source end electrode 5 and the drain end electrode 6 by peeling off process;

[0069] In this step, a reaction sputtering process is used. First, a molecular pump or a cold pump is used to pump the reaction chamber to a vacuum pressure of 0.02 Torr, and then under the conditions of a power of 350 W and an Ar pressure of 5 mTorr, metal W is selected as the target material to uniformly sputter the upper surface of the programming end medium layer 4, depositing a layer of metal W on the surface, thereby forming the source end electrode 5 and the drain end electrode 6.

[0070] Step four: use atomic layer deposition process, and use self-alignment process to successively deposit ferroelectric material to generate a storage end medium layer 2 and metal electrode material, etch the layer and the storage end medium layer 2 to form a storage end electrode 1, and complete the preparation of the reconfigurable ferroelectric transistor memory;

[0071] ​In this step, atomic layer deposition process is used, and tetraethyl methyl hafnium (TEMAHf) and tetraethyl methyl zirconium (TEMAZR) are used as hafnium precursor source and zirconium precursor source respectively, and ion water is used as precursor oxygen source, and the reaction temperature is 573K; then, by adjusting the pulse ratio of hafnium precursor source and zirconium precursor source, HZO ferroelectric material thin film is deposited on the passivation layer to form the storage end medium layer 2.

[0072] In this step, the reaction sputtering process is used, the reaction chamber is first pumped by a molecular pump or a cold pump until the vacuum pressure reaches 0.02 Torr, then under the condition of a power of 350W and an Ar pressure of 5mTorr, metal W is selected as the target material to uniformly sputter the surface of the storage end medium layer 2, deposit a layer of metal W on the surface, form the storage end electrode 1, and complete the preparation of the reconfigurable ferroelectric transistor memory.

[0073] Example 2:

[0074] The HYO ferroelectric material is used to make the storage end medium layer 2, N-type lightly doped Ge is used as the ultra-thin channel 7, and titanium metal is used as the material of the storage end electrode 1, the programming end electrode 3, the source end electrode 5 and the drain end electrode 6. The specific manufacturing method is as follows:

[0075] Step one: select a substrate composed of an ultra-thin channel layer 7, a silicon dioxide layer 8 and a silicon substrate 9, and etch the active area on the N-type lightly doped semiconductor Ge ultra-thin channel layer 7.

[0076] Step two: use atomic layer deposition technology to deposit a passivation layer on the ultra-thin channel layer 7, and immediately deposit a dielectric material to form a programming end medium layer 4, and sputter and grow a metal electrode on the programming end medium layer 4, and etch the metal layer to form a programming end electrode 3.

[0077] In this step, the reaction sputtering process is used, the reaction chamber is first pumped by a molecular pump or a cold pump until the vacuum pressure reaches 0.02 Torr, then under the condition of a power of 350W and an Ar pressure of 5mTorr, metal Ti is selected as the target material to uniformly sputter the surface of the programming end medium layer 4, deposit a layer of metal Ti on the surface, as shown in FIG. 4, to form the programming end electrode 3. Figure 3

[0078] Step three: use etching process to remove the medium layer of the source region and the drain region, use sputtering process to deposit a thin layer of metal on both ends of the active area, and form the source end electrode 5 and the drain end electrode 6 by peeling off.

[0079] ​In this step, the reaction sputtering process is used. First, the reaction cavity is vacuumed by molecular pump or cold pump until the vacuum pressure reaches 0.02 Torr. Then, under the conditions of 350 W power and 5 mTorr Ar pressure, metal Ti is selected as the target material to uniformly sputter the upper surface of the programming end medium layer 4, deposit a layer of metal Ti on the surface, thereby forming the source end electrode 5 and the drain end electrode 6.

[0080] Step four: using atomic layer deposition process, self-alignment process successively deposits ferroelectric material to generate the storage end medium layer 2 and metal electrode material, etches the layer and the storage end medium layer to form the storage end electrode 1, and completes the preparation of the reconfigurable ferroelectric transistor memory.

[0081] The pulse laser sputtering deposition process is used to alternately sputter and deposit HYO material thin film on the surface of the passivation layer 10 by double targets (HfO2 ceramic target 99.99%, Y2O3 ceramic target 99.99%), and then the HYO material is crystallized by annealing process to form the storage end medium layer 2.

[0082] In this step, the reaction sputtering process is used. First, the reaction cavity is vacuumed by molecular pump or cold pump until the vacuum pressure reaches 0.02 Torr. Then, under the conditions of 350 W power and 5 mTorr Ar pressure, metal Ti is selected as the target material to uniformly sputter the upper surface of the programming end medium layer 4, deposit a layer of metal Ti on the surface, thereby forming the source end electrode 5 and the drain end electrode 6.

[0083] Example 3:

[0084] The PZT material is used to make the storage end medium layer 2, the intrinsic Si substrate is used to make the semiconductor layer 2, and the metal copper is used as the material of the storage end electrode 1, the programming end electrode 3, the source end electrode 5 and the drain end electrode 6. The specific manufacturing method is as follows:

[0085] Step one: select a substrate composed of an ultrathin channel layer 7, a silicon dioxide layer 8 and a silicon substrate 9, and etch the active area on the intrinsic Si ultrathin channel layer 7.

[0086] Step two: use atomic layer deposition technology to deposit a passivation layer above the ultrathin channel layer 7, and immediately deposit a medium material to form a programming end medium layer 4, and sputter and grow a metal electrode above the programming end medium layer 4 to form a programming end electrode 3 by etching process.

[0087] In this step, the reaction sputtering process is used. First, the reaction cavity is vacuumed by molecular pump or cold pump until the vacuum pressure reaches 0.02 Torr. Then, under the conditions of 350 W power and 5 mTorr Ar pressure, metal Ti is selected as the target material to uniformly sputter the upper surface of the programming end medium layer 4, deposit a layer of metal Ti on the surface, thereby forming the source end electrode 5 and the drain end electrode 6.Figure 3 The programming end electrode 3 is formed.

[0088] Step three: the medium layer of the source region and the drain region is removed by using an etching process, a thin layer of metal is deposited at both ends of the active region by using a sputtering process, and the source end electrode 5 and the drain end electrode 6 are formed by using a stripping process;

[0089] In this step, a reaction sputtering process is used, a molecular pump or a cold pump is used to vacuum the reaction cavity until the vacuum pressure reaches 0.02 Torr, then under the condition that the power is 350 W and the Ar pressure is 5 mTorr, metal Cu is selected as the target material, the upper surface of the programming end medium layer 4 is uniformly sputtered, a layer of metal Cu is deposited on the surface, thereby forming the source end electrode 5 and the drain end electrode 6.

[0090] Step four: using an atomic layer deposition process, a self-aligned process is used to deposit a ferroelectric material to form a storage end medium layer 2 and a metal electrode material, and the storage end electrode 1 is formed by etching the layer and the storage end medium layer, thereby completing the preparation of the reconfigurable ferroelectric transistor memory.

[0091] In this step, an atomic layer deposition process is used, lead nitrate (Pb(NO3)2), titanium nitrate (Ti(NO3)4) and zirconium nitrate (Zr(NO3)4) are used as the precursor sources of lead, titanium and zirconium, ion water is used as the precursor oxygen source, and the reaction temperature is 573 K; then by adjusting the pulse ratio of the precursor sources of lead, titanium and zirconium, a PZT ferroelectric material thin film is deposited on the passivation layer to form the storage end medium layer 2.

[0092] In this step, a reaction sputtering process is used, a molecular pump or a cold pump is used to vacuum the reaction cavity until the vacuum pressure reaches 0.02 Torr, then under the condition that the power is 350 W and the Ar pressure is 5 mTorr, metal Cu is selected as the target material, the upper surface of the storage end medium layer 2 is uniformly sputtered, a layer of metal Cu is deposited on the surface, thereby forming the storage end electrode 1 and completing the preparation of the reconfigurable ferroelectric transistor memory.

[0093] The present application is not limited to the above-mentioned best embodiment, and anyone can derive other various forms of products under the inspiration of the present application, but regardless of any changes in shape or structure, any technical solution with the same or similar technical solution as the present application falls within the protection scope of the present application.

Claims

1. A reconfigurable ferroelectric transistor memory, characterized in that, It includes a storage terminal electrode (1), a storage terminal dielectric layer (2), a programming terminal electrode (3), a programming terminal dielectric layer (4), a source terminal electrode (5), a drain terminal electrode (6), an ultrathin channel layer (7), a silicon dioxide layer (8), and a silicon substrate (9). The silicon substrate (9), silicon dioxide layer (8) and ultrathin channel layer (7) are arranged in sequence, and the storage end dielectric layer (2), programming end dielectric layer (4), source end electrode (5) and drain end electrode (6) are arranged on the side of the ultrathin channel layer (7) away from the silicon dioxide layer (8); The storage electrode (1) is disposed on the side of the storage dielectric layer (2) away from the ultrathin channel layer (7), and the programming electrode (3) is disposed on the side of the programming dielectric layer (4) away from the ultrathin channel layer (7). The storage end dielectric layer (2) isolates the source end electrode (5), the drain end electrode (6) and the programming end electrode (3); By applying a pulse signal to the storage terminal electrode (1), the threshold voltage of the ultrathin channel layer (7) is adjusted, thereby changing the storage state and enabling the transistor to have information storage function; The turn-on voltage of the reconfigurable ferroelectric transistor memory represents the charge storage state of the transistor. The storage electrode (1) controls the threshold voltage of the ultrathin channel layer (7) and the switching of the device through charge storage, while the programming electrode (3) is responsible for regulating the type and concentration of the conductive charge in the ultrathin channel layer (7). The polarization state of the storage end dielectric layer (2) stores the information of the storage end electrode (1) and continuously regulates the working state of the device after the pulse ends; The work functions of the source electrode (5) and the drain electrode (6) are similar to those of the semiconductor, providing similar electron and hole tunneling barriers for the Schottky contact.

2. The reconfigurable ferroelectric transistor memory according to claim 1, characterized in that, The programming electrode (3) is located between the source electrode (5) and the drain electrode (6). The storage electrode (1) and the storage dielectric layer (2) are located in two places, one between the programming electrode (3) and the source electrode (5), and the other between the programming electrode (3) and the drain electrode (6).

3. The reconfigurable ferroelectric transistor memory according to claim 1, characterized in that, The reconfigurable ferroelectric transistor memory further includes: a passivation layer (10); the passivation layer (10) is disposed on the side of the ultrathin channel layer (7) away from the silicon dioxide layer (8), and the storage end dielectric layer (2) and the programming end dielectric layer (4) are disposed on the side of the passivation layer (10) away from the ultrathin channel layer (7).

4. The reconfigurable ferroelectric transistor memory according to claim 3, characterized in that, The passivation layer (10) is made of any one of Al2O3, SiO2, SiON, HfON, TiON, and ZrON.

5. The reconfigurable ferroelectric transistor memory according to claim 1, characterized in that, The ultrathin channel layer (7) is made of lightly doped or undoped semiconductor; When the source electrode (5) is grounded and the drain electrode (6) is connected to a positive voltage, the device operating state is adjusted to N-FeFET: when a positive voltage is applied to the programming electrode (3), the channel region presents a low resistance state. Under the combined action of the positive voltage on the storage electrode (1), the device is turned on, thereby realizing the N-type operating mode of the reconfigurable ferroelectric transistor memory. When the source electrode (5) is grounded and the drain electrode (6) is connected to the reverse voltage, the device operating state is adjusted to P-FeFET: when the reverse voltage is applied to the programming electrode (3), the channel region presents a low resistance state. Under the combined action of the reverse voltage on the storage electrode (1), the device is turned on, thereby realizing the P-type operating mode of the reconfigurable ferroelectric transistor memory.

6. The reconfigurable ferroelectric transistor memory according to claim 5, characterized in that, When performing a write operation on the N-FeFET, a positive pulse is applied to the storage electrode (1), and the storage dielectric layer (2) is polarized in the direction perpendicular to the inside of the channel. The electrons in the ultrathin channel layer (7) respond to the polarization charge inside the storage dielectric layer (2), which increases the accumulation of electrons in the ultrathin channel layer (7) and decreases the threshold voltage for device activation. The device storage state is 1. When performing an erase operation, a negative pulse is applied to the storage electrode (1), which causes the polarization charge in the storage dielectric layer (2) to flip. Some electrons in the ultrathin channel layer (7) are repelled, which increases the threshold voltage for device activation. The device storage state is 0. When performing a write operation on the P-FeFET, a negative pulse is applied to the storage electrode (1), and the storage dielectric layer (2) is polarized in the direction perpendicular to the inside of the channel. The holes in the ultrathin channel layer (7) respond to the polarization charge inside the storage dielectric layer (2), which increases the accumulation of holes in the ultrathin channel layer (7) and reduces the threshold voltage for device activation. The device storage state is 1. When performing an erase operation, a positive pulse is applied to the storage electrode (1), which causes the polarization charge in the storage dielectric layer (2) to flip. Some holes in the ultrathin channel layer (7) are repelled, which increases the threshold voltage for device activation. The device storage state is 0.

7. The reconfigurable ferroelectric transistor memory according to any one of claims 1 to 6, characterized in that, The materials of the storage terminal electrode (1), programming terminal electrode (3), source terminal electrode (5), and drain terminal electrode (6) are any one of tungsten, titanium, copper, aluminum, platinum, iridium, ruthenium, molybdenum, tungsten nitride, titanium nitride, tantalum nitride, iridium oxide, ruthenium oxide, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, and tantalum silicide; the materials of the ultrathin channel layer (7) are Si, Ge, SiGe, GaN, GaAs, and SiC. The material of the storage end medium layer (2) is any one of AlScN, HYO, HZO, HSO, HAO, BFO, PZT, BST, ZrO2, Al2O3, ZnSnO3; the material of the programming end medium layer (4) is any one of HfO2, SiO2, SiON, Si3N4, TiO2, HYO, HZO, HSO, HAO, BFO, PZT, BST, ZrO2, Al2O3, ZnSnO3.

8. The method for fabricating the reconfigurable ferroelectric transistor memory according to any one of claims 1 to 6, characterized in that, Includes the following steps: Step 1: Select a substrate consisting of an ultrathin channel layer (7), a silicon dioxide layer (8), and a silicon substrate (9) in sequence, and etch an active region on the ultrathin channel layer (7); Step 2: Deposit a programming dielectric layer (4) on the side of the ultrathin channel layer (7) away from the silicon dioxide layer (8), and use sputtering process to deposit metal material on the side of the programming dielectric layer (4) away from the ultrathin channel layer (7) and etch to form a programming electrode (3). Step 3: Use etching process to remove dielectric material from source and drain regions, use sputtering process to deposit thin electrode material at both ends of active region, and use lift-off process to form source electrode (5) and drain electrode (6). Step 4: Deposit ferroelectric material to form storage end dielectric layer (2), grow a metal electrode material on the side of storage end dielectric layer (2) away from ultrathin channel layer (7), etch the metal electrode material and storage end dielectric layer (2) to form storage end electrode (1), and complete the fabrication of reconfigurable ferroelectric transistor memory.

9. The preparation method according to claim 8, characterized in that, The storage electrode (1) is filled in the gap between the programming electrode (3) and the source electrode (5) and the drain electrode (6) in a self-aligned manner, based on the programming electrode (3), the source electrode (5) and the drain electrode (6).

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