Groove type Schottky barrier diode capable of being freely spliced

Abstract

The invention provides a groove type Schottky barrier diode capable of being freely spliced. The diode comprises a substrate, and the surface of the substrate comprises a groove type Schottky barrier diode formed by a plurality of rectangular unit blocks which can be spliced. Each unit block comprises a plurality of groove type cells and a closed terminal groove surrounding the cells; and the unit blocks are isolated from one another through the substrate. According to the technical scheme, through the structure of the plurality of unit blocks, the concentrated stress of the integral structure is dispersed to the isolation areas among the unit blocks, and the stress conduction efficiency is further weakened in combination with central symmetry arrangement and the vertical gate electrode direction, so that the warping degree of the wafer when the temperature is changed is reduced, and the reliability of the wafer is improved. And the electrical stability and the process yield are improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor devices, and more particularly to a trench-type Schottky barrier diode that can be freely spliced ​​together. Background Technology

[0002] Trenched semiconductor devices, such as TMBS devices, possess high voltage resistance. As high-performance semiconductor power devices, they are widely used in power management, new energy vehicles, and consumer electronics due to their low forward voltage drop, high switching speed, and good high-temperature stability. During the wafer manufacturing process of TMBS devices, the stress distribution inside the chip is one of the key factors affecting device performance and manufacturing yield. Among these, the trench structure, as the core functional structure of TMBS devices, is particularly sensitive to wafer warpage.

[0003] In existing technologies, the effective patterned area of ​​TMBS devices is typically designed as a single, continuous structure. The trench structure of TMBS devices requires processes such as deep trench etching, gate oxide growth, and polysilicon filling. However, the oxide layer (e.g., SiO2) on the trench sidewalls and the filling polysilicon have significantly different coefficients of thermal expansion compared to the silicon substrate. The coefficient of thermal expansion of SiO2 is 0.5 × 10⁻⁶. -6 At ℃, the coefficient of thermal expansion of silicon is 2.5 × 10⁻⁶. -6 At ℃, the coefficient of thermal expansion of polycrystalline silicon is 3.0 × 10⁻⁶. -6 / ℃. Therefore, in the photolithography, etching, ion implantation, and annealing processes of wafer manufacturing, temperature changes can cause significant compressive stress between the oxide layer and the substrate. At the same time, monolithic chip structures are prone to significant wafer warping due to the accumulation of internal stress within the structure itself. This warping is not only a global geometric deformation but may also form a complex saddle-shaped deformation.

[0004] Crucially, the size and stability of the trench structure directly impact the electrical properties of TMBS. Wafer warpage leads to non-uniform deformation of the trench structure: on one hand, stress concentration caused by warpage compresses or stretches the trench sidewalls, altering the actual width and depth of the trench and disrupting the electrical environment; on the other hand, stress is transmitted through the substrate to the doped regions surrounding the trench, causing changes in carrier mobility and severely affecting the device's switching characteristics and linear output performance. Furthermore, wafer warpage prevents different regions of the wafer from maintaining uniformity in subsequent processes such as thin film deposition and photolithography alignment. For example, during thin film deposition, the distance between different regions of the warped wafer and the deposition source is inconsistent, resulting in uneven filling layer thickness within the trench; during photolithography alignment, localized areas of the warped wafer cannot precisely align with the photomask, causing pattern transfer deviations and further exacerbating dimensional deviations in the trench structure. These problems ultimately lead to poor electrical performance consistency in TMBS devices, significantly reduced chip yield, increased manufacturing costs, and difficulty in meeting the demands of large-scale industrial production.

[0005] Therefore, designing a trench-type Schottky barrier diode that can effectively disperse chip stress, improve wafer warpage, and especially avoid electrical performance abnormalities caused by trench structure deformation, thereby improving manufacturing process consistency and yield, has become a technical challenge that urgently needs to be solved in this field. Summary of the Invention

[0006] The technical problem to be solved by the present invention is to provide a trench-type Schottky barrier diode that can be freely spliced ​​together. By optimizing the active region structure design of the device, stress dispersion and wafer warping can be achieved, while ensuring the integrity of the trench structure and the stability of electrical properties, thereby improving the device manufacturing yield and electrical performance consistency.

[0007] To address the aforementioned problems, this invention provides a freely combinable trench-type Schottky barrier diode, comprising a substrate, the surface of which includes a trench-type Schottky barrier diode composed of multiple combinable rectangular unit blocks; each unit block includes multiple trench-type cells and closed terminal trenches surrounding the cells; the unit blocks are isolated from each other by the substrate.

[0008] Optionally, the plurality of rectangular unit blocks are arranged symmetrically at the center.

[0009] Optionally, the unit blocks are assembled at the corners of the active area to form a missing corner outer contour.

[0010] Optionally, the tilt angle of the notched corner is 45°.

[0011] The above technical solution uses a multi-unit block structure to disperse the concentrated stress of the integral structure to the isolation area between each unit block. Combined with the central symmetry arrangement and the vertical gate electrode direction, it further weakens the stress transmission efficiency, thereby reducing the warpage of the wafer when the temperature changes, and improving electrical stability and process yield.

[0012] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit the invention. Techniques, methods, and apparatus known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and apparatus should be considered part of the specification. Attached Figure Description

[0013] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0014] Appendix Figure 1 The diagram shown is a structural schematic of a freely combinable trench Schottky barrier diode according to a specific embodiment of the present invention.

[0015] Appendix Figure 2A To be continued Figure 2C The attached image shows... Figure 1 A schematic diagram of the structure of a single unit block.

[0016] Appendix Figure 3 The diagram shown is a structural schematic of a freely combinable trench Schottky barrier diode according to a specific embodiment of the present invention.

[0017] Appendix Figure 4A -Appendix Figure 4E The diagram shown is a structural schematic of a freely combinable trench Schottky barrier diode according to some specific embodiments of the present invention. Detailed Implementation

[0018] The technical solutions in the embodiments of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] Appendix Figure 1The diagram shows a schematic representation of a freely combinable trench Schottky barrier diode according to a specific embodiment of the present invention. It includes a substrate and an active region on the substrate surface. The active region comprises multiple combinable rectangular unit blocks; each unit block includes multiple trench cells; the unit blocks are isolated from each other by the substrate.

[0020] The substrate 10 can be an N-type single-crystal silicon substrate with a thickness of 500-600 μm. The substrate 10 can also be made of any common semiconductor material such as silicon carbide or gallium nitride, and other locations can have different device structures. In this specific embodiment, the substrate 10 includes a trench-type Schottky barrier diode composed of four connectable rectangular unit blocks, namely unit blocks 111-114, separated by substrate isolation regions with a width of 5-30 μm. Preferably, the four unit blocks are arranged in a centrally symmetrical manner. In other specific embodiments, the number of unit blocks can be more or less, but at least two. The arrangement can preferably be symmetrical, or any other arbitrary arrangement. Since devices with three-dimensional structures are particularly sensitive to lateral thermal stress, bending of the chip under thermal stress leads to deformation, which in turn affects device performance. Therefore, the structure described in this specific embodiment is needed to reduce the impact of thermal stress on the chip.

[0021] In other specific embodiments, the number of unit blocks is not limited to four. It can be flexibly adjusted according to device current specifications, voltage withstand requirements, and chip area. It can be reduced to two blocks to suit low-current, low-power scenarios, or increased to six, eight, or even more blocks to meet the high-density integration requirements of high-power modules. However, the number of unit blocks must be at least two, which is the basis for achieving stress dispersion. Regarding the arrangement, in addition to the preferred centrally symmetrical arrangement, such as the four unit blocks in this specific embodiment distributed at 90° intervals around the center of the active region, axially symmetrical arrangements such as two unit blocks symmetrically distributed around the chip centerline, matrix arrangements, etc., can also be used. Even asymmetrical arrangements can be adopted according to the substrate shape and packaging requirements. For TMBS devices with three-dimensional structures such as trenches, the difference in thermal expansion coefficients between the trench sidewall oxide layer, polysilicon filling layer, and substrate will generate significant lateral thermal stress when the temperature changes. This lateral stress can easily cause the chip to bend and deform, which in turn compresses the trench structure, alters its size, and disrupts the carrier distribution in the doped region, ultimately leading to performance problems such as increased on-state voltage drop and decreased switching speed. A multi-unit block splicing structure can disperse lateral thermal stress through substrate isolation regions between the unit blocks; therefore, this structure is required to reduce the negative impact of thermal stress on chip performance.

[0022] Appendix Figure 2A The attached image shows... Figure 1A schematic diagram of a single unit block is shown, including a substrate 10 and trench structures within the substrate. The trenches include cell region trenches and terminal region trenches.

[0023] Substrate 10 typically uses N + Semiconductor substrates or silicon carbide substrates serve as the foundation for providing mechanical support and electrical connections for devices. N-type semiconductors can be selectively grown on the substrate. - Epitaxial layer. The epitaxial layer has periodically arranged trenches. The depth and width of the trenches can be adjusted according to actual application requirements. Multiple trench structures located within the substrate 10 include: a peripheral terminal trench structure 211 and multiple arrayed cell trench structures 212 located inside the terminal trench structure 211. A dielectric layer covering the inner walls of the trenches and a polysilicon layer located on the surface of the dielectric layer and filling the trenches are also present within the trench structure. The dielectric layer can be made of silicon oxide or any insulating material commonly used in semiconductor processes. The trench depth can be 0.3 μm to 10 μm, and the width can be 0.15 μm to 15 μm. The width and depth of the trenches within each cell structure, as well as the trenches between different cells, are configured independently and can be set to be the same or different. The distance between different trenches can be the same or different. The width and depth of the trenches within each cell structure and the trenches between different cells can be configured completely independently, allowing for both setting the same specifications according to functional requirements to simplify the process and adjusting to different parameters for different scenarios. In a specific implementation, the cell trenches within the unit, which bear the core function of current conduction, can be made deeper and wider according to the device's withstand voltage requirements. The trenches that isolate between units can have their dimensions adjusted to meet stress dispersion requirements, preventing stress transmission interference between adjacent units. Simultaneously, the distance between different trenches can also be flexibly set. Based on cell density and current distribution uniformity requirements, equidistant arrangement can be chosen to ensure process consistency, or a non-equidistant design can be used to adapt to local current concentration areas, further optimizing electrical performance. The terminal trench structure 211 surrounds the cell trench structure 212, serving as the terminal protection structure for the entire trench diode device. The terminal trench structure 211 is formed only at the device edge, significantly increasing the effective area of ​​the device.

[0024] In this specific embodiment, the terminal groove structure 211 consists of two annular structures. In other specific embodiments of the present invention, the terminal groove structure 211 may also be one or more annular structures arranged at intervals to improve the protective effect. (Reference) Figure 2B and Figure 2C These correspond to the cases of a single-layer terminal trench and a three-layer terminal trench, respectively.

[0025] In this specific embodiment, the unit blocks are separated by a 5-30 μm wide substrate isolation region, and the four unit blocks are arranged in a centrally symmetrical manner around the center of the active region. Each unit block contains multiple arrayed trench-type cells and closed terminal trenches surrounding the cells. Addressing the problems of stress accumulation and wafer warpage caused by differences in thermal expansion coefficients in existing monolithic TMBS device designs, which in turn lead to trench structure deformation, abnormal electrical properties, poor process consistency, and low die yield, this device utilizes unit block splicing, isolation, and specific arrangement designs. It employs the terminal trenches surrounding the unit blocks, which are relatively insensitive to deformation, to absorb thermal stress, reducing the deformation of the thermally stress-sensitive cell regions. This disperses stress and improves wafer warpage. During the process stage, reducing the warpage of the cell regions ensures the accuracy of photolithography alignment, avoiding reduced process yield due to decreased overlay accuracy caused by warpage. During operation, reduced thermal stress ensures the integrity of the trench structure, preventing changes in electrical properties due to trench deformation, and improving the consistency of device electrical performance and yield. The centrosymmetric arrangement ensures that the thermal stress generated by the four unit blocks during heating is symmetrically distributed, ultimately achieving global stress balance on the wafer. A 5-30μm substrate isolation region physically blocks stress transmission between adjacent unit blocks. This 5-30μm width range has been optimized for process adaptation, avoiding both insufficient isolation and stress penetration issues caused by excessive narrowness, and preventing wasted chip area due to excessive width.

[0026] Appendix Figure 3 The diagram shows a schematic representation of a freely combinable trench-type Schottky barrier diode according to a specific embodiment of the present invention. It includes a substrate and an active region on the substrate surface. The active region comprises multiple combinable rectangular unit blocks; each unit block includes multiple trench-type cells; the unit blocks are isolated from each other by the substrate. In this specific embodiment, there are five rectangular unit blocks, including a central rectangular unit block 41 and peripheral rectangular unit blocks 42-45 surrounding the rectangular unit block 41. Any one of the central unit block 41 and the peripheral unit blocks 42-45 can be independently selected from the surrounding rectangular unit blocks. Figure 2A To be continued Figure 2C Any one of them can be freely combined to form the above structure.

[0027] Similar to the above, the aforementioned structure can also disperse stress, improve wafer warpage, ensure the integrity and dimensional accuracy of the trench structure, and enhance the consistency and yield of device electrical performance. Furthermore, in this specific embodiment, the unit blocks are assembled at the corners of the active region to form a notched outer contour, preferably with a 45° angle, as shown in the attached figure. Figure 3As shown by the dotted line, this design allows for the reservation of blank areas without patterns at the corners. Since corners are stress concentration areas, reserving these blank areas can better improve wafer warpage and further prevent edge chipping during dicing. In the wafer dicing process, devices with traditional monolithic structures or right-angle corner designs tend to experience stress concentration in the densely patterned areas at the corners, especially when the dicing path passes through fine structures such as trench cells, and on hard and brittle semiconductor substrates such as Nd: + Monocrystalline silicon and silicon carbide are prone to cracking due to stress concentration, which can lead to edge chipping and damage to the integrity of the dielectric layer and polycrystalline silicon filling layer on the inner wall of the trench, resulting in device leakage or failure. The patternless cutout areas at the corners act as a buffer zone for cutting stress, dispersing the localized stress applied by the dicing tool and preventing stress from directly acting on the cells and terminal trench structure within the unit block. Simultaneously, the absence of photolithographic patterns and thin film stacking in the cutout areas reduces the uneven cutting resistance caused by differences in hardness at the interfaces of different materials (such as silicon, SiO2, and polycrystalline silicon), lowering the risk of substrate edge breakage, ensuring the structural integrity of the device edges after cutting, further improving the reliability of subsequent packaging and applications, and reducing yield losses due to edge chipping.

[0028] Appendix Figure 4A -Appendix Figure 4E The diagram shown is a structural schematic of a freely combinable trench Schottky barrier diode according to some specific embodiments of the present invention. As a simplified representation, each unit block is represented in block form; its specific structure can be found in the appendix. Figure 1 and attached Figure 2A -Appendix Figure 2C As shown, details are omitted here. In these specific embodiments, the element blocks are arranged in different ways to achieve the stress reduction function described above. Each of the above element blocks can be independently selected from the attached... Figure 2A To be continued Figure 2C Any one of the above-mentioned units can be freely combined to form the structure described above. For example, the unit block near the center can be selected as the structure shown in Figure 2C to enhance the stability of the core area, while the surrounding unit blocks can be selected as the structures shown in Figures 2A or 2B to balance performance and cost. Alternatively, the three structures can be flexibly combined according to the stress distribution and electrical requirements of different areas of the device to achieve customized design with on-demand splicing, further optimizing the overall performance and process compatibility of the device. The distance between different unit blocks can also be configured independently to be the same or different. It should be noted that more arrangement methods extended based on the above technical concept, including arbitrary numbers and symmetrical and asymmetrical arrangement combinations, should be considered within the scope of protection of this invention.

[0029] It should be noted that references to "an embodiment," "an embodiment," "an exemplary embodiment," "some embodiments," etc., in the specification indicate that the described embodiments may include specific features, structures, or characteristics, but each embodiment may not necessarily include that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. In addition, when a specific feature, structure, or characteristic is described in connection with an embodiment, whether explicitly described or not, implementing such a feature, structure, or characteristic in conjunction with other embodiments is within the knowledge of those skilled in the art.

[0030] It should be noted that the terms "comprising" and "having," and their variations, used in this invention document are intended to cover non-exclusive inclusion. The terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence, unless explicitly indicated by the context. It should be understood that such data used interchangeably where appropriate. Furthermore, embodiments and features within embodiments of this invention can be combined with each other unless otherwise specified. In addition, descriptions of well-known components and technologies have been omitted in the above description to avoid unnecessarily obscuring the concepts of this invention. In the various embodiments described above, each embodiment focuses on its differences from other embodiments; similar or identical parts between embodiments can be referred to interchangeably.

[0031] The above description is only a preferred embodiment of the present invention. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A freely combinable trench-type Schottky barrier diode, characterized in that, The device includes a substrate, the surface of which comprises a trench-type Schottky barrier diode composed of multiple connectable rectangular unit blocks; each unit block includes multiple trench-type cells and closed terminal trenches surrounding the cells; the unit blocks are isolated from each other by the substrate.

2. The diode according to claim 1, characterized in that, The multiple rectangular unit blocks are arranged symmetrically at the center.

3. The diode according to claim 1, characterized in that, The unit blocks are assembled at the corners of the active area to form a missing corner outer contour.

4. The diode according to claim 3, characterized in that, The angle of the missing corner is 45°.

Images