Method, device and medium for processing capacitors

Abstract

According to an example embodiment of the present disclosure, a method, device and medium for processing capacitance are provided. The method determines whether the positional relationship between a first processing unit and a second processing unit meets a predetermined approximate condition for an integrated circuit divided into a plurality of cells, the first processing unit corresponds to a first group of cells, the second processing unit corresponds to a second group of cells, and each processing unit is obtained by merging the corresponding cells; in response to the positional relationship meeting the predetermined approximate condition, based on the potential coefficient between the first processing unit and the second processing unit, the potential coefficient information for the plurality of cells is determined, which includes the potential coefficient between two cells in the plurality of cells; and based on the potential coefficient information and the potential of the plurality of cells, the first capacitance value of the integrated circuit is determined. Thus, the complexity and calculation time of the capacitance calculation are reduced, thereby improving the efficiency of capacitance processing in integrated circuit design.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to the field of integrated circuits, and more particularly, to methods, apparatus, and media for processing capacitance. Background Art

[0002] With the rapid development of integrated circuit manufacturing technology, the scale of circuits continues to increase and the feature size continues to shrink. The delay of interconnects in integrated circuits has exceeded the delay of devices and has become an important factor affecting chip performance. At present, the clock frequency of the central processing unit (CPU) has exceeded 5 GHz. At high frequencies, the circuit's duty cycle becomes shorter and the rise and fall times of signals become faster, resulting in more significant delays and distortions caused by parasitic effects.

[0003] On the one hand, the parasitic capacitance generated by the interconnection line will cause additional delays in the operation of the timing circuit. On the other hand, as the rise and fall time of the signal becomes shorter, the parasitic capacitance will cause the waveform of the signal to change, causing timing jitter, thus affecting the stability and reliability of the circuit. As integrated circuits become more complex, the increase in power consumption caused by parasitic capacitance has seriously affected the energy efficiency of the circuit.

[0004] Therefore, in the integrated circuit design process, accurate calculation of parasitic capacitance in interconnect circuits, guiding and verifying the design of integrated circuits has become a vital part of integrated circuit manufacturing. Summary of the invention

[0005] In a first aspect of the present disclosure, a method for processing capacitance is provided. The method includes: for an integrated circuit divided into a plurality of cells, determining whether the positional relationship between a first processing unit and a second processing unit satisfies a predetermined approximate condition, the first processing unit corresponds to a first group of cells in the plurality of cells, the second processing unit corresponds to a second group of cells in the plurality of cells, and each processing unit is obtained by merging the corresponding cells; in response to the positional relationship satisfying the predetermined approximate condition, based on the potential coefficient between the first processing unit and the second processing unit, determining potential coefficient information for the plurality of cells, the potential coefficient information including the potential coefficient between two cells in the plurality of cells; and determining a first capacitance value of the integrated circuit based on the potential coefficient information and the potential of the plurality of cells.

[0006] In a second aspect of the present disclosure, an electronic device is provided. The electronic device includes a processor and a memory coupled to the processor. The memory has instructions stored therein, and when the instructions are executed by the processor, the electronic device executes the method according to the first aspect of the present disclosure.

[0007] In a third aspect of the present disclosure, a computer-readable storage medium is provided. The computer-readable storage medium stores a computer program. When the computer program is executed by a processor, the method according to the first aspect of the present disclosure is implemented.

[0008] It will be understood from the following description that according to an embodiment of the present disclosure, the integrated circuit to be processed is gridded to divide it into a plurality of cells. According to the positions of these cells, cells that are close to each other can be merged into processing units. For processing units whose positional relationship meets a predetermined approximate condition, the potential coefficient between two processing units can be calculated without calculating the potential coefficient between each cell corresponding to these processing units. In this way, the complexity and calculation time of capacitance calculation are reduced, thereby improving the efficiency of capacitance processing in integrated circuit design. Other benefits will be described below in conjunction with the corresponding embodiments.

[0009] It should be understood that the contents described in the summary of the present invention are not intended to limit the key features or important features of the embodiments of the present disclosure, nor are they intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other features, advantages and aspects of the embodiments of the present disclosure will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. In the accompanying drawings, the same or similar reference numerals represent the same or similar elements, wherein:

[0011] Figure 1 A schematic diagram showing an example environment in which various embodiments of the present disclosure can be implemented;

[0012] Figure 2 A flow chart showing an example process of capacitance extraction according to some embodiments of the present disclosure;

[0013] Figure 3 A schematic diagram showing a hierarchical structure for a cell according to some embodiments of the present disclosure;

[0014] Figure 4 A flowchart illustrating an example process of mesh refinement according to some embodiments of the present disclosure;

[0015] Figure 5A A flow chart showing a method for processing capacitance according to some embodiments of the present disclosure is shown;

[0016] Figure 5B A flowchart showing a method for refining a mesh according to some embodiments of the present disclosure; and

[0017] Figure 6A block diagram of an electronic device is shown in which one or more embodiments of the present disclosure may be implemented. DETAILED DESCRIPTION

[0018] Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although certain embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be construed as being limited to the embodiments described herein, which are instead provided for a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are only for exemplary purposes and are not intended to limit the scope of protection of the present disclosure.

[0019] In the description of the embodiments of the present disclosure, the term "including" and similar terms should be understood as open inclusion, that is, "including but not limited to". The term "based on" should be understood as "based at least in part on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The terms "first", "second", etc. may refer to different or the same objects. Other explicit and implicit definitions may also be included below.

[0020] Figure 1 A schematic diagram of an example environment 100 is shown in which embodiments of the present disclosure can be implemented. The example environment 100 may generally include an electronic device 110.

[0021] The electronic device 110 obtains information related to the integrated circuit 120 to be processed, such as the design layout of the integrated circuit 120. The integrated circuit 120 can be used to implement any suitable type of chip or part of a chip. In addition to various devices, the integrated circuit 120 also includes an interconnection circuit for electrically coupling these devices together, also known as an interconnection line. The electronic device 110 can determine the capacitance generated by the interconnection line, also known as a parasitic capacitance, based on the information related to the integrated circuit 120 obtained.

[0022] In the example environment 100, the electronic device 110 can be any type of device with computing capabilities, including a terminal device or a server device. The terminal device can be any type of mobile terminal, fixed terminal or portable terminal, including a mobile phone, a desktop computer, a laptop computer, a notebook computer, a netbook computer, a tablet computer, a media computer, a multimedia tablet, a personal communication system (PCS) device, a personal navigation device, a personal digital assistant (PDA), an audio / video player, a digital camera / camcorder, a positioning device, a television receiver, a radio broadcast receiver, an e-book device, a gaming device, or any combination of the foregoing, including accessories and peripherals of these devices or any combination thereof. The server device can include, for example, a computing system / server, such as a mainframe, an edge computing node, a computing device in a cloud environment, and the like.

[0023] It should be understood that the structure and functionality of environment 100 are described for exemplary purposes only and does not imply any limitation on the scope of the present disclosure. Figure 1 The integrated circuits shown in and the diagrams therein are exemplary only and are not intended to limit the scope of the present disclosure.

[0024] As briefly mentioned above, calculating the capacitance in interconnects (also known as capacitance extraction) is an important part of integrated circuit manufacturing. At present, the capacitance extraction methods of interconnects mainly include analytical methods and numerical methods. The defect of the analytical method is that it cannot accurately calculate the capacitance parameters of complex non-Manhattan structure interconnects. The mainstream parasitic capacitance extraction methods mainly include integral method, differential method and random walk method.

[0025] The random walk method is based on the Monte Carlo method to deal with electrostatic field problems. Compared with the other two methods, it does not require a grid, so it occupies less memory and has higher computational efficiency. However, the random walk method is difficult to deal with non-Manhattan structures and multi-media structures. The integral method represented by the boundary element / moment method can deal with interconnects of arbitrary shapes and multi-media structures. This method only needs to calculate the surface charge of the interconnect structure, and the dimension of the linear equations to be solved is small. Therefore, the boundary element / moment method has become the mainstream numerical method for extracting the capacitance parameters of interconnects. However, the moment method / boundary element method is limited by the spatial globality of the Green's function, and the discrete matrix is ​​dense, resulting in high computational complexity.

[0026] As the industry's process node enters 28 nm, the size of the light source used by the lithography machine is comparable to the feature size of the mask, and there is a certain difference between the morphology of the silicon wafer surface and the morphology of the mask. The traditional two-dimensional (2D) approximate capacitance calculation method can no longer meet the accuracy requirements of advanced process nodes, and strict numerical algorithms are needed to accurately extract the capacitance parameters of the interconnect structure.

[0027] For example, some classic numerical algorithms, finite element or finite difference algorithms all explicitly solve coefficient matrices, which have high computational complexity. When dealing with some large interconnected structures, there are problems such as low computational efficiency, large memory usage, and difficulty in convergence.

[0028] At present, some capacitance extraction tools have high requirements for the mesh of the structure. The mesh quality is closely related to the calculation accuracy. Before the capacitance extraction, the structure needs to be strictly modeled and meshed, which further increases the difficulty of the capacitance extraction calculation.

[0029] As can be seen from the above, as the interconnects in integrated circuits become more and more complex, especially for large-scale and full-chip capacitance extraction, how to further reduce the computational complexity and improve computational efficiency is one of the problems that needs to be solved urgently.

[0030] To this end, an embodiment of the present disclosure provides a method for processing capacitance to solve or at least partially solve the above-mentioned problems and / or other potential problems in the conventional method. According to an embodiment of the present disclosure, the integrated circuit to be processed is divided into a plurality of cells, and based on the relative positions of the cells, a first processing unit corresponding to a first group of cells and a second processing unit corresponding to a second group of cells in the plurality of cells are determined, each processing unit being obtained by merging the corresponding cells. Determine whether the positional relationship between the first processing unit and the second processing unit satisfies a predetermined approximate condition. If the predetermined approximate condition is met, it means that the potential coefficient between any cell in the first group of cells and any cell in the second group of cells can be approximated by the potential coefficient between the first processing unit and the second processing unit. In this case, the potential coefficient information for these cells can be determined based on the potential coefficient between the first processing unit and the second processing unit, and the potential coefficient information includes the potential coefficient between any two cells in these cells. Then, based on the potential coefficient information and the potential of these cells, the capacitance of the integrated circuit is determined.

[0031] In an embodiment of the present disclosure, the integrated circuit to be processed is gridded to divide it into a plurality of cells. According to the positions of these cells, cells that are close to each other can be merged into processing units. For processing units whose positional relationship satisfies a predetermined approximate condition, the potential coefficient between two processing units can be calculated without calculating the potential coefficient between each cell corresponding to these processing units. In this way, the complexity and calculation time of capacitance calculation are reduced, thereby improving the efficiency of capacitance processing in integrated circuit design.

[0032] The exemplary embodiments of the present disclosure are described in detail below with continued reference to the accompanying drawings.

[0033] Figure 2 FIG. 2 is a flow chart showing an example process 200 for capacitance extraction according to some embodiments of the present disclosure. In some embodiments, process 200 may be performed by: Figure 1 The electronic device 110 shown is executed. It should be understood that the process 200 may also include additional blocks not shown and / or may omit one (or some) of the blocks shown, and the scope of the present disclosure is not limited in this respect.

[0034] In box 210, the electronic device 110 divides the integrated circuit 120 into a plurality of cells. That is, the integrated circuit 120 is gridded. The cells may have any suitable shape and size. The shapes and / or sizes of different cells may be different. In particular, in some embodiments, considering that the capacitance can be calculated based on the surface charge density, the surface of the integrated circuit 120 may be gridded. In this case, the cells divided may also be referred to as face elements, such as triangular face elements. In the following, some example embodiments will be described with reference to face elements, but it should be understood that this is merely exemplary, and the embodiments described with reference to face elements may also be applicable to other types of cells.

[0035] In block 220, the electronic device 110 determines a processing unit based on the position of the cell. Each processing unit corresponds to a group of cells and is obtained by merging the corresponding cells. In some cases, the processing unit can be used to replace the corresponding cell for approximate calculation, as described below. Note that a group of cells described herein may include one or more cells.

[0036] In order to more clearly understand the solution of replacing a cell with a larger processing unit in the embodiment of the present disclosure, the following first describes an example principle of capacitance calculation. Calculating capacitance requires solving the electrostatic potential integral equation and the capacitance matrix equation.

[0037] Capacitance extraction of interconnects in integrated circuits can be abstracted to the problem of dealing with a multi-conductor system in space, such as each cell can be considered as a conductor. The Maxwell capacitance matrix provides a relationship between the voltage on a set of conductors and the charge on the conductors. For example, for a single conductor (e.g., a single cell), the following relationship is valid:

[0038] (1)

[0039] in Q For charge ，C Capacitor ，V The electric potential 。 Extended to a multi-conductor system, the relationship between partial capacitance and charge is as follows:

[0040] (2)

[0041] in Q i For the i The charge of a cell, C ii and C ij Respectively represent i The capacitance of the cell itself and the cell i and jThe mutual capacitance between and Respectively represent i The potential of the cell and the j Then, the following linear equations can be constructed for the interconnect structure:

[0042] (3)

[0043] The diagonal matrix is ​​the mutual capacitance between conductors in a multi-conductor system. By solving the corresponding charge Q , the final capacitance matrix can be obtained.

[0044] The electrostatic potential integral equation is constructed to solve for the charge Q:

[0045] (4)

[0046] in represents the charge density of the current cell under consideration, represents the position vector of the cell, represents the position vector that affects the charge of this cell, Represents the dielectric constant.

[0047] For a complex multi-conductor system, the multi-conductor system structure is first divided into cells, and the electrostatic potential integral equation is applied to the discretized multi-conductor system to solve the charge density of each cell.

[0048] Expand the unknown charge density through basis functions:

[0049] (5)

[0050] in a n To solve for the coefficient, s n is the basis function ， is the charge density of the current cell 。 Apply formula (5) to formula (4):

[0051] (6)

[0052] Among them, the discrete integral equation can be expanded to obtain the following linear equation system:

[0053] (7)

[0054] in V N and a N For the NThe electric potential and coefficients of the unit cell are: Z is the potential coefficient between the cells. Finally, the capacitance solution in the multi-conductor system can be regressed to the potential coefficient calculation between the cells.

[0055] The linear equations in Eq. (7) are a dense matrix. For a multi-conductor system consisting of N cells (e.g., surface elements), we need to calculate The secondary potential coefficient. This process is extremely time-consuming. The inventors of the present disclosure realized that the number of solutions can be reduced based on the approximate relationship between charges.

[0056] Assume that there are three uniform charges A, B, and C in space. A and B are close to each other and far from C. Charges A and B can be regarded as a large charge D. The distance between charge D and charge C in space is R. When the distance between charge D and charge C satisfies the condition 1 / R<<1, the potential between charge D and charge C can be directly calculated to replace the potential between charge A, B and charge C, thereby reducing the potential coefficient Z The number of calculations is reduced to reduce the computational complexity.

[0057] It can be seen from the above description that if a group of cells are merged into a larger processing unit, when the distance between the processing unit and another processing unit or another cell is large enough, the processing unit can be used to replace the group of cells to calculate the potential coefficient.

[0058] Various suitable methods may be used to determine the processing unit or merge cells. Considering that a hierarchical structure (eg, a tree structure) is a structure that can clearly express a relationship, in some embodiments, a hierarchical structure such as a tree structure that represents the relative positions of multiple cells may be used. Figure 2 As shown, in block 222, a hierarchical structure may be constructed. That is, based on the positions of the cells in the integrated circuit, a hierarchical structure representing the relative positions of the cells is generated. The hierarchical structure may include a plurality of leaf nodes and a plurality of intermediate nodes located above the plurality of leaf nodes, each leaf node corresponding to one of the plurality of cells, and each intermediate node being allocated with cells corresponding to the leaf nodes below the intermediate node.

[0059] Figure 3A hierarchical structure 300 is shown as an example. In this example, the integrated circuit is divided into 6 cells, and the root node 310 in the hierarchical structure 300 represents all cells. The hierarchical structure 300 includes 6 leaf nodes 331, 341, 351, 352, 333 and 334, which correspond to the 6 cells respectively. In addition, the hierarchical structure 300 also includes intermediate nodes 321, 332, 342, 322. Each intermediate node is assigned or represents the cell corresponding to each leaf node under it. For example, the intermediate node 341 represents or is assigned the cell corresponding to the leaf nodes 351 and 352. For another example, the intermediate node 332 represents or is assigned the cell corresponding to the leaf nodes 341, 351 and 352.

[0060] This hierarchical structure may be constructed in any suitable manner. In some embodiments, the cells may be clustered hierarchically based on their locations in the integrated circuit. For example, all cells are first clustered into two clusters, one of which forms the intermediate node 321 and the other forms the intermediate node 322. Then, the two clusters are clustered separately, and so on until the clustering result is a cell.

[0061] In some embodiments, reference points may be used for stratification. For an intermediate node assigned with two or more cells, a reference point is determined based on the geometric properties of the two or more cells, and the reference point is located in the space where the two or more cells are distributed. The geometric properties of the cells may include, for example, the normal vector, area, centroid, and longest side of the cells.

[0062] Based on the relative position of two or more cells and the reference point, two or more cells are assigned to multiple nodes under the intermediate node. In some embodiments, the cell with a first position relationship with the reference point in the two or more cells can be assigned to the first node under the intermediate node, and the cell with a first position relationship with the reference point in the two or more cells can be assigned to the second node under the intermediate node. The second position relationship is different from the first position relationship. For example, the first position relationship is located on the right side of the reference point, and the second position relationship is located on the right side of the reference point.

[0063] After cells are allocated to each node, the types of the multiple nodes can be determined based on the number of cells allocated to the multiple nodes, and the types include leaf nodes or intermediate nodes. For example, a node that is only allocated with one cell is determined as a leaf node. A node that is allocated with multiple cells is determined as an intermediate node. The above process can be continued for the intermediate node until all cells are allocated.

[0064] Continue to refer to Figure 3The example of describes the example construction process. Based on computational geometry, the normal vector, area, centroid, and longest edge of each cell (for example, each triangular face) are determined for subsequent calculations. Figure 3 As shown, assume that there are six cells with uniformly distributed charges in space. First, traverse the spatial coordinates of all cell centroids, compare the size of each cell spatial coordinate x, y, z, and take out the maximum and minimum x, y, z values ​​of all cell vertex coordinates. Based on the maximum x, y, z value, a point in space can be determined, and based on the minimum x, y, z value, another point in space can be determined.

[0065] Through these two points in space, the largest edge is constructed and the middle point of the edge is taken as the reference point for dividing and constructing the binary tree structure. Then, the centroid coordinates of all cells are traversed and compared with the reference point, so that all cells can be initially grouped and left and right nodes, that is, middle nodes 321 and middle nodes 322, are constructed. Middle nodes 321 and middle nodes 322 are further grouped in a recursive manner until each node is an original cell. Thus, the construction of the hierarchical structure 300 is completed.

[0066] The above describes an example construction of a hierarchical structure by taking a binary tree as an example. It should be understood that other types of hierarchical structures are also applicable.

[0067] After the hierarchical structure is constructed, cells may be merged from bottom to top in block 225. Specifically, if the leaf nodes corresponding to a group of cells belong to the same intermediate node, the processing unit corresponding to the group of cells is determined based on the geometric properties of the group of cells (e.g., area, centroid, normal vector, vertex coordinates, etc.). Additionally, in some embodiments, the processing unit may correspond to the intermediate node in the hierarchical structure.

[0068] continue Figure 3 . Leaf node 351 and leaf node 352 belong to intermediate node 342. Assume that leaf node 351 and leaf node 352 correspond to cell A and cell B, respectively. The corresponding processing unit AB can be determined based on the geometric properties of cell A and cell B (e.g., area, centroid, normal vector, and vertex coordinates, etc.), for example, the vertex coordinates of processing unit AB are determined. Furthermore, processing unit AB can also be corresponded or associated with intermediate node 342.

[0069] For another example, assume that leaf node 342 corresponds to cell C. Leaf node 342, leaf node 351, and leaf node 352 belong to intermediate node 332. Based on the geometric properties of cells A, B, and C (e.g., area, centroid, normal vector, and vertex coordinates, etc.), the corresponding processing unit ABC can be determined, for example, the vertex coordinates of processing unit ABC can be determined. Further, processing unit ABC can also be corresponded or associated with intermediate node 332. By analogy, the processing units corresponding to all intermediate nodes can be determined from bottom to top.

[0070] In some embodiments, if the cells are bins, then the processing units may be referred to as panels. Figure 3 As shown, from the bottom of the binary tree, the initial face elements are merged two by two, the secondary parent node panel is constructed, and the area, center of mass, normal vector and vertex coordinates of the parent node panel are calculated, and the process is traversed level by level until they are merged into a largest panel.

[0071] Continue to refer Figure 2 After the construction of the processing unit is completed, for example, after the panel is completed, the link relationship between the cells can be constructed based on the predetermined approximate conditions. Figure 2 As shown, in block 230 , it is determined whether there are processing units to be compared. For example, the hierarchical structure 300 may be traversed from top to bottom starting from the middle nodes 321 and 322 at the highest level.

[0072] If there are two processing units to be compared, process 200 proceeds to block 235. At block 235, it is determined whether the positional relationship between the two processing units satisfies a predetermined proximity condition. The predetermined proximity condition may be set by a user. The predetermined proximity condition indicates whether the two processing units are far enough apart to be used as a whole as a charge for potential coefficient calculation.

[0073] In some embodiments, it may be determined whether the relative distance between the two processing units is greater than a threshold distance. If the relative distance is greater than the threshold distance, it may be determined that the predetermined proximity condition is satisfied.

[0074] Different processing units may have different sizes. For example, in the case of a two-dimensional cell, different processing units may have different areas; in the case of a three-dimensional cell, different processing units may have different volumes. To this end, in some embodiments, the normalized distances of the processing units may be compared. Specifically, the relative distance between the two processing units to be compared may be determined based on the centers (e.g., centroids) of the two processing units. However, the normalized distance between the two processing units may be determined based on the sizes (e.g., areas or volumes) and relative distances of the two processing units. If the normalized distance is less than a distance threshold (e.g., which may be set by a user), it may be determined that the positional relationship between the two processing units satisfies a predetermined approximation condition.

[0075] If it is determined in box 235 that the positional relationship between the two processing units does not satisfy the predetermined approximate condition, the process 200 returns to box 230 and continues to search for processing units. If it is determined in box 235 that the positional relationship between the two processing units satisfies the predetermined approximate condition, the process 200 proceeds to box 240. In box 240, the potential coefficient between the two processing units that meet the predetermined approximate condition can be determined. The calculation of the potential coefficient is known to those skilled in the art and can be performed in any suitable manner, and the embodiments of the present disclosure will not be repeated.

[0076] For example, the link relationship between facets can be constructed based on the hierarchical approximation condition set by the user. All nodes on the binary tree are traversed and compared with each other to determine whether the hierarchical approximation condition is met. If it is met, the parent node can be approximated to replace its child node. If not, the child node is continuously compared to see if it meets the approximation condition until the original cell node is traversed.

[0077] After completing the traversal of the processing units, the process 200 proceeds to block 245. In block 245, based on the potential coefficients between the processing units that satisfy the predetermined approximation condition, potential coefficient information for a plurality of cells is determined, the potential coefficient information including the potential coefficients between any two cells in the plurality of cells. For example, the matrix of the potential coefficient Z in equation (7) is calculated, also referred to as a potential coefficient array.

[0078] In some embodiments, the first group of cells corresponds to the first processing unit, and the second group of cells corresponds to the second processing unit. If the positional relationship between the first processing unit and the second processing unit satisfies a predetermined approximate condition, a reference potential coefficient between the first processing unit and the second processing unit can be calculated based on the geometric properties of the first processing unit and the geometric properties of the second processing unit. In the potential coefficient information, the potential coefficient between each cell in the first group of cells and each cell in the second group of cells is determined as the reference potential coefficient.

[0079] For example, it is assumed that the positional relationship between the processing units corresponding to cells 1, 2, and 3 and the processing units corresponding to cells 8 and 9 meets the predetermined approximate condition. The reference potential coefficient Zr between the two processing units can be calculated to replace the potential coefficient matrix and , , and , , and , and It can be seen that the original six potential coefficient calculations were reduced to one calculation.

[0080] Continuing with process 200, at block 250, the capacitance value of the integrated circuit may be calculated. For example, after determining the potential matrix in equation (7), the coefficients may be obtained according to equation (7): a N , (Note that for integrated circuits, the potential V is known). Then, the charge density can be obtained according to equation (5). For example, the charge density of each bin can be iteratively solved according to the generalized minimum residual method (GMRES). The charge Q in equation (1) can be obtained based on the charge density and area. Furthermore, the capacitance C can be calculated based on the charge Q and the potential V.

[0081] In some embodiments, subsequent processing may be performed to ensure the accuracy of the calculated capacitance value. Figure 2 As shown, at block 255, it is determined whether there is a cell refinement indication. In some embodiments, the cell refinement indication may come from a user. In some embodiments, the cell refinement indication may be that the capacitance value calculated at block 250 does not meet the accuracy requirement.

[0082] If there is no cell refinement indication, process 200 proceeds to block 265 . At block 265 , the capacitance is determined. That is, the capacitance value calculated at block 250 is determined as the capacitance of integrated circuit 120 .

[0083] If there is a cell refinement indication, the process 200 proceeds to block 260. In block 260, the division of the cell is refined, that is, mesh refinement is performed. For example, some cells are further refined into more cells with smaller areas. After the refinement is completed, the process 200 can return to block 220.

[0084] Reference below Figure 4 An example process 400 for mesh refinement is described. Process 400 may be viewed as an example implementation of block 260. However, it should be understood that reference Figure 4The described mesh refinement process 400 is not limited to the capacitance processing method described in the process 200. The process 400 may also be implemented separately from the blocks 210 to 250.

[0085] At block 410, two processing units to be considered are determined, which are processing units used to approximate the potential coefficient between cells when calculating the potential coefficient information. For example, the first processing unit and the second processing unit described above may be considered.

[0086] At block 420, it is determined whether the refinement degree of the two processing units meets a predetermined refinement condition. The refinement degree may be determined based on the size of the two processing units and the calculated potential coefficient. Exemplarily, the refinement degree may be represented by a refinement factor, which may be determined based on the size of the two processing units (e.g., the area of ​​the two panels) and the magnitude of the potential coefficient.

[0087] In some embodiments, refinement factors may be determined for the two processing units respectively. If a certain refinement factor is greater than a reference refinement factor, it is determined that the two processing units do not meet the predetermined refinement condition and need to be further refined. For example, based on the size of the first processing unit and the potential coefficient between the first processing unit and the second processing unit, a first refinement factor indicating the degree of refinement of the first processing unit is determined. Based on the size of the second processing unit and the potential coefficient between the first processing unit and the second processing unit, a second refinement factor indicating the degree of refinement of the second processing unit is determined. If at least one of the first refinement factor or the second refinement factor is greater than the reference refinement factor, it is determined that the degree of refinement of the first processing unit and the second processing unit does not meet the predetermined refinement condition. The reference refinement factor may be an initial refinement factor or a refinement factor determined by a previous round of refinement. The two processing units may share the same reference refinement factor, or may have respective reference refinement factors.

[0088] If it is determined that the predetermined refinement condition is not met, process 400 proceeds to block 430. At block 430, a processing unit to be refined is selected. In some embodiments, the two processing units can be selected at any time, or a processing unit with a large refinement factor can be selected.

[0089] In some embodiments, a processing unit with a larger size (e.g., a larger area) may be selected. Continuing with the example of a first processing unit and a second processing unit, the respective sizes of the first processing unit and the second processing unit may be determined. If the size of the first processing unit is larger than the size of the second processing unit, the first processing unit is selected.

[0090] In box 440, the cells corresponding to the selected processing unit are refined. After the refinement, it is determined whether a new processing unit is generated. In box 450, it is determined whether the newly generated processing unit meets the predetermined refinement condition. This step is similar to box 420 and is not described in detail. If the predetermined refinement condition is met, the refinement is stopped in box 460. That is, process 400 ends.

[0091] If the refinement condition is not met, process 400 returns to box 430 to select a processing unit to be refined from the newly generated processing units. The grid is thus refined in a recursive manner until no refinement is required. For example, at least a portion of a group of cells corresponding to the selected processing unit is refined to obtain an updated cell. Based on the geometric properties of the updated cell, at least two processing units corresponding to the updated cell are determined, similar to what is described in reference box 220, and thus will not be repeated. If the degree of refinement of the at least two processing units meets the predetermined refinement condition, the refinement of the cell is stopped. If the degree of refinement of the at least two processing units does not meet the predetermined refinement condition, the cell corresponding to one of the at least two processing units is refined until the predetermined refinement condition is met.

[0092] In some embodiments, the refinement factor may be updated as the mesh is refined. For example, after each refinement, if the refinement factor is greater than the previous refinement factor, the refinement factor of the refinement is determined as the reference refinement factor.

[0093] Return to process 200. As described above, in some embodiments, at block 255, it may be determined whether the capacitance value calculated by block 250 meets the accuracy requirement. The accuracy requirement may be determined by comparing the capacitance values ​​calculated before and after mesh refinement. For example, a first capacitance value is calculated before mesh refinement, and a second capacitance value is calculated after mesh refinement. The degree of change of the second capacitance value relative to the first capacitance value may be determined. For example, the rate of change of the second capacitance value relative to the first capacitance value. If the degree of change is less than a degree of change threshold, it may be considered that the accuracy requirement is met, and the second capacitance value may be determined as the capacitance of the integrated circuit.

[0094] Exemplarily, after the grid is refined, the next capacitance matrix calculation is performed. Then, the updated capacitance matrix can be compared with the previous capacitance matrix according to the following formula:

[0095] (8)

[0096] in Indicates the degree of change, MaxErro Indicates the change threshold.

[0097] If the result satisfies the above formula, the final capacitance matrix is ​​obtained.

[0098] The above describes the capacitance extraction scheme according to the embodiment of the present disclosure. When solving the capacitance matrix, the traditional moment method or boundary element method processes a dense coefficient matrix based on the discrete potential integral equation, and the computational complexity is O(N 2 ). It faces problems such as long calculation time and difficult matrix calculation convergence, and it is difficult to handle large integrated circuit interconnect structures.

[0099] The disclosed embodiment proposes a method for implicitly solving matrix equations with low computational complexity. In the moment method, a surface grid is applied to discretize the structure. The disclosed embodiment merges and groups cells based on the distance between cells and the size of the cells to construct a hierarchical structure, such as a binary tree data structure. When the cell distance is large, the parent node in the binary tree can be used to approximate the child node under the parent node, reducing the number of potential calculations between the child nodes, thereby saving a lot of computing time and memory usage.

[0100] On the other hand, in order to obtain accurate calculation results, the traditional finite element algorithm has high requirements on the quality and quantity of cells. As the number of cells increases, the calculation burden of the traditional algorithm is further increased, affecting the calculation efficiency.

[0101] Some embodiments of the present disclosure provide a method for automatically refining a mesh. Mesh refinement can be performed automatically based on the solution accuracy initially set. When the required calculation accuracy cannot be achieved, a larger mesh can be automatically identified for further meshing, and the next round of calculations can be automatically performed until the accuracy requirements are met. In this way, the requirements for mesh quality are reduced, and the calculation process can be automatically iterated to obtain the optimal result.

[0102] Figure 5A FIG. 5 is a flow chart showing a method 500 for processing a capacitor according to some embodiments of the present disclosure. In some embodiments, the method 500 may be performed as follows: Figure 1 The electronic device 110 shown executes. It should be understood that the method 500 may further include additional blocks not shown and / or may omit one (or some) of the blocks shown, and the scope of the present disclosure is not limited in this respect.

[0103] At block 520, for an integrated circuit divided into a plurality of cells, the electronic device 110 determines whether a positional relationship between a first processing unit and a second processing unit satisfies a predetermined approximation condition. The first processing unit corresponds to a first group of cells in the plurality of cells, and the second processing unit corresponds to a second group of cells in the plurality of cells. Each processing unit is obtained by merging the corresponding cells.

[0104] In some embodiments, the first processing unit and the second processing unit are determined as follows: based on the positions of the multiple cells in the integrated circuit, a hierarchical structure representing the relative positions between the multiple cells is generated, the hierarchical structure including multiple leaf nodes and multiple intermediate nodes located above the multiple leaf nodes, each leaf node corresponds to one of the multiple cells, and each intermediate node is assigned with cells corresponding to each leaf node under the intermediate node; in response to the leaf nodes corresponding to the first group of cells belonging to the first intermediate node, the first processing unit is determined based on the respective geometric properties of the first group of cells; and in response to the leaf nodes corresponding to the second group of cells belonging to the second intermediate node, the second processing unit is determined based on the respective geometric properties of the second group of cells.

[0105] In some embodiments, the method 500 further includes: in the hierarchical structure, corresponding the first processing unit to the first intermediate node; and in the hierarchical structure, corresponding the second processing unit to the second intermediate node.

[0106] In some embodiments, generating a hierarchical structure of multiple cells includes iteratively performing the following operations: in response to a third intermediate node in the hierarchical structure being assigned two or more cells, determining a reference point based on geometric properties of the two or more cells, the reference point being located in the space in which the two or more cells are distributed; based on the relative positions of the two or more cells and the reference point, assigning the two or more cells to multiple nodes below the third intermediate node; and determining the types of multiple nodes respectively based on the number of cells assigned to the multiple nodes, the types including leaf nodes or intermediate nodes.

[0107] In some embodiments, assigning two or more cells to multiple nodes below a third intermediate node includes: assigning cells among the two or more cells that have a first positional relationship with a reference point to a first node below the third intermediate node; and assigning cells among the two or more cells that have a first positional relationship with the reference point to a second node below the third intermediate node, the second positional relationship being different from the first positional relationship.

[0108] In some embodiments, determining whether the positional relationship between the first processing unit and the second processing unit satisfies a predetermined approximate condition includes: determining a relative distance between the first processing unit and the second processing unit based on a center of the first processing unit and a center of the second processing unit; determining a normalized distance between the first processing unit and the second processing unit based on a size of the first processing unit, a size of the second processing unit, and the relative distance; and in response to the normalized distance being less than a distance threshold, determining that the positional relationship between the first processing unit and the second processing unit satisfies a predetermined approximate condition.

[0109] In response to the positional relationship satisfying the predetermined approximation condition, the electronic device 110 determines potential coefficient information for the plurality of cells based on the potential coefficient between the first processing unit and the second processing unit at block 530. The potential coefficient information includes a potential coefficient between two cells in the plurality of cells.

[0110] In some embodiments, determining the potential coefficient information for multiple cells includes: calculating a reference potential coefficient between the first processing unit and the second processing unit based on the geometric properties of the first processing unit and the geometric properties of the second processing unit; and in the potential coefficient information, determining the potential coefficient between each cell in the first group of cells and each cell in the second group of cells as the reference potential coefficient.

[0111] At block 540 , the electronic device 110 determines a first capacitance value of the integrated circuit based on the potential coefficient information and the potentials of the plurality of cells.

[0112] In some embodiments, method 500 also includes: in response to a cell refinement indication, determining whether the refinement degree of the first processing unit and the second processing unit meets a predetermined refinement condition based on the geometric properties of the first processing unit and the geometric properties of the second processing unit; in response to the refinement degree of the first processing unit and the second processing unit not meeting the predetermined refinement condition, selecting a processing unit from the first processing unit and the second processing unit; refining a group of cells corresponding to the selected processing unit to obtain a plurality of updated cells; and determining a second capacitance value of the integrated circuit based on the potential coefficients between the updated plurality of cells.

[0113] In some embodiments, determining whether the refinement degree of the first processing unit and the second processing unit meets the predetermined refinement condition includes: determining a first refinement factor indicating the refinement degree of the first processing unit based on the size of the first processing unit and the potential coefficient between the first processing unit and the second processing unit; determining a second refinement factor indicating the refinement degree of the second processing unit based on the size of the second processing unit and the potential coefficient between the first processing unit and the second processing unit; and in response to at least one of the first refinement factor or the second refinement factor being greater than a reference refinement factor, determining that the refinement degree of the first processing unit and the second processing unit does not meet the predetermined refinement condition.

[0114] In some embodiments, selecting a processing unit from the first processing unit and the second processing unit includes: determining respective sizes of the first processing unit and the second processing unit; and selecting the first processing unit in response to the size of the first processing unit being greater than the size of the second processing unit.

[0115] In some embodiments, refining a group of cells corresponding to the selected processing unit includes: refining at least a portion of the cells in the group of cells to obtain updated cells; determining at least two processing units corresponding to the updated cells based on geometric properties of the updated cells; in response to determining that the refinement degree of the at least two processing units meets a predetermined refinement condition, stopping the refinement of the cells; and in response to determining that the refinement degree of the at least two processing units does not meet the predetermined refinement condition, refining the cells corresponding to one of the at least two processing units until the predetermined refinement condition is met.

[0116] In some embodiments, method 500 further includes: determining a degree of change of the second capacitance value relative to the first capacitance value; and in response to the degree of change being less than a degree of change threshold, determining the second capacitance value as the capacitance of the integrated circuit.

[0117] Figure 5B FIG. 5 shows a flow chart of a method 550 for refining a grid according to some embodiments of the present disclosure. In some embodiments, the method 550 may be performed as follows: Figure 1 The electronic device 110 shown executes. It should be understood that the method 550 may further include additional blocks not shown and / or may omit one (or some) of the blocks shown, and the scope of the present disclosure is not limited in this respect.

[0118] At block 560, for the integrated circuit divided into a plurality of cells, the electronic device 110 determines whether the refinement degree of the first processing unit and the second processing unit meets a predetermined refinement condition based on the geometric attributes of the first processing unit and the geometric attributes of the second processing unit. The first processing unit corresponds to a first group of cells in the plurality of cells, and the second processing unit corresponds to a second group of cells in the plurality of cells, and each processing unit is obtained by merging the corresponding cells.

[0119] In response to the refinement levels of the first processing unit and the second processing unit not satisfying a predetermined refinement condition, at block 570 , the electronic device 110 selects a processing unit from the first processing unit and the second processing unit.

[0120] In block 580 , the electronic device 110 refines a group of cells corresponding to the selected processing unit to obtain a plurality of updated cells.

[0121] In some embodiments, the method 550 further includes determining a second capacitance value of the integrated circuit based on the updated potential coefficients between the plurality of cells.

[0122] In some embodiments, determining whether the refinement degree of the first processing unit and the second processing unit meets the predetermined refinement condition includes: determining a first refinement factor indicating the refinement degree of the first processing unit based on the size of the first processing unit and the potential coefficient between the first processing unit and the second processing unit; determining a second refinement factor indicating the refinement degree of the second processing unit based on the size of the second processing unit and the potential coefficient between the first processing unit and the second processing unit; and in response to at least one of the first refinement factor or the second refinement factor being greater than a reference refinement factor, determining that the refinement degree of the first processing unit and the second processing unit does not meet the predetermined refinement condition.

[0123] In some embodiments, selecting a processing unit from the first processing unit and the second processing unit includes: determining respective sizes of the first processing unit and the second processing unit; and selecting the first processing unit in response to the size of the first processing unit being greater than the size of the second processing unit.

[0124] In some embodiments, refining a group of cells corresponding to the selected processing unit includes: refining at least a portion of the cells in the group of cells to obtain updated cells; determining at least two processing units corresponding to the updated cells based on geometric properties of the updated cells; in response to determining that the refinement degree of the at least two processing units meets a predetermined refinement condition, stopping the refinement of the cells; and in response to determining that the refinement degree of the at least two processing units does not meet the predetermined refinement condition, refining the cells corresponding to one of the at least two processing units until the predetermined refinement condition is met.

[0125] In some embodiments, method 550 also includes: determining a degree of change of the second capacitance value relative to the first capacitance value, the first capacitance value being the capacitance of the integrated circuit calculated before the grid is updated; and in response to the degree of change being less than a degree of change threshold, determining the second capacitance value as the capacitance of the integrated circuit.

[0126] Figure 6 1 is a block diagram of an electronic device 600 in which one or more embodiments of the present disclosure may be implemented. The electronic device 600 may be used to implement, for example, Figure 1 The electronic device 110 shown. It should be understood that Figure 6 The electronic device 600 shown is merely exemplary and should not constitute any limitation on the functionality and scope of the embodiments described herein.

[0127] like Figure 6As shown, the electronic device 600 is in the form of a general electronic device. The components of the electronic device 600 may include, but are not limited to, one or more processors 610 or processing units, a memory 620, a storage device 630, one or more communication units 640, one or more input devices 650, and one or more output devices 660. The processing unit may be an actual or virtual processor and is capable of performing various processes according to a program stored in the memory 620. In a multi-processor system, multiple processing units execute computer executable instructions in parallel to improve the parallel processing capability of the electronic device 600.

[0128] The electronic device 600 typically includes a plurality of computer storage media. Such media may be any available media accessible to the electronic device 600, including but not limited to volatile and non-volatile media, removable and non-removable media. The memory 620 may be a volatile memory (e.g., a register, a cache, a random access memory (RAM)), a non-volatile memory (e.g., a read-only memory (ROM), an electrically erasable programmable read-only memory (EEPROM), flash memory), or some combination thereof. The storage device 630 may be a removable or non-removable medium, and may include a machine-readable medium, such as a flash drive, a disk, or any other medium, which may be capable of being used to store information and / or data (e.g., training data for training) and may be accessed within the electronic device 600.

[0129] The electronic device 600 may further include additional removable / non-removable, volatile / non-volatile storage media. Figure 6 As shown in , a disk drive for reading or writing from a removable, non-volatile disk (e.g., a "floppy disk") and an optical drive for reading or writing from a removable, non-volatile optical disk may be provided. In these cases, each drive may be connected to the bus (not shown) by one or more data media interfaces. The memory 620 may include a computer program product 625 having one or more program modules that are configured to perform various methods or actions of various embodiments of the present disclosure.

[0130] The communication unit 640 enables communication with other electronic devices via a communication medium. Additionally, the functions of the components of the electronic device 600 can be implemented in a single computing cluster or multiple computing machines that can communicate via a communication connection. Therefore, the electronic device 600 can operate in a networked environment using a logical connection with one or more other servers, a network personal computer (PC), or another network node.

[0131] The input device 650 may be one or more input devices, such as a mouse, a keyboard, a tracking ball, etc. The output device 660 may be one or more output devices, such as a display, a speaker, a printer, etc. The electronic device 600 may also communicate with one or more external devices (not shown) through the communication unit 640 as needed, such as a storage device, a display device, etc., communicate with one or more devices that allow a user to interact with the electronic device 600, or communicate with any device (e.g., a network card, a modem, etc.) that allows the electronic device 600 to communicate with one or more other electronic devices. Such communication may be performed via an input / output (I / O) interface (not shown).

[0132] According to an exemplary implementation of the present disclosure, a computer-readable storage medium is provided, on which one or more computer instructions are stored, wherein the one or more computer instructions are executed by a processor to implement the method described above.

[0133] Various aspects of the present disclosure are described herein with reference to flowcharts and / or block diagrams of methods, devices (systems) and computer program products implemented according to the present disclosure. It should be understood that each box in the flowchart and / or block diagram and the combination of boxes in the flowchart and / or block diagram can be implemented by computer-readable program instructions.

[0134] These computer-readable program instructions can be provided to a processing unit of a general-purpose computer, a special-purpose computer, or other programmable data processing device, thereby producing a machine, so that when these instructions are executed by the processing unit of the computer or other programmable data processing device, a device that implements the functions / actions specified in one or more boxes in the flowchart and / or block diagram is generated. These computer-readable program instructions can also be stored in a computer-readable storage medium, and these instructions cause the computer, programmable data processing device, and / or other equipment to work in a specific manner, so that the computer-readable medium storing the instructions includes a manufactured product, which includes instructions for implementing various aspects of the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0135] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device so that a series of operating steps are performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to implement the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0136] The flow chart and block diagram in the accompanying drawings show the possible architecture, function and operation of the system, method and computer program product according to multiple implementations of the present disclosure. In this regard, each square box in the flow chart or block diagram can represent a part of a module, program segment or instruction, and a part of a module, program segment or instruction includes one or more executable instructions for realizing the logical function of the specification. In some implementations as replacements, the function marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two continuous square boxes can actually be executed substantially in parallel, and they can sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be realized by a special hardware-based system that performs the function or action of the specification, or can be realized by a combination of special hardware and computer instructions.

[0137] The above descriptions of various implementations of the present disclosure are exemplary, non-exhaustive, and not limited to the disclosed implementations. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described implementations. The selection of terms used herein is intended to best explain the principles of the implementations, practical applications, or improvements to the technology in the marketplace, or to enable other persons of ordinary skill in the art to understand the implementations disclosed herein.

Claims

1. A method for processing a capacitor, comprising: For an integrated circuit divided into a plurality of cells, determining whether a positional relationship between a first processing unit and a second processing unit satisfies a predetermined approximation condition, wherein the first processing unit corresponds to a first group of cells in the plurality of cells, and the second processing unit corresponds to a second group of cells in the plurality of cells, and each processing unit is obtained by merging corresponding cells; In response to the positional relationship satisfying the predetermined approximation condition, determining potential coefficient information for the plurality of cells based on the potential coefficient between the first processing unit and the second processing unit, the potential coefficient information including a potential coefficient between two cells of the plurality of cells; as well as Based on the potential coefficient information and the potentials of the plurality of cells, a first capacitance value of the integrated circuit is determined.

2. The method for processing a capacitor according to claim 1, characterized in that: The first processing unit and the second processing unit are determined in the following manner: Based on the positions of the plurality of cells in the integrated circuit, a hierarchical structure representing the relative positions of the plurality of cells is generated, wherein the hierarchical structure includes a plurality of leaf nodes and a plurality of intermediate nodes located above the plurality of leaf nodes, each leaf node corresponds to one of the plurality of cells, and each intermediate node is allocated with cells corresponding to the leaf nodes below the intermediate node; In response to the leaf node corresponding to the first group of cells belonging to the first intermediate node, determining the first processing unit based on the geometric attributes of the first group of cells; as well as In response to the leaf nodes corresponding to the second group of cells belonging to the second intermediate node, the second processing unit is determined based on the respective geometric attributes of the second group of cells.

3. The method for processing a capacitor according to claim 2, characterized in that: The method further comprises: In the hierarchical structure, the first processing unit is associated with the first intermediate node; and In the hierarchical structure, the second processing unit is associated with the second intermediate node.

4. The method for processing a capacitor according to claim 2, characterized in that: Generating the hierarchical structure of the plurality of cells comprises iteratively performing the following operations: In response to a third intermediate node in the hierarchical structure being allocated with two or more cells, determining a reference point based on geometric properties of the two or more cells, the reference point being located in a space in which the two or more cells are distributed; allocating the two or more cells to a plurality of nodes below the third intermediate node based on relative positions of the two or more cells and the reference point; as well as Based on the number of cells allocated to the nodes, types of the nodes are respectively determined, the types including leaf nodes or intermediate nodes.

5. The method for processing a capacitor according to claim 4, characterized in that: Allocating the two or more cells to a plurality of nodes below the third intermediate node comprises: assigning a cell having a first positional relationship with the reference point among the two or more cells to a first node below the third intermediate node; and A cell among the two or more cells that has a second positional relationship with the reference point is assigned to a second node below the third intermediate node, the second positional relationship being different from the first positional relationship.

6. The method for processing a capacitor according to claim 1, characterized in that: Determining whether the positional relationship between the first processing unit and the second processing unit satisfies a predetermined approximation condition includes: Determining a relative distance between the first processing unit and the second processing unit based on a center of the first processing unit and a center of the second processing unit; determining a normalized distance between the first processing unit and the second processing unit based on a size of the first processing unit, a size of the second processing unit, and the relative distance; and In response to the normalized distance being less than a distance threshold, it is determined that a positional relationship between the first processing unit and the second processing unit satisfies the predetermined approximation condition.

7. The method for processing a capacitor according to claim 1, characterized in that: Determining the potential coefficient information for the plurality of cells includes: Calculating a reference potential coefficient between the first processing unit and the second processing unit based on a geometric property of the first processing unit and a geometric property of the second processing unit; and In the potential coefficient information, the potential coefficient between each cell in the first group of cells and each cell in the second group of cells is determined as the reference potential coefficient.

8. The method for processing a capacitor according to claim 1, characterized in that: The method further comprises: In response to the cell refinement indication, determining whether refinement degrees of the first processing unit and the second processing unit meet a predetermined refinement condition based on the geometric attributes of the first processing unit and the geometric attributes of the second processing unit; In response to the refinement levels of the first processing unit and the second processing unit not satisfying the predetermined refinement condition, selecting a processing unit from the first processing unit and the second processing unit; Refining a group of cells corresponding to the selected processing unit to obtain a plurality of updated cells; and A second capacitance value of the integrated circuit is determined based on the updated potential coefficients between the plurality of cells.

9. The method for processing a capacitor according to claim 8, characterized in that: Determining whether the refinement degree of the first processing unit and the second processing unit meets a predetermined refinement condition includes: determining a first refinement factor indicating a refinement degree of the first processing unit based on a size of the first processing unit and a potential coefficient between the first processing unit and the second processing unit; determining a second refinement factor indicating a refinement degree of the second processing unit based on a size of the second processing unit and a potential coefficient between the first processing unit and the second processing unit; and In response to at least one of the first refinement factor or the second refinement factor being greater than a reference refinement factor, it is determined that the refinement degrees of the first processing unit and the second processing unit do not satisfy the predetermined refinement condition.

10. The method for processing a capacitor according to claim 8, characterized in that: Selecting a processing unit from the first processing unit and the second processing unit comprises: determining respective sizes of the first processing unit and the second processing unit; and In response to a size of the first processing unit being greater than a size of the second processing unit, the first processing unit is selected.

11. The method for processing a capacitor according to claim 8, characterized in that: Refining a set of cells corresponding to the selected processing unit includes: Refining at least a portion of the group of cells to obtain updated cells; Determining at least two processing units corresponding to the updated cell based on the geometric attributes of the updated cell; In response to determining that the refinement levels of the at least two processing units satisfy the predetermined refinement condition, stopping the refinement of the cell; and In response to determining that the refinement levels of the at least two processing units do not satisfy the predetermined refinement condition, a cell corresponding to one of the at least two processing units is refined until the predetermined refinement condition is satisfied.

12. The method for processing a capacitor according to claim 8, characterized in that: The method further comprises: determining a degree of change of the second capacitance value relative to the first capacitance value; and In response to the degree of change being less than a degree of change threshold, the second capacitance value is determined as the capacitance of the integrated circuit.

13. An electronic device, characterized in that: include: at least one processing unit; as well as At least one memory, the at least one memory being coupled to the at least one processing unit and storing instructions for execution by the at least one processing unit, the instructions causing the electronic device to perform the method according to any one of claims 1 to 12 when executed by the at least one processing unit.

14. A computer-readable storage medium, characterized in that: A computer program is stored thereon, characterized in that the computer program can be executed by a processor to implement the method according to any one of claims 1 to 12.

Images