A layout correction method, system, computer device, storage medium and computer program product

Abstract

The present invention relates to the field of computational lithography technology, and in particular to a layout correction method, system, computer equipment, storage medium, and computer program product. The method comprises: providing an initial mask layout, performing optical proximity correction processing on the initial mask layout to obtain an intermediate mask layout; providing a bad point detection model, the bad point detection model is obtained based on training of a real mask silicon wafer image; obtaining bad points on the intermediate mask layout based on the intermediate mask layout and the bad point detection model; repairing the bad points on the intermediate mask layout to obtain a corrected final mask layout. It can be understood that the bad point detection model is used to compensate for the poor versatility caused by the universality limitation of the photoresist model in the optical proximity correction model, so that the bad points on the mask layout can be better detected and repaired; this method improves the accuracy of mask layout correction, reduces the number of bad points in the circuit pattern on the silicon wafer, and improves the yield rate of integrated circuit manufacturing.

Description

Technical field

[0001] The present invention relates to the field of computational lithography technology, and in particular to a layout correction method, system, computer equipment, storage medium and computer program product. [Background Technology]

[0002] During integrated circuit manufacturing, chip factories must perform optical proximity correction (OPC) on the original design pattern before tape-out to obtain an optimized mask layout. This OPC process involves a series of optimization strategies and parameter settings.

[0003] The optical proximity correction (OPC) model is typically established during the R&D phase, primarily based on silicon wafer data from test mask layouts and a portion of the actual mask layout. The optimization strategies and parameter settings involved in the OPC process often include a photoresist model. Due to the limited universality of the photoresist model, it may not achieve the ideal effect for all design patterns, which can easily lead to deviations in the mask layout correction and result in defective pixels in the circuit pattern implemented on the silicon wafer. [Summary of the invention]

[0004] In order to solve the problem that the existing optical proximity correction model has poor universality, resulting in the correction of the mask layout still prone to bad pixels, the present invention provides a layout correction method, system, computer equipment, storage medium and computer program product.

[0005] In order to solve the above technical problems, the present invention provides the following technical solutions: a layout correction method, the method comprising:

[0006] An initial mask layout is provided, and optical proximity correction processing is performed on the initial mask layout to obtain an intermediate mask layout; a bad dot detection model is provided, the bad dot detection model includes a simulation sub-model for simulating the mask layout, the bad dot detection model is obtained based on mask silicon wafer image training, when training the bad dot detection model, the contour obtained from the mask silicon wafer image is used as the basic contour, the model contour obtained after simulation of the bad dot detection model is used as the reference contour, the difference between the basic contour and the reference contour is used as an evaluation parameter, and the bad dot detection model is iteratively optimized until the difference between the basic contour and the reference contour is less than a preset value; bad dots on the intermediate mask layout are obtained based on the intermediate mask layout and the bad dot detection model; the bad dots on the intermediate mask layout are repaired to obtain a corrected final mask layout.

[0007] Preferably, an initial mask layout is provided, and an optical proximity correction process is performed on the initial mask layout to obtain an intermediate mask layout, including: providing an initial mask layout; obtaining a target pattern in the initial mask layout; and performing an optical proximity correction process on the target pattern in the initial mask layout to obtain an intermediate mask layout.

[0008] Preferably, obtaining bad dots on the intermediate mask layout based on the intermediate mask layout and the bad dot detection model includes: simulating the intermediate mask layout using the bad dot detection model to obtain a first model contour; simulating the intermediate mask layout using the optical proximity correction model to obtain a second model contour; comparing the first model contour and the second model contour, and defining the position where the difference exceeds the preset specification as a bad dot.

[0009] Preferably, repairing the bad pixel on the intermediate mask layout includes: obtaining the area where the bad pixel is located on the intermediate mask layout; adjusting the target pattern in the area where the bad pixel is located on the intermediate mask layout; performing optical proximity correction processing on the adjusted target pattern to obtain the adjusted intermediate mask layout; using the bad pixel detection model to simulate the adjusted intermediate mask layout to obtain a third model profile; using the optical proximity correction model to simulate the adjusted intermediate mask layout to obtain a fourth model profile; comparing the third model profile and the fourth model profile, and judging whether the bad pixel is repaired according to the comparison result; if not, iteratively adjusting the target pattern in the area where the bad pixel is located until the bad pixel is repaired.

[0010] Preferably, obtaining bad dots on the intermediate mask layout based on the intermediate mask layout and the bad dot detection model includes: simulating the intermediate mask layout using the bad dot detection model to obtain a first model outline; and performing bad dot detection on the first model outline to obtain bad dots.

[0011] Preferably, repairing bad dots on the intermediate mask layout includes: obtaining an area on the intermediate mask layout where the bad dots are located; adjusting a target pattern on the intermediate mask layout where the bad dots are located; performing optical proximity correction processing on the adjusted target pattern to obtain an adjusted intermediate mask layout; simulating the adjusted intermediate mask layout using the bad dot detection model to obtain a fifth model profile; performing bad dot detection on the fifth model profile to determine whether the bad dots are repaired; if not, iteratively adjusting the target pattern in the area where the bad dots are located until the bad dots are repaired.

[0012] Preferably, after adjusting the target pattern in the region where the bad pixel is located on the intermediate mask layout, the model contour obtained during simulation is the local model contour corresponding to the region where the bad pixel is located on the intermediate mask layout.

[0013] Preferably, before using the bad pixel detection model to simulate the intermediate mask layout to obtain the first model profile, it also includes: providing an initial mask silicon wafer image corresponding to the initial mask layout; and adapting the bad pixel detection model based on the initial mask silicon wafer image.

[0014] In order to solve the above-mentioned technical problems, the present invention provides another technical solution as follows: a layout correction system, comprising: a correction module, used to provide an initial mask layout, perform optical proximity correction processing on the initial mask layout, and obtain an intermediate mask layout; a bad point detection module, used to provide a bad point detection model, and the bad point detection model is obtained based on mask silicon wafer image training; based on the intermediate mask layout and the bad point detection model, bad points on the intermediate mask layout are obtained; and a repair module, used to repair bad points on the intermediate mask layout to obtain a corrected final mask layout.

[0015] In order to solve the above technical problems, the present invention provides another technical solution as follows: a computer device includes a memory, a processor and a computer program stored in the memory, and the processor executes the computer program to implement the steps of the above method.

[0016] In order to solve the above technical problems, the present invention provides another technical solution as follows: a computer-readable storage medium stores a computer program, which implements the steps of the above method when executed by a processor.

[0017] In order to solve the above technical problems, the present invention provides another technical solution as follows: a computer program product, including a computer program / instruction, which implements the steps of the above method when executed by a processor.

[0018] Compared with the prior art, the layout correction method, system, computer device, storage medium and computer program product provided by the present invention have the following beneficial effects:

[0019] 1. The layout correction method provided in the embodiment of the present invention introduces a bad pixel detection model. Since the bad pixel detection model is obtained through training based on real mask silicon wafer images, the simulation results of the bad pixel detection model can more effectively represent the actual silicon wafer results of the current layout. By combining it with the optical proximity correction model, the bad pixel detection model can be used to compensate for the poor versatility caused by the universality limitations of the photoresist model in the optical proximity correction model, thereby better detecting and repairing bad pixels on the mask layout. From the final effect, this method improves the accuracy of mask layout correction, reduces the number of bad pixels in circuit patterns on silicon wafers, and improves the yield of integrated circuit manufacturing.

[0020] 2. In the training process of the bad pixel detection model, the embodiment of the present invention uses the difference between the base profile and the reference profile as an evaluation parameter. Through iterative optimization, the high accuracy of the simulation model can be ensured. Specifically, through iterative optimization, the difference between the base profile and the reference profile is continuously reduced, and eventually convergence is achieved, that is, the degree of similarity between the base profile and the reference profile is improved. The ultimate goal is to make the simulation results of the bad pixel detection model as close as possible to the reference mask wafer image, so that the simulation results can represent the mask wafer image. This helps to improve the accuracy of bad pixel detection during the layout correction process, thereby further improving the quality of the corrected mask layout.

[0021] 3. Embodiments of the Invention The present invention obtains an intermediate mask layout through optical proximity correction processing. This process optimizes the optical characteristics of the target pattern, and by adjusting the target pattern, uses specific algorithms and models to predict and correct the deviation of the target pattern, thereby significantly improving the lithography resolution and ensuring the accuracy of critical dimensions and the integrity of the pattern. In addition, the optical proximity correction processing also helps to improve the consistency of the pattern on the silicon wafer, reduce problems such as edge blur and center darkening caused by optical effects, thereby reducing manufacturing defects and improving the overall manufacturing yield. This pre-processing step provides more accurate basic data for the subsequent detection and repair of bad spots, thereby improving the accuracy and efficiency of the entire layout correction process. In addition, by reducing graphic distortion, this method helps to improve the performance of integrated circuits, especially in the manufacture of tiny graphic features, and can ensure the accuracy and consistency of circuit graphics.

[0022] 4. Embodiments of the Invention This invention utilizes a bad pixel detection model and an optical proximity correction model to perform dual simulations on the intermediate mask layout. This eliminates the need for traditional bad pixel detection. By comparing the resulting model profiles, locations with significant discrepancies between the two model profiles are designated as bad pixels, enabling rapid and efficient identification of bad pixels. This comparison method not only improves the efficiency of bad pixel detection but also ensures its accuracy by using the precise model profile of the bad pixel detection model as a comparison target. Accurate bad pixel location facilitates precise execution of subsequent repair steps, thereby avoiding over- or under-correction and ensuring the quality and reliability of the corrected mask layout.

[0023] 5. Embodiments of the Invention The repair process of the present invention iteratively adjusts the target graphics in the area where the bad pixel is located until the bad pixel is repaired. This iterative repair method can ensure that the bad pixel is completely repaired, avoiding the problems that may be left over from traditional single corrections. Through continuous optimization and adjustment, this method improves the reliability of the corrected mask layout, reduces the possibility of rework, and improves production efficiency. In addition, fine adjustments during the iterative process help to keep other parts of the layout from being unnecessarily affected, thereby ensuring the consistency and integrity of the entire layout. Moreover, the detection of the bad pixel repair results is also carried out through contour comparison, which further improves the iterative efficiency of this repair process.

[0024] 6. In an embodiment of the present invention, in addition to performing bad pixel detection by contour comparison, the bad pixel detection model can also be directly used to simulate the model contour obtained by simulating the intermediate mask layout to perform bad pixel detection. The intermediate mask layout is the result of optical proximity correction. Therefore, this method also introduces a bad pixel detection model to make up for the defects of the optical proximity correction model.

[0025] 7. In an embodiment of the present invention, since during bad pixel repair, generally only the target graphics in the area where the bad pixel is located are adjusted, that is, the target graphics in other areas remain unchanged, then when the bad pixel is subsequently detected to determine whether it has been repaired, there is no need to compare these unchanged target graphics. Therefore, when obtaining the model contour, only the local model contour corresponding to the area where the bad pixel is located can be obtained, and only the local model contour can be tested, thereby saving computing power and improving the efficiency of bad pixel correction.

[0026] 8. In an embodiment of the present invention, the current bad pixel detection model is continuously fine-tuned and updated according to the new mask silicon wafer image data. That is, the modeling process will continue to evolve as the tape-out data increases, so that the simulation results of the bad pixel detection model can always more effectively represent the actual silicon wafer results of the current layout, further ensuring the universality of this method.

[0027] 9. An embodiment of the present invention further provides a layout correction system. This layout correction system has the same beneficial effects as the above-mentioned layout correction method, which will not be described in detail here.

[0028] 10. An embodiment of the present invention further provides a computer device, which has the same beneficial effects as the above-mentioned layout correction method, and will not be described in detail here.

[0029] 11. An embodiment of the present invention further provides a computer-readable storage medium, which has the same beneficial effects as the above-mentioned layout correction method and will not be described in detail here.

[0030] 12. An embodiment of the present invention further provides a computer program product, which has the same beneficial effects as the above-mentioned layout correction method and is not described in detail here.

Brief Description of the Drawings

[0031] Figure 1 It is a flowchart of the layout correction method provided by the first embodiment of the present invention.

[0032] Figure 2 It is a flow chart of optimizing the bad pixel detection model in the layout correction method provided by the first embodiment of the present invention.

[0033] Figure 3 1 is a flow chart of step S1 in the layout correction method provided in the first embodiment of the present invention.

[0034] Figure 4 This is a flow diagram of step S2 in the layout correction method provided by the first embodiment of the present invention. Figure 1 .

[0035] Figure 5 This is a flow diagram of step S3 in the layout correction method provided by the first embodiment of the present invention. Figure 1 .

[0036] Figure 6 This is a flow diagram of step S2 in the layout correction method provided by the first embodiment of the present invention. Figure 2 .

[0037] Figure 7 This is a flow diagram of step S3 in the layout correction method provided by the first embodiment of the present invention. Figure 2 .

[0038] Figure 8 2 is a schematic diagram of a layout correction system provided by a second embodiment of the present invention.

[0039] Figure 9 FIG. 1 is a schematic diagram of a computer device provided in a third embodiment of the present invention.

[0040] Figure 10 is a schematic diagram of a computer-readable storage medium provided by a fourth embodiment of the present invention.

[0041] Description of the accompanying drawings:

[0042] 100. Layout correction system; 1. Correction module; 2. Bad pixel detection module; 3. Repair module;

[0043] 200. Computer equipment; 4. Processor; 5. Storage;

[0044] 300. Computer-readable storage medium; 6. Computer program. [Specific implementation method]

[0045] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below with reference to the accompanying drawings and implementation examples. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0046] In the embodiments provided herein, it should be understood that "B corresponding to A" means that B is associated with A and B can be determined based on A. However, it should also be understood that determining B based on A does not mean determining B based solely on A; B can also be determined based on A and / or other information.

[0047] It should be understood that references to "one embodiment" or "an embodiment" throughout this specification mean that specific features, structures, or characteristics associated with the embodiment are included in at least one embodiment of the present invention. Therefore, the appearance of "in one embodiment" or "in an embodiment" throughout this specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. Those skilled in the art should also be aware that the embodiments described in this specification are all optional embodiments, and the actions and modules involved are not necessarily required for the present invention.

[0048] In various embodiments of the present invention, it should be understood that the size of the serial numbers of the above-mentioned processes does not necessarily mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0049] The flow charts and block diagrams in the accompanying drawings of the present invention illustrate the possible implementation architecture, functions and operations of the systems, methods and computer program products according to various embodiments of the present application. In this regard, each box in the flow chart or block diagram can represent a module, program segment or a part of code, and the module, program segment or a part of code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementation schemes, the functions marked in the box can also occur in a different order than those marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, which is determined based on the functions involved. It should be noted that each box in the block diagram and / or flow chart, and the combination of the boxes in the block diagram and / or flow chart can be implemented by a dedicated hardware-based system that performs the specified function or operation, or can be implemented by a combination of dedicated hardware and computer instructions.

[0050] To facilitate understanding of this solution, we first provide a detailed introduction to the technical background: During the manufacturing process of integrated circuits, the chip factory (Fabrication, abbreviated as FAB) needs to obtain the mask data (Mask) after optical proximity correction (Optical Proximity Correction, abbreviated as OPC) from the initial mask layout, which is called the intermediate mask layout in the embodiment of the present invention, and then take the mask data to the wafer.

[0051] In practice, the initial mask layout is fed into an OPC recipe for processing. An OPC recipe is a technical solution for optical proximity correction (OPC), essentially a series of optimization strategies and parameter settings. The general process for OPC involves performing OPC optimization on the initial mask layout, followed by a lithography rule check (LRC). If any bad pixels are detected, the OPC recipe is iteratively refined.

[0052] The basis of the OPC recipe is the OPC lithography model, referred to as the optical proximity correction model in the embodiments of the present invention. The prerequisite for performing OPC correction is simulation using the OPC lithography model. The OPC lithography model includes an optical model and a photoresist model. The optical model is based on first principles and strictly follows physical methods to calculate an aerial image (AI) from a mask image (MI). The photoresist model is derived from the aerial image based on an empirical model in production practice. Based on real scanning electron microscopy (SEM) measurement data, a semi-empirical and semi-physical method is used to linearly add multiple photoresist terms to select the model with the optimal parameters from a preset solution space. The smaller the error between the model's simulation results and the actual situation, or the smaller the evaluation function, the better the model.

[0053] The OPC lithography model is established during the technology node R&D stage (TD) of FAB. It is mainly based on the silicon wafer data of some typical test patterns and some real patterns, but mainly based on typical test patterns.

[0054] The OPC recipe includes the OPC photoresist model, which is determined through repeated iterations during the development process by the FAB's R&D department. It should be highly applicable, meaning it should produce good results for different design patterns at the same technology node. Once the OPC recipe is finalized, it is transferred from the FAB's R&D department to the mass production department for large-scale production. However, in actual industrial practice, OPC photoresist models are difficult to achieve universal applicability and cannot achieve good results for all design patterns. Inaccuracies in the OPC photoresist model often lead to deviations in layout corrections, which in turn cause bad pixels on the actual silicon wafer.

[0055] A mask plate refers to a physically visible and tactile glass plate with a mask pattern.

[0056] The mask layout refers to the layout pattern on the above-mentioned mask plate.

[0057] See also Figure 1 A first embodiment of the present invention provides a layout correction method, the method comprising:

[0058] Step S1: providing an initial mask layout, performing optical proximity correction processing on the initial mask layout, and obtaining an intermediate mask layout;

[0059] Step S2: providing a bad pixel detection model, which is obtained based on mask silicon wafer image training; obtaining bad pixels on the intermediate mask layout based on the intermediate mask layout and the bad pixel detection model;

[0060] Step S3: Repair the bad spots on the intermediate mask layout to obtain a corrected final mask layout.

[0061] It can be understood that the layout correction method provided in the embodiment of the present invention introduces a bad pixel detection model. Since the bad pixel detection model is obtained through training based on real mask silicon wafer images, the simulation results of the bad pixel detection model can more effectively represent the actual silicon wafer results of the current layout; and by combining it with the optical proximity correction model, the bad pixel detection model can be used to compensate for the poor versatility caused by the universality limitations of the photoresist model in the optical proximity correction model, thereby better detecting and repairing bad pixels on the mask layout; from the final effect, this method improves the accuracy of mask layout correction, reduces the number of bad pixels in circuit graphics on silicon wafers, and improves the yield of integrated circuit manufacturing.

[0062] Furthermore, when training the bad pixel detection model, the contour obtained from the mask silicon wafer image is used as the basic contour, the model contour obtained after simulating the bad pixel detection model is used as the reference contour, and the difference between the basic contour and the reference contour is used as the evaluation parameter. The bad pixel detection model is iteratively optimized until the difference between the basic contour and the reference contour is less than the preset value.

[0063] It is understood that in the training process of the bad pixel detection model, the embodiment of the present invention uses the difference between the basic profile and the reference profile as an evaluation parameter. Through iterative optimization, the high accuracy of the simulation model can be ensured. Specifically, through iterative optimization, the difference between the basic profile and the reference profile is continuously reduced, and finally a convergence process is achieved, that is, a process of improving the similarity between the basic profile and the reference profile. The ultimate goal is to make the simulation results of the bad pixel detection model as close as possible to the reference mask silicon wafer image, so that the simulation results can represent the mask silicon wafer image. This helps to improve the accuracy of bad pixel detection during the layout correction process, thereby further improving the quality of the corrected mask layout. It is understood that the bad pixel detection model in this embodiment includes a simulation sub-model that can simulate the mask layout.

[0064] For further information, please refer to Figure 2 In this embodiment, a pair of basic simulation models are provided and optimized to obtain a bad pixel detection model. The optimization process includes:

[0065] S01: Provide multiple SEM images;

[0066] S02: Extract the contour lines of each SEM image;

[0067] S03: Obtain measurement points based on contour lines;

[0068] S04: providing a basic simulation model to simulate the mask layout corresponding to each SEM image to obtain a simulation profile;

[0069] S05: comparing the distance between the measurement point and the corresponding position of the simulation contour, and obtaining the evaluation function of the current model based on the distance;

[0070] S06: Determine whether the evaluation function converges; if so, end the optimization; if not, execute S07.

[0071] S07: Adjust the parameters of the basic simulation model and return to step S04.

[0072] Specifically, the SEM image in step S01 refers to the SEM image of the mask.

[0073] Specifically, in step S02 , the contour lines of the SEM image refer to the outer contours of the layout pattern on the mask, and the number of the contour lines is variable.

[0074] Specifically, in step S03 , the measurement points are points selected along the contour line.

[0075] As a feasible implementation method, measurement points are evenly selected along the contour line.

[0076] As a feasible implementation method, along different line segments of the contour line, measurement points are uniformly selected within the line segments with different densities.

[0077] As a feasible implementation method, more measurement points are selected within the line segment near the turning point of the line segment.

[0078] Specifically, the basic simulation model can be an existing photolithography simulation model, which will not be described in detail here. In this embodiment, by iteratively adjusting the parameters of the basic simulation model to converge the evaluation function, the resulting bad pixel detection model has the ability to accurately simulate the mask silicon wafer image.

[0079] As a feasible implementation, the evaluation function may be the sum of the distances between all measured points and corresponding positions of the simulation contour.

[0080] As a feasible implementation, the evaluation function can be the sum of the mean squared errors of the distances between all measured points and corresponding locations on the simulated contour. It is understood that the evaluation function can be configured in a variety of ways, as long as it reflects the degree of difference between the measured points and the simulated contour, and is not limited here.

[0081] Specifically, in step S06, the optimization is stopped after it is determined that the evaluation function has converged, that is, when the difference between the measured point and the simulated contour is less than a preset value, the optimization is stopped. At this time, the degree of closeness between the simulated contour and the SEM image contour line is high enough, and the simulated contour can fully represent the SEM image contour line.

[0082] Further, please combine Figure 1 and Figure 3 , providing an initial mask layout, performing optical proximity correction on the initial mask layout, and obtaining an intermediate mask layout, including:

[0083] S11: Provide initial mask layout;

[0084] S12: Obtain the target pattern in the initial mask layout;

[0085] S13: Performing optical proximity correction processing on the target pattern in the initial mask layout to obtain an intermediate mask layout.

[0086] It can be understood that the embodiment of the present invention obtains the intermediate mask layout through optical proximity correction processing. This process optimizes the optical characteristics of the target pattern, and by adjusting the target pattern, uses specific algorithms and models to predict and correct the deviation of the target pattern, thereby significantly improving the lithography resolution and ensuring the accuracy of critical dimensions and the integrity of the pattern. In addition, the optical proximity correction processing also helps to improve the consistency of the pattern on the silicon wafer, reduce problems such as edge blur and center darkening caused by optical effects, thereby reducing manufacturing defects and improving the overall manufacturing yield. This pre-processing step provides more accurate basic data for the subsequent detection and repair of bad spots, thereby improving the accuracy and efficiency of the entire layout correction process. In addition, by reducing graphic distortion, this method helps to improve the performance of integrated circuits, especially in the manufacture of tiny graphic features, and can ensure the accuracy and consistency of circuit graphics.

[0087] Specifically, the target pattern is usually a rectangle, but other shapes are not limited. Optical proximity correction processing has a relatively mature existing technical solution, which will not be described in detail here.

[0088] Further, please combine Figure 1 and Figure 4 As an optional implementation, step S2 scheme 1 includes:

[0089] S2a1: Using the bad pixel detection model to simulate the intermediate mask layout to obtain a first model outline;

[0090] S2a2: Using the optical proximity correction model to simulate the intermediate mask layout to obtain a second model profile;

[0091] S2a3: Compare the first model contour and the second model contour, and define a position where the difference exceeds a preset specification as a bad pixel.

[0092] As can be understood, the embodiments of the present invention utilize a bad pixel detection model and an optical proximity correction model to perform dual simulations on the intermediate mask layout. This eliminates the need for traditional bad pixel detection. By comparing the resulting model profiles, locations with significant discrepancies between the two model profiles are designated as bad pixels, enabling rapid and efficient identification of bad pixels. This comparison method not only improves the efficiency of bad pixel detection but also ensures the accuracy of bad pixel detection by using the precise model profile of the bad pixel detection model as a comparison target. Accurate bad pixel location facilitates the precise execution of subsequent repair steps, thereby avoiding over-correction or under-correction and ensuring the quality and reliability of the corrected mask layout.

[0093] It should be noted that the first model outline and the second model outline mentioned here are circuit patterns formed on the silicon wafer obtained through simulation, that is, the first model outline and the second model outline are graphic data obtained through simulation, rather than the circuit patterns on the actual silicon wafer.

[0094] In particular, the optical proximity correction model mentioned in step S2a2 can adopt the existing OPC lithography model, which will not be described in detail here.

[0095] Further, please combine Figure 1 and Figure 5 As an optional implementation, step S3 solution 1 includes:

[0096] S3a1: Obtain the area of ​​the bad pixel on the middle mask layout;

[0097] S3a2: adjusting the target pattern in the area where the bad pixel is located on the intermediate mask layout;

[0098] S3a3: performing optical proximity correction processing on the adjusted target pattern to obtain an adjusted intermediate mask layout;

[0099] S3a4: using the bad pixel detection model to simulate the adjusted intermediate mask layout to obtain a third model profile;

[0100] S3a5: simulating the adjusted intermediate mask layout using the optical proximity correction model to obtain a fourth model profile;

[0101] S3a6: Compare the third model contour and the fourth model contour, and determine whether the bad pixel is repaired according to the comparison result;

[0102] If not, iteratively adjust the target graphics in the area where the bad pixel is located until the bad pixel is repaired.

[0103] It can be understood that the repair process of the embodiment of the present invention iteratively adjusts the target graphics in the area where the bad point is located until the bad point is repaired. This iterative repair method can ensure that the bad point is completely repaired, avoiding the problems that may be left over from traditional single corrections. Through continuous optimization and adjustment, this method improves the reliability of the corrected mask layout, reduces the possibility of rework, and improves production efficiency. In addition, the fine adjustments during the iterative process help to keep other parts of the layout from being unnecessarily affected, thereby ensuring the consistency and integrity of the entire layout. Moreover, the detection of the bad point repair results is also carried out through contour comparison, which further improves the iterative efficiency of this repair process.

[0104] As a feasible implementation method, the method of obtaining the area in S3a1 can be to use the bad pixel as the center point and expand a certain radius outward as the area of ​​the bad pixel on the intermediate mask layout; it can be understood that the generation of bad pixels is often caused by the mutual influence between graphics or between edges within graphics. Therefore, to solve the bad pixel problem, we cannot only focus on the location of the bad pixel itself, but also need to pay attention to the environmental factors around the bad pixel.

[0105] Further, please combine Figure 1 and Figure 6 As an optional implementation, step S2 scheme 2 includes:

[0106] S2b1: Using the bad pixel detection model to simulate the intermediate mask layout to obtain a first model outline;

[0107] S2b2: Perform bad pixel detection on the first model contour to obtain bad pixels.

[0108] It can be understood that in the embodiment of the present invention, in addition to performing bad pixel detection by contour comparison, the bad pixel detection model can also be directly used to simulate the model contour obtained by simulating the intermediate mask layout to perform bad pixel detection. The intermediate mask layout is the result of optical proximity correction. Therefore, this method also introduces a bad pixel detection model to make up for the defects of the optical proximity correction model.

[0109] Further, please combine Figure 1 and Figure 7 As an optional implementation, step S3 scheme 2 includes:

[0110] S3b1: Get the area of ​​the bad pixel on the middle mask layout;

[0111] S3b2: Adjust the target pattern in the area where the bad pixel is located on the middle mask layout;

[0112] S3b3: performing optical proximity correction processing on the adjusted target pattern to obtain an adjusted intermediate mask layout;

[0113] S3b4: using the bad pixel detection model to simulate the adjusted intermediate mask layout to obtain a fifth model profile;

[0114] S3b5: performing bad pixel detection on the fifth model contour to determine whether the bad pixels are repaired;

[0115] If not, iteratively adjust the target graphics in the area where the bad pixel is located until the bad pixel is repaired.

[0116] It should be noted that the first solution of step S2 can be used in combination with the first solution or the second solution of step S3, and the second solution of step S2 can also be used in combination with the first solution or the second solution of step S3.

[0117] In order to ensure the consistency of ideas between the previous and subsequent steps, this embodiment only takes the combination of step S2 solution 1 and step S3 solution 1, and the combination of step S2 solution 2 and step S3 solution 2 as detailed examples.

[0118] Furthermore, after adjusting the target pattern in the region where the bad pixel is located on the intermediate mask layout, the model contour obtained during the simulation is the local model contour corresponding to the region where the bad pixel is located on the intermediate mask layout.

[0119] It can be understood that in the embodiment of the present invention, since when repairing bad pixels, generally only the target graphics in the area where the bad pixels are located are adjusted, that is, the target graphics in other areas remain unchanged, then when detecting whether the bad pixels are repaired later, there is no need to compare these unchanged target graphics. Therefore, when obtaining the model contour, we can only obtain the local model contour corresponding to the area where the bad pixels are located, and only perform the detection on the local model contour, thereby saving computing power and improving the efficiency of bad pixel correction.

[0120] It should be noted that, without considering efficiency and computing power or for other considerations, it is feasible to obtain the complete model outline throughout the process, and there will be no fundamental conflict with the solution mentioned in the embodiment of this application.

[0121] Furthermore, before simulating the intermediate mask layout using the bad pixel detection model to obtain the first model profile, the method further includes:

[0122] Providing an initial mask silicon wafer image corresponding to the initial mask layout;

[0123] The bad pixel detection model is adapted and adjusted based on the initial mask silicon wafer image.

[0124] It can be understood that in the embodiment of the present invention, the current bad pixel detection model is continuously fine-tuned and updated according to the new mask silicon wafer image data, that is, the modeling process will continue to evolve with the increase of tape-out data so that the simulation results of the bad pixel detection model can always more effectively represent the actual silicon wafer results of the current layout, further ensuring the universality of this method.

[0125] For further information, see Figure 8 The second embodiment of the present invention further provides a layout correction system 100, comprising:

[0126] Correction module 1, bad pixel detection module 2 and repair module 3; wherein, correction module 1 is used to provide an initial mask layout, perform optical proximity correction processing on the initial mask layout, and obtain an intermediate mask layout; bad pixel detection module 2 is used to provide a bad pixel detection model, and the bad pixel detection model is obtained based on mask silicon wafer image training; based on the intermediate mask layout and the bad pixel detection model, the bad pixels on the intermediate mask layout are obtained; repair module 3 is used to repair the bad pixels on the intermediate mask layout to obtain the corrected final mask layout.

[0127] It can be understood that the layout correction system 100 has the same beneficial effects as the above-mentioned layout correction method, which will not be described in detail here.

[0128] For further information, see Figure 9 The third embodiment of the present invention further provides a computer device 200, comprising a memory 5, a processor 4 and a computer program stored in the memory, wherein the processor 4 executes the computer program to implement the steps of the above method.

[0129] It can be understood that the computer device 200 has the same beneficial effects as the above-mentioned layout correction method, which will not be described in detail here.

[0130] For further information, see Figure 10 The fourth embodiment of the present invention further provides a computer-readable storage medium on which a computer program 6 is stored. When the computer program is executed by a processor, the steps of the above method are implemented.

[0131] It can be understood that the computer-readable storage medium has the same beneficial effects as the above-mentioned layout correction method, which will not be described in detail here.

[0132] Furthermore, a fourth embodiment of the present invention provides a computer program product comprising a computer program / instructions that, when executed by a processor, implement the steps of the above-described method. It is understood that this computer program product has the same beneficial effects as the above-described layout correction method, and further description thereof is omitted here.

[0133] Compared with the prior art, the layout correction method, system, computer device, storage medium and computer program product provided by the present invention have the following beneficial effects:

[0134] 1. The layout correction method provided in the embodiment of the present invention introduces a bad pixel detection model. Since the bad pixel detection model is obtained through training based on real mask silicon wafer images, the simulation results of the bad pixel detection model can more effectively represent the actual silicon wafer results of the current layout. By combining it with the optical proximity correction model, the bad pixel detection model can be used to compensate for the poor versatility caused by the universality limitations of the photoresist model in the optical proximity correction model, thereby better detecting and repairing bad pixels on the mask layout. From the final effect, this method improves the accuracy of mask layout correction, reduces the number of bad pixels in circuit patterns on silicon wafers, and improves the yield of integrated circuit manufacturing.

[0135] 2. In the training process of the bad pixel detection model, the embodiment of the present invention uses the difference between the base profile and the reference profile as an evaluation parameter. Through iterative optimization, the high accuracy of the simulation model can be ensured. Specifically, through iterative optimization, the difference between the base profile and the reference profile is continuously reduced, and eventually convergence is achieved, that is, the degree of similarity between the base profile and the reference profile is improved. The ultimate goal is to make the simulation results of the bad pixel detection model as close as possible to the reference mask wafer image, so that the simulation results can represent the mask wafer image. This helps to improve the accuracy of bad pixel detection during the layout correction process, thereby further improving the quality of the corrected mask layout.

[0136] 3. Embodiments of the Invention The present invention obtains an intermediate mask layout through optical proximity correction processing. This process optimizes the optical characteristics of the target pattern, and by adjusting the target pattern, uses specific algorithms and models to predict and correct the deviation of the target pattern, thereby significantly improving the lithography resolution and ensuring the accuracy of critical dimensions and the integrity of the pattern. In addition, the optical proximity correction processing also helps to improve the consistency of the pattern on the silicon wafer, reduce problems such as edge blur and center darkening caused by optical effects, thereby reducing manufacturing defects and improving the overall manufacturing yield. This pre-processing step provides more accurate basic data for the subsequent detection and repair of bad spots, thereby improving the accuracy and efficiency of the entire layout correction process. In addition, by reducing graphic distortion, this method helps to improve the performance of integrated circuits, especially in the manufacture of tiny graphic features, and can ensure the accuracy and consistency of circuit graphics.

[0137] 4. Embodiments of the Invention This invention utilizes a bad pixel detection model and an optical proximity correction model to perform dual simulations on the intermediate mask layout. This eliminates the need for traditional bad pixel detection. By comparing the resulting model profiles, locations with significant discrepancies between the two model profiles are designated as bad pixels, enabling rapid and efficient identification of bad pixels. This comparison method not only improves the efficiency of bad pixel detection but also ensures its accuracy by using the precise model profile of the bad pixel detection model as a comparison target. Accurate bad pixel location facilitates precise execution of subsequent repair steps, thereby avoiding over- or under-correction and ensuring the quality and reliability of the corrected mask layout.

[0138] 5. Embodiments of the Invention The repair process of the present invention iteratively adjusts the target graphics in the area where the bad pixel is located until the bad pixel is repaired. This iterative repair method can ensure that the bad pixel is completely repaired, avoiding the problems that may be left over from traditional single corrections. Through continuous optimization and adjustment, this method improves the reliability of the corrected mask layout, reduces the possibility of rework, and improves production efficiency. In addition, fine adjustments during the iterative process help to keep other parts of the layout from being unnecessarily affected, thereby ensuring the consistency and integrity of the entire layout. Moreover, the detection of the bad pixel repair results is also carried out through contour comparison, which further improves the iterative efficiency of this repair process.

[0139] 6. In an embodiment of the present invention, in addition to performing bad pixel detection by contour comparison, the bad pixel detection model can also be directly used to simulate the model contour obtained by simulating the intermediate mask layout to perform bad pixel detection. The intermediate mask layout is the result of optical proximity correction. Therefore, this method also introduces a bad pixel detection model to make up for the defects of the optical proximity correction model.

[0140] 7. In an embodiment of the present invention, since during bad pixel repair, generally only the target graphics in the area where the bad pixel is located are adjusted, that is, the target graphics in other areas remain unchanged, then when the bad pixel is subsequently detected to determine whether it has been repaired, there is no need to compare these unchanged target graphics. Therefore, when obtaining the model contour, only the local model contour corresponding to the area where the bad pixel is located can be obtained, and only the local model contour can be tested, thereby saving computing power and improving the efficiency of bad pixel correction.

[0141] 8. In an embodiment of the present invention, the current bad pixel detection model is continuously fine-tuned and updated according to the new mask silicon wafer image data. That is, the modeling process will continue to evolve as the tape-out data increases, so that the simulation results of the bad pixel detection model can always more effectively represent the actual silicon wafer results of the current layout, further ensuring the universality of this method.

[0142] 9. An embodiment of the present invention further provides a layout correction system. This layout correction system has the same beneficial effects as the above-mentioned layout correction method, which will not be described in detail here.

[0143] 10. An embodiment of the present invention further provides a computer device, which has the same beneficial effects as the above-mentioned layout correction method, and will not be described in detail here.

[0144] 11. An embodiment of the present invention further provides a computer-readable storage medium, which has the same beneficial effects as the above-mentioned layout correction method and will not be described in detail here.

[0145] 12. An embodiment of the present invention further provides a computer program product, which has the same beneficial effects as the above-mentioned layout correction method and is not described in detail here.

[0146] The above is a detailed introduction to a layout correction method, system, computer device and storage medium disclosed in an embodiment of the present invention. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention. Any modifications, equivalent replacements and improvements made within the principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A layout correction method, characterized in that: The method comprises: Providing an initial mask layout, performing optical proximity correction processing on the initial mask layout, and obtaining an intermediate mask layout; A bad pixel detection model is provided, the bad pixel detection model including a simulation sub-model for simulating a mask layout. The bad pixel detection model is obtained by training based on a real mask silicon wafer image. When training the bad pixel detection model, a contour obtained from the mask silicon wafer image is used as a basic contour, a model contour obtained after simulating the bad pixel detection model is used as a reference contour, and a difference between the basic contour and the reference contour is used as an evaluation parameter. The bad pixel detection model is iteratively optimized until the difference between the basic contour and the reference contour is less than a preset value. Bad pixels on the intermediate mask layout are obtained based on the intermediate mask layout and the bad pixel detection model. Repair the bad pixels on the intermediate mask layout to obtain the corrected final mask layout.

2. The layout correction method according to claim 1, wherein: Provide an initial mask layout, perform optical proximity correction on the initial mask layout, and obtain an intermediate mask layout, including: Provide initial mask layout; Obtain the target pattern in the initial mask layout; An optical proximity correction process is performed on the target pattern in the initial mask layout to obtain an intermediate mask layout.

3. The layout correction method according to claim 2, wherein: Obtain bad pixels on the reticle layout based on the reticle layout and bad pixel detection model, including: Using the bad pixel detection model to simulate the intermediate mask layout to obtain a first model profile; The optical proximity correction model is used to simulate the intermediate mask layout to obtain a second model profile; The first model outline and the second model outline are compared, and locations where the difference exceeds a preset specification are defined as bad pixels.

4. The layout correction method according to claim 3, wherein: Repair bad pixels on the intermediate mask layout, including: Obtain the area of ​​the bad pixel on the middle mask layout; Adjust the target pattern in the area where the bad pixels are located on the intermediate mask layout; Performing optical proximity correction processing on the adjusted target pattern to obtain an adjusted intermediate mask layout; Using the bad pixel detection model to simulate the adjusted intermediate mask layout to obtain a third model profile; Simulating the adjusted intermediate mask layout using an optical proximity correction model to obtain a fourth model profile; Comparing the third model outline with the fourth model outline, and determining whether the bad pixel has been repaired based on the comparison result; If not, iteratively adjust the target graphics in the area where the bad pixel is located until the bad pixel is repaired.

5. The layout correction method according to claim 2, wherein: Obtain bad pixels on the reticle layout based on the reticle layout and bad pixel detection model, including: Using the bad pixel detection model to simulate the intermediate mask layout to obtain a first model profile; Perform bad pixel detection on the first model contour to obtain bad pixels.

6. The layout correction method according to claim 5, wherein: Repair bad pixels on the intermediate mask layout, including: Obtain the area of ​​the bad pixel on the middle mask layout; Adjust the target pattern in the area where the bad pixels are located on the intermediate mask layout; Performing optical proximity correction processing on the adjusted target pattern to obtain an adjusted intermediate mask layout; Using the bad pixel detection model to simulate the adjusted intermediate mask layout to obtain a fifth model profile; Performing bad pixel detection on the fifth model contour to determine whether the bad pixels have been repaired; If not, iteratively adjust the target graphics in the area where the bad pixel is located until the bad pixel is repaired.

7. The layout correction method according to claim 4 or 6, wherein: After adjusting the target pattern in the region where the bad pixel is located on the intermediate mask layout, the model contour obtained during simulation is the local model contour corresponding to the region where the bad pixel is located on the intermediate mask layout.

8. The layout correction method according to claim 3, wherein: Before simulating the intermediate mask layout using the bad pixel detection model to obtain the first model profile, the method further includes: Providing an initial mask silicon wafer image corresponding to the initial mask layout; The bad pixel detection model is adapted and adjusted based on the initial mask silicon wafer image.

9. A layout correction system, characterized in that: include: A correction module is used to provide an initial mask layout, perform optical proximity correction processing on the initial mask layout, and obtain an intermediate mask layout; a bad pixel detection module, configured to provide a bad pixel detection model, the bad pixel detection model including a simulation sub-model for simulating a mask layout, the bad pixel detection model being trained based on a real mask silicon wafer image, and using the contour obtained from the mask silicon wafer image as a base contour when training the bad pixel detection model, and using the model contour obtained after simulating the bad pixel detection model as a reference contour, and using the difference between the base contour and the reference contour as an evaluation parameter, iteratively optimizing the bad pixel detection model until the difference between the base contour and the reference contour is less than a preset value; Obtaining bad pixels on the intermediate mask layout based on the intermediate mask layout and the bad pixel detection model; The repair module is used to repair the bad points on the intermediate mask layout to obtain the corrected final mask layout.

10. A computer device comprising a memory, a processor, and a computer program stored in the memory, wherein: The processor executes the computer program to implement the steps of the method according to any one of claims 1 to 8.

11. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 8 are implemented.

12. A computer program product comprising a computer program / instructions, characterized in that: When the computer program / instruction is executed by a processor, the steps of the method according to any one of claims 1 to 8 are implemented.

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