Signal Transmission Circuit, Control Method Thereof, and Electronic Device

Abstract

This application relates to a signal transmission circuit, its control method, and an electronic device, and belongs to the technical field of electronic devices. It is used to solve the problem of high cost of electronic devices. The signal transmission circuit includes a first signal outputter, a second signal outputter, a first connection line, a second connection line, and an actuator. The first connection line is respectively coupled to the second signal outputter and the actuator. The second connection line is respectively coupled to the first signal outputter and the first connection line. When the signal transmission circuit is in the first state, the first signal output by the first signal outputter is transmitted to the actuator via the second connection line and at least part of the first connection line. When the signal transmission circuit is in the second state, the second signal output by the second signal outputter is transmitted to the actuator via the first connection line.

Description

Technical Field

[0001] The present disclosure relates to the technical field of electronic devices, and particularly to a signal transmission circuit, a control method thereof, and an electronic device. Background Art

[0002] With the rapid development of electronic information technology, there are more and more functional modules that provide high-performance services for electronic devices. For different usage scenarios of an electronic device, multiple functional modules in the electronic device can respectively provide signals of different performance modes for the same hardware to drive the hardware to work in different performance scenarios. For example, for the same hardware, one functional module can provide a signal corresponding to a high-performance mode for it, and another functional module can provide a signal corresponding to a low-performance mode for it. The electronic device can select one of the two signals to access the hardware according to the usage scenario, so that the hardware works in the corresponding performance mode.

[0003] However, the above design architecture will result in more components and higher costs of the electronic device. Summary of the Invention

[0004] Embodiments of the present application provide a signal transmission circuit, a control method thereof, and an electronic device, which are used to solve the problem of high cost of the electronic device.

[0005] To achieve the above object, the embodiments of the present application adopt the following technical solutions:

[0006] In a first aspect, a signal transmission circuit is provided. The signal transmission circuit includes a first signal outputter, a second signal outputter, a first connection line, a second connection line, and an actuator. The first connection line is respectively coupled to the second signal outputter and the actuator. The second connection line is respectively coupled to the first signal outputter and the first connection line. When the signal transmission circuit is in a first state, a first signal output by the first signal outputter is transmitted to the actuator via the second connection line and at least part of the first connection line. When the signal transmission circuit is in a second state, a second signal output by the second signal outputter is transmitted to the actuator via the first connection line.

[0007] Embodiments of the present application can be a compatible architecture design for converting any signal transmission line of two or more paths into a single signal transmission line. For ease of understanding, an example is given where both a central processing unit (CPU) and a graphics processing unit (GPU) can provide image data signals for a display screen. Among them, the CPU represents the first signal outputter, the GPU represents the second signal outputter, the display screen represents the actuator, the first embedded display port (eDP) connection line represents the first connection line, and the second eDP connection line represents the second connection line.

[0008] The first end of the first eDP connection line is coupled to the GPU, and the second end of the first eDP connection line is coupled to the display screen. The first end of the second eDP connection line is coupled to the CPU, and the second end of the second eDP connection line is coupled to the first eDP connection line.

[0009] In a high-performance mode where the electronic device has a high refresh rate requirement for the display screen, the signal transmission circuit is in the second state, the GPU outputs an image data signal (representing the second signal) and the CPU is in a high impedance state, and the image data signal is transmitted to the display screen via the first eDP connection line.

[0010] In a low-performance mode where the electronic device has no high refresh rate requirement for the display screen, the signal transmission circuit is in the first state, the CPU outputs an image data signal (representing the first signal) and the GPU is in a high impedance state, and the image data signal is transmitted to the display screen via the second eDP connection line and at least part of the first eDP connection line.

[0011] It can be understood that in the transmission path between the CPU and the display screen, by adding a second eDP connection line with a shorter distance that connects the CPU and the GPU, the CPU can utilize the connection line (the first eDP connection line) between the GPU and the display screen. Compared with the CPU additionally setting a connection line with a longer distance to communicate with the display screen, the wiring quantity of the signal transmission circuit can be reduced.

[0012] In this way, compared with the signal transmission circuit in which the CPU and the GPU are each connected to the display screen through a connecting line, on the basis that both can realize the switching between the two states of the CPU controlling the display of the display screen and the GPU controlling the display of the display screen, the switching device for switching the CPU signal and the GPU signal can be omitted, reducing the cost of the signal transmission circuit. In addition, since the distance between the CPU and the GPU is closer than the distance between the CPU and the switching device, the total length of the connecting lines in the signal transmission circuit provided in this application is less than the total length of the connecting lines in the signal transmission circuit in which the CPU and the GPU are each connected to the display screen through a connecting line, and the wiring space of the signal transmission circuit on the circuit board can be reduced.

[0013] In some feasible implementation manners of the first aspect, the second connecting line includes a first connecting segment, a second connecting segment, and a switch. The switch includes a first end, a second end, and a third end. The first connecting segment is respectively coupled to the first signal outputter and the first end, and the second connecting segment is respectively coupled to the third end and the first connecting line. The signal transmission circuit further includes an impedance matcher; the impedance matcher is coupled to the second end. When the signal transmission circuit is in the first state, the third end is connected to the first end and the third end is disconnected from the second end. When the signal transmission circuit is in the second state, the third end is connected to the second end and the third end is disconnected from the first end.

[0014] The first connecting segment can be respectively coupled to the first end of the switch and the CPU. The second connecting segment can be respectively coupled to the third end of the switch and the second eDP connecting line. When the first end and the third end are conducting, the first connecting segment and the second connecting segment are connected to each other.

[0015] When the CPU outputs a signal and the GPU is in a high impedance state, the signal transmission circuit is in the first state, and the switch can make the first end and the third end conduct. In this way, the first connecting segment and the second connecting segment can be connected through the switch, and the signal output by the CPU can be sequentially transmitted to the display screen via the first connecting segment, the switch, the second connecting segment, and the second connecting line.

[0016] When the GPU outputs a signal and the CPU is in a high impedance state, the signal transmission circuit is in the second state, and the switch can make the second end and the third end conduct. In this way, the switch can disconnect the first connecting segment and the second connecting segment, and the signal output by the GPU can be transmitted to the display screen via the main display interface signal line. Among them, the switch and the second connecting segment are connected to the main display interface signal line as stub lines (also known as stub wires, wire ends, or skew wires).

[0017] However, due to the existence of the stub line, impedance discontinuity occurs at the stub line for high-speed signals, resulting in reflections, which in turn cause negative impacts such as deterioration of high-speed signal quality and timing, reducing the integrity and reliability of high-speed signal transmission. Among them, the longer the length of the stub line, the greater the negative impact on high-speed signals.

[0018] The impedance matcher is coupled to the second end of the switch and serves as the termination resistor for the stub line. The impedance matcher can be used to provide a resistor that matches the transmission link of the GPU output signal to the second end of the switch, so as to reduce the negative impact of the stub line on the GPU output signal in the transmission link and improve the reliability of the GPU output signal.

[0019] In some examples, the control end of the switch can be coupled to the CPU. The CPU can control the switch such that the first end is coupled to the third end and the second end is disconnected from the third end, or the CPU can control the switch such that the second end is coupled to the third end and the first end is disconnected from the third end.

[0020] In some other embodiments, the control end of the switch can be coupled to the GPU. The GPU can control the switch such that the second end is coupled to the third end and the first end is disconnected from the third end, or the GPU can control the switch such that the first end is coupled to the third end and the second end is disconnected from the third end.

[0021] In some other embodiments, the signal transmission circuit may further include a logic controller. The logic controller can be coupled to the CPU, the GPU, and the switch respectively. The logic controller can control the switch such that the second end is coupled to the third end and the first end is disconnected from the third end, or control the switch such that the first end is coupled to the third end and the second end is disconnected from the third end by detecting the states of the CPU and the GPU.

[0022] In some feasible implementation manners of the first aspect, the impedance matcher includes a variable resistor or a fixed-value resistor.

[0023] In some examples, the impedance matcher may include a fixed-value resistor. Since the resistance value of the resistor provided by the impedance matcher can depend on the transmission link of the GPU output signal, different resistance values can be pre-tested for the transmission link of the GPU output signal to determine the target resistance value that matches the link, and then the fixed-value resistor with the target resistance value can be coupled to the second end.

[0024] In this way, when the GPU outputs a signal and the CPU is in a high-impedance state, the second connection line is a stub line. The switch can conduct the second terminal and the third terminal, so that the fixed resistor can be connected to the first connection line through the switch and the second connection segment as the termination resistor of the stub line, thereby reducing the negative impact of the stub line on the GPU output signal in the transmission link and improving the reliability of the GPU output signal.

[0025] In some other examples, the impedance matcher may include a variable resistor. The variable resistor can flexibly adjust the resistance value of its own output. In each case where the second terminal is coupled to the third terminal, the variable resistor can traverse each resistance value, and the electronic device can detect the influence of the stub line on the transmission link of the GPU output signal when the variable resistor is at each resistance value, so as to determine the target resistance value matching the link and set the variable resistor to the target resistance value.

[0026] In this way, when the GPU outputs a signal and the CPU is in a high-impedance state, the first connection segment is a stub line. The switch SW can conduct the second terminal and the third terminal, so that the variable resistor can be connected to the main signal line of the display interface through the switch and the second connection segment, thereby reducing the negative impact of the stub line on the GPU output signal in the transmission link and improving the reliability of the GPU output signal.

[0027] In some feasible implementation manners of the first aspect, the impedance matcher includes a plurality of fixed resistors with different resistance values. The switch includes a plurality of second terminals, and the plurality of second terminals are respectively coupled to the plurality of fixed resistors. The third terminal is connected to the second terminal, including that the third terminal is coupled to one second terminal and disconnected from other second terminals.

[0028] In some examples, the impedance matcher may include a plurality of fixed resistors. The resistance values of the plurality of fixed resistors are different from each other. Exemplarily, the impedance matcher may include a first fixed resistor, a second fixed resistor, and a third fixed resistor. The resistance value of the first fixed resistor is less than the resistance value of the second fixed resistor, and the resistance value of the second fixed resistor is less than the resistance value of the third fixed resistor.

[0029] Correspondingly, the switch may include a plurality of second terminals, and the plurality of second terminals are coupled to the plurality of fixed resistors in one-to-one correspondence. Exemplarily, the impedance matcher includes three second terminals, one second terminal is coupled to the first fixed resistor, another second terminal is coupled to the second fixed resistor, and yet another second terminal is coupled to the third fixed resistor.

[0030] When the switch includes multiple second terminals, the conduction between the second terminal and the third terminal in the above-mentioned switch means that one of the second terminals in the switch is conductive with the third terminal. In this way, one of the first fixed resistor, the second fixed resistor, and the third fixed resistor can be used as the termination resistor of the second connection line segment.

[0031] Through pre-testing, each fixed resistor is used as the termination resistor of the second connection line segment to test which fixed resistor has better signal quality transmitted by the first connection line when it is used as the termination resistor of the second connection line segment, so as to determine the resistance value of the fixed resistor as the target resistance value.

[0032] When the GPU outputs a signal and the CPU is in a high impedance state, the second connection line is a stub line. The switch can conduct one of the second terminals and the third terminal, so that a fixed resistor with a suitable resistance value can be connected to the first connection line through the switch and the second connection line segment as the termination resistor of the stub line, thereby reducing the negative impact of the stub line on the GPU output signal in the transmission link and improving the reliability of the GPU output signal.

[0033] Moreover, since the impedance matcher has multiple fixed resistors, the impedance matcher can match the transmission links of various GPU output signals, improving the adaptability of the impedance matcher.

[0034] It should be noted that the impedance matcher can also be applied to other high-speed signal links including stub lines, such as other suitable links such as the mobile industry processor interface (MIPI) link related to cameras. This application does not limit this.

[0035] In some possible implementation manners of the first aspect, the length of the second connection line segment is less than the length of the first connection line segment.

[0036] The length of the second connection line segment is less than the length of the first connection line segment. By setting the switch close to the GPU, the length of the second connection line segment can be shortened.

[0037] In this way, when the second connection line segment is coupled with the impedance matcher as a stub line, the length of the stub line can be shortened, thereby further reducing the negative impact of the stub line on the signal output by the GPU transmitted on the main signal line of the display interface and improving the signal quality transmitted on the main signal line of the display interface.

[0038] In some possible implementation manners of the first aspect, the first signal outputter includes one of a system-on-chip (SOC) and a microcontroller unit (MCU), and the second signal outputter includes the other of the SOC and the MCU.

[0039] In some possible implementation manners of the first aspect, the junction point of the first connection line and the second connection line is located inside the second signal output device.

[0040] Each group of eDP connection lines may include 4 pairs of main display interface signal lines, 1 pair of auxiliary signal lines, and 1 pair of hot plug detection lines. Among them, the 4 pairs of main display interface signal lines of the first eDP connection line and the 4 pairs of main display interface signal lines 341 of the second eDP connection line can be coupled in one-to-one correspondence; similarly, the 1 pair of auxiliary display interface signal lines of the first eDP connection line can be coupled with the 1 pair of auxiliary display interface signal lines of the second eDP connection line; similarly, the 1 pair of hot plug detection lines of the first eDP connection line can be coupled with the 1 pair of hot plug detection lines of the second eDP connection line.

[0041] Taking the case where a pair of main display interface signal lines in the first eDP connection line are coupled with a pair of main display interface signal lines in the second eDP connection line as an example for illustration. The coupling point of the main display interface signal line in the first eDP connection line and the main display interface signal line in the second eDP connection line is called the junction point.

[0042] In the case where the CPU outputs a signal and the GPU is in a high impedance state, the high-speed signal output by the CPU first transmits from the main display interface signal line in the second eDP connection line to the main display interface signal line in the first eDP connection line, and then transmits from the first eDP connection line to the display screen. In this process, the high-speed signal does not pass through the line segment between the GPU and the junction point, that is, there is a stub line. The stub line will have a negative impact on the transmission signal in the first eDP connection line, reducing the reliability of signal transmission.

[0043] The signal transmission circuit of the present application can set the junction point of the main display interface signal line in the second eDP connection line and the main display interface signal line in the first eDP connection line inside the GPU. Exemplarily, the signal transmission circuit can set the junction point of the main display interface signal line in the second eDP connection line and the main display interface signal line in the second eDP connection line at the solder joint of the main display interface signal line in the first eDP connection line on the GPU.

[0044] In this way, in the case where the CPU outputs a signal and the GPU is in a high impedance state, the stub line in the main display interface signal line in the first eDP connection line can be minimized as much as possible, reducing the negative impact of the stub line on the high-speed signal output by the CPU and improving the reliability of the signal transmission circuit.

[0045] Further, the signal transmission circuit can also set the junction point of the auxiliary signal line in the first eDP connection line and the auxiliary signal line in the second eDP connection line at the solder joint of the auxiliary signal line in the first eDP connection line on the GPU.

[0046] In this way, when the CPU outputs a signal and the GPU is in a high-impedance state, the stub line in the auxiliary signal line in the first eDP connection line can be minimized, the negative impact of the stub line on the signal output by the CPU can be reduced, and the reliability of the signal transmission circuit can be improved.

[0047] Of course, in some other embodiments, the junction point of the auxiliary signal line in the first eDP connection line and the auxiliary signal line in the first eDP connection line may also be outside the GPU, and the present application does not limit this.

[0048] Similarly, the signal transmission circuit can also set the junction point of the hot plug detection line in the first eDP connection line and the hot plug detection line in the second eDP connection line at the solder joint of the hot plug detection line in the first eDP connection line on the GPU.

[0049] In this way, when the CPU outputs a signal and the GPU is in a high-impedance state, the stub line in the hot plug detection line in the first eDP connection line can be minimized, the negative impact of the stub line on the signal output by the CPU can be reduced, and the reliability of the signal transmission circuit can be improved.

[0050] Of course, in some other embodiments, the junction point of the hot plug detection line in the first eDP connection line and the hot plug detection line in the second eDP connection line may also be outside the GPU, and the present application does not limit this.

[0051] In a second aspect, a control method is provided. The control method is applied to the signal transmission circuit according to any one of the first aspect. The control method includes: a first signal outputter outputs a first signal, and the first signal is transmitted to the actuator via a second connection line and at least part of a first connection line. Alternatively, the control method includes: a second signal outputter outputs a second signal, and the second signal is transmitted to the actuator via the first connection line.

[0052] When the electronic device is in a high-performance mode with a high refresh rate requirement for the display screen, the signal transmission circuit is in a second state, the GPU outputs an image data signal (representing the second signal) and the CPU is in a high-impedance state, and the image data signal is transmitted to the display screen via the first eDP connection line.

[0053] When the electronic device is in a low-performance mode with no high refresh rate requirement for the display screen, the signal transmission circuit is in a first state, the CPU outputs an image data signal (representing the first signal) and the GPU is in a high-impedance state, and the image data signal is transmitted to the display screen via the second eDP connection line and at least part of the first eDP connection line.

[0054] Understandably, in the transmission path between the CPU and the display screen, by adding a second eDP connection line with a shorter distance that connects the CPU and the GPU, the CPU can utilize the connection line (the first eDP connection line) between the GPU and the display screen. Compared with the CPU additionally setting a connection line with a longer distance to communicate with the display screen, the wiring quantity of the signal transmission circuit can be reduced.

[0055] In this way, compared with the signal transmission circuit in which the CPU and the GPU are each connected to the display screen through a connection line, on the basis that both can realize the switching between two states of the CPU controlling the display of the display screen and the GPU controlling the display of the display screen, the switching device for switching the CPU signal and the GPU signal can be omitted, and the cost of the signal transmission circuit can be reduced. In addition, since the distance between the CPU and the GPU is closer than the distance between the CPU and the switching device, the total length of the connection lines in the signal transmission circuit provided in this application will be less than the total length of the connection lines in the signal transmission circuit in which the CPU and the GPU are each connected to the display screen through a connection line, and the wiring space of the signal transmission circuit on the circuit board can be reduced.

[0056] In some feasible implementation manners of the second aspect, the second connection line includes a first connection segment, a second connection segment, and a switch. The switch includes a first end, a second end, and a third end. The first connection segment is respectively coupled to the first signal outputter and the first end, and the second connection segment is respectively coupled to the third end and the first connection line. The signal transmission circuit further includes an impedance matcher, and the impedance matcher is coupled to the second end. When the second signal outputter outputs the second signal, the method further includes: the switch couples the third end to the second end and disconnects the third end from the first end.

[0057] When the CPU outputs a signal and the GPU is in a high impedance state, the signal transmission circuit is in the first state, and the switch can conduct the first end and the third end. In this way, the first connection segment and the second connection segment can be connected through the switch, and the signal output by the CPU can be sequentially transmitted to the display screen via the first connection segment, the switch, the second connection segment, and the second connection line.

[0058] When the GPU outputs a signal and the CPU is in a high impedance state, the signal transmission circuit is in the second state, and the switch can conduct the second end and the third end. In this way, the switch can disconnect the first connection segment and the second connection segment, and the signal output by the GPU can be transmitted to the display screen via the main display interface signal line. Among them, the switch and the second connection segment are connected to the main display interface signal line as stub lines.

[0059] The impedance matcher is coupled to the second end of the switch and serves as the termination resistor of the stub line. The impedance matcher can be used to provide a resistor that matches the transmission link of the GPU output signal to the second end of the switch, so as to reduce the negative impact of the stub line on the GPU output signal in the transmission link and improve the reliability of the GPU output signal.

[0060] In some examples, the control end of the switch can be coupled to the CPU. The CPU can control the switch such that the first end is coupled to the third end and the second end is disconnected from the third end, or the CPU can control the switch such that the second end is coupled to the third end and the first end is disconnected from the third end.

[0061] In some other embodiments, the control end of the switch can be coupled to the GPU. The GPU can control the switch such that the second end is coupled to the third end and the first end is disconnected from the third end, or the GPU can control the switch such that the first end is coupled to the third end and the second end is disconnected from the third end.

[0062] In some other embodiments, the signal transmission circuit can further include a logic controller. The logic controller can be coupled to the CPU, the GPU, and the switch respectively. The logic controller can control the switch such that the second end is coupled to the third end and the first end is disconnected from the third end, or control the switch such that the first end is coupled to the third end and the second end is disconnected from the third end by detecting the states of the CPU and the GPU.

[0063] In some feasible implementation manners of the second aspect, the impedance matcher includes a plurality of fixed-value resistors with different resistance values. The switch includes a plurality of second ends, and the plurality of second ends are respectively coupled to the plurality of fixed-value resistors. The switch coupling the third end to the second end includes: the switch coupling the third end to one second end and disconnecting from other second ends, so that one fixed-value resistor is coupled to the second connection segment.

[0064] In some examples, the impedance matcher can include a plurality of fixed-value resistors. The resistance values of the plurality of fixed-value resistors are different from each other. Exemplarily, the impedance matcher can include a first fixed-value resistor, a second fixed-value resistor, and a third fixed-value resistor. The resistance value of the first fixed-value resistor is less than the resistance value of the second fixed-value resistor, and the resistance value of the second fixed-value resistor is less than the resistance value of the third fixed-value resistor.

[0065] Correspondingly, the switch can include a plurality of second ends, and the plurality of second ends are coupled to the plurality of fixed-value resistors in a one-to-one correspondence. Exemplarily, the impedance matcher includes three second ends, one second end is coupled to the first fixed-value resistor, another second end is coupled to the second fixed-value resistor, and yet another second end is coupled to the third fixed-value resistor.

[0066] When the switch includes multiple second terminals, the conduction between the second terminal and the third terminal in the above-mentioned switch means that one of the second terminals in the switch is conducted with the third terminal. In this way, one of the first fixed resistor, the second fixed resistor, and the third fixed resistor can be used as the termination resistor of the second connection line segment.

[0067] Through pre-testing, each fixed resistor is used as the termination resistor of the second connection line segment to test which fixed resistor has better signal quality transmitted by the first connection line when used as the termination resistor of the second connection line segment, so as to determine the resistance value of the fixed resistor as the target resistance value.

[0068] When the GPU outputs a signal and the CPU is in a high impedance state, the second connection line is a stub line. The switch can conduct one of the second terminals and the third terminal, so that a fixed resistor with a suitable resistance value can be connected to the first connection line through the switch and the second connection line segment as the termination resistor of the stub line, thereby reducing the negative impact of the stub line on the GPU output signal in the transmission link and improving the reliability of the GPU output signal.

[0069] Moreover, since the impedance matcher has multiple fixed resistors, the impedance matcher can be enabled to match the transmission links of multiple GPU output signals, enhancing the adaptability of the impedance matcher.

[0070] It should be noted that the impedance matcher can also be applied to other high-speed signal links including stub lines, such as other suitable links such as the MIPI link related to the camera. The present application does not limit this.

[0071] In some feasible implementation manners of the second aspect, when the display screen is at the first refresh rate, the CPU outputs a first signal, and the switch couples the third terminal to the first terminal and disconnects the third terminal from the second terminal. Alternatively, when the display screen is at the second refresh rate, the GPU outputs a second signal, and the switch couples the third terminal to the second terminal and disconnects the third terminal from the first terminal. Wherein, the second refresh rate is greater than the first refresh rate.

[0072] It can be understood that in the high-performance mode where the electronic device has a high refresh rate requirement for the display screen, the signal transmission circuit is in the second state, the GPU outputs an image data signal (representing the second signal) and the CPU is in a high impedance state, and the switch couples the third terminal to the second terminal and disconnects the third terminal from the first terminal, so that the image data signal is transmitted to the display screen via the first eDP connection line.

[0073] At this time, the impedance matcher coupled to the second end of the switch serves as the termination resistor of the stub line. The impedance matcher can be used to provide a resistor that matches the transmission link of the GPU output signal to the second end of the switch, so as to reduce the negative impact of the stub line on the GPU output signal in the transmission link and improve the reliability of the GPU output signal.

[0074] When the electronic device is in a low-performance mode with no high refresh rate requirement for the display screen, the signal transmission circuit is in the first state, the CPU outputs an image data signal (representing the first signal) and the GPU is in a high impedance state, the switch couples the third end to the first end and disconnects the third end from the second end, and the image data signal is transmitted to the display screen via the second eDP connection line and at least part of the first eDP connection line.

[0075] In the transmission path between the CPU and the display screen, by adding a second eDP connection line with a shorter distance that connects the CPU and the GPU, the CPU can utilize the connection line (the first eDP connection line) between the GPU and the display screen. Compared with the CPU additionally setting a connection line with a longer distance to communicate with the display screen, the number of wirings of the signal transmission circuit can be reduced.

[0076] In a third aspect, an electronic device is provided. The electronic device includes: a main board and a signal transmission circuit. The signal transmission circuit is the signal transmission circuit according to any one of the first aspects. The first signal outputter and / or the second signal outputter are located on the main board.

[0077] In some feasible implementation manners of the third aspect, the first signal outputter includes one of a central processing unit CPU and a graphics processing unit GPU, the second signal outputter includes the other of the CPU and the GPU, and the actuator includes a display screen.

[0078] In some feasible implementation manners of the third aspect, the first connection line and the second connection line include an embedded display port connection line. Or, the first connection line and the second connection line include a system power management interface connection line.

[0079] For the technical effects of the third aspect, reference can be made to the technical effects of the first aspect or the second aspect, which will not be elaborated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0080] Figure 1 is a schematic structural diagram of a signal transmission circuit in some embodiments;

[0081] Figure 2 is Figure 1 a specific schematic structural diagram of the signal transmission circuit shown in a PC;

[0082] Figure 3Schematic diagram of the signal transmission circuit provided for some embodiments of the present application;

[0083] Figure 4 For Figure 3 Schematic diagram of signal transmission when the signal transmission circuit shown is in the first state;

[0084] Figure 5 For Figure 3 Schematic diagram of signal transmission when the signal transmission circuit shown is in the second state;

[0085] Figure 6 For Figure 3 Specific schematic diagram of one structure of the signal transmission circuit shown in an electronic device;

[0086] Figure 7 For Figure 6 Connection schematic diagram of a pair of main display interface signal lines in the first connection line and a pair of main display interface signal lines in the second connection line;

[0087] Figure 8 For Figure 3 Specific schematic diagram of another structure of the signal transmission circuit shown in an electronic device;

[0088] Figure 9 For Figure 8 Connection schematic diagram of a pair of main display interface signal lines in the first connection line and a pair of main display interface signal lines in the second connection line;

[0089] Figure 10 For the Figure 9 Signal quality simulation result diagram of the high-speed signal transmitted on a pair of main display interface signal lines in the first connection line;

[0090] Figure 11 Schematic diagram of one structure of a pair of main display interface signal lines in the second connection line;

[0091] Figure 12 Schematic diagram of another structure of a pair of main display interface signal lines in the second connection line;

[0092] Figure 13 For Figure 11 Schematic diagram of one connection relationship of the signal transmission circuit shown;

[0093] Figure 14 For Figure 11 Schematic diagram of another connection relationship of the signal transmission circuit shown;

[0094] Figure 15 For Figure 11 Schematic diagram of yet another connection relationship of the signal transmission circuit shown;

[0095] Figure 16 For Figure 11 Schematic diagram of a connection structure of a medium impedance matcher and a switch;

[0096] Figure 17 For Figure 11 Another schematic diagram of a connection structure of a medium impedance matcher and a switch;

[0097] Figure 18 For Figure 17 Simulation result diagram of the signal quality of the high-speed signals transmitted on a pair of main signal lines of a display interface in the first connection line of ;

[0098] Figure 19 For Figure 11 Another schematic diagram of a connection structure of a medium impedance matcher and a switch;

[0099] Figure 20 For Figure 11 Another schematic diagram of a connection structure of a medium impedance matcher and a switch;

[0100] Figure 21 Another schematic diagram of a pair of main signal lines of a display interface in the second connection line;

[0101] Figure 22 For Figure 11 And Figure 21 Curves of loss versus frequency in two cases;

[0102] Figure 23 For Figure 21 Simulation result diagram of the signal quality of the high-speed signals transmitted on a pair of main signal lines of a display interface in the first connection line of . Specific implementation manner

[0103] Next, the technical solutions in the embodiments of the present application will be described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments provided by the present application, all other embodiments obtained by those of ordinary skill in the art belong to the scope of protection of the present application.

[0104] Hereinafter, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the embodiments of the present application, unless otherwise stated, "a plurality" means two or more.

[0105] In describing some embodiments, the terms "connected", "coupled" and their derivatives may be used. For example, in describing some embodiments, the term "connected" may be used to indicate that two or more components have direct or indirect physical contact with each other. For example, A and B are connected, which may mean that A and B are directly connected, or that A and B are connected through other components. In addition, the term "coupled" may be a way of achieving electrical connection for signal transmission.

[0106] "At least one of A, B, and C" has the same meaning as "at least one of A, B, or C", and both include the following combinations of A, B, and C: only A, only B, only C, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0107] "A and / or B" includes the following three combinations: only A, only B, and the combination of A and B.

[0108] As used herein, "about", "substantially" or "approximately" includes the stated value and the average value within an acceptable deviation range of the specific value, where the acceptable deviation range is determined by those of ordinary skill in the art considering the measurement being discussed and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system).

[0109] Figure 1 The structural schematic diagram of the signal transmission circuit in some embodiments is shown.

[0110] Figure 1 The signal transmission circuit in can be applied to a personal computer (PC). The signal transmission circuit can be entirely located on the same circuit board (such as the motherboard) in the PC, or a part of it can be located on one circuit board and another part on another circuit board, and this application does not make any limitations in this regard.

[0111] The signal transmission circuit may include a central processing unit (CPU), a graphics processing unit (GPU), a multiplexer (MUX), and a display screen.

[0112] Specifically, the CPU can be coupled to the first input terminal In1 of the MUX through the first set of connection lines 01. The GPU can be coupled to the second input terminal In2 of the MUX through the second set of connection lines 02. The output terminal Out of the MUX can be coupled to the timing controller integrated circuit (Tcon IC) of the display screen through the third set of connection lines 03.

[0113] The MUX can include a first state and a second state. In the first state, the MUX can connect its first input terminal In1 and output terminal Out, enabling the first set of connection lines 01 and the third set of connection lines 03 to be interconnected, and the display signal provided by the CPU can be transmitted to the Tcon IC of the display screen. In the second state, the MUX can connect its second input terminal In2 and output terminal Out, enabling the second set of connection lines 02 and the third set of connection lines 03 to be interconnected, and the display signal provided by the GPU can be transmitted to the Tcon IC of the display screen.

[0114] The Tcon IC of the display screen can drive the display panel to perform corresponding image display based on the received image data signal provided by the CPU or GPU.

[0115] Figure 2 For Figure 1 the specific structural schematic diagram of the signal transmission circuit shown in the PC.

[0116] The above three sets of connection lines (01, 02, and 03) can be embedded display port (eDP) connection lines for transmitting image data signals. One set of eDP connection lines can include multiple high-speed signal lines and multiple low-speed signal lines. The high-speed signal lines can include 4 pairs of display interface main signal lines (DP main link, Figure 2 represented by solid black lines in the figure). The low-speed signal lines can include 1 pair of auxiliary signal lines (DP auxiliary, Figure 2 represented by dashed black lines in the figure) and 1 pair of hot plug detection lines (hot plug detection, HPD, Figure 2 represented by dash-dotted black lines in the figure).

[0117] In the architecture of the PC, since the display screen is far from the CPU and GPU, it usually exceeds the requirements of the eDP wiring specification. Therefore, the MUX needs to be integrated with a loss compensation function (redriver), so that the MUX can compensate the signal on the DP main link to ensure that the Tcon IC can correctly receive the transmitted signal.

[0118] In addition, the signal transmission circuit can further include an embedded controller (EC) and a logic control module in addition to the CPU, GPU, MUX, and display screen.

[0119] The logic control module can be coupled to the EC, CPU, GPU, and MUX respectively. Among them, the EC can provide at least one suitable signal such as a pulse width modulation (PWM) signal, an enable (EN) signal, and a backlight (BL) signal to the logic control module. The logic control module can determine whether the PC is currently in a high-performance mode or a low-performance mode based on the output signals of the CPU and GPU, and thus output corresponding connection signals to the MUX. The MUX connects the GPU or CPU to the Tcon IC of the display screen based on the received connection signals.

[0120] In some other examples, the logic control module can also be coupled to the display screen, which is not limited in this application.

[0121] When the PC is in the high-performance mode with a high refresh rate requirement for the display screen (for example, when the PC runs game software), the PC needs to provide a display signal to the display screen by the GPU. Therefore, the logic control module can control the MUX to conduct the connection between the GPU and the Tcon IC of the display screen, so that the display screen can achieve high refresh rate display.

[0122] When the PC is in the low-performance mode without a high refresh rate requirement for the display screen (for example, when the PC runs office software), in order to reduce the product power consumption, the PC needs to provide a display signal to the display screen by the CPU. Therefore, the logic control module can control the MUX to conduct the connection between the CPU and the Tcon IC of the display screen, so that the display screen can achieve low-power display.

[0123] Figure 1 and Figure 2 In the scheme shown, since the signal transmission circuit needs to use the MUX to switch the connection relationship, and the cost of the MUX is relatively high, the cost of the signal transmission circuit is also relatively high. Moreover, the signal transmission circuit depends on the supply of the MUX, and the signal transmission circuit cannot be formed in the case of the MUX out of stock.

[0124] In addition, since each group of eDP connection lines contains multiple signal lines, Figure 1 and Figure 2 the scheme shown includes three groups of eDP connection lines, occupying a large wiring space on the circuit board.

[0125] Based on this, the embodiments of the present application provide a signal transmission circuit, its control method, and an electronic device.

[0126] The electronic device provided by the embodiments of the present application can include, but is not limited to, a PC, a mobile phone, a smart phone, a tablet computer, a smart vehicle device, a navigator, an action camera, a smart home appliance, an artificial intelligence device, a wearable device, or a virtual reality / augmented reality / mixed reality device, etc.

[0127] Embodiments of the present application may be a compatible architecture design for converting any signal transmission line with two or more paths into a single signal transmission line. For ease of understanding, continue to take the example where both the CPU and GPU in a PC can provide image data signals for the display screen. However, it should be noted that the signal transmission circuit provided by the embodiments of the present application is not limited to the scenario where both the CPU and GPU can provide image data signals for the display screen. It can also be applied to the scenario where multiple power management units (PMUs) provide power signals for a functional module through system power management interface (SPMI) connection lines, or the scenario where both the system on chip (SOC) and microcontroller unit (MCU) in a smart phone can provide signals for a functional device, and other suitable scenarios. The embodiments of the present application are not limited thereto.

[0128] Figure 3 The schematic structural diagram of the signal transmission circuit provided by some embodiments of the present application is shown; Figure 4 is Figure 3 the signal transmission schematic diagram of the signal transmission circuit shown in the first state; Figure 5 is Figure 3 the signal transmission schematic diagram of the signal transmission circuit shown in the second state.

[0129] Figure 3 The signal transmission circuit shown includes a CPU (first signal outputter) 310, a GPU (second signal outputter) 320, a first eDP connection line (first connection line) 330, a second eDP connection line (second connection line) 340, and a display screen (actuator) 350.

[0130] The first end of the first eDP connection line 330 is coupled to the GPU, and the second end of the first eDP connection line 330 is coupled to the display screen 350. The first end of the second eDP connection line 340 is coupled to the CPU, and the second end of the second eDP connection line 340 is coupled to the first eDP connection line 330.

[0131] In the low-performance mode where the electronic device has no high refresh rate requirement for the display screen, the signal transmission circuit is in the first state, the CPU outputs an image data signal (first signal) and the GPU is in a high impedance state, and the image data signal is transmitted to the display screen 350 via the second eDP connection line 340 and at least part of the first eDP connection line 330. As Figure 4 shown, Figure 4The connecting lines through which the signal flows are shown in bold, and the transmission direction of the signal is indicated by an arrow.

[0132] When the electronic device is in the high-performance mode with a high refresh rate requirement for the display screen, the signal transmission circuit is in the second state, the GPU outputs an image data signal (the second signal), and the CPU is in a high-impedance state. The image data signal is transmitted to the display screen 350 via the first eDP connecting line 330. As Figure 5 shown, Figure 5 The connecting lines through which the signal flows are shown in bold, and the transmission direction of the signal is indicated by an arrow.

[0133] It can be understood that in the transmission path between the CPU and the display screen, by adding a second eDP connecting line 340 with a shorter distance and connecting the CPU and the GPU, the CPU can utilize the connection line (the first eDP connecting line 340) between the GPU and the display screen. Compared with the CPU additionally setting a connecting line with a longer distance to communicate with the display screen, the wiring quantity of the signal transmission circuit can be reduced.

[0134] In this way, Figures 3 to 5 the signal transmission circuit shown in Figure 1 compared with the signal transmission circuit shown in Figures 3 to 5 on the basis that both can realize the state switching between the two states of the CPU controlling the display of the display screen and the GPU controlling the display of the display screen, the MUX can be omitted, and the cost of the signal transmission circuit can be reduced. In addition, since the distance between the CPU and the GPU is closer than the distance between the CPU and the MUX, therefore Figure 1 the total length of the connecting lines in the signal transmission circuit shown in

[0135] It should be noted that Figures 3 to 5 it is taken as an example that the GPU is coupled to the display screen (the actuator) 350 through the first eDP connecting line (the first connecting line) 330. In some other examples, it can also be that the CPU is connected to the display screen (the actuator) 350 through the first eDP connecting line (the first connecting line) 330, and the GPU is coupled to the first eDP connecting line (the first connecting line) 330 through the second eDP connecting line (the second connecting line) 340. For the sake of easy understanding, it will still be taken as an example that the GPU is coupled to the display screen (the actuator) 350 through the first eDP connecting line (the first connecting line) 330, and the CPU is coupled to the first eDP connecting line (the first connecting line) 330 through the second eDP connecting line (the second connecting line) 340 for description, but it should not be regarded as a limitation to the present application.

[0136] Figure 6 For Figure 3A specific structural schematic diagram of a signal transmission circuit in an electronic device is shown; Figure 7 for Figure 6 A schematic diagram of connecting a pair of display interface main signal lines in the first connecting lines with a pair of display interface main signal lines in the second connecting lines. Figure 8 Shows Figure 3 The signal transmission circuit shown is another specific structural schematic diagram of an electronic device.

[0137] like Figure 6 As shown, exemplarily, the first eDP connection line 330 may include four pairs of display interface main signal lines ( Figure 6 331, 1 pair of auxiliary signal lines (indicated by black solid lines) Figure 6 332 and a pair of hot-swap detection lines (indicated by black dashed lines) Figure 6 Similarly, the second eDP connection line 340 may also include four pairs of display interface main signal lines ( Figure 6 341, 1 pair of auxiliary signal lines (indicated by black solid lines) Figure 6 342 and a pair of hot-swap detection lines (indicated by black dashed lines in the figure) Figure 6 (represented by a black single-point dashed line)343.

[0138] Among them, 4 pairs of display interface main signal lines 331 and 4 pairs of display interface main signal lines 341 can be coupled one by one; similarly, 1 pair of display interface auxiliary signal lines 332 can be coupled with 1 pair of display interface auxiliary signal lines 342; similarly, 1 pair of hot plug detection lines 333 can be coupled with 1 pair of hot plug detection lines 343.

[0139] When the electronic device is in a high-performance mode with a high refresh rate requirement for the display screen, the signal transmission circuit is in a first state, and the high-speed signal output by the GPU is transmitted from the display interface main signal line 331 to the display screen 350; one low-speed signal output by the GPU is transmitted from the auxiliary signal line 332 to the display screen 350; another low-speed signal output by the GPU is transmitted from the hot plug detection line 333 to the display screen 350.

[0140] When the electronic device is in a low-performance mode in which there is no high refresh rate requirement for the display screen, the signal transmission circuit is in the second state, and the high-speed signal output by the GPU is first transmitted from the display interface main signal line 341 to the display interface main signal line 331, and then transmitted from the display interface main signal line 331 to the display screen 350; one low-speed signal output by the GPU is transmitted from the auxiliary signal line 342 to the auxiliary signal line 332, and then transmitted from the auxiliary signal line 332 to the display screen 350; another low-speed signal output by the GPU is transmitted from the hot plug detection line 343 to the hot plug detection line 333, and then transmitted from the hot plug detection line 333 to the display screen 350.

[0141] As Figure 7 shown, a pair of display interface main signal lines 331 is coupled to a pair of display interface main signal lines 341. Among them, the coupling point of the display interface main signal line 331 and the display interface main signal line 341 is called the handover point ( Figure 7 represented by a black dot in

[0142] When the CPU outputs a signal and the GPU is in a high impedance state, the high-speed signal output by the CPU first transmits from the display interface main signal line 341 to the display interface main signal line 331, and then transmits from the display interface main signal line 331 to the display screen 350. In this process, the high-speed signal does not pass through the line segment between the GPU and the handover point ( Figure 7 represented by a double-dotted line in

[0143] However, due to the existence of the stub line, it will cause impedance discontinuity of the high-speed signal at the stub line, resulting in reflection, and thus causing negative impacts such as deterioration of the high-speed signal quality and timing, reducing the integrity and reliability of the high-speed signal transmission. Among them, the longer the length of the stub line, the greater the negative impact on the high-speed signal.

[0144] Therefore, in some embodiments, as Figure 8 shown, the signal transmission circuit can set the handover point of the display interface main signal line 331 and the display interface main signal line 341 inside the GPU. Exemplarily, the signal transmission circuit can set the handover point of the display interface main signal line 331 and the display interface main signal line 341 at the soldering point of the display interface main signal line 331 on the GPU. It can be understood that both the display interface main signal line 331 and the display interface main signal line 341 are coupled to the soldering points inside the GPU.

[0145] In this way, when the CPU outputs a signal and the GPU is in a high impedance state, the stub line in the display interface main signal line 331 can be minimized as much as possible, reducing the negative impact of the stub line on the high-speed signal output by the CPU and improving the reliability of the signal transmission circuit.

[0146] Furthermore, as Figure 8 shown in the signal transmission circuit, the handover point of the auxiliary signal line 332 and the auxiliary signal line 342 can also be set at the soldering point of the auxiliary signal line 332 on the GPU.

[0147] In this way, when the CPU outputs a signal and the GPU is in a high impedance state, the stub line in the auxiliary signal line 332 can be minimized as much as possible, reducing the negative impact of the stub line on the signal output by the CPU and improving the reliability of the signal transmission circuit.

[0148] Of course, in some other embodiments, the junction point of the auxiliary signal line 332 and the auxiliary signal line 342 may also be set outside the GPU, and the present application does not limit this.

[0149] Similarly, for the signal transmission circuit as Figure 8 shown, the junction point of the hot plug detection line 333 and the hot plug detection line 343 may also be set at the soldering point of the hot plug detection line 333 on the GPU.

[0150] In this way, when the CPU outputs a signal and the GPU is in a high impedance state, the stub line in the hot plug detection line 333 can be minimized as much as possible, reducing the negative impact of the stub line on the signal output by the CPU and improving the reliability of the signal transmission circuit.

[0151] Of course, in some other embodiments, the junction point of the hot plug detection line 333 and the hot plug detection line 343 may also be set outside the GPU, and the present application does not limit this.

[0152] Figure 9 For Figure 8 the connection schematic diagram of a pair of display interface main signal lines in the first connection line and a pair of display interface main signal lines in the second connection line; Figure 10 For Figure 9 the signal quality simulation result of the high-speed signal transmitted on a pair of display interface main signal lines in the first connection line.

[0153] When the GPU outputs a signal and the CPU is in a high impedance state, the high-speed signal output by the GPU directly first transmits from the display interface main signal line 331 to the display screen 350. In this process, as Figure 9 shown, the high-speed signal does not pass through the display interface main signal line 341 ( Figure 9 represented by a double dotted line in

[0154] ). At this time, the display interface main signal line 341 is a stub line.

[0155] However, affected by the environmental electromagnetic field, the stub line has a greater negative impact on the high-speed signal, reducing the integrity and reliability of the high-speed signal transmission. Figure 9 In the signal transmission circuit as Figure 10 shown, by performing signal quality modeling and simulation on the high-speed signal output by the GPU transmitted on the display interface main signal line 331 when the GPU outputs a signal and the CPU is in a high impedance state, the simulation result as Figure 10 shown is obtained. It can be seen from Figure 9 that the eye diagram shown in the simulation result is closed, indicating that there is still room for improvement in the signal quality of the high-speed signal transmitted on the display interface main signal line 331 in

[0156] To improve the signal quality of the high-speed signal output by the GPU transmitted on the main signal line 331 of the display interface, embodiments of the present application further improve the second connection line.

[0157] Figure 11 FIG. 4 shows a schematic structural diagram of a pair of main signal lines of the display interface in the second connection line; Figure 12 FIG. 5 shows another schematic structural diagram of a pair of main signal lines of the display interface in the second connection line; Figure 13 is Figure 11 a schematic connection diagram of a connection relationship of the signal transmission circuit shown in FIG. 6; Figure 14 is Figure 11 a schematic connection diagram of another connection relationship of the signal transmission circuit shown in FIG. 7; Figure 15 is Figure 11 a schematic connection diagram of still another connection relationship of the signal transmission circuit shown in FIG. 8.

[0158] In some embodiments, as shown in FIGS. 9 and 10, the main signal line 341 of the display interface may include a first connection segment L1, a second connection segment L2, and a switch SW. Among them, the switch SW is connected in series between the first connection segment L1 and the second connection segment L2. Figure 11 and Figure 12 The switch SW may include a first terminal D1, a second terminal D2, and a third terminal D3. When the signal transmission circuit is in the first state, the switch SW can conduct between the first terminal D1 and the third terminal D3 and disconnect between the second terminal D2 and the third terminal D3; when the signal transmission circuit is in the second state, the switch SW can conduct between the second terminal D2 and the third terminal D3 and disconnect between the first terminal D1 and the third terminal D3.

[0159] The first connection segment L1 can be respectively coupled to the first terminal D1 of the switch SW and the CPU. The second connection segment L2 can be respectively coupled to the third terminal D3 of the switch SW and the second eDP connection line. When the first terminal D1 and the third terminal D3 are conducting, the first connection segment L1 and the second connection segment L2 are interconnected.

[0160] The first connection segment L1 can be respectively coupled to the first terminal D1 of the switch SW and the CPU. The second connection segment L2 can be respectively coupled to the third terminal D3 of the switch SW and the second eDP connection line. When the first terminal D1 and the third terminal D3 are conducting, the first connection segment L1 and the second connection segment L2 are interconnected.

[0161] As Figure 11 and Figure 12 shown, the signal transmission circuit may further include an impedance matcher RZ. The impedance matcher RZ can be coupled to the second terminal D2.

[0162] When the CPU outputs a signal and the GPU is in a high-impedance state, the signal transmission circuit is in the first state, as shown in FIG. 11. Figure 11The switch SW shown can conduct the first terminal D1 and the third terminal D3. In this way, the first connection line segment L1 and the second connection line segment L2 can be connected through the switch SW, and the signal output by the CPU can be transmitted to the display screen 350 successively via the first connection line segment L1, the switch SW, the second connection line segment L2, and the main display interface signal line 331.

[0163] When the GPU outputs a signal and the CPU is in a high-impedance state, the signal transmission circuit is in the second state, as Figure 12 shown, the switch SW can conduct the second terminal D2 and the third terminal D3. In this way, the switch SW can disconnect the first connection line segment L1 and the second connection line segment L2, and the signal output by the GPU can be transmitted to the display screen 350 via the main display interface signal line 331. Among them, the switch SW and the second connection line segment L2 are connected to the main display interface signal line 331 as stub lines.

[0164] The impedance matcher RZ is coupled to the second terminal D2 of the switch SW and serves as the termination resistor of the stub line. The impedance matcher RZ can be used to provide a resistor that matches the transmission link of the GPU output signal to the second terminal D2 of the switch SW, so as to reduce the negative impact of the stub line on the GPU output signal in the transmission link and improve the reliability of the GPU output signal.

[0165] As Figure 13 shown, in some embodiments, the switch SW further includes a control terminal D4. The control terminal D4 of the switch SW can be coupled to the CPU. The CPU can control the first terminal D1 of the switch SW to be coupled to the third terminal D3 and the second terminal D2 to be disconnected from the third terminal D3, or the CPU can control the second terminal D2 of the switch SW to be coupled to the third terminal D3 and the first terminal D1 to be disconnected from the third terminal D3.

[0166] When the CPU outputs a signal and the GPU is in a high-impedance state, the CPU can control the first terminal D1 of the switch SW to be coupled to the third terminal D3 and the second terminal D2 to be disconnected from the third terminal D3. In this way, the first connection line segment L1 and the second connection line segment L2 are connected, and the signal output by the CPU can be transmitted to the display screen 350 successively via the first connection line segment L1, the switch SW, the second connection line segment L2, and the main display interface signal line 331.

[0167] When the GPU outputs a signal and the CPU is in a high-impedance state, the CPU can control the second terminal D2 of the switch SW to be coupled to the third terminal D3 and the first terminal D1 to be disconnected from the third terminal D3. In this way, the signal output by the GPU can be transmitted to the display screen 350 via the main display interface signal line 331. The impedance matcher RZ serves as the termination resistor of the stub line and can reduce the negative impact of the stub line on the GPU output signal in the transmission link and improve the reliability of the GPU output signal.

[0168] As Figure 14 shown, in some other embodiments, the control terminal D4 of the switch SW can be coupled to the GPU. The GPU can control the second terminal D2 and the third terminal D3 of the switch SW to be coupled and the first terminal D1 and the third terminal D3 to be disconnected, or the GPU can control the first terminal D1 and the third terminal D3 of the switch SW to be coupled and the second terminal D2 and the third terminal D3 to be disconnected.

[0169] In the case where the GPU outputs a signal and the CPU is in a high-impedance state, the GPU can control the second terminal D2 and the third terminal D3 of the switch SW to be coupled and the first terminal D1 and the third terminal D3 to be disconnected. In this way, the signal output by the GPU can be transmitted to the display screen 350 via the main display interface signal line 331. Moreover, the impedance matcher RZ, as the termination resistor of the stub line, can reduce the negative impact of the stub line on the signal output by the GPU in the transmission link and improve the reliability of the signal output by the GPU.

[0170] In the case where the CPU outputs a signal and the GPU is in a high-impedance state, the GPU can control the first terminal D1 and the third terminal D3 of the switch SW to be coupled and the second terminal D2 and the third terminal D3 to be disconnected, so that the first connection line segment L1 and the second connection line segment L2 are connected, and the signal output by the CPU can be sequentially transmitted to the display screen 350 via the first connection line segment L1, the switch SW, the second connection line segment L2, and the main display interface signal line 331.

[0171] As Figure 15 shown, in some other embodiments, the signal transmission circuit can further include a logic controller 360. The logic controller 360 can be respectively coupled to the CPU, the GPU, and the control terminal D4 of the switch SW. The logic controller 360 can control the second terminal D2 and the third terminal D3 of the switch SW to be coupled and the first terminal D1 and the third terminal D3 to be disconnected, or control the first terminal D1 and the third terminal D3 of the switch SW to be coupled and the second terminal D2 and the third terminal D3 to be disconnected by detecting the states of the CPU and the GPU.

[0172] The logic controller 360 can, when detecting that the CPU outputs a signal and the GPU is in a high-impedance state, control the first terminal D1 and the third terminal D3 of the switch SW to be coupled and the second terminal D2 and the third terminal D3 to be disconnected, so that the first connection line segment L1 and the second connection line segment L2 are connected, and the signal output by the CPU can be sequentially transmitted to the display screen 350 via the first connection line segment L1, the switch SW, the second connection line segment L2, and the main display interface signal line 331.

[0173] When the logic controller 360 detects the GPU output signal and the CPU is in a high-impedance state, the logic controller 360 can control the switch SW to couple the second terminal D2 to the third terminal D3 and disconnect the first terminal D1 from the third terminal D3. In this way, the signal output by the GPU can be transmitted to the display screen 350 via the main display interface signal line 331. Moreover, as the termination resistor of the stub line, the impedance matcher RZ can reduce the negative impact of the stub line on the GPU output signal in the transmission link and improve the reliability of the GPU output signal.

[0174] The specific structure of the impedance matcher RZ will be described in detail below.

[0175] Figure 16 For Figure 11 a schematic diagram of a connection structure between the impedance matcher and the switch; Figure 17 For Figure 11 another schematic diagram of a connection structure between the impedance matcher and the switch; Figure 18 For Figure 17 the signal quality simulation results of the high-speed signals transmitted on a pair of main display interface signal lines in the first connection line of

[0176] In some examples, as Figure 16 shown, the impedance matcher RZ can include a fixed resistor (such as R1). Since the resistance value of the resistor provided by the impedance matcher RZ can depend on the transmission link of the GPU output signal, different resistance values can be pre-tested for the transmission link of the GPU output signal to determine the target resistance value matching this link, and then the fixed resistor with this target resistance value can be coupled to the second terminal D2.

[0177] In this way, when the GPU outputs a signal and the CPU is in a high-impedance state, the main display interface signal line 341 is a stub line. The switch SW can conduct the second terminal D2 and the third terminal D3, so that the fixed resistor can be connected to the main display interface signal line 331 through the switch SW and the second connection segment L2 as the termination resistor of the stub line, thereby reducing the negative impact of the stub line on the GPU output signal in the transmission link and improving the reliability of the GPU output signal.

[0178] In other examples, the impedance matcher RZ can include a variable resistor. The variable resistor can flexibly adjust the resistance value it outputs. In each case where the second terminal D2 is coupled to the third terminal D3, the variable resistor can traverse each resistance value, and the electronic device can detect the impact of the stub line on the transmission link of the GPU output signal when the variable resistor is at each resistance value, so as to determine the target resistance value matching this link and set the variable resistor to this target resistance value.

[0179] In this way, when the GPU outputs a signal and the CPU is in a high-impedance state, the first connection line segment L1 is a stub line. The switch SW can conduct the second terminal D2 and the third terminal D3, so that the variable resistor can be connected to the main signal line 331 of the display interface through the switch SW and the second connection line segment L2, thereby reducing the negative impact of the stub line on the GPU output signal in the transmission link and improving the reliability of the GPU output signal.

[0180] In some other examples, as Figure 17 shown, the impedance matcher RZ may include a plurality of fixed resistors. The resistance values of the plurality of fixed resistors may be different from each other. Exemplarily, the impedance matcher RZ may include a first fixed resistor R1, a second fixed resistor R2, and a third fixed resistor R3. The resistance value of the first fixed resistor R1 is less than the resistance value of the second fixed resistor R2, and the resistance value of the second fixed resistor R2 is less than the resistance value of the third fixed resistor R3.

[0181] Correspondingly, the switch SW may include a plurality of second terminals D2, and the plurality of second terminals D2 are respectively coupled to the plurality of fixed resistors. Exemplarily, the impedance matcher RZ includes three second terminals D2 (D21, D22, and D23), one second terminal D21 is coupled to the first fixed resistor R1, another second terminal D22 is coupled to the second fixed resistor R2, and yet another second terminal D23 is coupled to the third fixed resistor R3.

[0182] When the switch SW includes a plurality of second terminals D2, the conduction of the second terminal D2 and the third terminal D3 in the above switch SW means that one second terminal D2 (for example, one of the second terminals D21, D22, and D23) in the switch SW is conducted with the third terminal D3. In this way, Figure 9 one of the first fixed resistor R1, the second fixed resistor R2, and the third fixed resistor R3 can be used as the termination resistor of the second connection line segment L2.

[0183] Exemplarily, Table 1 shows the signal quality of the GPU output received by the TconIC when the main signal line 341 of the display interface is used as a stub line and different fixed resistors with different resistance values are used as the termination resistors of the stub line in the scenario where the GPU outputs a signal and the CPU is in a high-impedance state.

[0184]

[0185] Table 1

[0186] Among them, Quality 2 is better than Quality 1, Quality 3, and Quality 4. Therefore, the resistance value of 25 Ω of the first fixed-value resistor R1 can be used as the target termination resistance value of the stub line. Subsequently, in the scenario where the GPU outputs a signal and the CPU is in a high-impedance state, the first fixed-value resistor R1 can be used as the termination resistor of the stub line.

[0187] In the scenario where the GPU outputs a signal and the CPU is in a high-impedance state, when the main signal line 341 of the display interface is used as the stub line and the end of the stub line is coupled to the 25-Ω first fixed-value resistor R1, a signal quality modeling and simulation of the high-speed signal output by the GPU transmitted on the main signal line 331 of the display interface is performed, and the simulation results are obtained as Figure 18 shown. It can be seen from Figure 18 that the eye diagram shown in the simulation results is open, indicating Figure 17 that the signal quality of the high-speed signal transmitted on the main signal line 331 of the display interface in the corresponding signal transmission circuit is better.

[0188] Table 2 shows that in the scenario where the GPU outputs a signal and the CPU is in a high-impedance state, taking the signal transmission rate of 5.4 Gbps / s under the high bandwidth random access memory (HBR) 2 as an example, for Figure 10 the eye diagram of the corresponding stub line without a termination resistor, and Figure 18 the specific data of the eye diagram of the corresponding stub line with the 25-Ω first fixed-value resistor R1 set as the termination resistor.

[0189] Signal output terminal Termination resistance of the stub Signal transmission rate Eye diagram range Eye height GPU / 5.4 Gbps / s ±35 mV 0 mV GPU 25 Ω 5.4 Gbps / s ±35 mV 38 mV

[0190] Table 2

[0191] As can be seen from Table 2, when a 25-Ω resistor is connected to the end of the stub line, the signal quality improvement effect of the high-speed signal transmitted on the main signal line 331 of the display interface is obvious, and the eye height is increased from 0 mV to 38 mV.

[0192] In summary, in the case where the GPU outputs a signal and the CPU is in a high-impedance state, the main signal line 341 of the display interface is the stub line. The switch SW can conduct a second terminal D2 and a third terminal D3, so that a fixed-value resistor with an appropriate resistance value can be connected to the main signal line 331 of the display interface through the switch SW and the second connection line segment L2 as the termination resistor of the stub line, thereby reducing the negative impact of the stub line on the GPU output signal in the transmission link and improving the reliability of the GPU output signal.

[0193] Moreover, since the impedance matcher RZ includes multiple fixed resistors, the impedance matcher RZ can match the transmission links of multiple GPU output signals, improving the adaptability of the impedance matcher RZ.

[0194] It should be noted that the impedance matcher RZ can also be applied to other high-speed signal links including stub lines, such as other suitable links like the mobile industry processor interface (MIPI) link related to a camera, etc. This application does not limit this.

[0195] The specific structure of the switch SW will be described in detail below. For ease of understanding, the structure of the switch SW is described below by taking the impedance matcher RZ including multiple fixed resistors as an example.

[0196] Figure 19 For Figure 11 Another schematic diagram of the connection structure between the impedance matcher and the switch; Figure 20 For Figure 11 Another schematic diagram of the connection structure between the impedance matcher and the switch.

[0197] In some examples, as Figure 19 shown, when the switch SW includes multiple second terminals D2 (D21, D22, and D23), the switch SW can include multiple transistors, and each transistor is connected in series between a second terminal D2 (for example, one of the second terminals D21, D22, and D23) and the third terminal D3. One of the multiple transistors is in the on state and the other transistors are in the off state. Herein, the transistor is connected in series between the second terminal D2 and the third terminal D3, which means that the first pole of the transistor is coupled to the second terminal D2 and the second pole of the transistor is coupled to the third terminal D3. The control pole of the transistor can be coupled to the control terminal of the switch SW. Exemplarily, the control pole of the transistor can be coupled to a CPU, a GPU, or a logic controller.

[0198] For example, the switch SW includes a first transistor T1, a second transistor T2, and a third transistor T3. The first transistor T1 is connected in series between the second terminal D21 coupled to the first fixed resistor R1 and the third terminal D3, the second transistor T2 is connected in series between the second terminal D22 coupled to the second fixed resistor R2 and the third terminal D3, and the third transistor T3 is connected in series between the second terminal D23 coupled to the third fixed resistor R3 and the third terminal D3.

[0199] When the first transistor T1 is in the conducting state, the second transistor T2 and the third transistor T3 are both in the cut-off state. At this time, the first fixed resistor R1 is coupled to the second connection line segment L2 as the termination resistor of the stub line, reducing the negative impact of the stub line on the GPU output signal on the transmission link and improving the reliability of the GPU output signal;

[0200] Alternatively, when the second transistor T2 is in the conducting state, the first transistor T1 and the third transistor T3 are both in the cut-off state. At this time, the second fixed resistor R2 is coupled to the second connection line segment L2 as the termination resistor of the stub line, reducing the negative impact of the stub line on the GPU output signal on the transmission link and improving the reliability of the GPU output signal;

[0201] Alternatively, when the third transistor T3 is in the conducting state, the first transistor T1 and the second transistor T2 are both in the cut-off state. At this time, the third fixed resistor R3 is coupled to the second connection line segment L2 as the termination resistor of the stub line, reducing the negative impact of the stub line on the GPU output signal on the transmission link and improving the reliability of the GPU output signal.

[0202] It should be noted that the transistors provided in the embodiments of the present application can be thin-film transistors, field-effect transistors or other switching devices with the same characteristics. The transistors in the present application can be enhancement-mode transistors or depletion-mode transistors. The present application does not limit this.

[0203] The control electrode of each transistor is the gate of the transistor, the first electrode is one of the source and drain of the transistor, and the second electrode is the other of the source and drain of the transistor. Since the source and drain of the transistor can be symmetric in structure, there can be no difference in their source and drain in structure. That is to say, the first and second electrodes of the transistors in the embodiments of the present disclosure can be without difference in structure. Exemplarily, when the transistor is a P-type transistor, the first electrode of the transistor is the source and the second electrode is the drain; Exemplarily, when the transistor is an N-type transistor, the first electrode of the transistor is the drain and the second electrode is the source.

[0204] By making one transistor in the conducting state and other transistors in the cut-off state, different fixed resistors (such as one of the first fixed resistor R1, the second fixed resistor R2, and the third fixed resistor R3) can be used as the termination resistor of the second connection line segment L2. In this way, a fixed resistor with a suitable resistance value can be connected to the main signal line 331 of the display interface through the switch SW and the second connection line segment L2, thereby reducing the negative impact of the stub line on the GPU output signal on the transmission link and improving the reliability of the GPU output signal.

[0205] Further, asFigure 19 As shown, a transistor may also be connected in series between the first terminal D1 and the third terminal D3 of the switch SW. For example, the switch SW further includes a fourth transistor T4, and the fourth transistor T4 is connected in series between the first terminal D1 and the third terminal D3.

[0206] Among the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4, one transistor is in the on state and the other transistors are in the off state.

[0207] As Figure 20 shown, when the switch SW includes multiple second terminals D2, the switch SW may include a single-pole multi-throw high-speed switch. The stationary terminal of the high-speed switch is coupled to the third terminal D3 of the switch SW, and the movable terminal of the high-speed switch is coupled to one of the second terminals D2 of the switch SW and disconnected from the other second terminals D2.

[0208] By coupling the movable terminal of the high-speed switch to different third terminals D3 of the switch SW, it is possible to use different fixed resistors (such as one of the first fixed resistor R1, the second fixed resistor R2, and the third fixed resistor R3) as the termination resistor of the second connection line segment L2. In this way, a fixed resistor with an appropriate resistance value can be connected to the display interface main signal line 331 through the switch SW and the second connection line segment L2, thereby reducing the negative impact of the stub line on the GPU output signal in the transmission link and improving the reliability of the GPU output signal.

[0209] Furthermore, the movable terminal of the high-speed switch is also coupled to the first terminal D1 of the switch SW. In this way, on the basis of selecting one of the multiple second terminals D2 to be coupled to the third terminal D3 by the high-speed switch, it is also possible to use the high-speed switch to select the first terminal D1 or a second terminal D2 to be coupled to the third terminal D3.

[0210] Of course, the switch SW may further include other functional devices similar to the high-speed switch, such as a multi-channel tuner and other suitable devices. This application only takes the high-speed switch as an example for illustration, but it is not a limitation on the switch SW.

[0211] Figure 21 shows another schematic structural diagram of a pair of display interface main signal lines in the second connection line; Figure 22 shows Figure 11 and Figure 21 two cases of the loss-frequency curve graph; Figure 23 is the signal quality simulation result of the high-speed signal transmitted on a pair of display interface main signal lines in the first connection line of Figure 21 .

[0212] Figure 21 AndFigure 11 The difference is that the length of the second connection line segment L2 is less than the length of the first connection line segment L1. Setting the switch SW closer to the GPU shortens the length of the second connection line segment L2.

[0213] In this way, when the second connection line segment L2 is coupled to the impedance matcher RZ as a stub line, the length of the stub line can be shortened, thereby further reducing the negative impact of the stub line on the signal output by the GPU transmitted on the main signal line 331 of the display interface and improving the signal quality of the signal transmitted on the main signal line 331 of the display interface.

[0214] In the embodiments of the present application, it is verified that when the length of the second connection line segment L2 is less than the length of the first connection line segment L1, the signal quality of the signal transmitted on the main signal line 331 of the display interface is better than that when the length of the second connection line segment L2 is greater than the length of the first connection line segment L1. Exemplarily, the verification process includes two parts: passive loss verification and active signal verification.

[0215] I. Passive loss verification: The test device respectively extracts the S parameters (used to evaluate the performance of the reflected signal and the transmitted signal on the link) on the main signal line 331 of the display interface in two cases: when the switch SW is set close to the CPU (i.e., the length of the second connection line segment L2 is greater than the length of the first connection line segment L1) and when the switch SW is set close to the GPU (i.e., the length of the second connection line segment L2 is less than the length of the first connection line segment L1), and obtains the losses of the link in the two cases as shown in Figure 22 Taking the working frequency of the signal transmitted on the link as 2.7 GHz as an example, in the case where the switch SW is set close to the CPU, the link loss corresponding to curve 1 in Figure 22 is -9.21 dB; in the case where the switch SW is set close to the GPU, the link loss corresponding to curve 2 in Figure 22 is -6.79 dB. Therefore, it can be found that in the case where the switch SW is set close to the GPU compared with the case where the switch SW is set close to the CPU, when the working frequency of the signal transmitted on the link is 2.7 GHz, the link loss on the main signal line 331 of the display interface can be improved by about 2.4 dB.

[0216] II. Active signal verification: On the premise that the termination resistors are all 25 Ω, for the case where the switch SW is set close to the GPU (i.e., the length of the second connection line segment L2 is less than the length of the first connection line segment L1), a signal quality modeling and simulation of the high-speed signal output by the GPU transmitted on the main signal line 331 of the display interface is performed, and the simulation results as shown in Figure 23 are obtained, where Figure 23 represents that the eye height of the high-speed signal transmitted on the main signal line 331 of the display interface is 45 mV.

[0217] Table 3 shows that in the scenario where the GPU outputs a signal and the CPU is in a high-impedance state, taking the signal transmission rate of 5.4 Gbps / s as an example, for Figure 10 the eye diagram of the corresponding stub line without terminating resistors, Figure 18 the eye diagram of the corresponding stub line with a first fixed-value resistor R1 of 25 Ω set as the terminating resistor, and Figure 23 the specific data of the eye diagram of the corresponding stub line with a first fixed-value resistor R1 of 25 Ω set as the terminating resistor.

[0218] Signal output terminal Termination resistance of the stub Signal transmission rate Eye diagram range Eye height GPU / 5.4 Gbps / s ±35 mV 0 mV GPU 25 Ω 5.4 Gbps / s ±35 mV 38 mV GPU 25 Ω 5.4 Gbps / s ±35 mV 45 mV

[0219] Table 3

[0220] It can be found from Table 3 that when the stub line is coupled with the same terminating resistor and the main signal line 331 of the display interface transmits the same signal transmission rate, the case where the switch SW is set closer to the GPU can improve the eye height by 7 mV compared with the case where the switch SW is set closer to the CPU. It can be understood that the case where the switch SW is set closer to the GPU has a smaller negative impact on the signal transmitted by the main signal line 331 of the display interface compared with the case where the switch SW is set closer to the CPU, and can improve the reliability of the signal transmission circuit.

[0221] It can be understood that the case where the length of the second connection segment L2 in the signal transmission circuit is less than the length of the first connection segment L1 has a smaller negative impact on the signal transmitted by the main signal line 331 of the display interface compared with the case where the length of the second connection segment L2 in the signal transmission circuit is greater than the length of the first connection segment L1, and can improve the reliability of the signal transmission circuit.

[0222] The above is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions within the technical scope disclosed in the present application should be covered by the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A signal transmission circuit, characterized in that, The signal transmission circuit is applied to an electronic device; the signal transmission circuit includes a first signal outputter, a second signal outputter, a first connection line, a second connection line, and an actuator, and the first signal outputter is different from the second signal outputter; The first connection line is respectively coupled to the second signal outputter and the actuator; the second connection line is respectively coupled to the first signal outputter and the first connection line; When the signal transmission circuit is in a first state, the second signal outputter is in a high impedance state, and a first signal output by the first signal outputter is transmitted to the actuator via the second connection line and at least part of the first connection line, so that the actuator meets the first performance requirement of the electronic device; When the signal transmission circuit is in a second state, the first signal outputter is in a high impedance state, and a second signal output by the second signal outputter is transmitted to the actuator via the first connection line, so that the actuator meets the second performance requirement of the electronic device; Wherein, the second connection line includes a first connection segment, a second connection segment, and a switch; the switch includes a first end, a second end, and a third end, the first connection segment is respectively coupled to the first signal outputter and the first end, and the second connection segment is respectively coupled to the third end and the first connection line; The signal transmission circuit further includes an impedance matcher; the impedance matcher is coupled to the second end; When the signal transmission circuit is in the first state, the third end is connected to the first end and the third end is disconnected from the second end; when the signal transmission circuit is in the second state, the third end is connected to the second end and the third end is disconnected from the first end.

2. The signal transmission circuit according to claim 1, wherein The impedance matcher includes a variable resistor or a fixed resistor.

3. The signal transmission circuit according to claim 1, characterized in that The impedance matcher includes a plurality of fixed resistors with different resistance values; the switch includes a plurality of second ends, and the plurality of second ends are respectively coupled to the plurality of fixed resistors; The connection of the third end to the second end includes that the third end is coupled to one of the second ends and disconnected from the other second ends.

4. The signal transmission circuit according to any one of claims 1-3, characterized in that The length of the second connection segment is less than the length of the first connection segment.

5. The signal transmission circuit according to any one of claims 1 to 3, characterized in that The first signal outputter includes one of a system-on-chip (SOC) and a microcontroller unit (MCU), and the second signal outputter includes the other of the SOC and the MCU.

6. The signal transmission circuit according to any one of claims 1-3, characterized in that, The first signal outputter includes one of a central processing unit (CPU) and a graphics processing unit (GPU), the second signal outputter includes the other of the CPU and the GPU, and the actuator includes a display screen.

7. The signal transmission circuit according to any one of claims 1 to 3, characterized in that, The intersection point of the first connection line and the second connection line is located inside the second signal outputter.

8. A control method, characterized in that, Applied to the signal transmission circuit according to any one of claims 1-7; the method includes: The first signal outputter outputs a first signal, and the first signal is transmitted to the actuator via the second connection line and at least part of the first connection line; or, The second signal outputter outputs a second signal, and the second signal is transmitted to the actuator via the first connection line.

9. The method according to claim 8, wherein The second connection line includes a first connection segment, a second connection segment, and a switch; the switch includes a first end, a second end, and a third end. The first connection segment is respectively coupled to the first signal outputter and the first end, and the second connection segment is respectively coupled to the third end and the first connection line. The signal transmission circuit further includes an impedance matcher; the impedance matcher is coupled to the second end. When the second signal outputter outputs a second signal, the method further includes: The switch couples the third end to the second end and disconnects the third end from the first end.

10. The method according to claim 9, wherein The impedance matcher includes a plurality of fixed resistors with different resistance values; the switch includes a plurality of second ends, and the plurality of second ends are respectively coupled to the plurality of fixed resistors. The switch coupling the third end to the second end includes: The switch couples the third end to one of the second ends and disconnects it from the other second ends, so that one fixed resistor is coupled to the second connection segment.

11. The method according to claim 9, characterized in that, The first signal outputter includes a CPU, the second signal outputter includes a GPU, and the actuator includes a display screen. The method includes: When the display screen is at a first refresh rate, the CPU outputs a first signal, and the switch couples the third end to the first end and disconnects the third end from the second end; or, When the display screen is at a second refresh rate, the GPU outputs a second signal, and the switch couples the third end to the second end and disconnects the third end from the first end; wherein, the second refresh rate is greater than the first refresh rate.

12. An electronic device, characterized in that, including: a main board; The signal transmission circuit according to any one of claims 1-7; the first signal outputter and / or the second signal outputter are / is located on the main board.

13. The electronic device according to claim 12, wherein The first connection line and the second connection line include an embedded display port connection line; or, The first connection line and the second connection line include a system power management interface connection line.

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