A method and device for sharing data cache of communication modules based on multi-entry FIFO

Abstract

The present invention relates to a method and device for sharing data cache of a communication module based on multi-entry FIFO, the method comprising: obtaining a current application scenario and an application program running therein, determining FIFO configuration information according to the application scenario, and sending the FIFO configuration information to a FIFO configuration module to configure a shared FIFO; when the application program needs to send / receive data, a write / read operation is performed through the shared FIFO. The present invention optimizes the on-chip resources of the shared data cache of the communication module with multi-entry FIFO based on the application scenario, fully utilizes the on-chip communication resources, and improves the efficiency of sending and receiving.

Description

Technical Field

[0001] The present invention belongs to the technical field of chip communication modules, and in particular, relates to a communication module shared data cache method and device based on multi-entry FIFO. Background Art

[0002] With the development of microelectronics technology, more and more functions and modules are integrated into a single chip. Among them, communication modules are a very common and widely used type. In common system architectures, communication bus protocol modules such as UART, SPI, I2C, CAN, etc. are connected to the system through the bus to realize various signal transmissions. Communication resources are important on-chip hardware resources. Communication modules generally have built-in TX / RX FIFOs and transceivers to realize the sending and receiving of different protocol data; however, the TX / RX FIFO size of a certain communication module is fixed when the chip is designed, but in actual applications, there may be too many or too few FIFOs; in addition, multiple different types of communication modules are integrated in the chip, but some communication modules are not needed in actual applications, which leads to idle waste of these communication modules; in addition, in automotive applications, in order to improve the functional safety requirements of communication, usually two or more FIFO caches are fixed in a single communication module for redundancy verification. Because of the increase in cache, additional hardware overhead occurs. In the prior art, the total FIFO size of the communication modules in the system is expanded by sharing FIFO to meet the needs of different applications; however, the shared FIFO can only provide cache for multiple communication modules by time division multiplexing, resulting in the inability of multiple communication modules to work in parallel; once the size of the shared sending FIFO and receiving FIFO provided in the prior art is set, it cannot be modified, which actually results in a large waste of hardware resources; based on the above problems, the present invention finds that the usage degree and busyness of different bus protocol modules in different application scenarios are different, and optimizes the use of on-chip resources in the communication module based on the application scenarios, makes full use of on-chip communication resources, transparently provides redundant checking for security applications, reduces hardware overhead and chip size, and provides transparent security. Summary of the invention

[0003] In order to solve the above problems in the prior art, the present invention proposes a communication module shared data cache method and system based on multi-entry FIFO, the system comprising:

[0004] Shared FIFO, shared decision module, multiple communication modules, multiple sending interfaces and multiple receiving interfaces;

[0005] The shared decision module is used to determine FIFO configuration information according to the application scenario, and send the FIFO configuration information to the FIFO configuration module to configure the transceiver FIFO; specifically: the shared decision module obtains the receiving and sending requirements of each application in the current application scenario; determines the total transceiver requirement based on the receiving and sending requirements of each application; allocates the FIFO space size of the shared FIFO to each application, so that the allocated FIFO space size meets the total transceiver requirement of the application; divides the address of the transceiver FIFO according to the FIFO space size to form a plurality of address ranges; each address range corresponds to a sub-transceiver FIFO; allocates the address space of the shared FIFO in sequence based on the address range, and uses the formed address division information as the FIFO configuration information; wherein: the FIFO configuration information contains the address division information of each sub-transceiver FIFO;

[0006] The sharing decision module is further used to generate a bus mapping signal based on the address division information, and the bus selector receives the bus mapping signal and logically divides the system bus into multiple communication buses, so that each of the multiple communication buses corresponds to a communication device and its corresponding sub-transceiver FIFO;

[0007] The shared FIFO includes: a FIFO configuration module, a bus selector and a transceiver FIFO, a front-end selector and a back-end selector;

[0008] The FIFO configuration module is used to configure the address division of the transceiver FIFO according to the FIFO configuration information, so that each address range corresponds to a sub-transceiver FIFO;

[0009] The bus selector is arranged between the system bus and the transceiver FIFO; it is used to route the system bus data into multi-channel communication bus data and connect them to each communication module or its corresponding sub-transceiver FIFO respectively based on the bus mapping signal sent by the sharing decision module and the shared FIFO configured by the bus configuration information;

[0010] The transceiver FIFO is divided into multiple sub-transceiver FIFOs according to the address division information. Each sub-transceiver FIFO corresponds to a communication module and is used for both receiving data buffering and sending data buffering. A front-end selector is set at the write interface of each sub-transceiver FIFO, and a back-end selector is set at the read interface.

[0011] The front-end selector is a selector for writing to the transceiver FIFO, and the two inputs of the front-end selector are the corresponding communication bus data and the corresponding receiving device; the back-end selector is a selector for reading the transceiver FIFO, and the two outputs of the back-end selector are the corresponding communication bus data and the corresponding sending device;

[0012] Each of the multiple communication modules is respectively connected to one or more communication bus protocol modules for data communication; specifically: each communication module corresponds to a sending interface and a receiving interface, and is connected to the communication bus protocol module through the sending interface and the receiving interface.

[0013] Furthermore, the sharing decision module is set in the operating system space.

[0014] Furthermore, each application program in the application scenario runs on a core in the multi-core chip.

[0015] Furthermore, the application scenario is an in-vehicle application scenario.

[0016] Furthermore, the multi-entry FIFO includes 4 groups of entry and exit.

[0017] Furthermore, there are four communication modules to support four different types of communication bus protocol modules.

[0018] Furthermore, when there is an application program in the application scenario and its total receiving and sending demand is 0, the address range of the shared FIFO is not allocated to the application program.

[0019] A chip comprises the communication module shared data cache system based on multi-entry FIFO.

[0020] A communication module shared data cache method based on multiple entry FIFOs, the method is applied to the communication module shared data cache system based on multiple entry FIFOs; comprising: configuring the shared FIFO based on FIFO configuration information before the application needs to send data.

[0021] A server is provided with the communication module shared data cache system based on multi-entry FIFO.

[0022] The beneficial effects of the present invention include:

[0023] (1) Starting from the application scenario, the transmit and receive FIFO size is dynamically set according to the actual transmit and receive requirements of each application in the application scenario, and the FIFO configuration information is dynamically generated, so that the FIFO configuration can dynamically adapt to the changing requirements of different application scenarios, thereby providing stronger transmit and receive capabilities and parallel transmit and receive capabilities on a limited chip area;

[0024] (2) Taking advantage of the application scenario characteristics, on the basis of dynamically configuring the FIFO space, the transmit and receive FIFO space is comprehensively utilized to construct a sub-transmit and receive FIFO that can be used for both receiving and transmitting, thereby improving the transmit and receive capabilities of FIFOs of the same size. In addition, a bus selector is set to further utilize the FIFO configuration information and perform bus selection and routing based on FIFO usage, further reducing the number of buses and bus ports and saving hardware overhead.

[0025] (3) Provide a transparent security state. Redundant operations are transparent to software layers such as the operating system and application layer, as well as to the outside of the communication module. Only one copy of data needs to be provided during write and read operations. The communication module transparently provides redundant space for redundant verification between multiple applications through a shared FIFO, providing the same overall security. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present application, but do not constitute an improper limitation of the present invention. In the drawings:

[0027] Figure 1 The figure is a schematic diagram of the architecture of the communication module data caching method in the prior art.

[0028] Figure 2 A schematic diagram of a communication module shared data cache system based on multi-entry FIFOs provided in one embodiment of the present invention.

[0029] Figure 3 A schematic diagram of a communication module shared data cache system based on multi-entry FIFOs provided in another embodiment of the present invention.

[0030] Figure 4 It is a schematic diagram of a method for sharing data cache of communication modules based on multi-entry FIFO of the present invention. DETAILED DESCRIPTION

[0031] The present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments, wherein the illustrative embodiments and descriptions are only used to explain the present invention but are not intended to limit the present invention.

[0032] Attached Figure 1The figure is a schematic diagram of the communication module data caching method in the prior art; it can be seen that FIFO can only provide cache for multiple communication modules by time division multiplexing, and the so-called sharing is time division multiplexing sharing. For FIFO, multiple communication modules cannot work in parallel; the shared transceiver FIFO is set separately, and its size can only be fixed and cannot be modified after the chip design is completed;

[0033] The present invention proposes a communication module shared data cache method and system based on multi-entry FIFO, as shown in the attached Figure 2 As shown, the system includes: a shared FIFO, multiple communication modules and multiple sending interfaces and receiving interfaces;

[0034] The system bus is used for data communication within the chip; the shared FIFO is set between the system bus and the communication module for data communication with the system bus and external devices;

[0035] Each communication module includes a sending device and a receiving device, wherein: the sending device is connected to the sending interface and the shared FIFO to send the data in the shared FIFO through the sending interface; the receiving device is connected to the receiving interface and the shared FIFO to send the data received from the receiving interface to the shared FIFO; specifically: the sending device is connected to the sending FIFO corresponding to it in the shared FIFO; the receiving device is connected to the receiving FIFO corresponding to it in the shared FIFO;

[0036] Preferably: the number of the communication modules is 4, 8, 16, 32, 64, or 128;

[0037] Preferably: each of the plurality of communication modules is respectively connected to one or more communication bus protocol modules for data communication; specifically: each communication module corresponds to a sending interface and a receiving interface, and is connected to the communication bus protocol module through the sending interface and the receiving interface;

[0038] The system also includes a sharing decision module; the sharing decision module is used to determine FIFO configuration information according to the application scenario, and send the FIFO configuration information to the FIFO configuration module to configure the transceiver FIFO; specifically: the sharing decision module obtains the receiving requirements and sending requirements of each application in the current application scenario; based on the receiving requirements and sending requirements of each application, the FIFO space size of the sending FIFO and the receiving FIFO are allocated to each application respectively, so that the allocated sending FIFO space size meets the sending requirement of the application; the allocated receiving FIFO space size meets the receiving requirement of the application; the sending FIFO and the receiving FIFO are respectively divided into addresses according to the sending FIFO space size and the receiving FIFO space size to form a plurality of address ranges; each address range corresponds to a sub-transmitting FIFO or a sub-receiving FIFO; based on the address range, the address space of the shared FIFO is allocated in sequence, and the formed address division information is used as the FIFO configuration information; wherein: the FIFO configuration information contains the address division information of each sub-transmitting FIFO and sub-receiving FIFO;

[0039] The shared FIFO includes: a FIFO configuration module, an internal bus interface (Bus0~Bus3) and a transceiver FIFO having multiple entrances and exits and including a transmit FIFO and a receive FIFO; wherein: the transceiver FIFO is divided in advance so that the address range of the transmit FIFO and the address range of the receive FIFO constitute the address range of the transceiver FIFO;

[0040] Wherein: the FIFO configuration module is used to configure the address division of the sending FIFO and the receiving FIFO respectively according to the FIFO configuration information; so that each address range in the address range of the configured sending FIFO corresponds to a sub-sending FIFO, and each address range in the address range of the receiving FIFO corresponds to a sub-receiving FIFO; so as to improve the utilization efficiency of the shared FIFO; wherein: the FIFO configuration information contains the address division information of each sub-sending FIFO and each sub-receiving FIFO;

[0041] The transmit FIFO and receive FIFO are divided into multiple sub-transmit FIFOs (TX FIFOs) and sub-receive FIFOs (RX FIFOs) according to the address division information, and each sub-transmit FIFO or sub-receive FIFO corresponds to an entry and exit; that is, the transmit FIFO and receive FIFO are dynamically logically sized through the FIFO configuration information;

[0042] One side of the internal bus interface is connected to the system bus for connecting the internal data of the chip, and the other side is connected to the corresponding sub-transmit FIFO and sub-receive FIFO through the entrance and exit; the internal bus interface is connected to the FIFO configuration module to receive the address division information, and performs address mapping of the read operation and the write operation according to the address division information, so as to realize the data reading and writing with different sub-transmit FIFOs and sub-receive FIFOs; specifically: when the system bus needs to access the sub-transmit FIFO and the sub-receive FIFO, the corresponding internal bus interface is selected, and the system bus reads and writes the corresponding sub-receive FIFO or sub-transmit FIFO through the corresponding internal bus interface; for example: when the system bus needs to access TX FIFO 0, RX FIFO 0, Bus0 is selected, and the system reads and writes TX FIFO 0, RX FIFO 0 through Bus0;

[0043] Preferably: the number of internal bus interfaces, sub-transmit FIFOs or sub-receive FIFOs formed by address division, and communication modules is equal; each internal bus interface corresponds to a group of transmit FIFOs and sub-receive FIFOs, and a communication module;

[0044] Preferably: the size of the receiving FIFO is the same as the size of the transmitting FIFO; equal to half the size of the transmitting and receiving FIFO;

[0045] Preferably, the space size of the transmit and receive FIFO in the shared FIFO is 256 words.

[0046] Example 1

[0047] Set the shared FIFO size to 256 words, and the number of communication modules is 4. It is detected that the requirements of an application for the size of the TX / RX FIFO (including TX FIFO 0~ TX FIFO 3; RX FIFO 0~ RX FIFO 3) of the four communication modules (COMU0~COMU3) are as follows:

[0048] COMU0 TX FIFO size is 16 words, RX FIFO size is 8 words COMU1 TX FIFO size is 64 words, RX FIFO size is 96 words COMU2 TX FIFO size is 40 words, RX FIFO size is 16 words COMU3 TX FIFO size is 8 words, RX FIFO size is 8 words

[0049] The configuration information of the FIFO configuration module for the shared FIFO of 8 entries is as follows:

[0050] TX FIFO 0 address =0 ~15, RX FIFO 0 address = 0 ~ 7 TX FIFO 1 address =16 ~79, RX FIFO 1 address = 8 ~ 103 TX FIFO 2 address = 80 ~ 119, RX FIFO 2 address = 104 ~ 119 TX FIFO 3 address =120 ~ 127, RX FIFO 3 address = 120 ~ 127

[0051] The system bus operates as follows:

[0052] When the system bus needs to access TX FIFO 0, RX FIFO 0, Bus 0 is selected, and the system reads and writes TX FIFO 0, RX FIFO 0 through Bus 0. When the system bus needs to access TX FIFO 1, RX FIFO 1, Bus 1 is selected, and the system reads and writes TX FIFO 1, RX FIFO 1 through Bus 1. When the system bus needs to access TX FIFO 2, RX FIFO 2, Bus 2 is selected, and the system reads and writes TX FIFO 2, RX FIFO 2 through Bus 2. When the system bus needs to access TX FIFO 3, RX FIFO 3, Bus 3 is selected, and the system reads and writes TX FIFO 3, RX FIFO 3 through Bus 3.

[0053] In many application scenarios, the communication module is limited by the receiving and sending speed of the communication bus protocol module, which makes the receiving and sending rate of the communication module much lower than the system bus transmission rate. In addition, since the communication module is simplex operation, the receiving and sending of a communication module will not occur at the same time. In order to further improve the access efficiency, the present invention further optimizes the communication module shared data cache system based on multi-entry FIFO so that different FIFOs and COMUs can access data in parallel.

[0054] Preferably, the application scenario is a user's life application scenario, for example, many specific application scenarios of vehicle-mounted equipment;

[0055] Based on the same inventive concept, the present invention also provides a communication module shared data cache method and system based on multi-entry FIFO, as shown in the attached Figure 3 As shown, the system includes: a shared FIFO, a shared decision module, multiple communication modules, multiple sending interfaces and multiple receiving interfaces;

[0056] The shared decision module is used to determine FIFO configuration information according to the application scenario, and send the FIFO configuration information to the FIFO configuration module to configure the transceiver FIFO; specifically: the shared decision module obtains the receiving and sending requirements of each application in the current application scenario; determines the total transceiver requirement based on the receiving and sending requirements of each application; allocates the FIFO space size of the shared FIFO to each application, so that the allocated FIFO space size meets the total transceiver requirement of the application; divides the address of the transceiver FIFO according to the FIFO space size to form a plurality of address ranges; each address range corresponds to a sub-transceiver FIFO; allocates the address space of the shared FIFO (transceiver FIFO) in sequence based on the address range, and uses the formed address division information as the FIFO configuration information; wherein: the FIFO configuration information contains the address division information of each sub-transceiver FIFO;

[0057] The FIFO configuration module is used to configure the address division of the transceiver FIFO according to the FIFO configuration information, so that each address range corresponds to a sub-transceiver FIFO respectively; wherein: the FIFO configuration information includes the address division information of each sub-transceiver FIFO;

[0058] Preferably: the sharing decision module is set in the operating system space, and the operating system monitors the communication requirements of each application in the current application scenario in real time according to the hardware configuration of the communication module and its shared FIFO, and determines the receiving requirements and sending requirements for each application; wherein: the sending requirements and the receiving requirements are the receiving requirements and the sending requirements during the execution process or an execution stage of each application;

[0059] Preferably: when an application program in an application scenario or an execution stage of an application program changes, the sharing decision module is triggered to re-determine FIFO allocation information (allocate the FIFO space size of a shared FIFO for each application program) according to the application scenario, and send the FIFO allocation information to the FIFO configuration module; the FIFO configuration module is triggered to re-determine the FIFO configuration information and configure the shared FIFO;

[0060] The step of making the allocated address range meet the total transceiver requirements of the application program is as follows: making the FIFO space size corresponding to the allocated address range larger than the storage space size involved in the total transceiver requirements of the application program;

[0061] The total receiving and sending demand is determined based on the receiving demand and sending demand of each application program, specifically: setting the total receiving and sending demand of the application to be equal to the larger value of the receiving demand and the sending demand;

[0062] Preferably: when there is an application in the application scenario and its total receiving and sending demand is 0, the address range of the shared FIFO is not allocated to the application; so that other applications in the application scenario can be allocated a larger address range of the shared FIFO; as in Example 2, if COMU3 will not be used, there is no need to allocate FIFO to the module, so that the FIFO can be used by COMU0 / 1 / 2, thereby increasing the available FIFO size of COMU0 / 1 / 2;

[0063] Preferably: when the allocated address range cannot meet the total transceiver demand of the application, the total transceiver demand of each application is proportionally reduced according to the proportional relationship between the total transceiver demand of each application, so that the application with a higher total transceiver demand is replaced by the application with a lower total transceiver demand; the reduced total transceiver demand is used as the determined total transceiver demand; at this time, because the address division situation fed back by the communication module to the operating system cannot meet the transceiver demand requested by the operating system for the application, the read and write operations corresponding to the transceiver demand of the application need to be split to apply the address division situation;

[0064] The shared FIFO includes: a FIFO configuration module, a bus selector (Bus Mux) and a transceiver FIFO, a front-end selector (MUX00, MUX10, MUX20, MUX30) and a back-end selector (MUX01, MUX11, MUX21, MUX31); the transceiver FIFO is no longer distinguished between a receiving FIFO and a transmitting FIFO; instead, it is directly divided into multiple sub-transceiver FIFOs;

[0065] The sharing decision module is further used to generate a bus mapping signal soc_mem_map based on the address division information; the bus selector receives the bus mapping signal and logically divides the system bus into multiple communication buses (comu0 / 1 / 2 / 3_bus), so that each of the multiple communication buses corresponds to a communication device and its corresponding sub-transceiver FIFO; that is, after receiving the bus mapping signal, the bus selector routes the system bus data to the corresponding sub-transceiver FIFO or the corresponding communication device;

[0066] The transceiver FIFO is divided into multiple sub-transceiver FIFOs (FIFO 0~FIFO 3) according to the address division. Each sub-transceiver FIFO corresponds to a communication module and is used for both receiving data buffering and sending data buffering. In other words, the transceiver FIFO is dynamically logically divided through the FIFO configuration information to form multiple sub-transceiver FIFOs. A front-end selector is set at the write interface of each sub-transceiver FIFO, and a back-end selector is set at the read interface. The front-end selector selects the corresponding communication bus data (comu0 / 1 / 2 / 3_bus) and the write operation of the receiving device of the corresponding communication module, and sends the selection result to the sub-transceiver FIFO. The back-end selector selects the corresponding communication bus data (comu0 / 1 / 2 / 3_bus) and the read operation of the sending device of the corresponding communication module.

[0067] The front-end selector is a selector for writing to the transceiver FIFO, and the two inputs of the front-end selector are the corresponding communication bus data and the corresponding receiving device. For example, MUX00 is a selector for writing to FIFO0, and the two inputs of this selector are: (1) comu0_bus (2) receiving device in COMU0.

[0068] The back-end selector is a selector for reading the transceiver FIFO, and the two outputs of the back-end selector are the corresponding communication bus data and the corresponding sending device; for example: MUX01 is to selectively send the data read from FIFO0 to comu0_bus or the sending device;

[0069] The bus selector is set between the system bus and the transceiver FIFO; it is used to route the system bus data into multiple communication bus data (comu0 / 1 / 2 / 3_bus) and connect them to each communication module (COMU0 / 1 / 2 / 3) or its corresponding sub-transceiver FIFO according to the bus mapping signal sent by the sharing decision module and the shared FIFO configured by the bus configuration information;

[0070] Preferably: the system is in a safe state; when there is an application program that is a safe application program in the application scenario, the sharing decision module is set to work in a safe state; in the safe state, the total transceiver demand of the safe application program is set to twice the original total transceiver demand, and then the address range of the shared FIFO is allocated to each application program; the address space of the shared FIFO is allocated in sequence based on the address range to form address division information as FIFO configuration information; when the transceiver FIFO is divided into multiple sub-transceiver FIFOs according to the address division, the address range corresponding to the safe application program is further divided into two parts, corresponding to two groups of sub-transceiver FIFOs; the two groups of sub-transceiver FIFOs correspond to one communication module; a redundancy decision unit is set at the inlet and outlet of the transceiver FIFO to verify the read and write data, and select one piece of data as the read and write data for the final read and write operation according to the verification result; in this way, for software layers such as the operating system and the application layer and the outside of the communication module, the redundant operation is transparent, and only one piece of data needs to be provided during the write and read operations. The communication module transparently provides redundant space between multiple applications through the shared FIFO for redundant verification, providing the same overall security;

[0071] Preferably: each of the multiple communication modules is respectively connected to one or more communication bus protocol modules for data communication; specifically: each communication module corresponds to a sending interface and a receiving interface, and is connected to the communication bus protocol module through the sending interface and the receiving interface.

[0072] Example 2

[0073] Set the shared FIFO size to 256 words, the number of communication modules to 4, and monitor the requirements of an application for the TX / RX FIFO size of four communication modules (COMU0~COMU3) as follows:

[0074] COMU0 TX FIFO size is 24 words, RX FIFO size is 8 words COMU1 TX FIFO size is 160 words, RX FIFO size is 96 words COMU2 TX FIFO size is 56 words, RX FIFO size is 16 words COMU3 TX FIFO size is 16 words, RX FIFO size is 8 words

[0075] The sub-transmitter and receive FIFO requirements determined by the shared decision module are as follows:

[0076] FIFO 0 size is 24 words FIFO 1 size is 160 words FIFO 2 size is 56 words FIFO 3 size is 16 words

[0077] The configuration information of the FIFO configuration module for the shared FIFO of 8 entries is as follows:

[0078] TX FIFO 0 address =0 ~23 TX FIFO 1 address =24 ~183 TX FIFO 2 address = 184 ~ 239 TX FIFO 3 address =240 ~ 255

[0079] The process of sending and receiving data is as follows:

[0080] (a) comu0_bus selects write FIFO0 through MUX00 to write the data to be sent into FIFO0; (b) COMU0 selects read FIFO0 through MUX01, reads the data in FIFO0 and sends the data; (c) COMU0 selects write FIFO0 through MUX00 to write the received data into FIFO0; (d) comu0_bus selects read FIFO0 through MUX01 to read the data of FIFO0 to the bus;

[0081] The present invention uses configuration information to time-share multiplex the system bus, and after uniformly configuring the sub-receiving FIFO and the sub-transmitting FIFO, it simplifies the FIFO structure and increases the amount of data received and sent at one time, thereby reducing hardware overhead;

[0082] In Example 2, after comu0_bus writes FIFO0, COMU0 reads FIFO0 and then sends data; at this time, comu0_bus is idle, and the system bus / bus mux is also idle; so at this time, the bus system can write FIFO1 through comu1_bus, COMU1 reads FIFO1, and then sends data. Compared with Example 1, only one bus is needed, saving hardware overhead; because the shared FIFO module and the system bus have only one bus port;

[0083] Based on the same inventive concept, as shown in the attached Figure 4 As shown, the present invention also provides a communication module shared data cache method based on multi-entry FIFO, the method comprising:

[0084] Step S1: obtain the current application scenario and the application running therein, determine the FIFO configuration information according to the application scenario, and send the FIFO configuration information to the FIFO configuration module to configure the shared FIFO; specifically: the sharing decision module obtains the receiving and sending requirements of each application in the current application scenario; determines the total receiving and sending requirements based on the receiving and sending requirements of each application; allocates the FIFO space size of the shared FIFO to each application, so that the allocated FIFO space size meets the total receiving and sending requirements of the application; divides the address of the sending FIFO and the receiving FIFO respectively according to the FIFO space size to form a plurality of address ranges; each address range corresponds to a sub-sending FIFO or a sub-receiving FIFO; allocates the address space of the shared FIFO in sequence based on the address range, and uses the formed address division information as the FIFO configuration information; wherein: the FIFO configuration information contains the address division information of each sub-sending FIFO and sub-receiving FIFO;

[0085] Step S2: When the application needs to send data, a write operation is performed through the shared FIFO, and a bus mapping signal is enabled so that the bus selector routes the system bus data to a front-end selector corresponding to the write operation address; the front-end selector selects the write data from the bus selector (comu0_bus) and writes the data into the transceiver FIFO; the back-end selector selects the sending device, and sends the data read from the transceiver FIFO to the sending device for data transmission, and sends the data after reading the data therein; for example: MUX00 selects comu0_bus, and MUX01 selects the sending device. When the system is in a receiving state: MUX00 selects the receiving device, and MUX01 selects comu0_bus;

[0086] Preferably: the enable signals of the front-end selector and the corresponding back-end selector are the same, and when data is sent, the enable signals are both send enable signals, and when data is received, the enable signals are both receive enable signals; based on the situation that sending and receiving are time-division multiplexed, sending and receiving will not occur at the same time, so the selection signal of MUX00 / MUX01 is fixed in the receiving and sending periods;

[0087] Step S3: When data reception is required, the front-end selector selects the receiving device, writes the data received by the receiving device into the transceiver FIFO, and writes the received data into the sub-transceiver FIFO; the back-end selector selects Comu0_bus, sends the data read from the transceiver FIFO to comu0_bus, and then sends the data to the system bus through the bus selector, and enables the bus mapping signal so that the bus selector reads the corresponding bus data to the system bus;

[0088] A computer program (also referred to as a program, software, software application, script, or code) can be written in any form of a programming language, including an assembled or interpreted language, a declarative or procedural language, and it can be deployed in any form, including as a stand-alone program or as a module, component, subroutine, object, or other unit suitable for use in a computing environment. A computer program may, but need not, correspond to a file in a file system. A program can be stored in a portion of a file that holds other programs or data (e.g., one or more scripts stored in a markup language document), in a single file dedicated to the program, or in multiple collaborative files (e.g., files storing one or more modules, subroutines, or code portions). A computer program can be deployed to execute on one computer or on multiple computers located at one site or distributed across multiple sites and interconnected by a communication network.

[0089] It will be appreciated by those skilled in the art that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Furthermore, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0090] The present invention is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0091] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0092] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process in the computer or other programmable device. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0093] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, ordinary technicians in the relevant field should understand that the specific implementation methods of the present invention can still be modified or replaced by equivalents. Any modification or equivalent replacement that does not depart from the spirit and scope of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. A communication module shared data cache system based on multi-entry FIFO, characterized in that: The system comprises: Shared FIFO, shared decision module, multiple communication modules, multiple sending interfaces and multiple receiving interfaces; The shared decision module is used to determine FIFO configuration information according to the application scenario, and send the FIFO configuration information to the FIFO configuration module to configure the transceiver FIFO; specifically: the shared decision module obtains the receiving and sending requirements of each application in the current application scenario; determines the total transceiver requirement based on the receiving and sending requirements of each application; allocates the FIFO space size of the shared FIFO to each application, so that the allocated FIFO space size meets the total transceiver requirement of the application; divides the address of the transceiver FIFO according to the FIFO space size to form a plurality of address ranges; each address range corresponds to a sub-transceiver FIFO; allocates the address space of the shared FIFO in sequence based on the address range, and uses the formed address division information as the FIFO configuration information; wherein: the FIFO configuration information contains the address division information of each sub-transceiver FIFO; The sharing decision module is further used to generate a bus mapping signal based on the address division information, and the bus selector receives the bus mapping signal and logically divides the system bus into multiple communication buses, so that each of the multiple communication buses corresponds to a communication device and its corresponding sub-transceiver FIFO; The sharing decision module is set in the operating system space. The operating system monitors the communication requirements of each application in the current application scenario in real time according to the hardware configuration of the communication module and its shared FIFO, and determines the receiving requirements and sending requirements for each application; wherein: the sending requirements and the receiving requirements are the receiving requirements and the sending requirements in the execution process or an execution stage of each application; When an application program in an application scenario or an execution phase of an application program changes, the sharing decision module is triggered to re-determine FIFO allocation information according to the application scenario, allocate a FIFO space size of a shared FIFO to each application program, and send the FIFO allocation information to the FIFO configuration module; the FIFO configuration module is triggered to re-determine the FIFO configuration information and configure the shared FIFO; The step of making the allocated address range meet the total transceiver requirements of the application program is as follows: making the FIFO space size corresponding to the allocated address range larger than the storage space size involved in the total transceiver requirements of the application program; The total receiving and sending demand is determined based on the receiving demand and sending demand of each application program, specifically: setting the total receiving and sending demand of the application to be equal to the larger value of the receiving demand and the sending demand; The shared FIFO includes: a FIFO configuration module, a bus selector and a transceiver FIFO, a front-end selector and a back-end selector; The FIFO configuration module is used to configure the address division of the transceiver FIFO according to the FIFO configuration information, so that each address range corresponds to a sub-transceiver FIFO; The bus selector is arranged between the system bus and the transceiver FIFO; it is used to route the system bus data into multi-channel communication bus data and connect them to each communication module or its corresponding sub-transceiver FIFO respectively based on the bus mapping signal sent by the sharing decision module and the shared FIFO configured by the bus configuration information; The transceiver FIFO is divided into multiple sub-transceiver FIFOs according to the address division information. Each sub-transceiver FIFO corresponds to a communication module and is used for both receiving data buffering and sending data buffering. A front-end selector is set at the write interface of each sub-transceiver FIFO, and a back-end selector is set at the read interface. The front-end selector is a selector for writing to the transceiver FIFO, and the two inputs of the front-end selector are the corresponding communication bus data and the corresponding receiving device; the back-end selector is a selector for reading the transceiver FIFO, and the two outputs of the back-end selector are the corresponding communication bus data and the corresponding sending device; Each of the plurality of communication modules is respectively connected to one or more communication bus protocol modules for data communication; specifically: each communication module corresponds to a sending interface and a receiving interface, and is connected to the communication bus protocol module through the sending interface and the receiving interface; The transceiver FIFO is divided into multiple sub-transceiver FIFOs according to the address division, each sub-transceiver FIFO corresponds to a communication module, and is used for both receiving data buffering and sending data buffering; the transceiver FIFO is dynamically logically divided through the FIFO configuration information to form multiple sub-transceiver FIFOs; a front-end selector is correspondingly set at the write interface of each sub-transceiver FIFO, and a back-end selector is correspondingly set at the read interface; the front-end selector selects the corresponding communication bus data and the write operation of the receiving device of the corresponding communication module, and sends the selection result to the sub-transceiver FIFO; the back-end selector selects the corresponding communication bus data and the read operation of the sending device of the corresponding communication module; The front-end selector is a selector for writing to the transceiver FIFO, and its two inputs are the corresponding communication bus data and the corresponding receiving device respectively; the back-end selector is a selector for reading the transceiver FIFO, and its two outputs are the corresponding communication bus data and the corresponding sending device respectively; the bus selector is arranged between the system bus and the transceiver FIFO; and is used to route the system bus data into multiple communication bus data and connect them to each or its corresponding sub-transceiver FIFO according to the bus mapping signal sent by the sharing decision module and the shared FIFO configured by the bus configuration information.

2. The communication module shared data cache system based on multi-entry FIFO according to claim 1, characterized in that: Each application in the application scenario runs on a core of the multi-core chip.

3. The communication module shared data cache system based on multi-entry FIFO according to claim 2, characterized in that: The application scenario is a vehicle-mounted application scenario.

4. The communication module shared data cache system based on multi-entry FIFO according to claim 3 is characterized in that: The multi-entry FIFO contains 4 sets of entry and exit.

5. The communication module shared data cache system based on multi-entry FIFO according to claim 4 is characterized in that: There are 4 communication modules to support 4 different types of communication bus protocol modules.

6. The communication module shared data cache system based on multi-entry FIFO according to claim 5, characterized in that: When there is an application in the application scenario and its total receiving and sending demand is 0, the address range of the shared FIFO is not allocated to the application.

7. A chip, characterized in that: The chip includes a communication module shared data cache system based on multi-entry FIFO as described in any one of claims 1-6.

8. A communication module shared data cache method based on multi-entry FIFO, characterized in that: The method is applied to a communication module shared data cache system based on multi-entry FIFOs as described in any one of claims 1-6; comprising: configuring the shared FIFO based on FIFO configuration information before the application needs to send data.

9. A server, characterized in that: The server is provided with a communication module shared data cache system based on multi-entry FIFO as described in any one of claims 1-6.

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