Ultra-high precision analog-to-digital converter sampling thermal noise cancellation circuit

Abstract

The ultra-high precision analog-to-digital converter (ADC) sampling thermal noise cancellation circuit provided by this invention includes: a lower plate sampling network and an amplifier circuit; the amplifier circuit includes a first reset unit, a second reset unit, a noise decoupling unit, a charge distribution adjustment unit, a feedback path control unit, and an operational amplifier U1; the noise decoupling unit is used to decouple the operational amplifier thermal noise and sampling thermal noise according to the change of the input signal of the lower plate sampling network after the feedback path is disconnected; the second reset unit is used to change the charge at the input terminal of the amplifier circuit according to the change of the input signal of the lower plate sampling network after the feedback path is disconnected, so as to achieve the effect of noise cancellation. By changing the configuration of the operational amplifier feedback capacitor, the sampling thermal noise and operational amplifier thermal noise are suppressed, thereby improving the thermal noise performance of the ultra-high precision analog-to-digital converter sampling thermal noise cancellation circuit.

Description

Technical Field

[0001] This invention relates to the field of electronic circuit technology, and more specifically to a sampling thermal noise cancellation circuit for an ultra-high precision analog-to-digital converter. Background Technology

[0002] The sample-and-hold circuit at the front end of a discrete analog-to-digital converter (ADC) introduces kT / C sampling thermal noise during sampling operations, which limits the overall accuracy of the ADC.

[0003] Increasing the size of the sampling capacitor can reduce sampling thermal noise, but it increases the design complexity and power consumption of the input driver and reference buffer. Furthermore, traditional sampling thermal noise cancellation methods use correlated double sampling to reduce sampling thermal noise, but this introduces additional operational amplifier thermal noise. Moreover, traditional sampling thermal noise cancellation methods heavily rely on the performance of the static amplifier, consuming more power and degrading the overall circuit's FoM value. Summary of the Invention

[0004] To address the aforementioned problems in the prior art, this invention provides an ultra-high precision analog-to-digital converter sampling thermal noise cancellation circuit, specifically comprising:

[0005] In a first aspect, the present invention provides an ultra-high precision analog-to-digital converter sampling thermal noise cancellation circuit, comprising:

[0006] Lower plate sampling network and amplifier circuit;

[0007] The lower plate sampling network includes an input signal switching unit and a sampling capacitor array connected in sequence, and the output terminal of the sampling capacitor array is connected to the input terminal of the amplifier circuit.

[0008] The input signal switching unit is used to control the input signal of the lower plate sampling network to switch between high level, low level and no signal;

[0009] The amplifier circuit includes a first reset unit, a second reset unit, a noise decoupling unit, a charge distribution adjustment unit, a feedback path control unit, and an operational amplifier U1. The first terminal of the first reset unit is connected to the first terminal of the noise decoupling unit and the input terminal of the operational amplifier U1. The second terminal of the first reset unit is connected to the third terminal of the charge distribution adjustment unit and the first terminal of the feedback path control unit. The second terminal of the noise decoupling unit is connected to the first terminal of the charge distribution adjustment unit, the first terminal of the second reset unit, and the second terminal of the charge distribution adjustment unit. The fourth terminals of the second reset unit and the charge distribution adjustment unit are both grounded. The first reset unit, the second reset unit, the noise decoupling unit, and the charge distribution and adjustment unit constitute the feedback path of the operational amplifier U1. The input terminal of the operational amplifier U1 is the input terminal of the amplifier circuit.

[0010] The first reset unit is used to reset the amplifier circuit in the initial stage. The feedback path control unit is used to control the on / off state of the feedback path. The noise decoupling unit is used to decouple the operational amplifier thermal noise and the sampling thermal noise according to the change of the input signal of the lower plate sampling network after the feedback path is disconnected. The second reset unit is used to change the charge at the input terminal of the amplifier circuit according to the change of the input signal of the lower plate sampling network after the feedback path is disconnected, so as to achieve the effect of noise elimination.

[0011] Optionally, the first reset unit includes a switch Φ1;

[0012] The second reset unit includes a switch Φ 41 ;

[0013] The noise decoupling unit includes capacitors C2 and C3 and a switch Φ. 31 ;

[0014] The charge distribution adjustment unit includes capacitors C1 and C4;

[0015] The feedback path control unit includes switch Φ2;

[0016] Specifically, the first terminals of Φ1, C3, and C2 are all connected to the input terminal of U1. The second terminal of Φ1 is connected to the first terminal of Φ2 and the second terminal of C4, respectively. The second terminal of Φ2 is connected to the output terminal of U1. The second terminal of C3 is connected to the input terminal of Φ2. 31 The first end is connected, Φ 31 The second end is connected to the second end of C2, the first end of C1, and Φ respectively. 42 The first end of C4 is connected to the first end of C1, and the second end of C1 is connected to Φ. 42 Both of the second terminals are grounded, and the input terminal of U1 is the input terminal of the amplifier circuit.

[0017] Optionally, the input signal switching unit includes a switch Φ 32 Φ42 ,

[0018] Where, Φ 32 The first end is the input end of the lower electrode sampling network, Φ 32 The second end is respectively with Φ 42 The first terminal is connected to the input terminal of the sampling capacitor array, Φ 42 The second terminal is grounded.

[0019] Optionally, U1 is a high-gain static operational amplifier.

[0020] Optionally, U1 includes PMOS transistors M3, M4, M5, and M6, and NMOS transistors M0, M1, M2, M7, M8, M9, and M6. 10 Capacitor C L1 and C L2 And operational amplifiers U2 and U3;

[0021] In this case, the source of M0 is grounded, and the gate is connected to the external signal V. b The drain is connected to the source of M1 and the source of M2, respectively.

[0022] The gate of M1 is connected to an external signal V. in The drain is connected to the drain of M3, the source of M5, and the first input terminal of U2, respectively.

[0023] The gate of M2 is connected to an external signal V. ip The drain is connected to the drain of M4, the source of M6, and the second input terminal of U2, respectively.

[0024] The sources of both M3 and M4 are connected to power supply V. dd The gates are all connected to an external signal V. bp ,

[0025] The gate of M5 is connected to the first output terminal of U2, and the drain is connected to C. L1 The first terminal and the drain of M7 are connected;

[0026] The gate of M6 is connected to the second output terminal of U2, and the drain is connected to C. L2 The first terminal and the drain of M8 are connected;

[0027] The gate of M7 is connected to the first output terminal of U3, and the source is connected to the first input terminal of U3 and the drain of M9 respectively.

[0028] The gate of M8 is connected to the second output terminal of U3, and the source is connected to the two input terminals of U3 and M8 respectively. 10 Drain connection;

[0029] M9 and M 10 The gates of all are connected to an external signal V. bn Both the source and the source are grounded.

[0030] Secondly, the present invention also provides a control method for a sampling thermal noise cancellation circuit of an ultra-high precision analog-to-digital converter, applied to the corresponding circuit as provided in the first aspect, comprising:

[0031] Control Φ1, Φ2, Φ 31 and Φ 32 Closed, Φ 41 and Φ 42 disconnect;

[0032] After the first preset time period, disconnect Φ1 while keeping Φ2 and Φ 31 Φ 32 Φ 41 and Φ 42 The state remains unchanged;

[0033] After the second preset time period, disconnect Φ2 while maintaining Φ1 and Φ2. 31 Φ 32 Φ 41 and Φ 42 The state remains unchanged;

[0034] After the third preset time period, disconnect Φ 31 and Φ 32 And maintain Φ1, Φ2, Φ3, Φ 41 and Φ 42 The state remains unchanged;

[0035] After the fourth preset time period, disconnect Φ 41 and Φ 42 And maintain Φ1, Φ2, Φ3, Φ 31 and Φ 32 The state remains unchanged.

[0036] Thirdly, the present invention also provides an ultra-high precision analog-to-digital converter, comprising:

[0037] The latch unit, the SAR logic unit, and the sampling thermal noise cancellation circuit of any ultra-high precision analog-to-digital converter as provided in the first aspect.

[0038] Fourthly, the present invention also provides a chip including any of the ultra-high precision analog-to-digital converter sampling thermal noise cancellation circuits provided in the first aspect.

[0039] Fifthly, the present invention also provides a chip comprising any of the ultra-high precision analog-to-digital converters provided in the third aspect.

[0040] In a sixth aspect, the present invention also provides an electronic device comprising any of the chips provided in the fourth or fifth aspect.

[0041] The beneficial effects of this invention are:

[0042] The present invention provides an ultra-high precision analog-to-digital converter sampling thermal noise cancellation circuit, comprising: a lower plate sampling network and an amplifier circuit; the lower plate sampling network includes an input signal switching unit and a sampling capacitor array connected in sequence, the output terminal of the sampling capacitor array being connected to the input terminal of the amplifier circuit; the input signal switching unit is used to control the input signal of the lower plate sampling network to switch between high level, low level, and no signal; the amplifier circuit includes a first reset unit, a second reset unit, a noise decoupling unit, a charge distribution adjustment unit, a feedback path control unit, and an operational amplifier U1, the first terminal of the first reset unit being connected to the first terminal of the noise decoupling unit and the input terminal of the operational amplifier U1, the second terminal of the first reset unit being connected to the third terminal of the charge distribution adjustment unit and the first terminal of the feedback path control unit, and the second terminal of the noise decoupling unit being connected to the third terminal of the charge distribution adjustment unit and the input terminal of the feedback path control unit, respectively. The first terminal of the charge distribution adjustment unit, the first terminal of the second reset unit, and the second terminal of the charge distribution adjustment unit are connected. The fourth terminals of both the second reset unit and the charge distribution adjustment unit are grounded. The first reset unit, the second reset unit, the noise decoupling unit, and the charge distribution and adjustment unit constitute the feedback path of operational amplifier U1. The input terminal of operational amplifier U1 is the input terminal of the amplifier circuit. The first reset unit is used to reset the amplifier circuit in the initial stage. The feedback path control unit is used to control the on / off state of the feedback path. The noise decoupling unit is used to decouple the operational amplifier thermal noise and sampling thermal noise based on the change in the input signal of the lower plate sampling network after the feedback path is disconnected. The second reset unit is used to change the charge at the input terminal of the amplifier circuit based on the change in the input signal of the lower plate sampling network after the feedback path is disconnected, thereby achieving the effect of noise elimination. This circuit, by changing the configuration of the operational amplifier feedback capacitor, achieves the effect of simultaneously suppressing sampling thermal noise and operational amplifier thermal noise, improving the overall thermal noise performance of the ultra-high precision analog-to-digital converter sampling thermal noise elimination circuit, and has low power consumption.

[0043] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0044] Figure 1 A schematic diagram of the overall circuit structure of an ADC using a conventional lower plate sampling method provided by the present invention;

[0045] Figure 2 A timing diagram provided by the present invention;

[0046] Figure 3 A schematic diagram of a sampling thermal noise cancellation circuit for an ultra-high precision analog-to-digital converter is provided for this invention.

[0047] Figure 4 Another timing diagram provided by the present invention;

[0048] Figure 5 A schematic diagram of the equivalent circuit structure of a conventional sample-and-hold circuit provided by the present invention;

[0049] Figure 6 This invention provides yet another timing diagram;

[0050] Figure 7 A schematic diagram of the structure of an operational amplifier provided by the present invention;

[0051] Figure 8 This is a schematic diagram of a simulation result provided by the present invention. Detailed Implementation

[0052] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0053] Figure 1 This is a schematic diagram of the overall circuit structure of an ADC using a conventional lower plate sampling method provided by the present invention. The ADC includes a sample-and-hold circuit 11, a comparator 12, and a SAR logic unit 13. The sample-and-hold circuit 11 includes switches Φ5, Φ6, and Φ7 and a sampling capacitor array 111. Each switch is configured according to... Figure 2 The timing diagram shown is operational. However, sampling operations based on this sample-and-hold circuit introduce kT / C sampling thermal noise, which limits the overall accuracy of the ADC.

[0054] To address the aforementioned problems, this invention proposes an ultra-high precision analog-to-digital converter sampling thermal noise cancellation circuit for sample-and-hold operation, such as... Figure 3 As shown, the ultra-high precision analog-to-digital converter sampling thermal noise cancellation circuit 30 includes:

[0055] The lower plate sampling network 301 and the amplifier circuit 302.

[0056] The lower plate sampling network 301 includes an input signal switching unit 3011 and a sampling capacitor array 3012 connected in sequence. The output terminal of the sampling capacitor array 3012 is connected to the input terminal of the amplifier circuit 302.

[0057] The input signal switching unit 3011 is used to control the input signal of the lower plate sampling network 301 to switch between high level, low level and no signal.

[0058] See Figure 3 In one possible implementation of the circuit shown, the input signal switching unit 3011 includes a switch Φ 32 Φ 42 .

[0059] Where, Φ 32The first end is the input end of the lower electrode sampling network 301, Φ 32 The second end is respectively with Φ 42 The first terminal is connected to the input terminal of the sampling capacitor array 3012, Φ 42 The second terminal is grounded.

[0060] By changing Φ 32 Φ 42 The switching state can change the input signal of the lower plate sampling network 301, see [link / reference]. Figure 4 The timing diagram shown shows that when Φ 32 Φ 42 When both are disconnected, there is no signal input; when Φ 32 Closed and Φ 42 When disconnected, the input signal is Vin, and when Φ 32 Disconnect and Φ 42 When closed, the input signal is ground, that is, the input terminal is grounded.

[0061] The amplifier circuit 302 includes a first reset unit 3021, a second reset unit 3022, a noise decoupling unit 3023, a charge distribution adjustment unit 3024, a feedback path control unit 3025, and an operational amplifier U1.

[0062] The first terminal of the first reset unit 3021 is connected to the first terminal of the noise decoupling unit 3023 and the input terminal of the operational amplifier U1, respectively. The second terminal of the first reset unit 3021 is connected to the third terminal of the charge distribution adjustment unit 3024 and the first terminal of the feedback path control unit 3025, respectively. The second terminal of the noise decoupling unit 3023 is connected to the first terminal of the charge distribution adjustment unit 3024, the first terminal of the second reset unit 3022, and the second terminal of the charge distribution adjustment unit 3024, respectively. The fourth terminals of the second reset unit 3022 and the charge distribution adjustment unit 3024 are both grounded. The first reset unit 3021, the second reset unit 3022, the noise decoupling unit 3023, and the charge distribution adjustment unit 3024 constitute the feedback path of the operational amplifier U1. The input terminal of the operational amplifier U1 is the input terminal of the amplifier circuit.

[0063] The first reset unit 3021 is used to reset the amplifier circuit in the initial stage.

[0064] The feedback path control unit 3025 is used to control the on / off state of the feedback path.

[0065] The noise decoupling unit 3023 is used to decouple the operational amplifier thermal noise and the sampling thermal noise based on the change of the input signal of the lower plate sampling network 301 after the feedback path is disconnected.

[0066] The second reset unit 3022 is used to change the charge at the input terminal of the amplifier circuit 302 according to the change of the input signal of the lower plate sampling network 301 after the feedback path is disconnected, so as to achieve the effect of noise elimination.

[0067] See Figure 3 In one possible implementation of the circuit shown, the first reset unit 3021 includes a switch Φ1; the second reset unit 3022 includes a switch Φ 41 The noise decoupling unit 3023 includes capacitors C2 and C3 and a switch Φ. 31 The charge distribution adjustment unit 3024 includes capacitors C1 and C4; the feedback path control unit 3025 includes switch Φ2.

[0068] Specifically, the first terminals of Φ1, C3, and C2 are all connected to the input terminal of U1. The second terminal of Φ1 is connected to the first terminal of Φ2 and the second terminal of C4, respectively. The second terminal of Φ2 is connected to the output terminal of U1. The second terminal of C3 is connected to the input terminal of Φ2. 31 The first end is connected, Φ 31 The second end is connected to the second end of C2, the first end of C1, and Φ respectively. 41 The first end of C4 is connected to the first end of C1, and the second end of C1 is connected to Φ. 41 Both of the second terminals are grounded, and the input terminal of U1 is the input terminal of the amplifier circuit.

[0069] See Figure 4 The control timing shown indicates that the sampling period of this circuit is mainly divided into three parts: tracking sampling stage (T), holding stage (H), and noise decoupling stage (D). The tracking sampling stage consists of Φ1, Φ2, and Φ... 31 Φ 32 Closed, Φ 41 Φ 42 Disconnect; maintain phases Φ2, Φ 31 Φ 32 Closed, Φ1, Φ 41 Φ 42 Disconnect; Noise decoupling stage Φ 31 Φ 32 Closed, Φ1, Φ2, Φ 41 Φ 42 disconnect.

[0070] At the initial moment of the tracking sampling phase, switches Φ1, Φ2, and Φ 31 Closed, Φ 41 Disconnect. When switch Φ1 is closed, the circuit is in the reset phase. At this time, both the input and output terminals of operational amplifier U1 are reset to the common-mode voltage V. cm At the instant switch Φ1 is opened, the sampling thermal noise is fixed at the input terminal of operational amplifier U1, i.e., node V. x Place.

[0071] For ease of description, this invention performs an equivalent transformation on the traditional sample-and-hold circuit to obtain the following: Figure 5 The equivalent circuit shown is Figure 6 for Figure 5 The circuit shown has a switch control timing sequence, where the timing of switch S1 and... Figure 2 Φ5 is consistent, S2 and Φ6 are consistent, and S3 and Φ7 are consistent. In the subsequent hold phase, a conventional sample-and-hold circuit will fix the value at node V. x The signal charge and the sampling thermal noise charge at the point are transferred together to the feedback capacitor C. f Above. Two points require special attention during the hold phase: First, when the open-loop gain is sufficiently large, the closed-loop op-amp can provide a virtual ground, i.e., V... x The voltage at the node approaches the DC level V. cm Secondly, the thermal noise charge introduced during the tracking and sampling phase will be redistributed to the feedback capacitor, such as... Figure 5 As shown in step ①, the holding phase ends the instant switch S2 is opened, and thermal noise from the op-amp is introduced. At this time, there are two types of noise at the op-amp output: sampling thermal noise and op-amp thermal noise. Due to the sampling capacitor C... s With feedback capacitor C f Since they are connected in series, the fixed noise charge on the two capacitors is equal. To eliminate the thermal noise of op-amp U1, the output of U1 can be forcibly reset to the common-mode output level, thereby reducing the noise of the feedback capacitor C. f The fixed operational amplifier thermal noise charge changes polarity and is sent to node V. x At sampling capacitor C s The fixed operational amplifier thermal noise charge cancels out, such as Figure 5 As shown in step ②. However, this reset operation will also send the sampled thermal noise charge transferred to the feedback capacitor back to node V. x While eliminating operational amplifier thermal noise, sampling thermal noise is also introduced.

[0072] To alleviate this contradiction, this invention improves the feedback circuit of the operational amplifier and proposes an ultra-high precision analog-to-digital converter (ADC) sampling thermal noise cancellation circuit. Based on this invention, the ultra-high precision ADC sampling thermal noise cancellation circuit, in the noise decoupling stage, redistributes the noise charge across the corresponding capacitors using a series-parallel capacitor configuration. After this operation, a reset operation can then send a smaller amount of sampling thermal noise charge back to node V. x At the same time, it eliminates most of the operational amplifier's thermal noise.

[0073] For example, see Figure 3 The noise charge is transferred to capacitors C1, C2, C3, C4 and C SThe charge is redistributed to ensure that less sampled thermal noise charge is returned to node V during the second reset operation. x .

[0074] Specifically, such as Figure 3 As shown, when Φ1 is open and Φ2 is closed, Φ 31 and Φ 32 Closed, Φ 41 and Φ 42 When disconnected, looking from the output terminal of U1 towards the input terminal, the equivalent load capacitance of U1 can be expressed by the following formula:

[0075]

[0076] Wherein, capacitor C a Equivalent to the following formula:

[0077]

[0078] Capacitor C b This is equivalent to capacitors C2 and C3 in parallel, and can be represented by the following formula:

[0079] C b =C2+C3 (3)

[0080] C1 represents the capacitance value of C1, C2 represents the capacitance value of C2, C3 represents the capacitance value of C3, and C4 represents the capacitance value of C4. s C represents s The capacitance value.

[0081] Furthermore, based on the connection of the feedback capacitor, the amount of sampled thermal noise charge fixed by capacitor C2 is obtained, expressed as:

[0082]

[0083] Among them, v ns This indicates the introduction of node V under the current capacitor configuration. x The thermal noise value at the sampling point, This indicates the introduction of node V under the current capacitor configuration. x The mean square value of the sampled thermal noise at that location.

[0084] Similarly, by closing Φ 41 Performing a reset operation transfers the operational amplifier noise charge fixed on C2 to the sampling capacitor C. s Right pole plate (i.e., node V) x This completes the function of operational amplifier noise charge cancellation, and the node V at this time can be obtained. x The remaining operational amplifier noise charge is:

[0085]

[0086] Among them, v out,na This represents the operational amplifier thermal noise value introduced at node Vx under the current capacitor configuration. This represents the mean square value of the operational amplifier thermal noise introduced at node Vx under the current capacitor configuration.

[0087] v ns v out,na Substituting the values ​​into formulas (4) and (5) respectively, we obtain the value of the second reset operation sent back to node V. x The sampled thermal noise charge is expressed as:

[0088]

[0089] in, C g This indicates that when calculating sampled thermal noise, the noise originates from node V. x The feedback capacitance value seen at [location], where γ represents the process constant, k represents the Boltzmann constant, and T represents the absolute temperature.

[0090] After noise cancellation, node V x The residual thermal noise charge at the operational amplifier is:

[0091]

[0092] Where β=C g / (C s +C g ).

[0093] From the theoretical analysis above, we know that to satisfy the op-amp input terminal (node ​​V) x To minimize the total noise charge at point (6), the sum of the results from formulas (6) and (7) must be minimized. This satisfies the following two points simultaneously: closing switch Φ 41 At that time, send back node V x The sampled thermal noise charge is small, and the reset operation cancels out node V. x The amount of residual operational amplifier thermal noise charge after the operational amplifier thermal noise charge at the point is relatively small. From formulas (4) and (5), it is easy to obtain the effect of the size change of each capacitor in the sampling thermal noise cancellation circuit of this ultra-high precision analog-to-digital converter on V. x The influence of sampling thermal noise and operational amplifier thermal noise is considered. For example, by importing the derived formulas into simulation software such as Matlab and plotting the corresponding noise performance change curves, the trend of the two thermal noises changing with the size of each capacitor can be intuitively obtained, and thus the corresponding capacitance value can be obtained.

[0094] The performance of an operational amplifier has a certain impact on noise cancellation effectiveness. The open-loop gain of the operational amplifier affects its settling error and linearity, which in turn affects the transfer of thermal noise charge. After the operational amplifier has stabilized, the residual voltage at its input terminal changes with the open-loop gain as follows: Figure 8 As shown. The bandwidth of an operational amplifier affects its settling speed and input swing. Additionally, the parasitic capacitance at the op-amp's input also influences the results of the above derivation.

[0095] Optionally, U1 is a high-gain static operational amplifier.

[0096] See Figure 7 In one possible implementation, U1 includes PMOS transistors M3, M4, M5, and M6, and NMOS transistors M0, M1, M2, M7, M8, M9, and M6. 10 Capacitor C L1 and C L2 , as well as operational amplifiers U2 and U3.

[0097] In this case, the source of M0 is grounded, and the gate is connected to the external signal V. b The drain of M1 is connected to the source of M2, and the gate of M1 is connected to the external signal V. in The drain of M2 is connected to the drain of M3, the source of M5, and the first input terminal of U2, respectively; the gate of M2 is connected to the external signal V. ip The drains of M3 and M4 are connected to the drain of M4, the source of M6, and the second input terminal of U2, respectively; the sources of M3 and M4 are both connected to the power supply V. dd The gates are all connected to an external signal V. bp The gate of M5 is connected to the first output terminal of U2, and the drain is connected to C. L1 The first terminal of M6 is connected to the drain of M7; the gate of M6 is connected to the second output terminal of U2, and the drain is connected to C. L2 The first terminal of M7 is connected to the drain of M8; the gate of M7 is connected to the first output terminal of U3, and the source is connected to the first input terminal of U3 and the drain of M9; the gate of M8 is connected to the second output terminal of U3, and the source is connected to the two input terminals of U3 and the drain of M9. 10 Drain connection; M9 and M 10 The gates of all are connected to an external signal V. bn Both the source and the source are grounded.

[0098] The present invention provides an ultra-high precision analog-to-digital converter sampling thermal noise cancellation circuit, comprising: a lower plate sampling network and an amplifier circuit; the lower plate sampling network includes an input signal switching unit and a sampling capacitor array connected in sequence, the output terminal of the sampling capacitor array being connected to the input terminal of the amplifier circuit; the input signal switching unit is used to control the input signal of the lower plate sampling network to switch between high level, low level, and no signal; the amplifier circuit includes a first reset unit, a second reset unit, a noise decoupling unit, a charge distribution adjustment unit, a feedback path control unit, and an operational amplifier U1, the first terminal of the first reset unit being connected to the first terminal of the noise decoupling unit and the input terminal of the operational amplifier U1, the second terminal of the first reset unit being connected to the third terminal of the charge distribution adjustment unit and the first terminal of the feedback path control unit, and the second terminal of the noise decoupling unit being connected to the third terminal of the charge distribution adjustment unit and the input terminal of the feedback path control unit, respectively. The first terminal of the charge distribution adjustment unit, the first terminal of the second reset unit, and the second terminal of the charge distribution adjustment unit are connected. The fourth terminals of both the second reset unit and the charge distribution adjustment unit are grounded. The first reset unit, the second reset unit, the noise decoupling unit, and the charge distribution and adjustment unit constitute the feedback path of operational amplifier U1. The input terminal of operational amplifier U1 is the input terminal of the amplifier circuit. The first reset unit is used to reset the amplifier circuit in the initial stage. The feedback path control unit is used to control the on / off state of the feedback path. The noise decoupling unit is used to decouple the operational amplifier thermal noise and sampling thermal noise based on the change in the input signal of the lower plate sampling network after the feedback path is disconnected. The second reset unit is used to change the charge at the input terminal of the amplifier circuit based on the change in the input signal of the lower plate sampling network after the feedback path is disconnected, thereby achieving the effect of noise elimination. This circuit, by changing the configuration of the operational amplifier feedback capacitor, achieves the effect of simultaneously suppressing sampling thermal noise and operational amplifier thermal noise, improving the overall thermal noise performance of the ultra-high precision analog-to-digital converter sampling thermal noise elimination circuit.

[0099] To further demonstrate the beneficial effects of this invention, a set of simulation data is also provided. The simulation circuit was designed using a standard 180nm CMOS process. The entire circuit operates at a power supply voltage of 1.8V, with a sampling frequency of 5MS / s and an input signal full differential swing of 3.6V. The total sampling capacitance of the ADC circuit is 340fF, and the total feedback capacitance is 324fF. The overall circuit's SNDR reaches 83.5dB in the Nyquist band. Compared to ADCs using traditional sample-and-hold circuits, under the same capacitor size and operating conditions, the architecture proposed in this invention improves noise performance by approximately 10dB.

[0100] This invention also provides a control method for a sampling thermal noise cancellation circuit of an ultra-high precision analog-to-digital converter, applicable to, for example... Figure 3 The circuit shown, the method includes:

[0101] Control Φ1, Φ2, Φ 31 and Φ 32 Closed, Φ 41 and Φ 42 Disconnect; after the first preset time, disconnect Φ1 while maintaining Φ2 and Φ 31 Φ 32 Φ 41 and Φ 42 The state remains unchanged; after a second preset time, Φ2 is disconnected while Φ1 and Φ2 remain unchanged. 31 Φ 32 Φ 41 and Φ 42 The state remains unchanged; after a third preset time, Φ is disconnected. 31 and Φ 32 And maintain Φ1, Φ2, Φ3, Φ 41 and Φ 42 The state remains unchanged; after the fourth preset time, Φ is disconnected. 41 and Φ 42 And maintain Φ1, Φ2, Φ3, Φ 31 and Φ 32 The state remains unchanged.

[0102] The present invention also provides an analog-to-digital converter, comprising: a latch unit, a SAR logic unit, and an ultra-high precision analog-to-digital converter sampling thermal noise cancellation circuit as provided in any of the above embodiments.

[0103] The present invention also provides a chip including an ultra-high precision analog-to-digital converter sampling thermal noise cancellation circuit as provided in any of the above embodiments.

[0104] The present invention also provides a chip including an analog-to-digital converter as provided in any of the above embodiments.

[0105] The present invention also provides an electronic device comprising a chip as provided in any of the above embodiments.

[0106] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. An ultra-high precision analog-to-digital converter sampling thermal noise cancellation circuit, comprising: The application relates to a high-precision analog-to-digital converter sampling thermal noise elimination circuit. The lower plate sampling network comprises an input signal switching unit and a sampling capacitor array connected in sequence, and the output end of the sampling capacitor array is connected with the input end of the amplification circuit. The input signal switching unit is used for switching the input signal of the lower plate sampling network between high level, low level and no signal. The amplification circuit comprises a first reset unit, a second reset unit, a noise decoupling unit, a charge distribution adjusting unit, a feedback path control unit and an operational amplifier U1, the first end of the first reset unit is connected with the first end of the noise decoupling unit and the input end of the operational amplifier U1 respectively, the second end of the first reset unit is connected with the third end of the charge distribution adjusting unit and the first end of the feedback path control unit respectively, the second end of the noise decoupling unit is connected with the first end of the charge distribution adjusting unit, the first end of the second reset unit and the second end of the charge distribution adjusting unit respectively, the fourth end of the second reset unit and the fourth end of the charge distribution adjusting unit are grounded, the first reset unit, the second reset unit, the noise decoupling unit and the charge distribution adjusting unit constitute a feedback path of the operational amplifier U1, and the input end of the operational amplifier U1 is the input end of the amplification circuit; the second end of the feedback path control unit is connected with the output end of the operational amplifier U1. The first reset unit is used for resetting the amplification circuit in an initial stage, the feedback path control unit is used for controlling the on-off state of the feedback path, the noise decoupling unit is used for realizing operational amplifier thermal noise and sampling thermal noise decoupling according to the change of the input signal of the lower plate sampling network after the feedback path is disconnected, and the second reset unit is used for changing the charge of the input end of the amplification circuit according to the change of the input signal of the lower plate sampling network after the feedback path is disconnected, so that the effect of eliminating noise is achieved. The first reset unit comprises a switch Phi1.

2. The circuit of claim 1, wherein, The charge distribution adjusting unit comprises capacitors C1 and C4. The second reset unit includes a switch Φ 41 ; The noise decoupling unit comprises capacitors C2, C3 and a switch Φ 31 ; The feedback path control unit comprises a switch Phi2. U1 is a high-gain static operational amplifier. Specifically, the first terminals of Φ1, C3, and C2 are all connected to the input terminal of U1. The second terminal of Φ1 is connected to the first terminal of Φ2 and the second terminal of C4, respectively. The second terminal of Φ2 is connected to the output terminal of U1. The second terminal of C3 is connected to the input terminal of Φ2. 31 The first end is connected, Φ 31 The second end is connected to the second end of C2, the first end of C1, and Φ respectively. 41 The first end of C4 is connected to the first end of C1, and the second end of C1 is connected to Φ. 41 Both of the second terminals are grounded, and the input terminal of U1 is the input terminal of the amplifier circuit.

3. The circuit of claim 2, wherein, The input signal switching unit includes a switch Φ 32 , Φ 42 , Where, Φ 32 The first end is the input end of the lower electrode sampling network, Φ 32 The second end is respectively with Φ 42 The first end is connected to the input end of the sampling capacitor array, Φ 42 The second terminal is grounded.

4. The circuit according to any of claims 1 to 3, characterized in that The gate of M7 is connected with the first output end of U3, and the source is connected with the first input end of U3 and the drain of M9 respectively.

5. The circuit of claim 4, wherein, U1 includes PMOS transistors M3, M4, M5 and M6, NMOS transistors M0, M1, M2, M7, M8, M9 and M 10 , capacitors C L1 and C L2 , and operational amplifiers U2 and U3; Wherein, the source of M0 is grounded, the gate is connected with external signal V b , the drain is connected with the source of M1 and the source of M2 respectively, The gate of M1 is connected to an external signal V in The drain of M1 is connected to the drain of M3, the source of M5 and the first input of U2, respectively. The gate of M2 is connected to an external signal V ip The drain of M2 is connected to the drain of M4, the source of M6 and the second input of U2, respectively. The sources of M3 and M4 are both connected to power supply V dd The gates of M3 and M4 are both connected to external signal V bp , The gate of M5 is connected to the first output of U2, and the drain of M5 is connected to the first end of C L1 and the drain of M7. The gate of M6 is connected to the second output of U2, and the drain of M6 is connected to the first end of C L2 and the drain of M8. The method is applied to the circuit as claimed in any one of claims 3-5, and the method comprises: The gate of M8 is connected to the second output of U3, and the source is connected to the two inputs of U3 respectively, and the drain is connected to the drain of M 10 7. M9 and M 10 The gates of M9 and M bn The sources are grounded.

6. A control method of a super-high-precision analog-to-digital converter sampling thermal noise cancellation circuit, characterized by, The application relates to a high-precision analog-to-digital converter sampling thermal noise elimination circuit. Control Φ1, Φ2, Φ 31 and Φ 32 Closed, Φ 41 and Φ 42 Open; After the first preset time duration, disconnect Φ1 and keep Φ2, Φ 31 , Φ 32 , Φ 41 and Φ 42 unchanged; After a second pre-set time duration, Φ2 is disconnected and Φ1, Φ 31 , Φ 32 , Φ 41 and Φ 42 remain unchanged. After a third preset time period, disconnect Φ 31 and Φ 32 and keep Φ1, Φ2, Φ3, Φ 41 and Φ 42 unchanged; After a fourth preset time period, disconnect Φ 41 and Φ 42 and keep Φ1, Φ2, Φ3, Φ 31 and Φ 32 unchanged.

7. An ultra-high precision analog-to-digital converter, characterized by The application relates to a high-precision analog-to-digital converter sampling thermal noise elimination circuit. The application relates to a high-precision analog-to-digital converter.

8. A chip, characterized by The application relates to a chip.

9. A chip, characterized by ​ 10. An electronic device, comprising: ​

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