Simulation speed measurement system, method, electronic device and storage medium

Abstract

The present invention provides a simulation speed measurement system, method, electronic device and storage medium, relating to the field of computer technology. The system includes: a host computer and a simulation tooling board, wherein the real tooling board includes a core processor, a field programmable logic gate array and a hardware circuit; the host computer is used to send a speed measurement instruction to the core processor; the core processor is used to determine a speed measurement mode and speed measurement simulation parameters according to the speed measurement instruction; when the speed measurement mode is a pulse width modulation control mode, the speed measurement simulation parameters are sent to the field programmable logic gate array; when the speed measurement mode is a current control mode, the speed measurement simulation parameters are sent to the hardware circuit to control the hardware circuit to perform simulation speed measurement in the current control mode; the field programmable logic gate array is used to control the hardware circuit to perform simulation speed measurement in the pulse width modulation control mode according to the speed measurement simulation parameters. The present invention can simultaneously support simulation speed measurement in both PWM and current control modes.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a simulation speed measurement system, method, electronic equipment and storage medium. Background Art

[0002] The technical complexity of train systems is increasing. Train systems consist of more than 40,000 subsystems and components, each with strong interdependencies and couplings. This means that a failure in a device or component can affect associated equipment or spare parts, causing fault propagation and, in severe cases, affecting the operation of the entire train. Therefore, to accurately analyze the safety and reliability of train systems, simulation and speed measurement of these systems is necessary. Summary of the Invention

[0003] In view of the problems existing in the prior art, embodiments of the present invention provide a simulation speed measurement system, method, electronic device and storage medium.

[0004] The present invention provides a simulation speed measurement system, comprising:

[0005] A host computer and a simulation tooling board, wherein the simulation tooling board includes a core processor, a field programmable logic gate array, and a hardware circuit;

[0006] The host computer is used to send the speed measurement instruction to the core processor;

[0007] The core processor is used to determine the speed measurement mode and speed measurement simulation parameters according to the speed measurement instruction; when the speed measurement mode is a pulse width modulation control mode, the speed measurement simulation parameters are sent to the field programmable logic gate array; when the speed measurement mode is a current control mode, the speed measurement simulation parameters are sent to the hardware circuit to control the hardware circuit to perform the simulation speed measurement of the current control mode;

[0008] The field programmable logic gate array is used to control the hardware circuit to perform the simulated speed measurement in the pulse width modulation control mode according to the speed measurement simulation parameters.

[0009] According to a simulation speed measurement system provided by the present invention, the core processor is specifically used to verify the speed measurement instruction; if the verification passes, the speed measurement method is obtained from the speed measurement instruction, and processing operations and logic code execution are performed based on the speed measurement method and the speed data carried in the speed measurement instruction to obtain speed measurement simulation parameters.

[0010] According to a simulation speed measurement system provided by the present invention, the hardware circuit includes two speed sensors, each of which includes three channels;

[0011] When the speed measurement method is a pulse width modulation control method, the speed measurement simulation parameters include the wheel diameter value, the minimum recognition speed parameter, the speed value of each channel, the phase value of each channel and the working configuration information, and the working configuration information includes channel enable, working mode and direct digital synthesizer enable.

[0012] According to a simulation speed measurement system provided by the present invention, the field programmable logic gate array is further used to calculate the frequency, duty cycle and phase difference under the pulse width modulation control mode based on the wheel diameter value, the minimum recognition speed parameter, the speed value of each channel, the phase value of each channel and the working configuration information; and according to the frequency, the duty cycle and the phase difference, control the hardware circuit to simulate the phase waveforms of the two speed sensors to perform simulation speed measurement using the pulse width modulation control mode.

[0013] According to a simulation speed measurement system provided by the present invention, the hardware circuit includes a signal operational amplifier circuit, a signal filtering and conditioning circuit, a power supply circuit and an isolation circuit. The power supply circuit and the isolation circuit are set based on the connection characteristics of the speed sensor and the interfaces of various components.

[0014] According to a simulation speed measurement system provided by the present invention, the hardware circuit is further used to collect signals for the simulation speed measurement to obtain a collected waveform; and send the collected waveform to the host computer.

[0015] According to a simulation speed measurement system provided by the present invention, the hardware circuit is further configured to feed back the collected waveform to the field programmable logic gate array when the speed measurement mode is a pulse width modulation control mode; and feed back the collected waveform to the core processor when the speed measurement mode is a current control mode;

[0016] The field programmable logic gate array is further configured to determine an actual speed value of each channel, an actual phase value of each channel, and actual working configuration information based on the collected waveform; and send the actual speed value, the actual phase value, and the actual working configuration information to the core processor;

[0017] The core processor is also used to generate test result information based on the speed value, the actual phase value and the actual working configuration information when the speed measurement mode is a pulse width modulation control mode; generate test result information based on the collected waveform when the speed measurement mode is a current control mode; and send the test result information to the host computer.

[0018] According to the simulation speed measurement system provided by the present invention, the host computer is further used to analyze the test result information and determine the speed control data.

[0019] According to a simulation speed measurement system provided by the present invention, the hardware circuit is also used to perform digital input testing and digital output testing.

[0020] The present invention also provides a simulation speed measurement method, comprising:

[0021] Send the speed measurement instruction to the core processor through the host computer;

[0022] Determining the speed measurement mode and speed measurement simulation parameters according to the speed measurement instruction by the core processor;

[0023] When the speed measurement mode is a current control mode, controlling the hardware circuit to perform simulation speed measurement of the current control mode according to the speed measurement simulation parameters;

[0024] Alternatively, when the speed measurement method is a pulse width modulation control method, the speed measurement simulation parameters are sent to a field programmable logic gate array through the core processor; and the field programmable logic gate array controls the hardware circuit to perform simulated speed measurement of the pulse width modulation control method according to the speed measurement simulation parameters.

[0025] The present invention also provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, any one of the above-described simulation speed measurement methods is implemented.

[0026] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the simulation speed measurement method described above is implemented.

[0027] The present invention also provides a computer program product, comprising a computer program, wherein when the computer program is executed by a processor, the computer program implements any of the above-mentioned simulation speed measurement methods.

[0028] The simulation speed measurement system, method, electronic device, and storage medium provided by the present invention are configured to send a speed measurement instruction to a core processor via a host computer; the core processor is configured to determine a speed measurement mode and speed measurement simulation parameters based on the speed measurement instruction; when the speed measurement mode is a pulse width modulation control mode, the speed measurement simulation parameters are sent to a field programmable logic gate array; when the speed measurement mode is a current control mode, the speed measurement simulation parameters are sent to the core processor to control a hardware circuit to perform simulation speed measurement using the current control mode; the field programmable logic gate array is configured to control the hardware circuit to perform simulation speed measurement using the pulse width modulation control mode based on the speed measurement simulation parameters. The present invention can simultaneously support simulation speed measurement using both PWM and current control modes, enabling simulation testing of speed sensors to be completed using a single test environment.

[0029] On this basis, it also supports train speed simulation, simulated train travel distance calculation, and train arrival auxiliary detection; it can meet the needs of train speed simulation system, greatly shorten the R&D cycle, and save development costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions in the present invention or the prior art, a brief introduction is given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0031] Figure 1 It is a structural diagram of the simulation speed measurement system provided by the present invention;

[0032] Figure 2 It is a transmission schematic diagram of the rapid transmission analog signal provided by the present invention;

[0033] Figure 3 It is a schematic flow chart of the simulation speed measurement system provided by the present invention;

[0034] Figure 4 It is a structural schematic diagram of the electronic device provided by the present invention. DETAILED DESCRIPTION

[0035] To make the objectives, technical solutions, and advantages of the present invention more clear, the technical solutions of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the embodiments described are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0036] In order to facilitate a clearer understanding of the embodiments of the present invention, some relevant knowledge is first introduced as follows.

[0037] Most train test simulation tools only support either pulse width modulation (PWM) or current control. During the R&D process, if testing two speed sensors is required, two different test tools are required.

[0038] Train simulation methods in related technologies can only simulate one transmission method to simulate vehicle speed, namely motor speed. They only support current control for train speed, lacking PWM control, and lack the digital input (DI) and digital output (DO) testing capabilities of the Automatic Train Protection (ATP) system.

[0039] The following combination Figures 1-4 The simulation speed measurement system, method, electronic device and storage medium of the present invention are described.

[0040] Figure 1 This is a schematic diagram of the structure of the simulation speed measurement system provided by the present invention, see Figure 1 As shown, it includes a host computer 110 and a simulation tooling board 120, and the simulation tooling board includes a core processor 121, a field programmable logic gate array 122 and a hardware circuit 123;

[0041] The host computer 110 is used to send the speed measurement instruction to the core processor 121;

[0042] The core processor 121 is used to determine the speed measurement mode and speed measurement simulation parameters according to the speed measurement instruction; when the speed measurement mode is the pulse width modulation control mode, the speed measurement simulation parameters are sent to the field programmable logic gate array 122; when the speed measurement mode is the current control mode, the speed measurement simulation parameters are sent to the hardware circuit 123 to control the hardware circuit 123 to perform the simulation speed measurement of the current control mode;

[0043] The field programmable logic gate array 122 is used to control the hardware circuit 123 to perform the simulation speed measurement in the pulse width modulation control mode according to the speed measurement simulation parameters.

[0044] Specifically, the host computer, or host computer simulation software, is deployed on a PC (Personal Computer) or industrial computer. The core processor, or CPU (Central Processing Unit), serves as the computing and control core of the computer system and is the final execution unit for information processing and program execution. A field-programmable gate array (FPGA), a semi-custom circuit within an application-specific integrated circuit (ASIC), is a programmable logic array that effectively addresses the limited gate count of existing devices.

[0045] In practical applications, see Figure 1, the host computer and the core processor exchange information through RS232, where the RS232 interface is one of the communication interfaces on personal computers and is an asynchronous transmission standard interface developed by the Electronic Industries Association (EIA). The CPU logic processing is responsible for the interaction of data instructions with the host computer through RS232, that is, receiving the speed measurement instructions issued by the host computer through RS232. Furthermore, the core processor can process the speed measurement instructions and run the logic code to obtain the speed measurement method and speed measurement simulation parameters. Among them, there are two speed measurement methods, one is the PWM control method, and the other is the current control method. The speed measurement simulation parameters refer to the parameters set for speed measurement simulation.

[0046] When the speed measurement mode is PWM control mode, the core processor will send the speed measurement simulation parameters to the field programmable logic gate array; the field programmable logic gate array is used to control the hardware circuit according to the speed measurement simulation parameters and perform simulated speed measurement in pulse width modulation control mode.

[0047] When the speed measurement method is current control method, the core processor can directly control the hardware circuit according to the speed measurement simulation parameters to perform simulated speed measurement in current control method, that is, the speed measurement simulation parameters are sent to the hardware circuit, and the hardware circuit performs simulated speed measurement in current control method based on the speed measurement simulation parameters.

[0048] It should be noted that the core processor and the field programmable gate array communicate through an interface. To increase the reading speed, preferably, the core processor and the field programmable gate array communicate through the FMC (FPGA Mezzanine Card) interface. Furthermore, when the host computer and the tooling simulation board communicate based on the RS232 communication protocol and communication mechanism, the following conditions must be met: 1) Use a specific communication message format, including a special start frame, check frame, and tooling speed measurement parameter frame; 2) Require a specific packet sequence to ensure that error frames are identified in a timely manner during transmission to avoid serious test errors caused by the incorrect use of error frames.

[0049] In addition, the host computer can also receive data uploaded by the core processor. The field programmable logic gate array can also measure or collect modulated pulses input from the outside.

[0050] The simulation speed measurement system provided by the present invention uses a host computer to send a speed measurement instruction to a core processor; the core processor is used to determine a speed measurement mode and speed measurement simulation parameters based on the speed measurement instruction; when the speed measurement mode is a pulse width modulation control mode, the speed measurement simulation parameters are sent to a field programmable logic gate array; when the speed measurement mode is a current control mode, the speed measurement simulation parameters are sent to the core processor to control the hardware circuit to perform simulation speed measurement using the current control mode; the field programmable logic gate array is used to control the hardware circuit to perform simulation speed measurement using the pulse width modulation control mode based on the speed measurement simulation parameters. The present invention can simultaneously support simulation speed measurement using both PWM and current control modes, enabling simulation testing of speed sensors to be completed using a single test environment.

[0051] On this basis, it also supports train speed simulation, simulated train travel distance calculation, and train arrival auxiliary detection; it can meet the needs of train speed simulation system, greatly shorten the R&D cycle, and save development costs.

[0052] In one or more optional embodiments of the present invention, the core processor 121 is specifically used to verify the speed measurement instruction; if the verification passes, the speed measurement method is obtained from the speed measurement instruction, and processing operations and logic code execution are performed based on the speed measurement method and the speed data carried in the speed measurement instruction to obtain speed measurement simulation parameters.

[0053] In actual applications, the host computer may not have the simulation speed measurement permission or the speed measurement instruction may contain data errors. Therefore, after receiving the speed measurement instruction, the core processor can verify the host computer's simulation speed measurement permission and / or the reliability of the data in the speed measurement instruction (whether the data is accurate or correct) based on the speed measurement instruction.

[0054] If the verification fails, the core processor may not respond to the speed measurement instruction, that is, may not perform the simulation speed measurement, or the core processor may feed back the verification result and / or error information to the host computer.

[0055] If verification passes, the core processor responds to the speed measurement instruction by obtaining the speed measurement mode from the instruction. For example, the core processor obtains the test mode identifier from the speed measurement mode flag in the instruction, thereby determining the speed measurement mode. Furthermore, based on the speed measurement mode and the speed data contained in the instruction (such as the required speed and duration), the core processor performs processing operations and executes logic code to obtain speed measurement simulation parameters (such as PWM control data or current control data).

[0056] In this way, verifying the speed measurement instruction can not only ensure the reliability and accuracy of the simulation speed measurement, but also reject the simulation speed measurement if the verification fails, thereby reducing the data processing amount to a certain extent.

[0057] In one or more optional embodiments of the present invention, the hardware circuit 123 includes two speed sensors, each of which includes three channels;

[0058] When the speed measurement method is a pulse width modulation control method, the speed measurement simulation parameters include the wheel diameter value, the minimum recognition speed parameter, the speed value of each channel, the phase value of each channel and the working configuration information, and the working configuration information includes channel enable, working mode and direct digital synthesizer enable.

[0059] In actual applications, the simulation speed measurement system supports the analog output of two speed sensors (referred to as speed transmitters). A single speed transmitter includes 3 channels, and two speed transmitters have a total of 6 channels for waveform simulation.

[0060] The field-programmable gate array uses the Verilog HDL language and exchanges data and instructions with the core processor via the FMC interface. The core processor transmits wheel diameter values, minimum recognition speed parameters, speed and phase values ​​for each channel, and operating configuration information to the core processor via the FMC interface. The operating configuration information includes three parameters: channel enable, operating mode, and direct digital synthesizer (DDS) enable. This improves the accuracy and efficiency of simulation speed measurement.

[0061] In addition, the two speed sensors can be used in both PWM control mode and current control mode, and the present invention does not impose any limitation on this.

[0062] In one or more optional embodiments of the present invention, the field programmable logic gate array 122 is further used to calculate the frequency, duty cycle and phase difference under the pulse width modulation control mode based on the wheel diameter value, the minimum recognition speed parameter, the speed value of each channel, the phase value of each channel and the working configuration information; and control the hardware circuit 123 to simulate the phase waveforms of two speed sensors based on the frequency, the duty cycle and the phase difference to perform simulated speed measurement of the pulse width modulation control mode.

[0063] In actual applications, after receiving the wheel diameter value, minimum recognition speed parameter, speed value of each channel, phase value of each channel and working configuration information, the field programmable logic gate array can further calculate based on these speed measurement simulation parameters to obtain the frequency, duty cycle and phase difference of the control waveform, that is, the frequency, duty cycle and phase difference under the pulse width modulation control method, that is, the specific signal. Furthermore, after the general-purpose input / output (GPIO) port of the field programmable logic gate array outputs a specific signal, the hardware circuit can generate a simulated speed waveform, that is, realize the simulated speed measurement of the pulse width modulation control method. In this way, the accuracy and efficiency of the simulated speed measurement can be improved.

[0064] In one or more optional embodiments of the present invention, the hardware circuit 123 includes a signal operational amplifier circuit, a signal filtering and conditioning circuit, a power supply circuit and an isolation circuit, and the power supply circuit and the isolation circuit are set based on the connection characteristics of the speed sensor and the interfaces of each component.

[0065] In practical applications, the hardware circuit includes a signal amplifier (signal operational amplifier circuit), a signal filtering and conditioning circuit, and a power supply and isolation circuit designed based on the connection characteristics of the speed sensor and various electrical interfaces (component interfaces). This ensures the accuracy and safety of the hardware circuit's simulated speed waveform.

[0066] In one or more optional embodiments of the present invention, the hardware circuit 123 is further configured to collect signals for the simulated speed measurement to obtain a collected waveform; and send the collected waveform to the host computer.

[0067] In actual applications, the simulation speed measurement system can also measure the analog output, that is, collect the signal of the simulation speed measurement, and then send the collected waveform to the host computer for easy viewing by the staff.

[0068] It should be noted that when the speed measurement method is pulse width modulation control method, the hardware circuit can send the acquired waveform to the field programmable logic gate array, which will forward it to the core processor, and then the core processor will forward the acquired waveform to the host computer; when the speed measurement method is current control method, the hardware circuit can send the acquired waveform directly to the core processor, and then the core processor will forward the acquired waveform to the host computer.

[0069] In one or more optional embodiments of the present invention, the hardware circuit 123 is further configured to feed back the collected waveform to the field programmable logic gate array 122 when the speed measurement mode is a pulse width modulation control mode; and to feed back the collected waveform to the core processor 121 when the speed measurement mode is a current control mode;

[0070] The field programmable logic gate array 122 is further configured to determine the actual speed value of each channel, the actual phase value of each channel, and actual working configuration information based on the collected waveform; and send the actual speed value, the actual phase value, and the actual working configuration information to the core processor 121;

[0071] The core processor 121 is also used to generate test result information based on the speed value, the actual phase value and the actual working configuration information when the speed measurement mode is a pulse width modulation control mode; generate test result information based on the collected waveform when the speed measurement mode is a current control mode; and send the test result information to the host computer.

[0072] The hardware circuit 123 is further configured to feed back the collected waveform to the field programmable logic gate array 122 when the speed measurement mode is a pulse width modulation control mode; and to feed back the collected waveform to the core processor 121 when the speed measurement mode is a current control mode.

[0073] The field programmable logic gate array 122 is further configured to determine the actual speed value of each channel, the actual phase value of each channel, and actual working configuration information based on the collected waveform; and send the actual speed value, the actual phase value, and the actual working configuration information to the core processor 121;

[0074] The core processor 121 is also used to generate test result information based on the speed value, the actual phase value and the actual working configuration information when the speed measurement mode is a pulse width modulation control mode; generate test result information based on the collected waveform when the speed measurement mode is a current control mode; and send the test result information to the host computer.

[0075] In practical applications, PWM or DC current sampling and measurement is performed through hardware circuits. The PWM acquisition hardware circuit consists of an input isolation module, a signal amplification and filtering circuit, and a signal conditioning circuit. The signal is acquired via the CPU's GPIO pins, generating the acquired waveform. The DC (direct current) current acquisition hardware circuit consists of an input isolation module, a V / I circuit, a multiplication circuit, and a filtering circuit.

[0076] When the speed measurement mode is current control, the hardware circuit sends the collected waveform to the core processor, which processes the waveform. For example, the voltage signal of the collected waveform is converted to an analog-to-digital converter (A / D) by the core processor's built-in ADC to obtain the test result information. The final analog data collected (test result information) is uploaded to the host computer via RS232.

[0077] When the speed measurement mode is pulse-width modulation (PWM), the hardware circuit sends the collected waveform to the field-programmable gate array (FPGA). The FPGA processes the collected waveform, determining the actual speed value, actual phase value, and actual operating configuration information for each channel based on the collected waveform. These values ​​are then sent to the core processor. Furthermore, the core processor determines the test results based on these values. The final analog acquisition data (test results) is then uploaded to the host computer via RS232.

[0078] In one or more optional embodiments of the present invention, the host computer is further configured to parse the test result information and determine speed control data.

[0079] After the host computer receives the data (test result information) uploaded by the simulation tooling board, it can calculate the speed control data issued by ATP according to the formula, and determine the vehicle's running speed and position at this time according to the application scenario code logic.

[0080] When the speed measurement mode is current control mode, see Figure 1 The hardware circuit 123 is also used to perform digital input testing and digital output testing.

[0081] The simulation speed measurement system provided by the present invention is further described below.

[0082] The simulation speed measurement system includes a host computer, a CPU logic processing unit, an FPGA computing unit, and hardware circuits including signal generation, acquisition circuits and related working power supplies.

[0083] The CPU logic processing is responsible for verifying and interacting with the host computer through RS232, processing and operating the instructions issued by the host computer and running the logic code, collecting analog signals, packaging and sending data information messages.

[0084] The FPGA computing unit, using Verilog HDL, exchanges data and instructions with the logic processing unit (CPU) through the FMC interface. The CPU transmits wheel diameter, minimum recognition speed parameter, speed and phase values ​​for each channel, and operating configuration information. The operating configuration information includes three parameters: channel enable, operating mode, and DDS enable.

[0085] The CPU can read the actual speed value and actual phase value of each channel of the FPGA computing unit, as well as the actual working configuration information, through the FMC interface.

[0086] The FPGA unit calculates speed and phase data, generating two simulated speed waveforms through hardware circuitry. This hardware circuitry consists of a signal amplifier, signal filtering and conditioning circuitry, and a power supply and isolation circuit designed based on the speed sensor's characteristics and electrical interface. This hardware circuitry generates simulated speed waveforms by causing the FPGA's GPIO to output specific signals (PWM timing, implementing high and low level changes).

[0087] The speed sensor waveform is collected by the ATP speed measurement to generate speed collection information.

[0088] The speed measuring tool measures the analog output of the ATO (Automatic Train Operation) system and samples and measures PWM and DC current through a hardware circuit. The PWM acquisition hardware circuit consists of an input isolation module, a signal amplification and filtering circuit, and a signal conditioning circuit, and is collected through the CPU's GPIO pins.

[0089] The DC circuit acquisition hardware circuit consists of an input isolation module, a V / I circuit, a multiplication circuit, and a filter circuit. The final voltage signal is converted to A / D by the CPU's built-in ADC. The final analog acquisition data is uploaded to the host computer via RS232.

[0090] After the upper computer receives the data uploaded by the speed measuring tool, it can calculate the speed control data issued by ATP according to the formula, and determine the train running speed and position at this time according to the application scenario code logic.

[0091] The simulation speed measurement system provided by the present invention supports analog output of two speed transmissions, and a single speed transmission includes 3 channels, for a total of 6 channels of channel waveform simulation.

[0092] It can be applied to the train FAO (Fully Automatic Operation) system speed measurement simulation test fixture, ATO system analog output measurement, train ATO, ATP and AOM (Application Operations Management) platform software verification and debugging simulation device.

[0093] The train FAO system platform hardware serves as a companion test device to test the IO boards of the FAO system ATP system and ATO system, and to test the software and hardware functions of the ATP system; the train FAO system platform software serves as a companion test device;

[0094] The simulation speed measurement system supports DI and DO functional testing of the train ATP system; the DI board, relay normally open contacts, and normally closed contacts provide train ATP system output simulation; the DO board, relay normally open contacts and normally closed contacts provide train ATP system input simulation. The host computer software can control the speed transmission simulation board to emit speed pulses that simulate speed transmission. PWM and DC direct current analog quantities can be collected by the speed transmission simulation board and uploaded to the host computer via RS232. This function collects ATO output analog quantities. The host computer sends control commands to control the speed simulation board to simulate two-way speed transmission pulses with adjustable speed and phase difference. Each speed transmission contains three speed channels.

[0095] See also Figure 2 , Figure 2 This is a transmission diagram of the fast-transmitted analog signal provided by the present invention: the fast-transmitted analog signal is transmitted from the PC end (host computer) of the speed measurement software control device to the speed measurement tooling device (simulation tooling board), and then transmitted from the speed measurement tooling device to the train speed sensor acquisition device, and then transmitted from the train speed sensor acquisition device to the train data processing platform, and then fed back to the PC end of the speed measurement software control device by the train data processing platform.

[0096] The simulation speed measurement system design provided in this embodiment has the function of simulating train speed and direction; it can output train speed control analog quantity, supports PWM and current output, and has analog quantity output recovery function; it can simulate and output two-way speed sensor waveforms with adjustable frequency, adjustable duty cycle, and adjustable phase; and provides test tooling, debugging equipment, product demonstration equipment, hardware testing equipment, and software testing equipment.

[0097] On this basis, it also supports train speed simulation, simulated train travel distance calculation, and train arrival auxiliary detection; it can meet the FAO system's needs for a train speed simulation system, greatly shortening the R&D cycle and saving development costs.

[0098] The simulation speed measurement method provided by the present invention is described below. The simulation speed measurement method described below and the simulation speed measurement system described above can be referenced to each other.

[0099] Figure 3 This is a flow chart of the simulation speed measurement system provided by the present invention, see Figure 3 As shown, it includes steps 301 to 304, wherein:

[0100] Step 301: Send the speed measurement instruction to the core processor via the host computer.

[0101] First of all, it should be noted that the execution subject of the present invention can be any electronic device that performs simulation speed measurement, for example, it can be any one of a smart phone, a smart watch, a desktop computer, a laptop computer, etc.

[0102] Step 302: Determine the speed measurement mode and speed measurement simulation parameters according to the speed measurement instruction through the core processor.

[0103] Step 303: When the speed measurement mode is a current control mode, controlling the hardware circuit to perform simulation speed measurement of the current control mode according to the speed measurement simulation parameters;

[0104] Step 304: Alternatively, when the speed measurement method is a pulse width modulation control method, the speed measurement simulation parameters are sent to a field programmable logic gate array through the core processor; and the field programmable logic gate array controls the hardware circuit to perform simulated speed measurement of the pulse width modulation control method according to the speed measurement simulation parameters.

[0105] The simulation speed measurement method provided by the present invention includes sending a speed measurement instruction to a core processor via a host computer; determining a speed measurement mode and speed measurement simulation parameters via the core processor based on the speed measurement instruction; controlling a hardware circuit to perform simulation speed measurement using the current control mode based on the speed measurement simulation parameters when the speed measurement mode is a current control mode; or, if the speed measurement mode is a pulse width modulation control mode, sending the speed measurement simulation parameters to a field programmable logic gate array via the core processor; controlling the hardware circuit to perform simulation speed measurement using the pulse width modulation control mode based on the speed measurement simulation parameters via the field programmable logic gate array. The present invention can simultaneously support simulation speed measurement using both PWM and current control modes, thereby enabling simulation testing of speed sensors to be completed using a single test environment.

[0106] On this basis, it also supports train speed simulation, simulated train travel distance calculation, and train arrival auxiliary detection; it can meet the needs of train speed simulation system, greatly shorten the R&D cycle, and save development costs.

[0107] In one or more optional embodiments of the present invention, before determining the speed measurement mode and the speed measurement simulation parameters according to the speed measurement instruction by the core processor, the method further includes:

[0108] Verifying the speed measurement instruction by the core processor;

[0109] Accordingly, the determining of the speed measurement mode and the speed measurement simulation parameters according to the speed measurement instruction by the core processor includes:

[0110] If the verification is passed, the core processor obtains the speed measurement mode from the speed measurement instruction, and performs processing operations and logic code execution according to the speed measurement mode and the speed data carried in the speed measurement instruction to obtain speed measurement simulation parameters.

[0111] In one or more optional embodiments of the present invention, the hardware circuit includes two speed sensors, each of which includes three channels;

[0112] When the speed measurement method is a pulse width modulation control method, the speed measurement simulation parameters include the wheel diameter value, the minimum recognition speed parameter, the speed value of each channel, the phase value of each channel and the working configuration information, and the working configuration information includes channel enable, working mode and direct digital synthesizer enable.

[0113] In one or more optional embodiments of the present invention, controlling the hardware circuit to perform the simulated speed measurement using the pulse width modulation control method according to the speed measurement simulation parameters through the field programmable logic gate array includes:

[0114] Calculating the frequency, duty cycle, and phase difference under the pulse width modulation control mode by the field programmable logic gate array according to the wheel diameter value, the minimum identification speed parameter, the speed value of each channel, the phase value of each channel, and the working configuration information;

[0115] The field programmable logic gate array controls the hardware circuit to simulate the phase waveforms of two speed sensors according to the frequency, the duty cycle and the phase difference, so as to perform simulated speed measurement in the pulse width modulation control mode.

[0116] In one or more optional embodiments of the present invention, the hardware circuit includes a signal operational amplifier circuit, a signal filtering and conditioning circuit, a power supply circuit and an isolation circuit, and the power supply circuit and the isolation circuit are set based on the connection characteristics of the speed sensor and the interfaces of each component.

[0117] In one or more optional embodiments of the present invention, the present invention further includes:

[0118] Performing signal acquisition on the simulated speed measurement by the hardware circuit to obtain an acquisition waveform;

[0119] The collected waveform is sent to the host computer through the hardware circuit.

[0120] In one or more optional embodiments of the present invention, the present invention further includes:

[0121] When the speed measurement mode is a pulse width modulation control mode, the collected waveform is fed back to the field programmable logic gate array through the hardware circuit; when the speed measurement mode is a current control mode, the collected waveform is fed back to the core processor;

[0122] determining, by the field programmable logic gate array, an actual speed value of each channel, an actual phase value of each channel, and actual working configuration information based on the collected waveform; and sending the actual speed value, the actual phase value, and the actual working configuration information to the core processor;

[0123] When the speed measurement mode is a pulse width modulation control mode, the core processor generates test result information according to the speed value, the actual phase value and the actual working configuration information; when the speed measurement mode is a current control mode, the core processor generates test result information according to the collected waveform; and sends the test result information to the host computer.

[0124] In one or more optional embodiments of the present invention, the present invention further includes:

[0125] The host computer analyzes the test result information to determine the speed control data.

[0126] In one or more optional embodiments of the present invention, the present invention further includes:

[0127] Digital input test and digital output test are performed through the hardware circuit.

[0128] Figure 4 An example of a physical structure diagram of an electronic device is shown below. Figure 4As shown, the electronic device may include: a processor 410, a communication interface 420, a memory 430 and a communication bus 440, wherein the processor 410, the communication interface 420 and the memory 430 communicate with each other via the communication bus 440. The processor 410 may call the logic instructions in the memory 430 to execute a simulation speed measurement method, which includes: sending a speed measurement instruction to a core processor via a host computer; determining a speed measurement mode and a speed measurement simulation parameter according to the speed measurement instruction by the core processor; when the speed measurement mode is a current control mode, controlling the hardware circuit to perform simulation speed measurement of the current control mode according to the speed measurement simulation parameter; or, when the speed measurement mode is a pulse width modulation control mode, sending the speed measurement simulation parameter to a field programmable logic gate array via the core processor; and controlling the hardware circuit to perform simulation speed measurement of the pulse width modulation control mode according to the speed measurement simulation parameter by the field programmable logic gate array.

[0129] In addition, the logic instructions in the above-mentioned memory 430 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when sold or used as an independent product. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0130] On the other hand, the present invention also provides a computer program product, which includes a computer program, which can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the simulation speed measurement method provided by the above methods, which includes: sending a speed measurement instruction to a core processor through a host computer; determining a speed measurement mode and speed measurement simulation parameters according to the speed measurement instruction through the core processor; when the speed measurement mode is a current control mode, controlling the hardware circuit to perform simulation speed measurement of the current control mode according to the speed measurement simulation parameters; or, when the speed measurement mode is a pulse width modulation control mode, sending the speed measurement simulation parameters to a field programmable logic gate array through the core processor; and controlling the hardware circuit to perform simulation speed measurement of the pulse width modulation control mode according to the speed measurement simulation parameters through the field programmable logic gate array.

[0131] On the other hand, the present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, is implemented to execute the simulation speed measurement method provided by the above-mentioned methods, the method comprising: sending a speed measurement instruction to a core processor through a host computer; determining a speed measurement mode and speed measurement simulation parameters according to the speed measurement instruction through the core processor; when the speed measurement mode is a current control mode, controlling the hardware circuit to perform simulation speed measurement of the current control mode according to the speed measurement simulation parameters; or, when the speed measurement mode is a pulse width modulation control mode, sending the speed measurement simulation parameters to a field programmable logic gate array through the core processor; and controlling the hardware circuit to perform simulation speed measurement of the pulse width modulation control mode according to the speed measurement simulation parameters through the field programmable logic gate array.

[0132] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, i.e., they may be located in one location or distributed across multiple network units. Some or all of the modules may be selected based on actual needs to achieve the objectives of the present embodiment. Persons of ordinary skill in the art will be able to understand and implement the present invention without inventive effort.

[0133] Through the description of the above embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus a necessary general hardware platform, or of course, by hardware. Based on this understanding, the essence of the above technical solution or the part that contributes to the existing technology can be embodied in the form of a software product. The computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a magnetic disk, an optical disk, etc., and includes a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or certain parts of the embodiments.

[0134] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A simulation speed measurement system, characterized in that: include: A host computer and a simulation tooling board, wherein the simulation tooling board includes a core processor, a field programmable logic gate array, and a hardware circuit; The host computer is used to send the speed measurement instruction to the core processor; The core processor is used to determine the speed measurement mode and speed measurement simulation parameters according to the speed measurement instruction; When the speed measurement mode is a pulse width modulation control mode, sending the speed measurement simulation parameters to the field programmable logic gate array; When the speed measurement mode is a current control mode, sending the speed measurement simulation parameter to the hardware circuit to control the hardware circuit to perform the simulation speed measurement in the current control mode; The field programmable logic gate array is used to control the hardware circuit to perform the simulation speed measurement of the pulse width modulation control mode according to the speed measurement simulation parameters; The hardware circuit is further configured to collect signals for the simulated speed measurement to obtain a collected waveform; and to send the collected waveform to the host computer; and to feed back the collected waveform to the field programmable logic gate array when the speed measurement mode is a pulse width modulation control mode; and to feed back the collected waveform to the core processor when the speed measurement mode is a current control mode. The field programmable logic gate array is further configured to determine an actual speed value of each channel, an actual phase value of each channel, and actual working configuration information based on the collected waveform; and send the actual speed value, the actual phase value, and the actual working configuration information to the core processor; The core processor is further configured to generate test result information according to the speed value, the actual phase value and the actual working configuration information when the speed measurement mode is a pulse width modulation control mode; When the speed measurement mode is a current control mode, generating test result information according to the collected waveform; The test result information is sent to the host computer.

2. The simulation speed measurement system according to claim 1, characterized in that: The core processor is specifically used to verify the speed measurement instruction; if the verification passes, the speed measurement method is obtained from the speed measurement instruction, and processing operations and logic code execution are performed according to the speed measurement method and the speed data carried in the speed measurement instruction to obtain speed measurement simulation parameters.

3. The simulation speed measurement system according to claim 1 or 2, characterized in that: The hardware circuit includes two speed sensors, each of which includes three channels; When the speed measurement method is a pulse width modulation control method, the speed measurement simulation parameters include the wheel diameter value, the minimum recognition speed parameter, the speed value of each channel, the phase value of each channel and the working configuration information, and the working configuration information includes channel enable, working mode and direct digital synthesizer enable.

4. The simulation speed measurement system according to claim 3, characterized in that: The field programmable logic gate array is further configured to calculate the frequency, duty cycle, and phase difference under the pulse width modulation control mode according to the wheel diameter value, the minimum identification speed parameter, the speed value of each channel, the phase value of each channel, and the working configuration information; According to the frequency, the duty cycle and the phase difference, the hardware circuit is controlled to simulate the phase waveforms of two speed sensors to perform simulated speed measurement using the pulse width modulation control method.

5. The simulation speed measurement system according to claim 3, characterized in that: The hardware circuit includes a signal operational amplifier circuit, a signal filtering and conditioning circuit, a power supply circuit and an isolation circuit. The power supply circuit and the isolation circuit are set based on the connection characteristics of the speed sensor and the interfaces of various components.

6. The simulation speed measurement system according to claim 1, characterized in that: The host computer is also used to analyze the test result information and determine speed control data.

7. The simulation speed measurement system according to claim 1 or 2, characterized in that: The hardware circuit is also used to perform digital input testing and digital output testing.

8. A simulation speed measurement method, characterized in that: include: Send the speed measurement instruction to the core processor through the host computer; Determining the speed measurement mode and speed measurement simulation parameters according to the speed measurement instruction by the core processor; When the speed measurement mode is a current control mode, controlling the hardware circuit to perform simulation speed measurement of the current control mode according to the speed measurement simulation parameters; Alternatively, when the speed measurement mode is a pulse width modulation control mode, the speed measurement simulation parameters are sent to a field programmable logic gate array through the core processor; Controlling the hardware circuit to perform the simulation speed measurement in the pulse width modulation control mode according to the speed measurement simulation parameters through the field programmable logic gate array; The method further comprises: Performing signal acquisition on the simulated speed measurement by the hardware circuit to obtain an acquisition waveform; Sending the collected waveform to the host computer through the hardware circuit; When the speed measurement mode is a pulse width modulation control mode, the collected waveform is fed back to the field programmable logic gate array through the hardware circuit; when the speed measurement mode is a current control mode, the collected waveform is fed back to the core processor; determining, by the field programmable logic gate array, an actual speed value of each channel, an actual phase value of each channel, and actual working configuration information based on the collected waveform; and sending the actual speed value, the actual phase value, and the actual working configuration information to the core processor; When the speed measurement mode is a pulse width modulation control mode, the core processor generates test result information according to the speed value, the actual phase value and the actual working configuration information; when the speed measurement mode is a current control mode, the core processor generates test result information according to the collected waveform; and sends the test result information to the host computer.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the program, the simulation speed measurement method as claimed in claim 8 is implemented.

10. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the simulation speed measurement method as claimed in claim 8 is implemented.

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