Implementation Method of Sampling Working Mode for a Radio Signal Storage and Playback Device

Abstract

The present invention discloses a method for implementing a sampling working mode of a radio signal storage and playback device. The sampling working mode includes a recording and playback working mode. The recording and playback working mode is divided into raw IQ data recording and playback and narrowband IQ data recording and playback based on different data sources. The implementation of raw IQ data recording and playback includes transmitting real-time sampling data to a storage and playback control module through a digital frequency shift control module of an FPGA processor. The storage and playback control module performs abnormal signal recognition, data packaging, and interface protocol conversion processing on the real-time sampling data. When performing data playback, the storage and playback control module reads data from a DDR3 storage chip according to the required data volume set by the host computer, and performs data rate matching to make the playback data match the rate of the real-time sampling data and send it to a digital signal processing module for processing. The processed data is respectively transmitted to a digital walkie-talkie for playback or to the host computer for real-time spectrum display.

Description

[0001] Division Case Explanation:

[0002] This application is a divisional application of a Chinese application with an application date of May 6, 2022, an application number of 202210478282.0, and an invention title of "A Radio Signal Storage and Playback Device". Technical Field

[0003] This specification relates to the field of radio monitoring, and particularly to a method for implementing a sampling working mode of a radio signal storage and playback device. Background Art

[0004] With the development of society, wireless communication plays an increasingly important role in national security and people's livelihood. A radio signal storage and playback device is used for searching, measuring, analyzing, and identifying radio signals, as well as direction finding and positioning of radiation sources, and is an important part of wireless communication technology. As the radio environment becomes more and more complex, relevant technical indicators such as the sensitivity, stability, miniaturization, bandwidth, and analysis speed of the monitoring system also need to be upgraded accordingly. In particular, some application scenarios for offline analysis have been added.

[0005] Therefore, it is desired to provide a spectrum analysis device, method, and storage medium for a radio signal storage and playback device, which can achieve classified storage management of data sources, identification and storage of abnormal signals, and matching of playback rates through an FPGA processor, enriching the offline analysis function of radio signals. Summary of the Invention

[0006] One or more embodiments of this specification provide a method for implementing a sampling working mode of a radio signal storage and playback device. The radio signal storage and playback device includes: a radio frequency front end, an AD data acquisition module, an FPGA processor, a DDR3 storage chip, a digital walkie-talkie, and a host computer; the radio frequency front end is communicatively connected to the AD data acquisition module, and the radio frequency front end is configured to receive a signal to be analyzed through an antenna and perform at least one of amplification, filtering, and frequency mixing on the signal to be analyzed to obtain an intermediate frequency signal; the AD data acquisition module is communicatively connected to the FPGA processor, and the AD data acquisition module is configured to sample the intermediate frequency signal and upload the obtained sampled data to the FPGA processor; the FPGA processor is communicatively connected to the DDR3 storage chip, the host computer, and the digital walkie-talkie respectively, and the FPGA processor is configured to perform at least one of digital frequency shift, spectrum calculation, digital demodulation, storage and playback control, trigger signal recognition and trigger processing on the sampled data, and upload the data generated during the processing to the host computer when receiving an instruction from the host computer; the DDR3 storage chip is configured to classify and store the data received by the FPGA processor based on an instruction issued by the FPGA processor, and serve as a data source when the FPGA processor plays back data; the digital walkie-talkie is communicatively connected to the FPGA processor, and the digital walkie-talkie is configured to perform data interaction with the FPGA processor to receive voice signals on each channel; the host computer is configured to run a human-computer interaction software, obtain user instructions based on the running human-computer interaction software, issue the user instructions to the FPGA processor, and display spectrum information based on the data generated during the processing; the sampling working mode includes a recording and playback working mode; the recording and playback working mode is divided into raw IQ data recording and playback and narrowband IQ data recording and playback based on different data sources; the raw IQ data recording and playback is implemented in the following manner: the AD data acquisition module transfers real-time sampled data to a storage and playback control module through a digital frequency shift control module of the FPGA processor; the storage and playback control module performs at least one of abnormal signal recognition, data packaging, and interface protocol conversion on the real-time sampled data, and transfers the processed data to the DDR3 storage chip for storage; when performing data playback, the storage and playback control module reads data from the DDR3 storage chip according to the required data volume set by the host computer, and performs data rate matching to make the playback data match the rate of the real-time sampled data and send it to a digital signal processing module for processing; the digital signal processing module transfers the processed data to the digital walkie-talkie for playback or the host computer for real-time spectrum display respectively;The narrowband IQ data recording and playback is implemented based on the following method: the AD data acquisition module sequentially transmits the real-time sampled data to the digital filter of the digital signal processing module through the digital frequency shift control module and the data source selection module of the FPGA processor; wherein, the digital filter includes several filtering units and the decimation rate of each filtering unit is different; the digital filter processes the received data and outputs narrowband IQ data with different bandwidths, and the bandwidth range of the narrowband IQ data is 2 kHz - 160 MHz; the digital filter then sends the narrowband IQ data to the storage and playback control module for at least one of the processes of abnormal signal recognition, data packing, and interface protocol conversion; the storage and playback control module sends the processed data to the DDR3 storage chip for storage; when performing data playback, the storage and playback control module reads data from the DDR3 storage chip according to the required data volume set by the host computer, and performs data rate matching to make the playback data match the rate of the narrowband IQ data of the real-time sampling and sends it to the digital signal processing module for processing.

[0007] In some embodiments, the FPGA processor includes the digital frequency shift control module, the data source selection module, the digital signal processing module, and the storage and playback control module; the digital frequency shift control module is communicatively connected to the storage and playback control module and the data source selection module respectively, and the storage and playback control module is communicatively connected to the data source selection module and the digital signal processing module respectively; the data source selection module is communicatively connected to the digital signal processing module.

[0008] In some embodiments, the digital signal processing module includes: the digital filter, the FFT unit, the detection unit, and the digital demodulation unit; the digital filter is communicatively connected to the digital demodulation unit and the FFT unit respectively, and the FFT unit is communicatively connected to the detection unit.

[0009] In some embodiments, the sampling working mode of the radio signal storage and playback device further includes a real-time sampling working mode.

[0010] In some embodiments, the real-time sampling working mode is implemented based on the following method: the AD data acquisition module transfers the real-time sampling data to the data source selection module through the digital frequency shift control module of the FPGA processor; the data source selection module transfers the received real-time sampling data to the digital filter of the FPGA processor; the digital filter transfers the received real-time sampling data to the FFT unit and the digital demodulation unit respectively to perform narrowband filtering, digital demodulation, spectrum calculation and digital detection operations on the real-time sampling data; the digital demodulation unit and the detection unit transfer the processed data to the digital walkie-talkie for playback or to the host computer for real-time spectrum display respectively.

[0011] In some embodiments, the working mode of the storage and playback control module includes a normal mode;

[0012] In the normal mode, the radio signal storage and playback device is configured to perform the following operations: based on the host computer, obtain the storage parameters set by the user, and the storage parameters include the storage data source, the storage start point, and the storage length; the FPGA processor stores the received sampling data in the DDR3 storage chip based on the storage parameters; after the storage length is satisfied, the FPGA processor generates a storage completion signal and notifies the host computer in an interrupt manner; wherein, the execution times of the above storage process are not less than 1, and for each execution of the storage process, the host computer has a corresponding file record of the storage settings; when performing data playback, determine the data source for playback based on the host computer; control the playback data volume and playback speed based on the FPGA processor to simulate real sampling data; process the playback data based on the FPGA processor and transfer the processed data to the digital walkie-talkie for playback or to the host computer for real-time spectrum display respectively.

[0013] In some embodiments, the working mode of the storage and playback control module includes a trigger mode;

[0014] In the trigger mode, the radio signal storage and playback device is configured to perform the following operations: Before storage, based on the host computer, obtain trigger parameters and storage parameters. The trigger parameters include trigger lead data volume and trigger threshold; the storage parameters include storage start point and storage length. During storage, the FPGA processor stores the received sampling data into the DDR3 storage chip based on the storage parameters, and judges abnormal signals and counts the stored data volume during the storage process. Based on the detection status of the abnormal signal, the FPGA processor respectively performs the following operations: If the abnormal signal is detected only after the stored data volume exceeds the trigger lead data volume, continue to store the abnormal signal and the data of the remaining data length, and record the storage position of the abnormal signal; If the abnormal signal is detected before the stored data volume reaches the trigger lead data volume, discard the abnormal signal and clear the stored data; Restart detecting new abnormal signals and counting the stored data volume until the condition that the abnormal signal is detected only after the stored data volume exceeds the trigger lead data volume is met. After the storage length is satisfied, the FPGA processor generates a storage completion signal and notifies the host computer in an interrupt manner and uploads the storage position of the abnormal signal at the same time. When performing data playback, the host computer first issues parameters such as the storage position and storage boundary of the abnormal signal, and determines the data source for playback. Based on the FPGA processor, control the playback data volume and playback speed to simulate real sampling data. Based on the FPGA processor, process the playback data and transfer the processed data to the digital walkie-talkie for playback or the host computer for real-time spectrum display respectively. Description of the Drawings

[0015] This specification will be further described in the form of exemplary embodiments, and these exemplary embodiments will be described in detail through the drawings. These embodiments are not restrictive. In these embodiments, the same numbers represent the same structures, where:

[0016] Figure 1 is a schematic diagram of the application scenario of the radio signal storage and playback device shown in some embodiments of this specification;

[0017] Figure 2 is a schematic diagram of the exemplary structural composition of the radio signal storage and playback device shown in some embodiments of this specification;

[0018] Figure 3 is an exemplary flowchart of the real-time sampling working mode shown in some embodiments of this specification;

[0019] Figure 4 is an exemplary flowchart of the original IQ data recording and playback in the recording and playback working mode shown in some embodiments of this specification;

[0020] Figure 5 is an exemplary flowchart of narrowband IQ data recording and playback shown in some embodiments of this specification;

[0021] Figure 6 is an exemplary flowchart in the normal mode shown in some embodiments of this specification;

[0022] Figure 7 is an exemplary flowchart of the trigger mode shown in some embodiments of this specification. Detailed implementation manners

[0023] To more clearly illustrate the technical solutions of the embodiments of this specification, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some examples or embodiments of this specification. For those of ordinary skill in the art, without creative efforts, this specification can also be applied to other similar scenarios based on these drawings. Unless obvious from the language context or otherwise stated, the same reference numerals in the figures represent the same structure or operation.

[0024] It should be understood that the "system", "device", "unit" and / or "module" used herein is a method for distinguishing different components, elements, parts, portions or assemblies at different levels. However, if other words can achieve the same purpose, the said words can be replaced by other expressions.

[0025] As shown in this specification and the claims, unless the context clearly indicates an exception, words such as "a", "an", "one" and / or "the" are not specifically singular and may also include the plural. Generally speaking, the terms "comprising" and "including" only indicate the inclusion of the clearly identified steps and elements, and these steps and elements do not constitute an exclusive list. The method or device may also include other steps or elements.

[0026] Flowcharts are used in this specification to illustrate the operations performed by the systems according to the embodiments of this specification. It should be understood that the operations before or after may not necessarily be executed precisely in sequence. On the contrary, the steps can be processed in reverse order or simultaneously. At the same time, other operations can also be added to these processes, or one or several steps can be removed from these processes.

[0027] Figure 1 is a schematic diagram of application scenario 100 of a radio signal storage and playback device shown in some embodiments of this specification.

[0028] In some embodiments, the application scenario 100 can be configured for radio monitoring and analysis, etc. It can be applied in corresponding communication control scenarios such as radio monitoring, radio identification, and radio management. The application scenario 100 can include a server 110, a network 120, a user terminal 130, a storage device 140, and a signal source 150. The server 110 can include a processing engine 112. In some embodiments, the server 110, the user terminal 130, the storage device 140, and the signal source 150 can be connected to and / or communicate with each other via a wireless connection (e.g., the network 120), a wired connection, or a combination thereof.

[0029] The server 110 can be used to implement radio processing, such as radio signal storage and playback, etc. In some embodiments, it can be specifically used for monitoring radios such as satellites.

[0030] The server 110 refers to a system with computing capabilities. In some embodiments, the server 110 can be a single server or a server group. The server group can be centralized or distributed (e.g., the server 110 can be a distributed system). In some embodiments, the server 110 can be local or remote. For example, the server 110 can access information and / or data stored in the user terminal 130 and / or the storage device 140 via the network 120. Also, for example, the server 110 can be directly connected to the user terminal 130 and / or the storage device 140 to access the stored information and / or data. In some embodiments, the server 110 can be implemented on a cloud platform. By way of example only, the cloud platform can include a private cloud, a public cloud, a hybrid cloud, a community cloud, a distributed cloud, an internal cloud, a multi-layer cloud, etc., or any combination thereof.

[0031] In some embodiments, the server 110 can include a processing engine 112. The processing engine 112 can process information and / or data related to wireless signals. For example, the processing engine 112 can implement radio monitoring in the information data obtained by the signal source 150. In some embodiments, the processing engine 112 can include one or more processing engines (e.g., a single-core processing engine or a multi-core processor). By way of example only, the processing engine 112 can include one or more hardware processors, such as a central processing unit (CPU), an application-specific integrated circuit (ASIC), an application-specific instruction set processor (ASIP), a graphics processing unit (GPU), a physics processing unit (PPU), a digital signal processor (DSP), a field-programmable gate array (FPGA), a programmable logic device (PLD), a controller, a microcontroller unit, a reduced instruction set computer (RISC), a microprocessor, etc., or any combination thereof.

[0032] Network 120 can facilitate the exchange of information and / or data. In some embodiments, one or more components in application scenario 100 (e.g., server 110, user terminal 130, storage device 140, and signal source 150) can send information and / or data to other components in application scenario 100 via network 120. For example, processing engine 112 can send the analysis results of the monitored radio to user terminal 130 via network 120. In some embodiments, network 120 can be a wired network, a wireless network, or any combination thereof. By way of example only, network 120 can include a cable network, a wired network, an optical fiber network, a telecommunication network, an intranet, the Internet, a local area network (LAN), a wide area network (WAN), a wireless local area network (WLAN), a metropolitan area network (MAN), a wide area network (WAN), a public switched telephone network (PSTN), a Bluetooth TM network, a ZigBee network, a near field communication (NFC) network, or the like, or any combination thereof. In some embodiments, network 120 can include one or more network access points. For example, network 120 can include wired or wireless network access points such as base stations and / or Internet exchange points 120-1, 120-2, …, and one or more components of application scenario 100 can be connected to network 120 via the wired or wireless network access points to exchange data and / or information.

[0033] In some embodiments, user terminal 130 can include a mobile device 130-1, a tablet computer 130-2, a laptop computer 130-3, a desktop computer 130-4, etc., or any combination thereof. In some embodiments, mobile device 140-1 can include a smart home device, a wearable device, a mobile device, a virtual reality device, an augmented reality device, etc., or any combination thereof. In some embodiments, the smart home device can include a smart lighting device, a smart appliance control device, a smart monitoring device, a smart TV, a smart camera, an intercom, etc., or any combination thereof. In some embodiments, the wearable device can include a bracelet, shoes and socks, glasses, a helmet, a watch, clothing, a backpack, a smart accessory, etc., or any combination thereof. In some embodiments, the mobile device can include a mobile phone, a personal digital assistant (PDA), a gaming device, a navigation device, a point of sale (POS) device, a laptop computer, a desktop computer, etc., or any combination thereof. In some embodiments, the virtual reality device and / or the augmented reality device can include a virtual reality helmet, virtual reality glasses, a virtual reality eye mask, an augmented reality helmet, augmented reality glasses, an augmented reality eye mask, etc., or any combination thereof. For example, the virtual reality device and / or the augmented reality device can include GoogleGlass TM, RiftCon TM, Fragments TM, GearVR TM, etc.

[0034] In some embodiments, the user terminal 130 may be a mobile terminal configured to collect radio signals. The user terminal 130 may send and / or receive information related to radio signal monitoring and identification to / from the processing engine 112 or a processor installed in the user terminal 130 via a user interface. For example, the user terminal 130 may send radio signal data captured by the user terminal 130 to the processing engine 112 or the processor installed in the user terminal 120 via the user interface. The user interface may be in the form of an application for identifying satellites implemented on the user terminal 130. The user interface implemented on the user terminal 130 may facilitate communication between the user and the processing engine 112. For example, the user may input and / or import radio signal data to be identified via the user interface. The processing engine 112 may receive the input signal data via the user interface. As another example, the user may input a request for identifying radio signals via the user interface implemented on the user terminal 130.

[0035] In some embodiments, in response to an identification request, the user terminal 130 may directly process radio signal data based on a signal acquisition device installed in the user terminal 130 described elsewhere in this application via the processor of the user terminal 130. In some embodiments, in response to an identification request, the user terminal 130 may send the identification request to the processing engine 112 for determining radio signals based on a signal source 150 or a signal acquisition device installed elsewhere in this application. In some embodiments, the user interface may facilitate presenting or displaying information and / or data (e.g., signals) related to radio monitoring received from the processing engine 112. For example, the information and / or data may include results indicating radio monitoring content, or indications of performing radio monitoring, etc. In some embodiments, the information and / or data may be further configured to cause the user terminal 130 to display the results to the user.

[0036] The storage device 140 can store data and / or instructions. In some embodiments, the storage device 140 can store data obtained from the signal source 150. The storage device 140 can store data and / or instructions that the processing engine 112 can execute or use to execute the exemplary methods described in this application. In some embodiments, the storage device 140 may include a mass storage device, a removable memory, a volatile read-write memory, a read-only memory (ROM), etc. or any combination thereof. Exemplary mass storage devices can include magnetic disks, optical disks, solid state drives, etc. Exemplary removable memories can include flash drives, floppy disks, optical disks, memory cards, compact disks, magnetic tapes, etc. Exemplary volatile read-write memories can include random access memory (RAM). Exemplary RAM can include dynamic random access memory (DRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), static random access memory (SRAM), thyristor random access memory (T-RAM), and zero capacitor random access memory (Z-RAM), etc. Exemplary ROM can include mask ROM (MROM), programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), compact disk read-only memory (CD-ROM), and digital versatile disk read-only memory, etc. In some embodiments, the storage device 140 can be executed on a cloud platform. By way of example only, the cloud platform can include a private cloud, a public cloud, a hybrid cloud, a community cloud, a distributed cloud, an internal cloud, a multi-layer cloud, etc. or any combination thereof.

[0037] In some embodiments, the storage device 140 can be connected to the network 120 to communicate with one or more components (e.g., the server 110, the user terminal 130) in the application scenario 100. One or more components in the application scenario 100 can access the data or instructions stored in the storage device 140 via the network 120. In some embodiments, the storage device 140 can be directly connected to or communicate with one or more components (e.g., the server 110, the user terminal 130) in the application scenario 100. In some embodiments, the storage device 140 can be part of the server 110.

[0038] The signal source 150 is a signal terminal that emits radio signals. For example, the signal source can be a satellite, a signal generator, a base station, etc. Based on the corresponding signal acquisition device, the radio signals generated by the signal source 150 can be acquired.

[0039] It should be noted that the above description is intended to be illustrative and not to limit the scope of the present application. Many alternatives, modifications, and variations will be apparent to those skilled in the art. The features, structures, methods, and other characteristics of the exemplary embodiments described herein can be combined in various ways to obtain additional and / or alternative exemplary embodiments. For example, the signal source 150 can be configured with a storage module, a processing module, a communication module, and the like. However, these changes and modifications do not depart from the scope of the present application.

[0040] Figure 2 It is a schematic structural composition diagram of a radio signal storage and playback device according to some embodiments of this specification.

[0041] As Figure 2 shown, the radio signal storage and playback device 200 may include: a radio frequency front end, an AD data acquisition module, an FPGA processor, a DDR3 memory chip, a digital walkie-talkie, and a host computer.

[0042] The radio frequency front end is communicatively connected to the AD data acquisition module. The radio frequency front end is configured to receive a signal to be analyzed through an antenna and perform at least one of amplification, filtering, and mixing processing on the signal to be analyzed to obtain an intermediate frequency signal.

[0043] The AD data acquisition module is communicatively connected to the FPGA processor. The AD data acquisition module is configured to sample the intermediate frequency signal and upload the obtained sampled data to the FPGA processor.

[0044] The FPGA processor is communicatively connected to the DDR3 memory chip, the host computer, and the digital walkie-talkie respectively. The FPGA processor is configured to perform at least one of digital frequency shift, spectrum calculation, digital demodulation, storage and playback control, trigger signal recognition and trigger processing on the sampled data, and upload the data generated during the processing to the host computer when receiving an instruction from the host computer.

[0045] In some embodiments, the FPGA processor includes a digital frequency shift control module, a data source selection module, a digital signal processing module, and a storage and playback control module; the digital frequency shift control module is communicatively connected to the storage and playback control module and the data source selection module respectively, the storage and playback control module is communicatively connected to the data source selection module and the digital signal processing module respectively; the data source selection module is communicatively connected to the digital signal processing module.

[0046] Among them, the digital frequency shift control module can be used to perform digital frequency shift processing on the received signal; the data source selection module determines the data source read by the FPGA processor during data playback processing; the digital signal processing module is used to process the read data, and the storage and playback control module is used to read data and perform playback processing.

[0047] In some embodiments, the FPGA processor may further include an external connection module, which can be used to implement communication between the FPGA processor and at least some of the devices other than the processor in the radio signal storage and playback device. For example, the external connection module may include a PCIe interface, a jesd204b interface, etc. The FPGA processor can be connected to the DDR3 storage chip through the PCIe interface, and the AD data acquisition module can be communicatively connected to the FPGA processor through the jesd204b interface. Specifically, the AD data acquisition module can transmit data to the FPGA processor through the jesd204b interface for subsequent processing. Also, as a signal processing unit, the FPGA processor can receive sampled data from the AD data acquisition module through the jesd204b interface, and further perform operations such as digital frequency shift, spectrum calculation, digital demodulation, storage and playback control, trigger signal recognition and triggering, etc., and then selectively upload the generated data to the host computer through the PCIe interface.

[0048] In some embodiments, the digital signal processing module may include: a digital filter, an FFT unit, a detection unit, and a digital demodulation unit; among them, inside the digital signal processing module, the digital filter is communicatively connected to the digital demodulation unit and the FFT unit respectively, and the FFT unit is communicatively connected to the detection unit; in the entire FPGA processor, the digital filter is communicatively connected to the data source selection module and the storage and playback control module respectively. The digital demodulation unit can also be communicatively connected to the digital walkie-talkie. The detection unit can also be communicatively connected to the host computer. In some embodiments, the digital filter, the FFT unit, the detection unit, and the digital demodulation unit can be used to perform operations such as digital filtering, spectrum calculation, digital detection, and digital demodulation on the received data respectively.

[0049] The DDR3 storage chip is used to classify and store the data received by the FPGA processor based on the instructions issued by the FPGA processor, and serve as the data source when the FPGA processor plays back data. In some embodiments, as the main storage space, the DDR3 storage chip can classify and store the original IQ data and narrowband IQ data through a data source selection command. During data playback, the DDR3 storage chip retrieves the data to replace the sampling data source.

[0050] DDR3 is used as the storage unit. Under the design scheme of a sampling clock of 1866Mhz and a 64-bit data bus, the highest transmission speed that can be supported is 14.9GMB / s, which is much greater than the throughput rate of IQ data. Therefore, the loss of sampling signals will not be caused by the bottleneck of the memory transmission rate. Moreover, if the storage space of DDR3 is extended to 4GB, for real-time IQ data of 160MHz (sampling rate of 204.8MHz and data bit width of 32biit), it can store up to 5s at most; for narrowband IQ data, it can store for several hours at most. Such a storage duration can meet the conventional monitoring of radio signals.

[0051] The digital walkie-talkie is communicatively connected to the FPGA processor. The digital walkie-talkie is used to interact with the FPGA processor to receive voice signals on each channel. For example, the digital walkie-talkie can interact with the digital demodulation module to receive voice signals on each channel.

[0052] The upper computer is used to run the human-computer interaction software, obtain user instructions based on the running of the human-computer interaction software, send the user instructions to the FPGA processor, and display spectrum information based on the data generated during the processing.

[0053] It should be noted that the parameters required to be used in this specification can be set by the user according to the actual situation, such as input through the upper computer.

[0054] It should be noted that the above description of the system and its components is only for the convenience of description and does not limit this specification within the scope of the examples given. It can be understood that for those skilled in the art, after understanding the principle of the system, they may, without departing from this principle, make any combination of the components, or form a subsystem and connect it with other components. For example, the RF front end and the AD data acquisition module can be integrated into one component. Another example is that all components can share a storage device, or each component can have its own storage device. Such variations are all within the protection scope of this specification.

[0055] In some embodiments, the radio signal storage and playback device supports a real-time sampling working mode and a recording and playback working mode.

[0056] As Figure 3 Shown is an exemplary flowchart of the real-time sampling working mode according to some embodiments of this specification. In some embodiments, process 300 can be executed by the radio signal storage and playback device 200. In some embodiments, process 300 can include the following steps:

[0057] Step 310: The AD data acquisition module transfers the real-time sampled data to the data source selection module through the digital frequency shift control module of the FPGA processor.

[0058] In some embodiments, the radio signal storage and playback device may first collect and receive signals based on the RF front-end through an antenna, and then process the collected signals such as amplification, filtering, mixing, etc. based on the RF front-end, and output an intermediate frequency signal.

[0059] In some embodiments, the RF front-end may transmit the obtained intermediate frequency signal to an AD data acquisition module designed with an AD high-speed AD chip. The AD data acquisition module samples and processes the received intermediate frequency signal to obtain corresponding digital signals such as IQ data.

[0060] In some embodiments, the AD data acquisition module may transfer its real-time sampled data to the data source selection module through the digital frequency shift control module of the FPGA processor.

[0061] Step 320: The data source selection module transfers the received real-time sampled data to the digital filter of the FPGA processor.

[0062] Step 330: The digital filter transfers the received real-time sampled data to the FFT unit and the digital demodulation unit respectively to perform narrowband filtering, digital demodulation, spectrum calculation, and digital detection operations on the real-time sampled data respectively.

[0063] Step 340: The digital demodulation unit and the detection unit transfer the processed data to the digital walkie-talkie for playback or to the host computer for real-time spectrum display respectively.

[0064] Merely by way of example, in the real-time sampling working mode, the real-time sampled data of the AD data acquisition module reaches the FPGA processor through the digital frequency shift control module and the data source selection module, and further performs operations such as narrowband filtering, digital demodulation, spectrum calculation, and digital detection. The processed data is respectively sent to the digital walkie-talkie for playback or to the host computer for real-time spectrum display.

[0065] It should be noted that the above description of process 300 is merely for illustration and explanation, and does not limit the scope of application of this specification. For those skilled in the art, various modifications and changes can be made to process 400 under the guidance of this specification. However, these modifications and changes are still within the scope of this specification.

[0066] In some embodiments, in the recording and playback working mode, it can be further specifically divided into original IQ data recording and playback and narrowband IQ data recording and playback according to different data sources.

[0067] Figure 4 is an exemplary flowchart of the recording and playback of original IQ data in the recording and playback working mode shown in some embodiments of this specification; in some embodiments, process 400 may be executed by the radio signal storage and playback device 200. In some embodiments, process 400 may include the following steps:

[0068] Step 410, the AD data acquisition module transfers the real-time sampled data to the storage and playback control module through the digital frequency shift control module of the FPGA processor.

[0069] Step 420, the storage and playback control module performs at least one of abnormal signal recognition, data packing, and interface protocol conversion on the real-time sampled data, and transfers the processed data to the DDR3 storage chip for storage.

[0070] Step 430, when data playback is performed, the storage and playback control module reads data from the DDR3 storage chip according to the required data volume set by the host computer, and performs data rate matching to make the playback data match the rate of the real-time sampled data and send it to the digital signal processing module for processing.

[0071] Step 440, the digital signal processing module transfers the processed data to the digital walkie-talkie for playback or to the host computer for real-time spectrum display.

[0072] Merely by way of example, when recording and playing back the original IQ data, the real-time sampled data of the AD data acquisition module enters the storage and playback control module through the digital frequency shift control module, and further operations such as abnormal signal recognition, data packing, and interface protocol conversion are performed before being stored in the DDR3 storage chip. During playback, the storage and playback control module retrieves data from the DDR3 storage chip according to the required data volume set by the host computer, and performs data rate matching to make the playback data match the rate of the real-time sampled data and pour it into the subsequent digital signal processing module. The processed data is then sent to the digital walkie-talkie for playback or to the host computer for spectrum display.

[0073] It should be noted that the above description of process 400 is only for illustration and explanation, and does not limit the scope of application of this specification. For those skilled in the art, various modifications and changes can be made to process 400 under the guidance of this specification. However, these modifications and changes are still within the scope of this specification.

[0074] Figure 5It is an exemplary flowchart of narrowband IQ data recording and playback shown in some embodiments of this specification; in some embodiments, process 500 may be executed by radio signal storage and playback device 200. In some embodiments, process 500 may include the following steps:

[0075] Step 510, the AD data acquisition module sequentially passes the real-time sampled data through the digital frequency shift control module and the data source selection module of the FPGA processor to the digital filter of the digital signal processing module.

[0076] Step 520, the digital filter processes the received data and outputs narrowband IQ data with different bandwidths.

[0077] Step 530, the digital filter further sends the narrowband IQ data of each level to the storage and playback control module for at least one of the processes of abnormal signal identification, data packaging, and interface protocol conversion.

[0078] Step 540, the storage and playback control module sends the processed data to the DDR3 storage chip for storage.

[0079] Step 550, when data playback is performed, the storage and playback control module reads data from the DDR3 storage chip according to the required data volume set by the host computer and performs data rate matching.

[0080] Step 560, make the playback data match the rate of the narrowband IQ data of the real-time sampling and send it to the digital signal processing module for processing.

[0081] Step 570, the digital signal processing module respectively transmits the processed data to the digital walkie-talkie for playback or the host computer for real-time spectrum display.

[0082] Only by way of example, when narrowband IQ data is recorded and played back, the real-time sampled data of the AD data acquisition module passes through the digital frequency shift module and the digital filter bank (where the decimation rates of each level of the filter bank are different), and narrowband IQ data with different bandwidths can be output. The bandwidth range is 2 kHz - 160 MHz, and it can be divided into n levels according to user requirements.

[0083] The narrowband IQ data of each gear enters the storage and playback control module, and further operations such as abnormal signal recognition, data packing, and interface protocol conversion are performed and stored in the DDR3 storage chip. During playback, the storage and playback control module retrieves data from the DDR3 storage chip according to the required data volume set by the host computer, and performs data rate matching to make the playback data match the narrowband IQ data rate of real-time sampling and pour it into the subsequent digital demodulation, spectrum calculation, and detection modules for processing. The processed data is respectively sent to the digital walkie-talkie for playback or the host computer for spectrum display.

[0084] It should be noted that the above description of process 500 is only for illustration and explanation, and does not limit the scope of application of this specification. For those skilled in the art, various modifications and changes can be made to process 500 under the guidance of this specification. However, these modifications and changes are still within the scope of this specification.

[0085] In some embodiments, the working mode of the storage and playback control module includes a normal mode.

[0086] Figure 6 It is an exemplary flowchart in the normal mode according to some embodiments shown in this specification; in some embodiments, process 600 can be executed by the radio signal storage and playback device 200. In some embodiments, process 600 may include the following steps:

[0087] Step 610, obtaining the storage parameters set by the user based on the host computer, where the storage parameters include the storage data source, storage start point, and storage length.

[0088] Step 620, the FPGA processor stores the received sampling data into the DDR3 storage chip based on the storage parameters.

[0089] Step 630, after the storage length is satisfied, the FPGA processor generates a storage completion signal and notifies the host computer in an interrupt manner.

[0090] Step 640, determining the data source for playback based on the host computer during data playback.

[0091] Step 650, controlling the playback data volume and playback speed based on the FPGA processor to simulate real sampling data.

[0092] Step 660, processing the playback data based on the FPGA processor and respectively transmitting the processed data to the digital walkie-talkie for playback or the host computer for real-time spectrum display.

[0093] For example, in the normal mode, the starting position and the amount of data for storage and playback can be freely selected. The host computer selects the data source for storage, sets parameters such as the storage start point and storage length. After the parameters take effect, data storage begins. After the storage length meets the set requirements, the FPGA processor generates a storage completion signal and notifies the host computer in an interrupt manner. Among them, the storage process can be executed multiple times, and each time the host computer has a corresponding file record of the storage settings.

[0094] During playback, the host computer selects the data source for playback, and then clicks to start playback. The FPGA processor performs logical control on the amount of playback data and the playback speed to match the real sampling data source. And replaces the real-time sampling data with the playback data for subsequent signal analysis, digital demodulation and other operations. The spectral waveform generated by the playback data is also displayed on the host computer interface.

[0095] It should be noted that the above description of process 600 is only for illustration and explanation, and does not limit the scope of application of this specification. For those skilled in the art, various modifications and changes can be made to process 600 under the guidance of this specification. However, these modifications and changes are still within the scope of this specification.

[0096] Figure 7 It is an exemplary flowchart of a trigger mode shown according to some embodiments of this specification; in some embodiments, process 700 can be executed by the radio signal storage and playback device 200. In some embodiments, process 700 can include the following steps:

[0097] Step 710, before storage, based on the host computer, obtain trigger parameters and storage parameters, where the trigger parameters include trigger lead data amount and trigger threshold; the storage parameters include storage start point and storage length.

[0098] Step 720, during storage, the FPGA processor stores the received sampling data into the DDR3 storage chip based on the storage parameters, and judges the abnormal signal according to the trigger threshold and counts the amount of stored data during the storage process.

[0099] Step 730, based on the detection status of the abnormal signal, the FPGA processor performs different operations respectively.

[0100] In some embodiments, based on the detection status of the abnormal signal, the FPGA processor performs the following operations respectively:

[0101] If the abnormal signal is detected only after the amount of stored data exceeds the trigger lead data amount, continue to store the abnormal signal and the data of the remaining data length, and record the storage position of the abnormal signal;

[0102] If the abnormal signal is detected before the stored data volume reaches the trigger advanced data volume, the abnormal signal is discarded and the stored data is cleared;

[0103] New abnormal signals are detected again and the stored data volume is counted until the condition that the stored data volume exceeds the trigger advanced data volume and then the abnormal signal is detected is satisfied.

[0104] Step 740, after the storage length is satisfied, the FPGA processor generates a storage completion signal and notifies the host computer in an interrupt manner to upload the storage location of the abnormal signal at the same time. Among them, the execution times of the above storage process are not less than 1, and for each execution of the storage process, the host computer has a corresponding file record storage setting.

[0105] Step 750, when data playback is performed, the host computer first issues parameters such as the storage location and storage boundary of the abnormal signal, and determines the data source for playback.

[0106] Step 760, based on the FPGA processor, control the playback data volume and playback speed to simulate real sampled data.

[0107] Step 770, based on the FPGA processor, process the playback data and transfer the processed data to the digital walkie-talkie for playback or to the host computer for real-time spectrum display respectively.

[0108] Only as an example, in the trigger mode, it mainly focuses on the recording and playback of abnormal signals. Its playback operation is restricted by the storage process and cannot be set arbitrarily. In the storage operation, first set parameters such as the trigger advanced data volume, trigger threshold, storage start, and storage length through the host computer. After the parameters take effect, data storage starts, and during the storage process, abnormal signals are judged according to the trigger threshold and the stored data volume is counted. According to the state of the abnormal signal, it can be divided into two cases:

[0109] a. If the stored data volume exceeds the set trigger advanced data volume and then the abnormal signal is detected, then continue to store the abnormal signal and the data of the remaining data length, and record the storage location of the abnormal point;

[0110] b. If the stored data volume does not reach the set trigger advanced data volume and the abnormal signal is detected, then discard the abnormal signal, clear the stored data, start detecting new abnormal signals again and count the stored data until case a is satisfied.

[0111] When the length meets the set requirements, the FPGA processor generates a storage completion signal, notifies the host computer in an interrupt manner, and uploads the storage location of the abnormal signal at the same time. The storage process can be executed multiple times, and the host computer has a corresponding file record storage setting for each storage.

[0112] In the playback operation, the host computer first sends down parameters such as the storage location and storage boundary of the abnormal signal, and selects the data source for playback. Then, click to start playback. The FPGA processor logically controls the playback data volume and playback speed to match the real sampling data source. The playback data replaces the real-time sampling data for subsequent signal analysis, digital demodulation and other operations. The spectral waveform generated by the playback data is also displayed on the host computer interface.

[0113] It should be noted that the above description of process 700 is only for illustration and explanation, and does not limit the scope of application of this specification. For those skilled in the art, various corrections and changes can be made to process 700 under the guidance of this specification. However, these corrections and changes are still within the scope of this specification.

[0114] In some embodiments of the present invention, by designing rich storage and playback functions. It can be divided into a normal mode and a trigger mode according to the working mode. Among them, the trigger mode is for capturing abnormal signals, which can greatly improve the retrieval efficiency of abnormal signals; it can be divided into a single playback mode and a loop playback mode according to the number of playback times, enabling users to more clearly analyze signals and observe spectral phenomena. At the same time, the storage data sources can be classified, and the original IQ data and narrowband IQ data can be stored separately, and the playback speed is matched with the real-time sampling speed, so that there is no difference in the sampling rate between the playback data source and the real-time sampling data source.

[0115] The basic concepts have been described above. Obviously, for those skilled in the art, the above detailed disclosure is only an example and does not constitute a limitation of this specification. Although not explicitly stated here, those skilled in the art may make various modifications, improvements and corrections to this specification. Such modifications, improvements and corrections are proposed in this specification, so such modifications, improvements and corrections still belong to the spirit and scope of the exemplary embodiments of this specification.

[0116] At the same time, this specification uses specific terms to describe the embodiments of this specification. Such as "one embodiment", "an embodiment", and / or "some embodiments" mean a certain feature, structure or characteristic related to at least one embodiment of this specification. Therefore, it should be emphasized and noted that the "one embodiment" or "an embodiment" or "an alternative embodiment" mentioned twice or more at different positions in this specification does not necessarily refer to the same embodiment. In addition, certain features, structures or characteristics in one or more embodiments of this specification can be appropriately combined.

[0117] In addition, unless clearly stated in the claims, the order of the processing elements and sequences, the use of numerical and alphabetical characters, or the use of other names described in this specification are not used to limit the order of the processes and methods in this specification. Although some currently useful embodiments of the invention are discussed through various examples in the above disclosure, it should be understood that such details are for illustrative purposes only. The appended claims are not limited to the disclosed embodiments. On the contrary, the claims are intended to cover all modifications and equivalent combinations that conform to the essence and scope of the embodiments of this specification. For example, although the system components described above can be implemented by hardware devices, they can also be implemented only through software solutions, such as installing the described system on existing servers or mobile devices.

[0118] Similarly, it should be noted that, in order to simplify the presentation of the disclosure in this specification and thus help the understanding of one or more embodiments of the invention, in the foregoing description of the embodiments of this specification, sometimes multiple features are merged into one embodiment, drawing, or description thereof. However, this method of disclosure does not mean that the features required by the subject matter of this specification are more than those mentioned in the claims. In fact, the features of the embodiments are less than all the features of the individual embodiments disclosed above.

[0119] In some embodiments, numbers are used to describe components and attribute quantities. It should be understood that such numbers used for the description of embodiments are modified by the modifiers "about", "approximate" or "substantially" in some examples. Unless otherwise stated, "about", "approximate" or "substantially" indicate that the said numbers allow a variation of ±20%. Accordingly, in some embodiments, the numerical parameters used in the specification and claims are approximate values, and such approximate values may change according to the characteristics required by individual embodiments. In some embodiments, the numerical parameters should consider the specified significant digits and adopt the method of retaining the general number of digits. Although the numerical ranges and parameters used in some embodiments of this specification to confirm the breadth of their scope are approximate values, in specific embodiments, such numerical settings are as precise as possible within the feasible range.

[0120] For each patent, patent application, patent application publication, and other materials cited in this specification, such as articles, books, specifications, publications, documents, etc., their entire contents are hereby incorporated into this specification by reference. Except for the application history documents that are inconsistent with or conflict with the content of this specification, and also except for the documents that limit the broadest scope of the claims of this specification (currently or subsequently appended to this specification). It should be noted that if there are any inconsistencies or conflicts between the descriptions, definitions, and / or the use of terms in the attached materials of this specification and the content described in this specification, the descriptions, definitions, and / or the use of terms in this specification shall prevail.

[0121] Finally, it should be understood that the embodiments described in this specification are only used to illustrate the principles of the embodiments of this specification. Other variations may also fall within the scope of this specification. Therefore, by way of example and not limitation, alternative configurations of the embodiments of this specification may be regarded as consistent with the teachings of this specification. Accordingly, the embodiments of this specification are not limited to the embodiments explicitly presented and described in this specification.

Claims

1. A method for implementing the sampling working mode of a radio signal storage and playback device, characterized in that The radio signal storage and playback device includes: a radio frequency front end, an AD data acquisition module, an FPGA processor, a DDR3 memory chip, a digital walkie-talkie, and a host computer; The radio frequency front end is communicatively connected to the AD data acquisition module. The radio frequency front end is used to receive a signal to be analyzed through an antenna and perform at least one of amplification, filtering, and mixing on the signal to be analyzed to obtain an intermediate frequency signal; The AD data acquisition module is communicatively connected to the FPGA processor. The AD data acquisition module is used to sample the intermediate frequency signal and upload the obtained sampled data to the FPGA processor; The FPGA processor is communicatively connected to the DDR3 memory chip, the host computer, and the digital walkie-talkie respectively. The FPGA processor is used to perform at least one of digital frequency shift, spectrum calculation, digital demodulation, storage and playback control, trigger signal recognition and trigger processing on the sampled data, and upload the data generated during the processing to the host computer when receiving an instruction from the host computer; The DDR3 memory chip is used to classify and store the data received by the FPGA processor based on an instruction issued by the FPGA processor, and serve as a data source when the FPGA processor replays data; The digital walkie-talkie is communicatively connected to the FPGA processor. The digital walkie-talkie is used to interact with the FPGA processor to receive voice signals on each channel; The host computer is used to run human-computer interaction software, obtain user instructions based on the running human-computer interaction software, issue the user instructions to the FPGA processor, and display spectrum information based on the data generated during the processing; The sampling working mode includes a recording and playback working mode; The recording and playback working mode is divided into raw IQ data recording and playback and narrowband IQ data recording and playback based on different data sources; The raw IQ data recording and playback is implemented based on the following method: The AD data acquisition module transfers real-time sampled data to the storage and playback control module through the digital frequency shift control module of the FPGA processor; The storage and playback control module performs at least one of abnormal signal recognition, data packing, and interface protocol conversion on the real-time sampled data, and transfers the processed data to the DDR3 memory chip for storage; When performing data playback, the storage and playback control module reads data from the DDR3 memory chip according to the required data volume set by the host computer, and performs data rate matching to make the playback data match the rate of the real-time sampled data and send it to the digital signal processing module for processing; The digital signal processing module transfers the processed data to the digital walkie-talkie for playback or the host computer for real-time spectrum display respectively; The narrowband IQ data recording and playback is implemented based on the following method: The AD data acquisition module sequentially transmits the real-time sampled data to the digital filter of the digital signal processing module through the digital frequency shift control module and the data source selection module of the FPGA processor; wherein, the digital filter includes a plurality of filtering units and the decimation rate of each filtering unit is different; The digital filter processes the received data and outputs narrowband IQ data with different bandwidths, and the bandwidth range of the narrowband IQ data is 2 kHz - 160 MHz; The digital filter then sends the narrowband IQ data to the storage and playback control module for at least one of abnormal signal recognition, data packing, and interface protocol conversion processing; The storage and playback control module sends the processed data to the DDR3 storage chip for storage; When data playback is performed, the storage and playback control module reads data from the DDR3 storage chip according to the required data volume set by the host computer and performs data rate matching, so that the playback data matches the rate of the narrowband IQ data of the real-time sampling and is sent to the digital signal processing module for processing.

2. The method according to claim 1, characterized in that, The FPGA processor includes the digital frequency shift control module, the data source selection module, the digital signal processing module, and the storage and playback control module; the digital frequency shift control module is respectively communicatively connected to the storage and playback control module and the data source selection module, and the storage and playback control module is respectively communicatively connected to the data source selection module and the digital signal processing module; the data source selection module is communicatively connected to the digital signal processing module.

3. The method according to claim 2, wherein The digital signal processing module includes: the digital filter, the FFT unit, the detection unit, and the digital demodulation unit; The digital filter is respectively communicatively connected to the digital demodulation unit and the FFT unit, and the FFT unit is communicatively connected to the detection unit.

4. The method according to claim 3, wherein The sampling working mode of the radio signal storage and playback device further includes a real-time sampling working mode.

5. The method according to claim 4, characterized in that, The real-time sampling working mode is implemented based on the following method: The AD data acquisition module transmits the real-time sampled data to the data source selection module through the digital frequency shift control module of the FPGA processor; The data source selection module transmits the received real-time sampled data to the digital filter of the FPGA processor; The digital filter transmits the received real-time sampled data to the FFT unit and the digital demodulation unit respectively to perform narrowband filtering, digital demodulation, spectrum calculation, and digital detection operations on the real-time sampled data respectively; The digital demodulation unit and the detection unit respectively transmit the processed data to the digital walkie-talkie for playback or the host computer for real-time spectrum display.

6. The method according to any one of claims 1-5, characterized in that The working mode of the storage and playback control module includes a normal mode; In the normal mode, the radio signal storage and playback device is configured to perform the following operations: Based on the host computer, obtain the storage parameters set by the user, and the storage parameters include the storage data source, the storage start point, and the storage length; The FPGA processor stores the received sampled data into the DDR3 memory chip based on the stored parameters; After the storage length is satisfied, the FPGA processor generates a storage completion signal and notifies the host computer in an interrupt manner; Among them, the execution times of the above storage process are not less than 1, and for each execution of the storage process, the host computer has a corresponding file record of the storage settings; When performing data playback, determine the data source for playback based on the host computer; Based on the FPGA processor, control the playback data volume and playback speed to simulate real sampled data; Based on the FPGA processor, process the playback data and transfer the processed data to the digital walkie-talkie for playback or to the host computer for real-time spectrum display respectively; 7. According to the method described in any one of claims 1-5, characterized in that, The working mode of the storage and playback control module includes a trigger mode; In the trigger mode, the radio signal storage and playback device is configured to perform the following operations: Before storage, obtain the trigger parameters and storage parameters based on the host computer. The trigger parameters include the trigger lead data volume and the trigger threshold; the storage parameters include the storage start point and the storage length; During storage, the FPGA processor stores the received sampled data into the DDR3 memory chip based on the storage parameters, and judges the abnormal signal and counts the stored data volume according to the trigger threshold during the storage process; Based on the detection status of the abnormal signal, the FPGA processor performs the following operations respectively: If the abnormal signal is detected only after the stored data volume exceeds the trigger lead data volume, continue to store the abnormal signal and the data of the remaining data length, and record the storage location of the abnormal signal; If the abnormal signal is detected before the stored data volume reaches the trigger lead data volume, discard the abnormal signal and clear the stored data; Restart detecting new abnormal signals and counting the stored data volume until the condition that the abnormal signal is detected only after the stored data volume exceeds the trigger lead data volume is satisfied; After the storage length is satisfied, the FPGA processor generates a storage completion signal and notifies the host computer in an interrupt manner and uploads the storage location of the abnormal signal at the same time; When performing data playback, the host computer first issues the storage location and storage boundary parameters of the abnormal signal and determines the data source for playback; Based on the FPGA processor, control the playback data volume and playback speed to simulate real sampled data; based on the FPGA processor, process the playback data and transfer the processed data to the digital walkie-talkie for playback or to the host computer for real-time spectrum display respectively.

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