A packaging method of a high-density pop packaging structure and a product thereof

Abstract

The application discloses a packaging method of a high-density POP packaging structure and a product thereof. The packaging method comprises the following steps: mounting a first chip set on a carrier plate I; packaging the first chip set; removing the carrier plate I to form a first packaging body; mounting the first packaging body on a carrier plate II; pressing a dry film on the carrier plate II to form a copper column; mounting a second chip set on a second metal redistribution layer, packaging the second chip set; removing the carrier plate II to expose the copper column; forming a third metal redistribution layer, and ball mounting. The application adopts the dry film and the metal redistribution layer to replace a commonly used TSV adapter plate, reduces the packaging manufacturing cost, electrically connects the first chip set and the second chip set through the first metal redistribution layer and the second metal redistribution layer, electrically couples to an external packaging unit through the third metal redistribution layer and the copper column, can realize two-layer high-density stacked packaging, effectively improves the integration of the product, and realizes the multifunctionalization of the product.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor packaging, and particularly relates to a packaging method of a high-density POP packaging structure and a product thereof. BACKGROUND

[0002] Semiconductor devices have been widely used in integrated circuits, consumer electronics, communications, photovoltaic power generation and other different fields. With the coming of the physical and technical limits of Moore's Law, the semiconductor industry is more focused on technology innovation and application while pursuing chip performance improvement. In this context, how to integrate various heterogeneous chips together is an important development direction, and high-density integration and high-performance heterogeneous chips are the inevitable choice in the post-Moore era.

[0003] Chips using POP (Package on Package) packaging structure can realize heterogeneous integration and have been widely used in electronic products, with a large market size. Existing POP packaging forms through holes on a silicon interposer to realize interconnection between the upper and lower two layers, one of which is a through silicon via (TSV) method. However, silicon material is a semiconductor material, which has a strong electromagnetic coupling effect when transmitting electrical signals, resulting in poor signal integrity performance. The other method is a through resin via (TMV) method, which forms a copper column through laser drilling and plugging in the plastic package to conduct signals. However, this method easily damages the morphology of the plastic package, and the drilling and plugging technology is difficult. At the same time, it is very difficult to increase the through holes on the silicon interposer and realize high-density wiring on both sides, which increases the processing difficulty and manufacturing cost of packaging. SUMMARY

[0004] To solve the technical problems of high manufacturing cost, large packaging volume and poor heat dissipation of semiconductor packaging in the prior art, the purpose of the present application is to provide a packaging method of a high-density POP packaging structure and a product thereof.

[0005] To achieve the above purposes and achieve the above technical effects, the technical solution adopted by the present application is as follows:

[0006] A packaging method of a high-density POP packaging structure, comprising the following steps:

[0007] Step 1: providing a carrier plate I, and manufacturing a first metal redistribution layer on the carrier plate I;

[0008] Step 2: attaching a first chip set on the first metal redistribution layer;

[0009] Step 3: curing and encapsulating the first chip set by bottom dispensing;

[0010] Step 4: removing the carrier plate I to form a first packaging body.

[0011] Step five: providing a carrier plate II, and mounting the first package obtained in step four on the carrier plate II with heat dissipation fins arranged therebetween;

[0012] Step six: laminating a dry film on the carrier plate II, and forming a copper pillar opening by using a photoetching technique;

[0013] Step seven: plugging the copper pillar opening to form a copper pillar;

[0014] Step eight: grinding and thinning the top of the first package to expose the copper pillar and the first metal redistribution layer;

[0015] Step nine: manufacturing a second metal redistribution layer to form an under bump metallization layer on the surface of the topmost layer of circuit;

[0016] Step ten: mounting a second chip set on the surface of the under bump metallization layer, curing and encapsulating the second chip set by bottom dispensing, and removing the carrier plate II to expose the copper pillar;

[0017] Step eleven: redistributing the package obtained in step ten to form a third metal redistribution layer, and forming a solder ball on the surface of the third metal redistribution layer to complete signal export.

[0018] Further, in step one, the step of manufacturing the first metal redistribution layer on the carrier plate I comprises:

[0019] coating a layer of temporary bonding glue on the carrier plate I, and then manufacturing a plurality of first metal redistribution layers and a plurality of first dielectric layers on the temporary bonding glue.

[0020] Further, the first dielectric layer has a total of 5 layers, each layer has a thickness of 5-8 μm, and the total thickness of the plurality of first metal redistribution layers and the plurality of first dielectric layers is 30-40 μm.

[0021] Further, in step two, the first chip set is mounted on the first metal redistribution layer by flip-chip mounting technology, and the first chip set is a storage chip or a logic chip.

[0022] Further, in step three, the bottom of the first chip set is dispensed and cured by using underfill glue, the first chip set is encapsulated by a first encapsulation layer, and the first chip set is exposed by grinding and thinning the back of the first encapsulation layer.

[0023] Further, in step four, the carrier plate I and the temporary bonding glue thereon are removed by laser debonding or thermal release.

[0024] Further, in step five, the step of mounting the first package obtained in step four on the carrier plate II comprises:

[0025] A temporary bonding layer is coated on the carrier plate II, and the heat dissipation sheet is attached to the temporary bonding layer, and the first package obtained in step four is attached to the heat dissipation sheet through the DAF material, so that the first chip group is below and the multi-layer first metal redistribution layer is above.

[0026] Further, in step six, the thickness of the dry film is greater than 100 μm.

[0027] Further, step ten comprises the following steps:

[0028] The second chip group is attached to the surface of the bumping lower metallization layer through flip chip technology, the bottom of the second chip group is glued and solidified through the underfill glue, the second chip group is encapsulated through the second encapsulation layer, and the second chip group is exposed by grinding and thinning the second encapsulation layer; the carrier plate II and the temporary bonding layer thereon are removed through laser debonding or thermal release, and the copper column is exposed.

[0029] The application further discloses a high-density POP packaging structure prepared by the packaging method.

[0030] Compared with the prior art, the application has the following beneficial effects:

[0031] 1) The existing POP packaging commonly uses expensive silicon adapter plate bonding, the application uses dry film material and metal redistribution layer to replace the commonly used TSV adapter plate, reduces the packaging manufacturing cost, realizes high-density fan-out packaging unit through high-density wiring with a line width / line spacing of 2 μm / 2 μm or below, reduces the pitch between pins, and increases the density of I / O ports; the thickness of the conventional silicon adapter plate is about 100 μm, and it is difficult to further reduce the thickness, the total thickness of the metal redistribution layer of the application is as low as 50 μm, the thickness of the package can be greatly reduced, and the miniaturization and thinning of the packaging structure are facilitated;

[0032] 2) The first metal redistribution layer and the second metal redistribution layer are adopted to electrically connect the first chip group and the second chip group, and the third metal redistribution layer and the copper column are adopted to electrically couple to the external packaging unit, so that two-layer high-density stacked packaging can be realized, the integration of the product is effectively improved, and multifunctionalization of the product is realized;

[0033] 3) The existing chip is difficult to dissipate heat after being stacked, the heat dissipation of the whole packaging structure is significantly improved by embedding the heat dissipation sheet, the product reliability is higher, and the technical problems of high manufacturing cost, large packaging volume and difficult heat dissipation of the semiconductor packaging in the prior art are solved. BRIEF DESCRIPTION OF DRAWINGS

[0034] Figure 1 It is a structure schematic diagram of step one of the application;

[0035] Figure 2 It is a structure schematic diagram of step two of the application;

[0036] Figure 3 It is a structure schematic diagram of step three of the application;

[0037] Figure 4 It is a structure schematic diagram of step four of the application;

[0038] Figure 5 It is a structure schematic diagram of step five of the application;

[0039] Figure 6 It is a structure schematic diagram of step six of the application;

[0040] Figure 7 It is a structure schematic diagram of step seven of the application;

[0041] Figure 8 It is a structure schematic diagram of step eight of the application;

[0042] Figure 9 It is a structure schematic diagram of step nine of the application;

[0043] Figure 10 It is a structure schematic diagram of step ten of the application;

[0044] Figure 11 It is a structure schematic diagram of step eleven of the application;

[0045] Wherein, 101 - carrier plate I; 102 - temporary bonding glue; 103 - first metal redistribution layer; 104 - first dielectric layer; 201 - first chip group; 301 - underfill glue; 302 - first encapsulation layer; 303 - DAF material; 111 - carrier plate II; 112 - temporary bonding glue layer; 202 - heat sink; 401 - dry film; 402 - copper column opening; 403 - copper column; 404 - second dielectric layer; 405 - second metal redistribution layer; 406 - under bump metallization layer; 501 - second chip group; 502 - second encapsulation layer; 503 - underfill glue; 601 - third metal redistribution layer; 602 - tin ball; 603 - third dielectric layer. DETAILED DESCRIPTION

[0046] The application will be described in detail below so that the advantages and features of the application can be more easily understood by those skilled in the art, and the scope of protection of the application can be more clearly defined.

[0047] The following presents a simplified summary of one or more aspects in order to provide a basic understanding of such aspects. This summary is not an extensive overview of all contemplated aspects, and is intended to neither identify key or critical elements of all aspects nor delineate the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form as a prelude to the more detailed description that is presented later.

[0048] As shown in Figures 1-11 , a packaging method of a high-density POP packaging structure includes the following steps:

[0049] Step one: as shown in Figure 1 , a layer of temporary bonding glue 102 is coated on the carrier plate I 101, and a plurality of layers of first metal redistribution layer 103 and a plurality of layers of first dielectric layer 104 are formed on the temporary bonding glue 102. The first dielectric layer 104 is a polyimide material, a total of 5 layers, each layer has a thickness of 5-8 μm, and a conductive opening is formed through coating, exposure, development, and baking processes; a seed layer is sputtered on the first dielectric layer 104, the thickness of the seed layer is generally 0.1-0.5 μm, and the material is Ti or Cu; a layer of process glue is coated on the seed layer, a line opening is formed through coating, exposure, development, and baking processes, and the line width and line spacing are 2 μm / 2 μm or less; the opening is plated to form the first metal redistribution layer 103 through plating, glue removal, and etching processes, and the thickness of the plated line is generally about 2.5 μm. The above processes are repeated to form the plurality of layers of first metal redistribution layer 103. The total thickness of the plurality of layers of first metal redistribution layer 103 and the first dielectric layer 104 is 30-40 μm.

[0050] Step two: as shown in Figure 2As shown, the first chip set 201 is mounted on the first multi-layer metal redistribution layer 103 by flip chip technology. The first chip set 201 can be a memory chip or a logic chip, such as DRAM, HBM, or a passive device, such as a resistor, inductor, or capacitor.

[0051] Step three: as shown, the bottom of the first chip set 201 is dispensed with underfill glue 301 and cured, and then encapsulated by the first encapsulation layer 302. The first encapsulation layer 302 is generally made of polyimide or epoxy resin, with a thickness of about 100 μm. Figure 3 Step four: as shown, the carrier board I 101 and the temporary bonding glue 102 are removed by laser debonding or thermal release, forming the first encapsulated body.

[0052] Figure 4 Step five: as shown, a layer of temporary bonding glue 112 is coated on the carrier board II 111, the heat sink 202 is attached to the temporary bonding glue layer 112, and the first encapsulated body obtained in step four is attached to the heat sink 202 by DAF (Die Attach Film) material 303, with the first chip set 201 below and the first metal redistribution layer 103 above. The heat sink 202 can be made of any of metal, ceramic, or silicon.

[0053] Step six: as shown, a layer of dry film 401 is laminated on the carrier board II 111, the thickness of the dry film 401 is greater than 100 μm, the dry film 401 is made of photosensitive material, and copper pillar openings 402 are formed by photolithography technology. Figure 5 Step seven: as shown, the copper pillar openings 402 are plugged by electroplating process, forming copper pillars 403.

[0054] Figure 6 Step eight: as shown, the top of the first encapsulated body is thinned by CMP grinding, the copper pillars 403 and the circuit are ground to the same plane, the height is flush, and the copper pillars 403 and the first metal redistribution layer 103 are exposed.

[0055] Step nine: as shown, the second metal redistribution layer 405 and the second dielectric layer 404 are made again according to the conventional bumping process (shown in step one), and the under bump metallization layer (UBM) 406 is formed on the surface of the uppermost layer of circuit. Figure 7 Step ten: as shown, the second chip set 202 is mounted on the second metal redistribution layer 405 by flip chip technology.

[0056] Figure 8 Step eleven: as shown, the second chip set 202 is encapsulated by the second encapsulation layer 407, and the second encapsulation layer 407 is generally made of polyimide or epoxy resin, with a thickness of about 100 μm.

[0057] Step twelve: as shown, the carrier board II 111 and the temporary bonding glue 112 are removed by laser debonding or thermal release, forming the second encapsulated body. Figure 9 Step thirteen: as shown, the second encapsulated body is attached to the first encapsulated body by DAF (Die Attach Film) material 408, with the second chip set 202 below and the second metal redistribution layer 405 above.

[0058] Figure 10 ​​​​As shown, the second chipset 501 is mounted on the surface of the under-bump metallization layer 406 using flip-chip technology. The second chipset 501 is encapsulated by the second encapsulation layer 502 and underfill adhesive 503. The second encapsulation layer 502 is then polished to expose the second chipset 501, which facilitates chip heat dissipation. The carrier board II 111 and the temporary bonding adhesive layer 112 are removed using laser debonding or thermal release methods, exposing the copper pillars 403.

[0059] Step 11: As Figure 11 As shown, redistribution is performed on the bottom surface of the package obtained in step ten to form a third metal redistribution layer 601 and a third dielectric layer 603. Solder balls 602 are formed on the surface of the third metal redistribution layer 601 by electroplating, balling, or solder paste printing to complete signal output.

[0060] The present invention also discloses a high-density POP packaging structure, including a first package body, the first package body including a first chipset 201, the first chipset 201 being flip-chip mounted on a multilayer first metal redistribution layer 103, the first chipset 201 being encapsulated by a first packaging layer 302, the first package body being mounted on a heat sink 202, the first package body and the heat sink 202 being covered by a dry film 401, copper pillars 403 being disposed on the dry film 401, a second chipset 501 being disposed on the first package body, the second chipset 501 being encapsulated by a second packaging layer 502, a third metal redistribution layer 601 being formed on the side of the first package body away from the second chipset 501, and solder balls 602 being formed on the surface of the third metal redistribution layer 601 to complete signal output.

[0061] Example 1

[0062] like Figures 1-11 As shown, a packaging method for a high-density POP packaging structure includes the following steps:

[0063] Step 1: As Figure 1As shown, a layer of temporary bonding glue 102 is coated on the carrier plate I 101 using existing mature products and technologies, and a plurality of layers of first metal redistribution layers 103 and a plurality of layers of first dielectric layers 104 are formed on the temporary bonding glue 102. The first dielectric layers 104 are polyimide materials, and there are 5 layers in total, each with a thickness of 5 μm. Conductive openings are formed through coating, exposure, development and baking processes. A seed layer with a thickness of 0.1 μm and made of Ti and Cu is sputtered on the first dielectric layers 104. A layer of process glue is coated on the seed layer, and line openings are formed through coating, exposure, development and baking processes. The line width and the line spacing are 1 μm / 1 μm. The openings are plated to form the first metal redistribution layers 103 through plating, glue removal and etching processes. The thickness of the plated lines is about 2.5 μm. The above processes are repeated to form the plurality of layers of first metal redistribution layers 103. The total thickness of the plurality of layers of first metal redistribution layers 103 and the first dielectric layers 104 is 40 μm.

[0064] Step two: as shown in Figure 2 , the first chip set 201 is attached on the plurality of layers of first metal redistribution layers 103 through flip chip technology. The first chip set 201 is a storage chip DRAM.

[0065] Step three: as shown in Figure 3 , the bottom of the first chip set 201 is glued and solidified using underfill glue 301 and encapsulated by the first encapsulation layer 302 using existing mature products and technologies. The first chip set 201 is exposed by grinding and thinning the back of the first encapsulation layer 302. The first encapsulation layer 302 is made of polyimide and has a thickness of 100 μm.

[0066] Step four: as shown in Figure 4 , the carrier plate I 101 and the temporary bonding glue 102 are removed by laser debonding to form the first package using existing mature products and technologies.

[0067] Step five: as shown in Figure 5 , a layer of temporary bonding glue layer 112 is coated on the carrier plate II 111 using existing mature products and technologies. The heat sink 202 is attached on the temporary bonding glue layer 112. The first package obtained in step four is attached on the heat sink 202 through DAF (Die Attach Film) material 303, with the first chip set 201 at the bottom and the first metal redistribution layers 103 at the top. The heat sink 202 is made of metal.

[0068] Step six: as shown in Figure 6 , a layer of dry film 401 is laminated on the carrier plate II 111. The thickness of the dry film 401 is 110 μm. The dry film 401 is made of photosensitive material, and copper pillar openings 402 are formed using photolithography technology.

[0069] Step Seven: As Figure 7 As shown, the opening 402 of the copper pillar is plugged by electroplating to form the copper pillar 403.

[0070] Step 8: As Figure 8 As shown, using existing mature products and technologies, the top of the first package is thinned by CMP grinding, and the copper pillar 403 and the circuit are ground to the same plane and flush with each other, exposing the copper pillar 403 and the first metal redistribution layer 103.

[0071] Step Nine: Figure 9 As shown, following the conventional bumping process (as shown in step one), a second metal redistribution layer 405 and a second dielectric layer 404 are fabricated again, and a bump under metallization layer (UBM) 406 is formed on the surface of the topmost circuit layer.

[0072] Step 10: As Figure 10 As shown, the second chipset 501 is mounted on the surface of the under-bump metallization layer 406 using flip chip technology. Employing existing mature products and technologies, the second chipset 501 is encapsulated by the second encapsulation layer 502 and underfill adhesive 503. The second encapsulation layer 502 is then thinned by grinding to expose the second chipset 501, which facilitates chip heat dissipation. The carrier board II 111 and the temporary bonding adhesive layer 112 are removed using laser debonding, exposing the copper pillars 403.

[0073] Step 11: As Figure 11 Figures 1-11 As shown, redistribution is performed on the bottom surface of the package obtained in step ten to form a third metal redistribution layer 601 and a third dielectric layer 603. Solder balls 602 are formed on the surface of the third metal redistribution layer 601 by electroplating to complete signal output.

[0074] A high-density POP packaging structure includes a first package body, which includes a first chipset 201. The first chipset 201 is flip-chip mounted on a multilayer first metal redistribution layer 103. The first chipset 201 is encapsulated by a first packaging layer 302. The first package body is mounted on a heat sink 202. The first package body and the heat sink 202 are surrounded by a dry film 401. Copper pillars 403 are disposed on the dry film 401. A second chipset 501 is disposed on the first package body. The second chipset 501 is encapsulated by a second packaging layer 502. A third metal redistribution layer 601 is formed on the side of the first package body away from the second chipset 501. Solder balls 602 are formed on the surface of the third metal redistribution layer 601 to complete signal output.

[0075] Any parts or structures not specifically described in this invention can be made using existing technologies or products, and will not be elaborated upon here.

[0076] The above merely illustrates the embodiments of the present application, and does not limit the patent scope of the present application, and any equivalent structure or equivalent process transformation, or direct or indirect application in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A packaging method of a high-density POP packaging structure, characterized by, The method comprises the following steps: Step 1: providing a carrier plate I, and manufacturing a first metal redistribution layer on the carrier plate I; Step 2: mounting a first chip group on the first metal redistribution layer; Step 3: curing and encapsulating the first chip group by bottom dispensing; Step 4: removing the carrier plate I to form a first package; Step 5: providing a carrier plate II, and mounting the first package obtained in Step 4 on the carrier plate II with a heat sink arranged therebetween; Step 6: laminating a dry film on the carrier plate II, and forming a copper column opening by using a photoetching technology; Step 7: plugging the copper column opening to form a copper column; Step 8: grinding and thinning the top of the first package to expose the copper column and the first metal redistribution layer; Step 9: manufacturing a second metal redistribution layer; Step 10: mounting a second chip group on the second metal redistribution layer, and curing and encapsulating the second chip group by bottom dispensing; removing the carrier plate II to expose the copper column; Step 11: redistributing the package obtained in Step 10 to form a third metal redistribution layer, and forming a tin ball on the surface of the third metal redistribution layer to complete signal leading-out.

2. The packaging method of a high-density POP package structure according to claim 1, wherein, In Step 1, the step of manufacturing the first metal redistribution layer on the carrier plate I comprises the following steps: coating a layer of temporary bonding glue on the carrier plate I, and then manufacturing a plurality of first metal redistribution layers and a plurality of first dielectric layers on the temporary bonding glue.

3. The packaging method of a high-density POP package structure according to claim 2, wherein, The first dielectric layer has a total of 5 layers, each layer has a thickness of 5-8 μm, and the total thickness of the plurality of first metal redistribution layers and the plurality of first dielectric layers is 30-40 μm.

4. The packaging method of a high-density POP package structure according to claim 1, wherein, In Step 2, the first chip group is mounted on the first metal redistribution layer by flip-chip mounting technology, and the first chip group is a storage chip or a logic chip.

5. The packaging method of a high-density POP package structure according to claim 1, wherein, In Step 3, the bottom of the first chip group is dispensed and cured by using a bottom filling glue; the first chip group is encapsulated by a first encapsulation layer, and the first chip group is exposed by grinding and thinning the back of the first encapsulation layer.

6. The method of claim 1, wherein the POP package structure is high density. In Step 4, the carrier plate I and the temporary bonding glue thereon are removed by laser debonding or heat release.

7. The method of claim 1, wherein the POP package structure is high density. In Step 5, the step of mounting the first package obtained in Step 4 on the carrier plate II comprises the following steps: coating a layer of temporary bonding glue on the carrier plate II, attaching the heat sink to the temporary bonding glue layer, and attaching the first package obtained in Step 4 to the heat sink by DAF material, so that the first chip group is below and the plurality of first metal redistribution layers are above.

8. The method of claim 1, wherein the POP package structure is high density. In Step 6, the thickness of the dry film is greater than 100 μm.

9. The method of claim 1, wherein the POP package structure is high density. Step 10 comprises the following steps: mounting the second chip group on the surface of the bumping under metal layer by flip-chip mounting technology, dispensing and curing the bottom of the second chip group by using a bottom filling glue, encapsulating the second chip group by a second encapsulation layer, exposing the second chip group by grinding and thinning the second encapsulation layer, removing the carrier plate II and the temporary bonding glue layer thereon by laser debonding or heat release, and exposing the copper column.

10. A high density POP package structure, characterized in that, The high-density POP packaging structure is prepared by a packaging method according to any one of claims 1-9, and the POP packaging structure comprises a first packaging body, the first packaging body comprises a first chip set, the first chip set is flip-chip mounted on a multilayer first metal redistribution layer, the first chip set is encapsulated by a first encapsulation layer, the first packaging body is mounted on a heat sink, the first packaging body and the heat sink are peripherally coated with a dry film, a copper column is arranged on the dry film, a second chip set is arranged on the first packaging body, the second chip set is encapsulated by a second encapsulation layer, a third metal redistribution layer is formed on a side of the first packaging body away from the second chip set, tin balls are formed on a surface of the third metal redistribution layer, and signal output is completed.

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