Multi-DSP Remote Debugging Device and Debugging Method

Abstract

The present invention discloses a multi-DSP remote debugging device and a debugging method, belonging to the field of signal processing, including: an Ethernet physical layer device PHY connected to a PC and a module support unit MSU, an Ethernet switch Ethernet Switch connected through the PHY; the PC is connected to the built-in processor system PS of the MSU, the PS is connected to a PSPLIF bus reader / writer, and the PSPLIF bus reader / writer is connected to an operation mode control register 1, a reset signal generator 1, a mode control register 2, a reset signal generator 2, a mode control register 3, a reset signal generator 3..., a mode control register n, and a reset signal generator n through a programmable logic PL and an internal logic circuit. The present invention can be compatible with a debugging mode and a normal operation mode, can provide convenience for long-distance remote debugging, and at the same time debug a remote debugging device for multiple DSPs.

Description

Technical Field

[0001] The present invention relates to the field of signal processing, and more specifically, to a multi-DSP remote debugging device and a debugging method. Background Art

[0002] Due to its advantages such as flexibility, stability, good repeatability, large-scale integration, and easy real-time implementation, the Digital Signal Processor (DSP) is widely used in many aspects such as radar. Modern radar signal processing basically adopts a radar signal processor based on multiple DSPs.

[0003] Currently, DSP software developers usually use the JTAG emulator provided by the DSP manufacturer for software debugging. One end of the JTAG emulator is usually connected to the target DSP through JTAG, and the other end is connected to the PC through USB. Then, in many cases, the radar signal processor is sometimes installed on a bracket several meters or even dozens of meters above the ground, making it difficult to directly connect the JTAG emulator for debugging. At the same time, modern radars have added signal processing processes to cope with electromagnetic interference, making the signal processing more complex. Multiple DSPs need to cooperate for processing, and it is difficult to directly connect the JTAG emulator to control multiple DSPs simultaneously during debugging. Summary of the Invention

[0004] The purpose of the present invention is to overcome the deficiencies of the prior art and provide a multi-DSP remote debugging device and a debugging method. Specifically, a remote debugging device that can be compatible with the debugging mode and the normal operation mode, facilitate long-distance remote debugging, and debug multiple DSPs simultaneously is provided. A flexible and reliable multi-DSP remote debugging method is also provided.

[0005] The purpose of the present invention is achieved through the following solutions:

[0006] A multi-DSP remote debugging device includes: an Ethernet physical layer device PHY connected to a PC and a module support unit MSU, an Ethernet switch Ethernet Switch connected through the PHY; the PC is connected to the built-in processor system PS of the MSU, the PS is connected to a PSPLIF bus reader / writer, and the PSPLIF bus reader / writer is connected to a run mode control register 1, a reset signal generator 1, a mode control register 2, a reset signal generator 2, a mode control register 3, a reset signal generator 3..., a mode control register n, a reset signal generator n through a programmable logic PL and an internal logic circuit. The reset signal generator is connected to the corresponding DSP hardware reset pin HRST, and the mode control register is connected to the external storage interface of the corresponding DSP; after the PSPLIF bus reader / writer receives the access signal from the PS, it writes the run mode into the corresponding run mode control register; after the PSPLIF bus reader / writer receives the access signal from the PS, it writes the start signal into the corresponding reset signal generator, and the reset signal generator controls the reset of the DSP hardware reset pin HRST; the PC is connected to the Ethernet switch EthernetSwitch via the PHY and is further connected to the DSP media access control interface MAC through the Ethernet Switch to achieve remote debugging of the target DSP.

[0007] Further, the connection between the PC and the built-in processor system PS of the MSU specifically includes: the PC is connected to the built-in processor system PS of the MSU through its own remote control bus interface RCIF.

[0008] Further, the connection between the PS and the PSPLIF bus reader / writer specifically includes: the PS is connected to the PSPLIF bus reader / writer through its own PSPLIF interface.

[0009] Further, the external storage interface of the DSP is specifically an EMIF module.

[0010] Further, the connection between the reset signal generator and the corresponding DSP hardware reset pin HRST specifically includes: the reset signal generator is connected to the corresponding DSP hardware reset pin HRST through discrete lines.

[0011] Further, the reset signal generator controls the reset of the DSP hardware reset pin HRST specifically includes: the reset signal generator controls the reset of the DSP hardware reset pin HRST through output discrete lines.

[0012] A multi-DSP remote debugging method based on the multi-DSP remote debugging device includes the following steps:

[0013] Step 1: The PC sends a running mode control instruction to the DSP via the Module Support Unit (MSU), starts the command-line debugging tool GDB, loads the debugging file to start debugging, executes the debugging program, and compiles the command to obtain the debugging information.

[0014] Step 2: The PS receives the DSP running mode instruction sent by the PC according to the design process, and determines whether it has received the DSP running mode instruction sent by the PC before the timeout. If so, it sets the corresponding running mode control register in the Programmable Logic (PL) to the debugging mode, and sets the remaining running mode control registers to the normal running mode. Otherwise, the PS sets all the running mode control registers in the PL to the normal running mode.

[0015] Step 3: The PS controls the reset signal generator to generate a DSP hardware reset signal.

[0016] Step 4: Load the local application program with the debugging server into the DSP.

[0017] Step 5: The DSP reads the running mode control register and judges the debugging mode. If it is not the debugging mode, the DSP directly runs the application program. Otherwise, the DSP initializes the Ethernet and the debugging server.

[0018] Step 6: The PC establishes a connection with the debugging server, sends debugging commands and receives debugging results, and the DSP receives GDB commands and debugs the application program.

[0019] Furthermore, in Step 1, the specific process of the PC sending a running mode control instruction to the DSP via the Module Support Unit (MSU) is as follows: The PC sends a running mode control instruction to the DSP via the Remote Control Interface (RCIF) through the Module Support Unit (MSU).

[0020] Furthermore, in Step 2, the specific process of the PS receiving the DSP running mode instruction sent by the PC according to the design process is as follows: The PS receives the DSP running mode instruction sent by the PC through the RCIF according to the design process.

[0021] The beneficial effects of the present invention include:

[0022] In the present invention, a PC is used to connect to the built-in processor system PS of the MSU through the RCIF. The PS is connected to the PSPLIF bus reader / writer through the PSPLIF interface. The PSPLIF bus reader / writer is connected to the operation mode control register and the reset signal generator through internal logic circuits. The reset signal generator is connected to the DSP hardware reset pin HRST through discrete lines. The mode control register is connected to the external memory interface (EMIF) of the corresponding DSP. Moreover, the PC is connected to the Ethernet switch Ethernet Switch through the PHY, and then connected to the MAC of the DSP through the Ethernet Switch, realizing that the PC can select and control whether the DSP operates in the debug state or the normal operation state, being compatible with the debug mode and the normal operation mode, facilitating the application program with a debug server without modification to be applied to the final product until now, what is adjusted is what is obtained.

[0023] In the present invention, a PC is used to connect to the built-in processor system PS of the MSU through the RCIF. The PS is connected to the PSPLIF bus reader / writer through the PSPLIF interface. The PSPLIF bus reader / writer is connected to the operation mode control register and the reset signal generator through internal logic circuits. The reset signal generator is connected to the DSP hardware reset pin HRST through discrete lines. The mode control register is connected to the external memory interface (EMIF) of the corresponding DSP. Moreover, the PC is connected to the Ethernet switch Ethernet Switch through the PHY, and then connected to the MAC of the DSP through the Ethernet Switch, realizing the remote control bus interface RCIF of the PS based on the MSU to receive PC instructions in real time and set the operation mode and reset the target processor. As long as the target module is powered on, the PC can initiate debugging at any time without re-powering, and it does not affect other DSPs. Brief Description of the Drawings

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0025] Figure 1 Schematic diagram of the multi-DSP remote debugging device for the embodiments of the present invention;

[0026] Figure 2 For Figure 1 Multi-DSP remote debugging flowchart of the device. Detailed Embodiments

[0027] All features disclosed in all embodiments in this specification, or steps in all methods or processes implicitly disclosed, except for mutually exclusive features and / or steps, can be combined and / or extended and replaced in any manner.

[0028] As Figure 1 shown, in the following described schematic preferred embodiment, a multi-DSP remote debugging device is provided, including: an Ethernet physical layer device PHY connected to a PC and a module support unit MSU, an Ethernet switch Ethernet Switch connected via the PHY, the PC is connected to the built-in processor system PS of the MSU through the built-in remote control bus interface RCIF of the PC, the PS is connected to the PSPLIF bus reader / writer through the self-provided PSPLIF interface, the PSPLIF bus reader / writer is connected to the operation mode control register 1, the reset signal generator 1, the mode control register 2, the reset signal generator 2, the mode control register 3, the reset signal generator 3..., the mode control register n, the reset signal generator n through the programmable logic PL through the internal logic circuit, the reset signal generator is connected to the corresponding DSP hardware reset pin HRST through the discrete line, and the mode control register is connected to the external storage interface (EMIF) of the corresponding DSP; after receiving the access signal from the PS, the PSPLIF bus reader / writer writes the operation mode into the corresponding operation mode control register; after receiving the access signal from the PS, the PSPLIF bus reader / writer writes the start signal into the corresponding reset signal generator, and the reset signal generator controls the reset of the DSP hardware reset pin HRST through the output discrete line; the PC is connected to the Ethernet switch Ethernet Switch via the PHY and is further connected to the above DSP media access control interface MAC through the Ethernet Switch to realize the remote debugging of the target DSP.

[0029] As Figure 2As shown in the figure, this embodiment provides a multi-DSP remote debugging method for the above multi-DSP remote debugging device, including the following steps: The PC sends a running mode control instruction to the DSP through the remote control bus interface RCIF via the module support unit MSU, and starts GDB; The PS, according to the design process, receives the DSP running mode instruction sent by the PC through the RCIF, and judges whether it has received the DSP running mode instruction sent by the PC before timeout. If so, it sets the corresponding running mode control register in the PL to the debugging mode, and sets the remaining running mode control registers to the normal running mode. Otherwise, the PS sets all running mode control registers in the PL to the normal running mode; The PS controls the reset signal generator to generate a DSP hardware reset signal; The DSP loads the local application program containing the debugging server; The DSP reads the running mode control register and judges whether it is in the debugging mode. If it is not in the debugging mode, the DSP directly runs the application program. If it is in the debugging mode, the DSP initializes the Ethernet and the debugging server; The PC establishes a connection with the debugging server, sends debugging commands and receives debugging results, and the DSP receives GDB commands and debugs the application program.

[0030] It should be noted that within the scope of protection defined in the claims of the present invention, the following embodiments can be combined and / or extended, replaced in any logical manner from the above specific implementation manners, such as the disclosed technical principles, disclosed technical features or implicitly disclosed technical features.

[0031] Embodiment 1

[0032] A multi-DSP remote debugging device, characterized by comprising:

[0033] The Ethernet physical layer device PHY connected to the PC and the module support unit MSU, and the Ethernet switch Ethernet Switch connected through the PHY; The PC is connected to the built-in processor system PS of the MSU, the PS is connected to the PSPLIF bus reader / writer, and the PSPLIF bus reader / writer is connected through the programmable logic PL and through the internal logic circuit to the running mode control register 1, the reset signal generator 1, the mode control register 2, the reset signal generator 2, the mode control register 3, the reset signal generator 3…, the mode control register n, the reset signal generator n. The reset signal generator is connected to the corresponding DSP hardware reset pin HRST, and the mode control register is connected to the external storage interface of the corresponding DSP;

[0034] After the PSPLIF bus reader / writer receives the access signal from the PS, it writes the operating mode into the corresponding operating mode control register; after the PSPLIF bus reader / writer receives the access signal from the PS, it writes the start signal into the corresponding reset signal generator, and the reset signal generator controls the reset of the hardware reset pin HRST of the DSP; the PC is connected to the Ethernet switch EthernetSwitch via the PHY and then connected to the DSP media access control interface MAC through the Ethernet Switch to realize the remote debugging of the target DSP.

[0035] In other embodiments, based on Embodiment 1, the connection between the PC and the MSU built-in processor system PS specifically includes: the PC is connected to the MSU built-in processor system PS through its own remote control bus interface RCIF.

[0036] In other embodiments, based on Embodiment 1, the connection between the PS and the PSPLIF bus reader / writer specifically includes: the PS is connected to the PSPLIF bus reader / writer through its own PSPLIF interface.

[0037] In other embodiments, based on Embodiment 1, the external storage interface of the DSP is specifically the EMIF module.

[0038] In other embodiments, based on Embodiment 1, the connection between the reset signal generator and the corresponding DSP hardware reset pin HRST specifically includes: the reset signal generator is connected to the corresponding DSP hardware reset pin HRST through discrete lines.

[0039] In other embodiments, based on Embodiment 1, the reset of the DSP hardware reset pin HRST controlled by the reset signal generator specifically includes: the reset signal generator controls the reset of the DSP hardware reset pin HRST through the output discrete lines.

[0040] A multi-DSP remote debugging method based on a multi-DSP remote debugging device includes the following steps:

[0041] Step 1, the PC sends a running mode control instruction to the DSP through the module support unit MSU, starts the command line debugging tool GDB, loads the debugging file to start debugging, executes the debugging program, and compiles the command to compile and obtain the debugging information;

[0042] Step 2, the PS receives the DSP running mode instruction sent by the PC according to the design process, judges whether it receives the DSP running mode instruction sent by the PC before timeout. If so, it sets the corresponding running mode control register in the programmable logic PL to the debugging mode, and the remaining running mode control registers are set to the normal running mode. Otherwise, the PS sets all the running mode control registers in the PL to the normal running mode;

[0043] Step 3, the PS control reset signal generator generates a DSP hardware reset signal;

[0044] Step 4, load the application program containing the debug server locally to the DSP;

[0045] Step 5, the DSP reads the operation mode control register and judges the debug mode. If it is not the debug mode, the DSP directly runs the application program. Otherwise, the DSP initializes the Ethernet and the debug server;

[0046] Step 6, the PC establishes a connection with the debug server, sends debug commands and receives debug results, and the DSP receives GDB commands and debugs the application program.

[0047] In other embodiments, based on Embodiment 7, in Step 1, the specific process of the PC sending the operation mode control instruction to the DSP through the module support unit MSU includes: the PC sends the operation mode control instruction to the DSP through the remote control bus interface RCIF and the module support unit MSU.

[0048] In other embodiments, based on Embodiment 7, in Step 2, the PS receives the DSP operation mode instruction sent by the PC according to the design process, which specifically includes: the PS receives the DSP operation mode instruction sent by the PC through the RCIF according to the design process.

[0049] The units involved in the embodiments of the present invention can be implemented in software or in hardware, and the described units can also be provided in a processor. Among them, the names of these units do not constitute a limitation to the unit itself in some cases.

[0050] According to one aspect of the embodiments of the present invention, a computer program product or a computer program is provided. The computer program product or the computer program includes computer instructions, and the computer instructions are stored in a computer-readable storage medium. The processor of the computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device executes the methods provided in the above various optional implementation manners.

[0051] As another aspect, the embodiments of the present invention further provide a computer-readable medium, which may be included in the electronic device described in the above embodiments; or may exist separately without being assembled into the electronic device. The above computer-readable medium carries one or more programs, and when the one or more programs are executed by an electronic device, the electronic device implements the methods described in the above embodiments.

Claims

1. A multi-DSP remote debugging device, characterized in that, Comprising: An Ethernet physical layer device PHY connected to a PC and a module support unit MSU, and an Ethernet switch Ethernet Switch connected via the PHY; The PC is connected to the built-in processor system PS of the MSU, the PS is connected to a PSPLIF bus reader / writer, and the PSPLIF bus reader / writer is connected via a programmable logic PL and an internal logic circuit to operation mode control register 1, reset signal generator 1, mode control register 2, reset signal generator 2, mode control register 3, reset signal generator 3…, mode control register n, reset signal generator n. The reset signal generator is connected to the corresponding DSP hardware reset pin HRST, and the mode control register is connected to the external storage interface of the corresponding DSP; After the PSPLIF bus reader / writer receives an access signal from the PS, it writes the operation mode into the corresponding operation mode control register; the PS, according to the designed process, receives a DSP operation mode instruction sent by the PC, and judges whether it receives the DSP operation mode instruction sent by the PC before timeout. If so, it sets the corresponding operation mode control register in the programmable logic PL to the debug mode, and the remaining operation mode control registers are set to the normal operation mode. Otherwise, the PS sets all the operation mode control registers in the PL to the normal operation mode; after the PSPLIF bus reader / writer receives an access signal from the PS, it writes a start signal into the corresponding reset signal generator, and the reset signal generator controls the reset of the DSP hardware reset pin HRST; the PC is connected to the Ethernet switch Ethernet Switch via the PHY and then connected to the DSP media access control interface MAC through the Ethernet Switch to realize remote debugging of the target DSP.

2. The multi-DSP remote debugging device according to claim 1, characterized in that, The connection of the PC to the built-in processor system PS of the MSU specifically includes: the PC is connected to the built-in processor system PS of the MSU through its own remote control bus interface RCIF.

3. The multi-DSP remote debugging device according to claim 1, wherein, The connection of the PS to the PSPLIF bus reader / writer specifically includes: the PS is connected to the PSPLIF bus reader / writer through its own PSPLIF interface.

4. The multi-DSP remote debugging device according to claim 1, characterized in that, The external storage interface of the DSP is specifically an EMIF module.

5. The multi-DSP remote debugging device according to claim 1, characterized in that The connection of the reset signal generator to the corresponding DSP hardware reset pin HRST specifically includes: the reset signal generator is connected to the corresponding DSP hardware reset pin HRST through discrete lines.

6. The multi-DSP remote debugging device according to claim 1, characterized in that The reset signal generator controls the reset of the DSP hardware reset pin HRST specifically includes: the reset signal generator controls the reset of the DSP hardware reset pin HRST through output discrete lines.

7. A multi-DSP remote debugging method based on a multi-DSP remote debugging device, characterized in that, Including the following steps: Step 1, the PC sends an operation mode control instruction to the DSP via the module support unit MSU, and starts the command line debugging tool GDB, loads the debug file to start debugging, executes the debug program, and compiles the command to compile to obtain debug information; Step 2: The PS receives the DSP operation mode instruction sent by the PC according to the design process, and determines whether it has received the DSP operation mode instruction sent by the PC before timeout. If so, it sets the corresponding operation mode control register in the programmable logic (PL) to the debug mode, and sets the remaining operation mode control registers to the normal operation mode. Otherwise, the PS sets all the operation mode control registers in the PL to the normal operation mode; Step 3: The PS controls the reset signal generator to generate the DSP hardware reset signal; Step 4: Load the local application program containing the debug server into the DSP; Step 5: The DSP reads the operation mode control register and determines the debug mode. If it is not the debug mode, the DSP directly runs the application program. Otherwise, the DSP initializes the Ethernet and the debug server; Step 6: The PC establishes a connection with the debug server, sends debug commands and receives debug results, and the DSP receives GDB commands and debugs the application program.

8. The multi-DSP remote debugging method based on the multi-DSP remote debugging device according to claim 7, characterized in that In Step 1, the PC sends the operation mode control instruction to the DSP via the Module Support Unit (MSU), which specifically includes: The PC sends the operation mode control instruction to the DSP via the Remote Control Interface (RCIF) and the MSU.

9. The multi-DSP remote debugging method based on the multi-DSP remote debugging device according to claim 7, characterized in that, In Step 2, the PS receives the DSP operation mode instruction sent by the PC according to the design process, which specifically includes: The PS receives the DSP operation mode instruction sent by the PC via the RCIF according to the design process.

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