A multi-bit read decision circuit, memory and multi-bit binary data reading method

Abstract

The present invention discloses a multi-bit read decision circuit, a memory, and a multi-bit binary data reading method. The multi-bit read decision circuit includes: a multiplexing module for performing gating control on a memory column; a voltage clamping module electrically connected to the multiplexing module, the voltage clamping module for reading a first current signal from a memory array, converting the first current signal into a first converted voltage signal for output; a multi-bit parallel comparison module electrically connected to the voltage clamping module, the multi-bit parallel comparison module for receiving the first converted voltage signal and converting the first converted voltage signal into multiple copied current signals according to a specific copy ratio relationship, comparing the multiple copied current signals with multiple reference current signals, and outputting a comparison result; and a biasing module electrically connected to both the voltage clamping module and the multi-bit parallel comparison module, the biasing module for providing the first clamping voltage signal to the voltage clamping module. The present invention avoids the generation of complex reference currents.

Description

Technical Field

[0001] The present invention relates to the field of memory, and in particular to a multi-bit read decision circuit, a memory and a multi-bit binary data reading method. Background Art

[0002] The basic structure of a memory device consists of one or more memory arrays, a data bus, a control bus, an address bus, an address decoder, and read / write circuits. A memory array is composed of multiple memory cells, which are organized in rows and columns to form a multidimensional matrix or array structure.

[0003] Information is stored by programming the memory cells in the memory into various states. The memory cell contains at least one semiconductor device. A single memory cell can support two or more storage states. The storable states in the memory cell are binary programmed, that is, they support multi-bit binary numbers (2 m , m is an integer greater than zero) states, and the storage unit can be programmed into the above 2 states according to input data and control instructions m One of two supported states. Based on the number of binary states a memory cell can store, it can be categorized as single-bit binary memory and multi-bit binary memory. A single-bit binary memory cell only supports storing one bit of binary data and can be programmed to only one of two supported states, typically represented by logic 1 or logic 0. Multi-bit binary memory can support multiple binary data states, where m > 1.

[0004] Regardless of whether a multi-bit binary memory employs a parallel or serial read circuit, storing multiple bits of binary data in a memory cell can provide a larger data storage capacity and higher data storage density than storing a single bit of data. However, compared to single-bit data memory, multi-bit binary memory requires multiple reference voltage or current signals for comparison in order to distinguish between multiple data states within the memory cell. Generating these reference signals is inherently complex. Summary of the Invention

[0005] Embodiments of the present invention provide a multi-bit read decision circuit, a memory, and a multi-bit binary data reading method, which are used to at least solve the problem in the prior art of requiring the use of multiple reference voltages or current signals for comparison.

[0006] A first embodiment of the present invention provides a multi-bit read decision circuit for performing data read decision on a memory. The multi-bit read decision circuit includes:

[0007] a multiplexing module electrically connected to a memory rank group of the memory, wherein the memory rank group includes at least one memory rank, and the multiplexing module is used to perform strobe control on the memory rank;

[0008] a voltage clamping module, electrically connected to the multiplexing module, configured to read a first current signal from the storage array and convert the first current signal into a first converted voltage signal for output;

[0009] a multi-bit parallel comparison module, electrically connected to the voltage clamping module, configured to receive the first converted voltage signal, convert the first converted voltage signal into multiple copied current signals according to a specific copy ratio, compare the multiple copied current signals with multiple reference current signals, output a comparison result, and complete a read decision operation on the memory column group;

[0010] The bias module is electrically connected to the voltage clamp module and the multi-bit parallel comparison module. The bias module is used to provide a first clamp voltage signal to the voltage clamp module and a first common mode voltage signal to the multi-bit parallel comparison module.

[0011] According to some embodiments of the present invention, the multiplexing module includes:

[0012] a plurality of selection switches, wherein the number of the selection switches corresponds to the number of the memory columns, the selection switches and the memory columns have a single mapping relationship and are electrically connected; the selection switches have at least three ports, the first port is electrically connected to the bit line of the corresponding memory column, the second port is electrically connected to the voltage clamping module, and the third port is electrically connected to the enable signal control port of the memory.

[0013] According to some embodiments of the present invention, the voltage clamping module includes: a first PMOS transistor and a first operational amplifier; the negative input terminal of the first operational amplifier is electrically connected to the bias module for receiving the first clamping voltage signal, the positive input terminal of the first operational amplifier is electrically connected to the drain terminal of the first PMOS transistor, the output terminal of the first operational amplifier is electrically connected to the gate terminal of the first PMOS transistor, and the gate terminal of the first PMOS transistor is electrically connected to the second port; the first PMOS transistor and the first operational amplifier form a high-gain negative feedback, clamping the drain terminal of the first PMOS transistor to the first clamping voltage, the first PMOS transistor receives the first current signal from the second port, converts it into the first converted voltage signal, and outputs it at the gate terminal of the first PMOS transistor;

[0014] According to some embodiments of the present invention, the multi-bit parallel comparison module is composed of several comparison submodules, each of which is provided with a replica current circuit. The replica current circuit includes at least one second PMOS transistor. When there are multiple second PMOS transistors, the second PMOS transistors share a source, a gate, and a drain. The gate terminal of the second PMOS transistor is electrically connected to the gate terminal of the first PMOS transistor, and is configured to receive the first converted voltage signal and convert the first converted voltage signal into the multiple replicated current signals according to a specific replication ratio.

[0015] A plurality of reference current generating circuits, the number of which matches the number of the comparison submodules, the reference current generating circuits being electrically connected to the replica current circuit, and the reference current generating circuits outputting reference current signals to the replica current circuit.

[0016] According to some embodiments of the present invention, the specific replication ratio is adjustable by changing the ratio of the width-to-length ratio of the second PMOS transistor to the width-to-length ratio of the first PMOS transistor, or by changing the number of the second PMOS transistors.

[0017] A second aspect of the present invention provides a memory, comprising: a plurality of storage column groups, and a multi-bit read decision circuit as described in any one of the first aspect embodiments, wherein the storage column groups are coupled to the multi-bit read decision circuit, and the multi-bit read decision circuit is configured to perform a read decision operation on the storage cells.

[0018] According to some embodiments of the present invention, the memory column group has a read-write separation feature, and each memory cell of the memory column group has an independent read electrical path and an independent write electrical path; the data stored in the memory cell is read out by converting it into a first current signal.

[0019] According to some embodiments of the present invention, the memory cell has quasi-non-volatility, the memory cell retains the written data for more than 100 seconds, and the data written to the memory cell can be correctly read after the retention time.

[0020] A third aspect of the present invention provides a method for reading multi-bit binary data, which uses the multi-bit read decision circuit described in any one of the first aspect embodiments to read data, specifically comprising:

[0021] The bias module provides a first clamping voltage signal to the voltage clamping module;

[0022] The voltage clamping module receives a first clamping voltage signal, reads a first current signal from the storage array, and converts the first current signal into a first converted voltage signal for output;

[0023] The multi-bit parallel comparison module receives the first conversion voltage signal, converts the first conversion voltage signal into multiple copied current signals according to a specific copy ratio, compares the multiple copied current signals with multiple reference current signals, and outputs a comparison result.

[0024] The technical solutions in the embodiments of the present invention compare the replica current with the reference current and, through the setting of the replica ratio, distinguish the compared replica current from the original read current. Multiple reference currents can be equal to the read currents corresponding to various data states of the memory cell, avoiding the generation of complex reference currents. Furthermore, by applying a clamping structure to maintain the array bitline voltage stable, the bitline voltage of the target memory array is unaffected by the data state stored in the target array during a read operation.

[0025] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are specifically listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Various other advantages and benefits will become apparent to those skilled in the art by reading the detailed description of the embodiments below. The accompanying drawings are only for the purpose of illustrating preferred embodiments and are not to be considered as limiting the present invention. In the accompanying drawings:

[0027] Figure 1 1 is a schematic structural diagram of a multi-bit read decision circuit according to an embodiment of the present invention;

[0028] Figure 2 1 is a schematic structural diagram of a multi-bit read decision circuit according to an embodiment of the present invention;

[0029] Figure 3 is a structural diagram of a current comparison submodule in an embodiment of the present invention;

[0030] Figure 4 is a simplified schematic diagram of an amorphous oxide 2TOC memory array according to an embodiment of the present invention;

[0031] Figure 5 FIG. 1 is a schematic structural diagram of a multi-bit read decision circuit applied to data reading of a multi-bit binary memory cell in an amorphous oxide 2T0C cell memory array according to an embodiment of the present invention. DETAILED DESCRIPTION

[0032] Exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present invention and to fully convey the scope of the present invention to those skilled in the art.

[0033] A first embodiment of the present invention provides a multi-bit read decision circuit for performing data read decision on a memory, the multi-bit read decision circuit comprising:

[0034] A multiplexing module is electrically connected to a memory rank group of the memory. The memory rank group includes at least one memory rank and is the target of a multi-way read decision circuit. During a read decision process, a decision operation can only be performed on one memory rank in the memory rank group at a time. The multiplexing module is used to perform strobe control on the one memory rank in the memory rank group.

[0035] The voltage clamping module is electrically connected to the multiplexing module. The voltage clamping module implements a voltage clamping function on a read bit line of the read memory, reads a first current signal input from the bit line, and converts the first current signal into a first converted voltage signal for output.

[0036] a multi-bit parallel comparison module, electrically connected to the voltage clamping module, configured to receive the first converted voltage signal, convert the first converted voltage signal into multiple copied current signals according to a specific copy ratio, compare the multiple copied current signals with multiple reference current signals, output a comparison result, and complete a read decision operation on the memory column group;

[0037] The bias module is electrically connected to the voltage clamp module and the multi-bit parallel comparison module. The bias module is used to provide a first clamp voltage signal to the voltage clamp module and a first common mode voltage signal to the multi-bit parallel comparison module.

[0038] The technical solutions in the embodiments of the present invention compare the replica current with the reference current and, through the setting of the replica ratio, distinguish the compared replica current from the original read current. Multiple reference currents can be equal to the read currents corresponding to various data states of the memory cell, avoiding the generation of complex reference currents. Furthermore, by applying a clamping structure to maintain the array bitline voltage stable, the bitline voltage of the target memory array is unaffected by the data state stored in the target array during a read operation.

[0039] Based on the above embodiment, various modified embodiments are further proposed. It should be noted that, in order to simplify the description, only the differences from the above embodiment are described in each modified embodiment.

[0040] According to some embodiments of the present invention, a multi-bit read decision circuit is suitable for making a decision on a multi-bit binary memory. A minimum storage unit of the multi-bit binary memory can store a multi-bit binary data. The storage unit of the memory can store 2 m More than one different storage state, wherein m is the number of binary data bits stored in the memory. The storage unit can support a number equal to or greater than the number of binary bits stored, that is, 2 m One or more resistance states or conduction states. A certain data state corresponds to a certain resistance state or conduction state. The multi-bit binary memory may be a memory based on amorphous oxide transistors, a memory based on resistive switching materials, a memory based on phase change materials, or a memory based on magnetic tunnel junctions.

[0041] According to some embodiments of the present invention, the multiplexing module includes:

[0042] a plurality of selection switches, wherein the number of the selection switches corresponds to the number of the memory columns, the selection switches and the memory columns have a single mapping relationship and are electrically connected; the selection switches have at least three ports, the first port is electrically connected to the bit line of the corresponding memory column, the second port is electrically connected to the voltage clamping module, and the third port is electrically connected to the enable signal control port of the memory.

[0043] According to some embodiments of the present invention, the voltage clamping module includes: a first PMOS transistor and a first operational amplifier; the negative input terminal of the first operational amplifier is electrically connected to the bias module for receiving the first clamping voltage signal, the positive input terminal of the first operational amplifier is electrically connected to the drain terminal of the first PMOS transistor, the output terminal of the first operational amplifier is electrically connected to the gate terminal of the first PMOS transistor, and the gate terminal of the first PMOS transistor is electrically connected to the second port; the first PMOS transistor and the first operational amplifier form a high-gain negative feedback, so that the drain terminal of the first PMOS transistor is clamped to the first clamping voltage, the first PMOS transistor receives the first current signal from the second port, and converts it into the first conversion voltage signal and outputs it at the gate terminal of the first PMOS transistor.

[0044] According to some embodiments of the present invention, a pre-charging operation is performed on the voltage clamping module before a read operation, so that the voltage clamping module can be started quickly.

[0045] According to some embodiments of the present invention, the multi-bit parallel comparison module is composed of several comparison sub-modules, each of which is provided with a replica current circuit, and the replica current circuit includes at least one second PMOS transistor. When there are multiple second PMOS transistors, the second PMOS transistors share a source, a gate, and a drain; the gate end of the second PMOS transistor is electrically connected to the gate end of the first PMOS transistor, and is used to receive the first conversion voltage signal and convert the first conversion voltage signal into the multiple replica current signals according to a specific replication ratio.

[0046] A plurality of reference current generating circuits, the number of which matches the number of the comparison submodules, the reference current generating circuits being electrically connected to the replica current circuit, and the reference current generating circuits outputting reference current signals to the replica current circuit.

[0047] According to some embodiments of the present invention, the specific circuit connection mode of the comparison submodule is as follows: Figure 3 .

[0048] According to some embodiments of the present invention, the relationship between the number M of the comparison submodules and the number m of binary data bits stored in the memory is M=2m-1.

[0049] According to some embodiments of the present invention, the specific replication ratio relationship is determined based on statistical distribution characteristics of storage states of minimum storage units in a memory.

[0050] According to some embodiments of the present invention, the specific replication ratio is adjustable by changing the ratio of the width-to-length ratio of the second PMOS transistor to the width-to-length ratio of the first PMOS transistor, or by changing the number of second PMOS transistors. Implementation of this replication ratio improves the accuracy of the decision result of the current comparison submodule. Furthermore, when the gate terminals of multiple second PMOS transistors synchronously read the first converted voltage signal, the multi-bit read decision circuit performs data reading operations at a faster speed.

[0051] According to some embodiments of the present invention, current signals of different reference current generating circuits may be set between replica current signals generated by different data current signals. To improve readability, the reading of two current signals is taken as an example. Reference Table 1 illustrates the relationship between the two-bit data unit current signal Idata and the corresponding replica current signal Isen, wherein Idata0, Idata1, Idata2, and Idata3 represent four current signals of the two-bit current signal, and their specific numerical values ​​are arranged from small to large as follows: Idata0, Idata1, Idata2, and Idata3; wherein Isen1, Isen2, Isen3, and Isen4 represent the corresponding replica current signals output by the four current signals of the two-bit current signal in the multi-bit parallel comparison module; wherein Q represents the width-to-length ratio of the first PMOS transistor in the voltage clamp module, and K represents the width-to-length ratio of the second PMOS transistor in the multi-bit parallel comparison module; Table 2 illustrates the relationship between the reference current signal Iref and the two-bit data unit current signal Idata and the corresponding replica current signal Isen; wherein Iref1, Iref2, and Iref3 represent the first reference current signal, the second reference current signal, and the third reference current signal, respectively.

[0052]

[0053] Table 1

[0054] Referring to Table 2, the magnitude of the reference current signal is equal to the unit current signal Idata. Taking the example of reading two current signals, the magnitude of the first reference current Iref1 is set to the unit current signal Idata2 for storing the "1" current signal; the magnitude of the second reference current Iref2 is set to the unit current signal Idata3 for storing the "2" current signal; and the magnitude of the third reference current Iref3 is set to the unit current signal Idata4 for storing the "3" current signal. By setting the width-to-length ratio Q of the first PMOS transistor in the voltage clamp module 1032 and the width-to-length ratio K of the second PMOS transistor in the multi-bit parallel comparison module 1033, the reference current signals conform to the reference current signal ranges specified in Table 2. The advantage of having the magnitude of the reference current signal equal to the unit current signal Idata is that the write conditions for storing the reference current are consistent with the write conditions for storing the memory cell, and the fluctuations of the reference current signal and the unit current signal are completely consistent across different processes, temperatures, and voltages.

[0055] Reference circuit current signal Reference current signal range <![CDATA[I ref1 ]]> <![CDATA[(I sen1 ,I sen2 )]]> <![CDATA[I ref2 ]]> <![CDATA[(I sen2 ,I sen3 )]]> <![CDATA[I ref3 ]]> <![CDATA[(I sen3 ,I sen4 )]]>

[0056] Table 2

[0057] According to some embodiments of the present invention, the width-to-length ratio of the second PMOS transistor in the current comparison submodule in the multi-bit parallel comparison module is not necessarily equal to K. The width-to-length ratio of the second PMOS transistor in different current comparison submodules can be adjusted according to simulation results to obtain the highest reading accuracy.

[0058] According to some embodiments of the present invention, reference Figure 4 For amorphous oxide 2T0C memory, embodiments of the multi-bit read decision circuit of the present invention can be used, and also include a series of multi-bit binary memory arrays, such as resistive random access memory (RRAM) arrays, magnetic random access memory (MRAM) arrays, amorphous oxide 3T0C memory arrays, flash memory arrays, etc. To improve readability, the memory array in the figure does not show all necessary components. For example, only three write bit lines (WBL1, WBL2, WBL3) are shown in the figure, but the actual number of write bit lines required should be determined by the memory density. The array includes an amorphous oxide 2T0C memory array, which is arranged in columns 104, 105, and 106. The amorphous oxide 2T0C cell is composed of an amorphous oxide transistor M1 and an amorphous oxide transistor M2, where M1 is a write transistor and M2 is a read transistor. The gate terminal of M1 is connected to the write word line (WWL), the source terminal is connected to the write bit line (WBL), and the drain terminal is connected to the gate terminal of M2. The source terminal of M2 is connected to the read word line (RWL) and the drain terminal is connected to the read bit line (RBL). Each amorphous oxide 2T0C cell is connected in the columns of the memory array via the source interconnects of the write transistors and the drain interconnects of each read transistor. A write bit line (WWL) spanning columns 104, 105, and 106 connects to the source terminals of the write transistors of each amorphous oxide 2T0C cell in the row, while a read bit line (RWL) spanning columns 104, 105, and 106 connects to the source terminals of the read transistors of each amorphous oxide 2T0C cell in the row to control read and write operations. The read bit lines (RBL0-RBL2) are ultimately connected to a read decision circuit (not shown) that detects the state of each amorphous oxide 2T0C cell.

[0059] According to some embodiments of the present invention, for the amorphous oxide 2TOC cell, during a write operation, the write transistor is turned on via the write word line (WWL), and different amounts of charge are written and stored on the gate capacitance of the read transistor by giving different write bit line (WBL) voltage values ​​or different write transistor on-times. Each cell can be programmable as a single-level cell (single-level cell) or multiple bits per cell (multi-level cell), and the amount of charge on the gate capacitance of each cell determines the data stored in the cell. During a read operation, a voltage is applied to the read word line (RWL) of the read transistor, and different read currents are formed on the read bit line (RBL) depending on the amount of charge stored on the gate capacitance of the read transistor.

[0060] According to some embodiments of the present invention, for an amorphous oxide 2TOC cell, during a write operation, the write transistor is turned on via the write bit line (WBL), and different amounts of charge are written and stored on the gate capacitance of the read transistor by varying the write word line (WWL) voltage. During a read operation, a voltage is applied to the read word line (RWL) of the read transistor, and different read currents are generated on the read bit line (RBL) depending on the amount of charge stored on the gate capacitance of the read transistor. Optionally, the threshold voltage of the read transistor in the amorphous oxide 2TOC cell is different from the write crystal voltage, and the amorphous oxide 2TOC cell can be composed of a write transistor with a high threshold voltage and a read transistor with a low threshold voltage.

[0061] According to some embodiments of the present invention, reference Figure 5 The multi-bit read decision circuit is used for reading data from a multi-bit binary memory cell of an amorphous oxide 2T0C cell memory array. The amorphous oxide 2T0C cell memory array includes:

[0062] An amorphous oxide 2T0C cell memory array is provided, wherein the amorphous oxide 2T0C cell memory array is used to store a plurality of multi-bit binary data and output an amorphous oxide 2T0C memory cell current signal to a multi-bit read decision circuit.

[0063] A reference voltage generating circuit is configured to output a reference voltage signal Vcm.

[0064] A plurality of multi-bit read decision circuits are configured to receive a reference voltage signal Vcm and an amorphous oxide 2T0C memory cell current signal, and output a multi-bit binary read result of the amorphous oxide 2T0C memory cell based on the reference voltage signal Vcm and the amorphous oxide 2T0C memory cell current signal.

[0065] The encoder circuit is used to receive the multi-bit binary data reading result output by the multi-bit read decision circuit and convert it into a digital binary signal based on the result output by the multi-bit read decision circuit module.

[0066] Optionally, multiple read bit lines in the memory array are connected to a multi-bit read decision circuit. The specific requirement for the multi-bit read decision circuit in the array depends on the density of the memory array and the number of read bit lines connected to a multi-bit read decision circuit.

[0067] Specifically, in the multi-bit binary data read mode, the write bit line and the write word line of the amorphous oxide 2T0C cell array are both applied with a ground voltage signal GND to ensure that the write transistor is in the off state; the selection switch of the multiplexing module in the multi-bit read decision circuit to which the target read unit read bit line is connected is turned on, and the selection switch of the multiplexing module in the multi-bit read decision circuit to which the target read unit read bit line is not connected is turned off; the read word line of the row where the target read unit is located is applied with a ground voltage signal voltage GND, and the row where the non-target read unit is located is applied with a common mode voltage Vcm; the voltage clamping module in the multi-bit read decision circuit clamps the read bit line of the column where the target read unit is located The common mode voltage Vcm makes the source-drain voltage Vds of the read transistor of the target read unit Vcm; the source-drain voltage Vds of the read transistor of the same line as the non-target read unit is 0V; thus, the current flowing through the first PMOS tube in the voltage clamping module in the multi-bit read decision circuit is equal to the target read unit current signal, and a first conversion voltage signal is output based on the target read unit current signal; the multi-bit parallel comparison module in the multi-bit read decision circuit outputs a multi-bit binary data read result based on the first conversion voltage signal; the encoder receives the multi-bit binary data read result, and outputs a digital binary signal based on the multi-bit binary data read result.

[0068] The reference cell for the multi-bit parallel comparison module of the multi-bit read decision circuit of the amorphous oxide 2T0C cell array is an amorphous oxide 2T0C reference cell. Its circuit structure is identical to that of the amorphous oxide 2T0C cell, and its write method is also consistent with that of the memory cell. Therefore, the reference current signal generated by the amorphous oxide 2T0C reference cell and the current signal of the amorphous oxide 2T0C cell fluctuate in the same manner under different process / temperature / voltage conditions, improving read accuracy under different process / temperature / voltage conditions.

[0069] A second aspect of the present invention provides a memory comprising at least: a plurality of storage column groups, and a multi-bit read decision circuit as described in any one of the first aspect embodiments, wherein the storage column groups are coupled to the multi-bit read decision circuit, and the multi-bit read decision circuit is configured to perform a read decision operation on the storage cells.

[0070] According to some embodiments of the present invention, the memory column group has a read-write separation feature, and each memory cell of the memory column group has an independent read electrical path and an independent write electrical path; the data stored in the memory cell is read out by converting it into a first current signal.

[0071] According to some embodiments of the present invention, the memory cell has quasi-non-volatility, the memory cell retains the written data for more than 100 seconds, and the data written to the memory cell can be correctly read after the retention time.

[0072] A third aspect of the present invention provides a method for reading multi-bit binary data, which uses the multi-bit read decision circuit described in any one of the first aspect embodiments to read data, specifically comprising:

[0073] The bias module provides a first clamping voltage signal to the voltage clamping module;

[0074] The voltage clamping module receives a first clamping voltage signal, reads a first current signal from the storage array, and converts the first current signal into a first converted voltage signal for output;

[0075] The multi-bit parallel comparison module receives the first conversion voltage signal, converts the first conversion voltage signal into multiple copied current signals according to a specific copy ratio, compares the multiple copied current signals with multiple reference current signals, and outputs a comparison result.

[0076] The following describes a multi-bit read decision circuit according to an embodiment of the present invention in detail using a specific embodiment with reference to the accompanying drawings. It should be understood that the following description is merely illustrative and does not limit the present invention. Any similar structures and variations thereof employing the present invention should be included within the scope of protection of the present invention.

[0077] refer to Figure 1-2 The multi-bit read decision circuit includes a multiplexing module, a voltage clamping module, a multi-bit parallel comparison module, and a bias module which are connected in sequence.

[0078] The multiplexing module is connected to multiple (read) bit lines of the memory array, receives multiple (read) bit line current signals, and outputs a first data current signal via a control signal. The voltage clamping module is configured to receive the first data current signal and output a first converted voltage signal based on the first data current signal. The bias module can provide a stable fixed voltage; the bias module is connected to the voltage clamping module and is configured to provide a first clamping voltage signal Vcm to the voltage clamping module 1. The bias module is connected to the multi-bit parallel comparison module and is configured to provide a first common-mode voltage signal Vcm to the multi-bit parallel comparison module. The multi-bit parallel comparison module includes multiple current comparison submodules, the number of which is equal to 2m-1, where m represents the number of stored binary bits. The multi-bit parallel comparison module is configured to receive the first converted voltage signal and generate multiple replica current signals based on the first converted voltage signal. The replica current is a current signal that replicates the first data current signal at a certain ratio. The replica current signals are compared with a reference current signal to obtain multiple output voltage signals, i.e., the data output results.

[0079] The multiplexing module is composed of a plurality of selection switches connected to a plurality of read bit lines of the memory array, and receives and outputs a first data current signal based on a control signal. Each selection switch includes at least three ports, the first port of which is respectively connected to a plurality of read bit lines of the memory cell array, and the second ports of the plurality of selection switches are all connected to the voltage clamping module. The current signal of a selected bit line can be used as the first current signal I data The voltage clamp module is composed of a first operational amplifier (OP) and a first PMOS transistor, wherein the width-to-length ratio of the first PMOS transistor is equal to Q. It is used to clamp the (read) bit line voltage and receive the first data current signal I data , and based on the first data current signal I data , outputs the first conversion voltage signal Vg. The multi-bit parallel comparison module is composed of multiple current comparison sub-modules, wherein the current comparison sub-module is composed of a second PMOS transistor, a comparison switch, a reference current generation circuit and a signal comparison module. The circuit structures of the multiple current comparison sub-modules are consistent. The second PMOS transistor is used to receive the first conversion voltage signal Vg and output a replica current signal I based on the first conversion voltage signal Vg. sen ; Wherein, the width-to-length ratio of the second PMOS is equal to K, and the size of the copy current signal is equal to the first data current signal times; the first replica current signal I sen The reference current generating circuit is connected to output the first feedback voltage signal Vf, and the first signal comparison module compares the first feedback voltage signal Vf with the first common mode voltage signal Vcm to output the voltage signal V1. Obviously, multiple current comparison submodules output multiple voltage signals, that is, output multiple-bit binary data reading results.

[0080] It should be noted that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention are intended to be within the scope of protection of the present invention.

[0081] It should be noted that, in the description of this specification, well-known methods, structures and technologies are not shown in detail so as not to obscure the understanding of this specification.

Claims

1. A multi-bit read decision circuit for performing data read decision on a memory, characterized in that: The multi-bit read decision circuit comprises: a multiplexing module electrically connected to a memory rank group of the memory, wherein the memory rank group includes at least one memory rank, and the multiplexing module is used to perform strobe control on the memory rank; a voltage clamping module, electrically connected to the multiplexing module, configured to read the first current signal of the memory column group and convert the first current signal into a first converted voltage signal for output; a multi-bit parallel comparison module, electrically connected to the voltage clamping module, configured to receive the first converted voltage signal, convert the first converted voltage signal into multiple copied current signals according to a specific copy ratio, compare the multiple copied current signals with multiple reference current signals, output a comparison result, and complete a read decision operation on the memory column group; a bias module, electrically connected to the voltage clamping module and the multi-bit parallel comparison module, the bias module being configured to provide a first clamping voltage signal to the voltage clamping module and a first common-mode voltage signal to the multi-bit parallel comparison module; The multi-bit parallel comparison module is composed of a plurality of comparison submodules, each of which is provided with a replica current circuit. The replica current circuit includes at least one second PMOS transistor. When there are multiple second PMOS transistors, the second PMOS transistors share a source, a gate, and a drain. The gate terminal of the second PMOS transistor is electrically connected to the gate terminal of the first PMOS transistor, and is configured to receive the first converted voltage signal and convert the first converted voltage signal into the multiple replicated current signals according to a specific replication ratio. a plurality of reference current generating circuits, the number of the reference current generating circuits being adapted to the number of the comparison submodules, the reference current generating circuits being electrically connected to the replica current circuit, and the reference current generating circuits outputting reference current signals to the replica current circuit; The specific replication ratio relationship is adjustable, and the adjustment method is to change the ratio of the width-to-length ratio of the second PMOS tube to the width-to-length ratio of the first PMOS tube, or to change the number of the second PMOS tubes.

2. The multi-bit read decision circuit according to claim 1, wherein: The multiplexing module includes: a plurality of selection switches, wherein the number of the selection switches corresponds to the number of the memory columns, the selection switches and the memory columns have a single mapping relationship and are electrically connected; the selection switches have at least three ports, a first port is electrically connected to a bit line of the corresponding memory column, a second port is electrically connected to the voltage clamping module, and a third port is electrically connected to an enable signal control port of the memory.

3. The multi-bit read decision circuit according to claim 2, wherein: The voltage clamping module includes: a first PMOS transistor and a first operational amplifier; the negative input terminal of the first operational amplifier is electrically connected to the bias module for receiving the first clamping voltage signal, the positive input terminal of the first operational amplifier is electrically connected to the drain terminal of the first PMOS transistor, the output terminal of the first operational amplifier is electrically connected to the gate terminal of the first PMOS transistor, and the gate terminal of the first PMOS transistor is electrically connected to the second port; the first PMOS transistor and the first operational amplifier form a high-gain negative feedback, clamping the drain terminal of the first PMOS transistor to the first clamping voltage, and the first PMOS transistor receives the first current signal from the second port, converts it into the first converted voltage signal, and outputs it at the gate terminal of the first PMOS transistor.

4. A memory, characterized in that: include: A plurality of memory column groups, and a multi-bit read decision circuit according to any one of claims 1 to 3, wherein the memory column groups are coupled to the multi-bit read decision circuit, the memory column groups have a read-write separation characteristic, and each memory cell in the memory column groups has an independent read electrical path and an independent write electrical path; the multi-bit read decision circuit is configured to perform a read decision operation on the memory cells.

5. The memory according to claim 4, wherein The data stored in the memory cell is read out by converting the data into a first current signal.

6. The memory according to claim 4, wherein: The memory cell has quasi-non-volatility, the memory cell retains the written data for more than 100 seconds, and the data written into the memory cell can be correctly read out after the retention time.

7. A method for reading multi-bit binary data, characterized in that: Using the multi-bit read decision circuit according to any one of claims 1 to 3 to perform data reading specifically includes: The bias module provides a first clamping voltage signal to the voltage clamping module; The voltage clamping module receives a first clamping voltage signal, reads a first current signal of the memory column group, and converts the first current signal into a first converted voltage signal for output; The multi-bit parallel comparison module receives the first conversion voltage signal, converts the first conversion voltage signal into multiple copied current signals according to a specific copy ratio, compares the multiple copied current signals with multiple reference current signals, and outputs a comparison result.

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