Semiconductor device

Abstract

The application provides a semiconductor device, comprising: a substrate and a plurality of semiconductor structures, the plurality of semiconductor structures being arranged on the substrate, each semiconductor structure comprising a source structure, a channel layer structure, a gate structure and a drain structure, wherein the source structure is arranged on the substrate, the channel layer structure is arranged on the source structure, the gate structure is arranged on the sidewall of the channel layer structure, and the drain structure is arranged on the channel layer structure and the gate structure; and the plurality of semiconductor structures are arranged at intervals, and at least one gap is arranged between at least two adjacent semiconductor structures. The application can increase the isolation performance between the two adjacent semiconductor structures, thereby improving the reliability of the semiconductor device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more particularly to a semiconductor device. Background Technology

[0002] Semiconductor transistors (such as metal-oxide-semiconductor transistors (MOS transistors)) have been used in various applications, such as power supplies, power converters, and switches. Traditional MOS transistors employ a planar structure. However, with the continuous development of semiconductor integrated circuit technology, MOS transistors have adopted a stacked structure to achieve miniaturization. In the design of a stacked structure, the isolation performance between two adjacent semiconductor structures affects the reliability of the semiconductor device. Poor isolation between adjacent semiconductor structures will reduce the reliability of the semiconductor device. Summary of the Invention

[0003] The purpose of this invention is to provide a semiconductor device that can increase the isolation performance between two adjacent semiconductor structures, thereby improving the reliability of the semiconductor device.

[0004] To achieve the above objectives, the present invention provides a semiconductor device comprising:

[0005] Substrate;

[0006] Multiple semiconductor structures are located on the substrate, each of the semiconductor structures comprising:

[0007] The source structure is located on the substrate;

[0008] A channel layer structure is located on the source structure;

[0009] A gate structure is located on the sidewall of the channel layer structure;

[0010] A drain structure is disposed on the channel layer structure and the gate structure;

[0011] The semiconductor structures are arranged at intervals, and there is at least one gap between at least two adjacent semiconductor structures.

[0012] Optionally, at least one of the gaps is located between the two gate structures of two adjacent semiconductor structures.

[0013] Optionally, the sidewall of the gate structure has a first recess, and the gap is located between two adjacent first recesses of the gate structures.

[0014] Optionally, the gate structure includes a gate barrier layer and a gate metal layer stacked sequentially from bottom to top, and the first recess is located on the sidewall at the junction of the gate barrier layer and the gate metal layer.

[0015] Optionally, at least one of the gaps is located between the two drain structures of two adjacent semiconductor structures.

[0016] Optionally, the highest vertex of at least one of the gaps is lower than the lowest surface of the two adjacent drain structures.

[0017] Optionally, the sidewall of the drain structure has a second recess, and the gap is located between two adjacent second recesses of the drain structures.

[0018] Optionally, the drain structure includes a drain barrier layer and a drain metal layer stacked sequentially from bottom to top, and the second recess is located on the sidewall of the drain metal layer.

[0019] Optionally, the drain structure includes a drain barrier layer and a drain metal layer stacked sequentially from bottom to top, with at least two gaps located between the drain structures, wherein the bottom point of one gap is higher than the bottom surface of the drain metal layer, and the top point of the other gap is lower than the bottom surface of the drain metal layer.

[0020] Optionally, at least one of the gaps is located between the two source structures of two adjacent semiconductor structures.

[0021] The present invention also provides a semiconductor device, comprising:

[0022] Substrate;

[0023] Multiple source structures are located on the substrate, the source structures extending along a first direction and arranged in a second direction perpendicular to the first direction;

[0024] Multiple gate structures are located on the source structure, the gate structures extending along the second direction and arranged in the first direction;

[0025] Multiple channel layer structures are located on the source structure and within the gate structure;

[0026] Multiple drain structures are located on the channel layer structure;

[0027] Wherein, at least one gap is located between at least two adjacent source structures and / or gate structures and / or drain structures.

[0028] The semiconductor device provided by this invention includes: a substrate and multiple semiconductor structures. The multiple semiconductor structures are located on the substrate, and each semiconductor structure includes a source structure, a channel layer structure, a gate structure, and a drain structure. The source structure is located on the substrate, the channel layer structure is located on the source structure, the gate structure is located on the sidewall of the channel layer structure, and the drain structure is disposed on the channel layer structure and the gate structure. The multiple semiconductor structures are arranged at intervals, with at least one gap between at least two adjacent semiconductor structures. By providing at least one gap between at least two adjacent semiconductor structures, this invention increases the isolation performance between adjacent semiconductor structures, thereby improving the reliability of the semiconductor device. Attached Figure Description

[0029] Figure 1 This is a partial top view of a semiconductor device provided in an embodiment of the present invention.

[0030] Figure 2 This is a first cross-sectional schematic diagram of a semiconductor device provided in an embodiment of the present invention.

[0031] Figure 3 This is a second cross-sectional schematic diagram of a semiconductor device provided in an embodiment of the present invention.

[0032] Figure 4 This is an enlarged view of point S1 in a first cross-sectional view of a semiconductor device provided in an embodiment of the present invention.

[0033] Figure 5 This is an enlarged view of point S2 in a first cross-sectional view of a semiconductor device provided in an embodiment of the present invention.

[0034] The attached figures are labeled as follows:

[0035] 10-Substrate; 20-Dielectric layer; 22-Electrical connector; 30-Source structure; 31-First source barrier layer; 32-Source metal layer; 33-Second source barrier layer; 34-Source semiconductor layer; 41-First isolation material layer; 42-Second isolation material layer; 43-Third isolation material layer; 44-Fourth isolation material layer; 45-Fifth isolation material layer; 40a-Void; 50-Gate structure; 51-Gate barrier layer; 52-Gate metal layer; 54-Through hole; 50a-First recess; 60-Gate dielectric layer structure; 62-Sacrificial layer; 70-Channel layer structure; 80-Capping layer; 90-Drain structure; 91-Drain barrier layer; 92-Drain metal layer; 90a-Second recess; 100-Sidewall structure. Detailed Implementation

[0036] To make the objectives, advantages, and features of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clarify the explanation of the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and may sometimes use different scales.

[0037] Figure 1 This is a partial top view of the semiconductor device provided in this embodiment; Figure 2 This is a first cross-sectional schematic diagram of the semiconductor device provided in this embodiment. Figure 3 This is a second cross-sectional schematic diagram of the semiconductor device provided in this embodiment, wherein... Figure 2 for Figure 1 A schematic cross-sectional view along section line A1A2. Figure 3 for Figure 1 A schematic diagram of the cross-section along section line B1B2. Figure 1 Only some important structures are shown in the diagram, and for clarity, Figure 1 Not all of them have been filled in.

[0038] Please refer to Figure 2 and Figure 3 This embodiment provides a semiconductor device, including: a substrate 10 and a plurality of semiconductor structures (such as...). Figure 2 and Figure 3 As shown in the dashed box D (only one semiconductor structure is circled), the substrate 10 can be a silicon substrate, gallium arsenide substrate, germanium substrate, germanium-silicon substrate, or silicon-on-insulator substrate, and is not limited to these. In this embodiment, a dielectric layer 20 is also formed on the substrate 10. The dielectric layer 20 can be a stacked structure composed of different material layers, such as a stacked structure composed of an oxide layer and a nitride layer, or it can be a single material layer, such as an oxide layer or a nitride layer, and is not limited to these. A plurality of electrical connectors 22 are formed in the dielectric layer 20. Figure 2 Only one electrical connector 22 is shown in the diagram. The electrical connector 22 penetrates the dielectric layer 20 and is electrically connected to the substrate 10 and the semiconductor structure. Figure 2 The intermediate electrical connector 22 is connected to the source structure 30. Figure 3 The intermediate power connector 22 is connected to the gate structure 50. Figure 1 (The electrical connector is not shown in the figure). The electrical connector 22 is formed by forming a connection hole in the dielectric layer 20, forming a barrier layer to cover the inner wall of the connection hole, and forming a metal material to fill the connection hole to form the electrical connector 22.

[0039] Each semiconductor structure includes a source structure 30, a channel layer structure 70, a gate structure 50, and a drain structure 90. The source structure 30 is located on the substrate 10. Since a dielectric layer 20 is also formed on the substrate 10, the source structure 30 is located on the dielectric layer 20, and the source structure 30 extends along a first direction D1 and is arranged in a second direction D2 perpendicular to the first direction D1 (e.g., ...). Figure 1 (As shown). In this embodiment, the source structure 30 includes a first source barrier layer 31, a source metal layer 32, a second source barrier layer 33, and a source semiconductor layer 34 stacked sequentially from bottom to top. The materials of the first source barrier layer 31 and the second source barrier layer 33 may include TiN, the material of the source metal layer 32 may include W, and the material of the source semiconductor layer 34 may include polysilicon, but is not limited to the above materials.

[0040] The channel layer structure 70 is located on the source structure 30. The channel layer structure 70 is U-shaped in cross-sectional view, and its bottom surface is in contact with the source structure 30. In this embodiment, the material of the channel layer structure 70 may include polycrystalline silicon (with doped ions), or one or more combinations of metal silicides, ferroelectric materials, high-k dielectric materials, and IGZO, and is not limited to the above materials.

[0041] The gate structure 50 is located on the sidewall of the channel layer structure 70, and the gate structure 50 extends along the second direction D2 and is arranged in the first direction D1 (e.g., Figure 1As shown in the diagram, a gate dielectric layer structure 60 and a sacrificial layer 62 are formed between the gate structure 50 and the channel layer structure 70, and a first isolation material layer 41 is formed between the gate structure 50 and the source structure 30. Specifically, the gate structure 50 and the gate dielectric layer structure 60 are both located on the first isolation material layer 41. The channel layer structure 70 penetrates the first isolation material layer 41 and the gate structure 50 and contacts the source structure 30. The gate dielectric layer structure 60 is L-shaped in cross-sectional view. The sacrificial layer 62 is located on the gate dielectric layer structure 60 and is located between the gate dielectric layer structure 60 and the channel layer structure 70. The gate dielectric layer structure 60 is located between the sacrificial layer 62 and the gate structure 50, and the top surface of the gate structure 50 is lower than the top surface of the gate dielectric layer structure 60. The top surfaces of the gate dielectric layer structure 60, the sacrificial layer 62, and the channel layer structure 70 are flush. In this embodiment, the material of the first isolation material layer 41 may include one of low-k dielectric materials, oxides, nitrides, oxynitrides, and silicon oxynitride; the gate structure 50 includes a gate barrier layer 51 and a gate metal layer 52 stacked sequentially from bottom to top, wherein the material of the gate barrier layer 51 may include TiN, and the material of the gate metal layer 52 may include W; the gate dielectric layer structure 60 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride; the sacrificial layer 62 may include polysilicon (with doped ions), and may also include one or more combinations of metal silicides, ferroelectric materials, high-k dielectric materials, and IGZO, and is not limited to the above materials.

[0042] Furthermore, a second isolation material layer 42 and a capping layer 80 are formed within the channel layer structure 70. The second isolation material layer 42 fills a portion of the depth inside the channel layer structure 70, and the capping layer 80 covers the top surface of the second isolation material layer 42. The bottom surface of the capping layer 80 is higher than the top surface of the gate structure 50, and the top surface of the capping layer 80 is flush with the top surface of the channel layer structure 70. In this embodiment, the material of the second isolation material layer 42 may include one of low-k dielectric materials, oxides, nitrides, oxynitrides, and silicon oxynitride; the material of the capping layer 80 may include at least one of insulating materials, semiconductor materials, metal materials, and metal silicide materials, and is not limited to the above materials.

[0043] Furthermore, it also includes a third isolation material layer 43, which fills the space between two adjacent gate structures 50 and covers the top surface of the gate structure 50, and is located on the source structure 30. In this embodiment, the material of the third isolation material layer 43 may include one of low-k dielectric materials, oxides, nitrides, oxynitrides, and silicon oxynitride, and is not limited to the above materials.

[0044] A drain structure 90 is disposed on the channel layer structure 70 and the gate structure 50, and a portion of the third isolation material layer 43 is located between the gate structure 50 and the drain structure 90. The bottom surface of the drain structure 90 is in contact with the top surface of the channel layer structure 70. In this embodiment, the drain structure 90 includes a drain barrier layer 91 and a drain metal layer 92 stacked sequentially from bottom to top. The material of the drain barrier layer 91 may include TiN, and the material of the drain metal layer 92 may include W, but is not limited to the above materials.

[0045] Furthermore, it also includes a sidewall structure 100 and a fourth insulating material layer 44. The sidewall structure 100 covers the sidewall of the drain structure 90, and the bottom surface of the drain structure 90 is lower than the bottom surface of the drain structure 90. The fourth insulating material layer 44 fills the space between two adjacent drain structures 90, and the fourth insulating material layer 44 is in contact with the sidewall structure 100. The bottom surface of the fourth insulating material layer 44 is lower than the bottom surface of the drain structure 90, and the bottom surfaces of the sidewall structure 100 and the fourth insulating material layer 44 are flush. In this embodiment, the material of the fourth insulating material layer 44 may include one of low-k dielectric materials, oxides, nitrides, oxynitrides, and silicon oxynitride, and is not limited to the above materials.

[0046] Furthermore, it also includes a fifth isolation material layer 45, which is located on the dielectric layer 20 and fills the space between two adjacent source structures 30. The electrical connector 22 extends through the fifth isolation material layer 45 and the first isolation material layer 41 to connect with the gate structure 50 (e.g., Figure 5 (As shown). In this embodiment, the material of the fifth insulating material layer 45 may include one of the following: low-k dielectric material, oxide, nitride, oxynitride, and silicon oxynitride, and is not limited to the above materials.

[0047] In this embodiment, multiple semiconductor structures are arranged at intervals, and there is at least one gap 40a between at least two adjacent semiconductor structures (e.g., Figure 2 The elliptical gap 40a is shown in the diagram (only a simplified illustration of the possible locations of the gap 40a is provided). By providing at least one gap 40a between two adjacent semiconductor structures, the gap 40a can increase the isolation performance between the two adjacent semiconductor structures, thereby improving the reliability of the semiconductor device.

[0048] In this embodiment, at least one gap 40a is located between two gate structures 50 of two adjacent semiconductor structures; and / or, at least one gap 40a is located between two drain structures 90 of two adjacent semiconductor structures; and / or, at least one gap 40a is located between two source structures 30 of two adjacent semiconductor structures.

[0049] Figure 4 This is an enlarged view of point S1 in the first cross-sectional view of the semiconductor device provided in this embodiment. Please refer to... Figure 4 The sidewall of the gate structure 50 has a first recess 50a, which is located at the junction of the gate barrier layer 51 and the gate metal layer 52. When at least one gap 40a is located between two gate structures 50 of two adjacent semiconductor structures, the gap 40a is located between the first recesses 50a of the two adjacent gate structures 50. Figure 4 Only one gap 40a is shown in the diagram. In this embodiment, the gap 40a between the two gate structures 50 of two adjacent semiconductor structures is located in the third isolation material layer 43.

[0050] Figure 5 This is an enlarged view of point S2 in the first cross-sectional view of the semiconductor device provided in this embodiment. Please refer to... Figure 5 The drain structure 90 has a second recess 90a on its sidewall. A gap 40a is located between the second recesses 90a of two adjacent drain structures 90. Specifically, the second recess 90a is located on the sidewall of the drain metal layer 92 and close to the drain barrier layer 91. The sidewall structure 100 covers the second recess 90a and is recessed into the drain structure 90. When at least one gap 40a is located between two drain structures 90 of two adjacent semiconductor structures, the highest point of the at least one gap 40a can be lower than the lowest surface of the two adjacent drain structures 90. Figure 5 The diagram illustrates two gaps 40a, referring here to the lowest gap 40a; alternatively, gap 40a could be located between the second recesses 90a of two adjacent drain structures 90. Figure 5 The uppermost gap 40a); or, at least two gaps 40a may be located between the drain structures 90, wherein the lowest point of one gap 40a is higher than the lowest surface of the drain metal layer 92, and the highest point of the other gap 40a is lower than the lowest surface of the drain metal layer 92. In this embodiment, the gap 40a between the two drain structures 90 of two adjacent semiconductor structures is located in the fourth isolation material layer 44.

[0051] In this embodiment, the formation of the first recess 50a is due to the side etching effect when etching the gate barrier layer 51 and the gate metal layer 52, and the formation of the second recess 90a is due to the side etching effect when etching the drain barrier layer 91 and the drain metal layer 92. The reason why gaps 40a are easily generated at the first recess 50a and the second recess 90a is that the width of the first recess 50a of two adjacent gate structures 50 along the D1 direction is greater than the width of other parts between the two adjacent gate structures 50, and the width of the second recess 90a of two adjacent drain structures 90 along the D1 direction is greater than the width of other parts between the two adjacent drain structures 90. When the isolation material is deposited between two adjacent gate structures 50 and two adjacent drain structures 90, at the same deposition rate, due to the presence of the first recess 50a and the second recess 90a, other parts between two adjacent gate structures 50 and two adjacent drain structures 90 are filled, while the gaps 40a are left because the gaps between the first recess 50a of two adjacent gate structures 50 and the gaps between the second recess 90a of two adjacent drain structures 90 are not filled.

[0052] Please refer to Figure 3 The gap 40a between the two source structures 30 of two adjacent semiconductor structures is located in the fifth isolation material layer 45.

[0053] In this embodiment, by providing at least one gap between two gate structures and / or two drain structures and / or two source structures of at least two adjacent semiconductor structures, the gap can increase the isolation performance between two adjacent semiconductor structures, thereby improving the reliability of the semiconductor device.

[0054] Please refer to Figure 1 The present invention also provides a semiconductor device, comprising: a substrate, a plurality of source structures 30, a plurality of gate structures 50, a plurality of channel layer structures 70, and a plurality of drain structures 90, wherein the plurality of source structures 30 are located on the substrate ( Figure 1 On a surface (not shown), multiple source structures 30 extend along a first direction D1 and are arranged in a second direction D2 perpendicular to the first direction D1, with an insulating material layer between adjacent source structures 30. Figure 1 (Not shown in the image). Multiple gate structures 50 are located on the source structure 30, extending along the second direction D2 and arranged along the first direction D1, with an isolation material layer between adjacent gate structures 50. Figure 1 (not shown in the image), and an isolation material layer is provided between the gate structure 50 and the source structure 30. Figure 1(Not shown in the image). Multiple channel layer structures 70 are located on the source structure 30 and within the gate structure 50. Specifically, the channel layer structures 70 penetrate the gate structure 50 and the isolation material layer between the gate structure 50 and the source structure 30, and contact the source structure 30. A gate dielectric layer structure 60 is located between the channel layer structures 70 and the gate structure 50. Multiple drain structures 90 ( Figure 1 The rectangular dashed frame (as shown) is located on the channel layer structure 70, and there is an isolation material layer between two adjacent drain structures 90. Figure 1 (Not shown in the image). At least one gap 40a ( Figure 1 The elliptical pore 40a, Figure 1 The diagram only briefly illustrates the possible locations of the gap 40a. It is located between at least two adjacent source structures 30 and / or gate structures 50 and / or drain structures 90. Specifically, at least one gap 40a is located in the isolation material layer between at least two adjacent source structures 30, and / or, at least one gap 40a is located in the isolation material layer between at least two adjacent gate structures 50, and / or, at least one gap 40a is located in the isolation material layer between at least two adjacent drain structures 90.

[0055] In summary, the semiconductor device provided by this invention includes: a substrate and multiple semiconductor structures. The multiple semiconductor structures are located on the substrate, and each semiconductor structure includes a source structure, a channel layer structure, a gate structure, and a drain structure. The source structure is located on the substrate, the channel layer structure is located on the source structure, the gate structure is located on the sidewall of the channel layer structure, and the drain structure is disposed on the channel layer structure and the gate structure. The multiple semiconductor structures are arranged at intervals, with at least one gap between at least two adjacent semiconductor structures. By providing at least one gap between at least two adjacent semiconductor structures, this invention increases the isolation performance between adjacent semiconductor structures, thereby improving the reliability of the semiconductor device.

[0056] The above are merely preferred embodiments of the present invention and do not constitute any limitation on the present invention. Any equivalent substitutions or modifications made by those skilled in the art to the technical solutions and content disclosed in the present invention without departing from the scope of the present invention shall be deemed to have remained within the protection scope of the present invention.

Claims

1. A semiconductor device, characterized in that, include: Substrate; Multiple semiconductor structures are located on the substrate, each of the semiconductor structures comprising: The source structure is located on the substrate; A channel layer structure is located on the source structure; A gate structure is located on the sidewall of the channel layer structure; A drain structure is disposed on the channel layer structure and the gate structure; The semiconductor structures are arranged at intervals, with at least one gap between at least two adjacent semiconductor structures. At least one gap is located between two gate structures of two adjacent semiconductor structures, and the sidewall of the gate structure has a first recess, with the gap located between the first recesses of two adjacent gate structures.

2. The semiconductor device as claimed in claim 1, characterized in that, The gate structure includes a gate barrier layer and a gate metal layer stacked sequentially from bottom to top, and the first recess is located on the sidewall at the junction of the gate barrier layer and the gate metal layer.

3. The semiconductor device as described in claim 1, characterized in that, At least one of the gaps is located between the two drain structures of two adjacent semiconductor structures.

4. The semiconductor device as described in claim 3, characterized in that, The highest vertex of at least one of the gaps is lower than the lowest surface of the two adjacent drain structures.

5. The semiconductor device as described in claim 3, characterized in that, The sidewall of the drain structure has a second recess, and the gap is located between two adjacent second recesses of the drain structure.

6. The semiconductor device as claimed in claim 5, characterized in that, The drain structure includes a drain barrier layer and a drain metal layer stacked sequentially from bottom to top, and the second recess is located on the sidewall of the drain metal layer.

7. The semiconductor device as claimed in claim 3, characterized in that, The drain structure includes a drain barrier layer and a drain metal layer stacked sequentially from bottom to top, with at least two gaps located between the drain structures, wherein the bottom point of one gap is higher than the bottom surface of the drain metal layer, and the top point of the other gap is lower than the bottom surface of the drain metal layer.

8. The semiconductor device as claimed in claim 1, characterized in that, At least one of the gaps is located between the two source structures of two adjacent semiconductor structures.

9. A semiconductor device, characterized in that, include: Substrate; Multiple semiconductor structures are located on the substrate, each of the semiconductor structures comprising: The source structure is located on the substrate; A channel layer structure is located on the source structure; A gate structure is located on the sidewall of the channel layer structure; A drain structure is disposed on the channel layer structure and the gate structure; The semiconductor structures are arranged at intervals, with at least one gap between at least two adjacent semiconductor structures. At least one gap is located between the two drain structures of the two adjacent semiconductor structures, and the highest vertex of the gap is lower than the lowest surface of the two adjacent drain structures.

10. The semiconductor device as claimed in claim 9, characterized in that, The drain structure includes a drain barrier layer and a drain metal layer stacked sequentially from bottom to top, with at least two gaps located between the drain structures, wherein the bottom point of one gap is higher than the bottom surface of the drain metal layer, and the top point of the other gap is lower than the bottom surface of the drain metal layer.

11. A semiconductor device, characterized in that, include: Substrate; Multiple semiconductor structures are located on the substrate, each of the semiconductor structures comprising: The source structure is located on the substrate; A channel layer structure is located on the source structure; A gate structure is located on the sidewall of the channel layer structure; A drain structure is disposed on the channel layer structure and the gate structure; The plurality of semiconductor structures are arranged at intervals, with at least one gap between at least two adjacent semiconductor structures, and at least one gap is located between two drain structures of two adjacent semiconductor structures, and the sidewall of the drain structure has a second recess, with the gap located between the second recesses of two adjacent drain structures.

12. The semiconductor device as claimed in claim 11, characterized in that, The drain structure includes a drain barrier layer and a drain metal layer stacked sequentially from bottom to top, and the second recess is located on the sidewall of the drain metal layer.

13. The semiconductor device as claimed in claim 11, characterized in that, The drain structure includes a drain barrier layer and a drain metal layer stacked sequentially from bottom to top, with at least two gaps located between the drain structures, wherein the bottom point of one gap is higher than the bottom surface of the drain metal layer, and the top point of the other gap is lower than the bottom surface of the drain metal layer.

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