A time compensation method and system for interference testing equipment

Abstract

The application discloses a time compensation method and system of an interference test device, and the method comprises the following steps: acquiring a first delay time and a second delay time; decomposing the first delay time and the second delay time to obtain a nanosecond-level delay time corresponding to the first delay time and a picosecond-level delay time corresponding to the second delay time; performing advance compensation on the nanosecond-level delay time through a configurable advance compensation and output module to obtain a nanosecond-level advance compensation time; performing lag compensation on the picosecond-level delay time through a delay compensation module to obtain a picosecond-level delay compensation time, and calculating the sum of the nanosecond-level advance compensation time and the picosecond-level delay compensation time to obtain a picosecond-level advance compensation time; and based on the picosecond-level advance compensation time, applying an interference signal on a CAN bus. Thus, through the cascading mode of a plurality of time sequence controllers in the delay compensation module, the picosecond-level delay compensation time is realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of vehicle communication testing, in particular to a time compensation method and system of interference testing equipment. BACKGROUND

[0002] The vehicle CAN(FD) bus technology is a communication technology applied to the monitoring and control of various devices in the vehicle communication field. The CAN(FD) bus technology contains a signal error processing mechanism, which can be used to ensure the correctness of the identified logic level signal. In order to ensure that the CAN(FD) bus technology automobile electronic controller can still communicate stably and accurately match the sampling points under the bus interference scene, the prior art uses CAN(FD) bus interference testing equipment to generate signal interference, thereby implementing fault injection and sampling point testing.

[0003] However, the main chip of the interference testing equipment is generally a microcontroller (MCU) or a programmable logic gate array (FPGA), and its working clock frequency is at most hundreds of megahertz, and the clock period is at the nanosecond (ns) level, so that the interference testing equipment cannot achieve high-precision time compensation with a resolution lower than the nanosecond level, and thus cannot guarantee the accuracy of the interference signal and the test error of the sampling points. SUMMARY

[0004] Based on the deficiencies of the prior art, the present application provides a time compensation method and system of interference testing equipment to solve the problem that the prior art cannot achieve high-precision time compensation with a resolution lower than the nanosecond level.

[0005] In order to achieve the above-mentioned purpose, the present application provides the following technical solutions:

[0006] The first aspect of the present application provides a time compensation method of interference testing equipment, comprising:

[0007] obtaining a first delay time and a second delay time;

[0008] decomposing the first delay time and the second delay time to obtain a nanosecond-level delay time corresponding to the first delay time and a picosecond-level delay time corresponding to the second delay time;

[0009] performing advance compensation on the nanosecond-level delay time by a configurable advance compensation and output module to obtain a nanosecond-level advance compensation time; wherein the configurable advance compensation and output module is composed of a preset logic code;

[0010] The picosecond delay time is compensated by a delay compensation module to obtain a picosecond delay compensation time, and the sum of the nanosecond advance compensation time and the picosecond delay compensation time is calculated to obtain a picosecond advance compensation time; wherein the delay compensation module is composed of a plurality of time sequence controllers connected in cascade, and the picosecond delay time is adjusted by the plurality of time sequence controllers.

[0011] Based on the picosecond advance compensation time, an interference signal is applied to the CAN bus.

[0012] Optionally, in the time compensation method of the interference test equipment, the method further comprises:

[0013] Obtaining bus parameters on the CAN bus;

[0014] Based on the bus parameters, obtaining a current acquisition signal on the CAN bus at the current time;

[0015] The current acquisition signal is analyzed to obtain an interference position of the current acquisition signal on the CAN RX signal line;

[0016] According to the interference position, a target interference signal is applied to the CAN bus.

[0017] Optionally, in the time compensation method of the interference test equipment, the method further comprises:

[0018] Extracting the baud rate and the sampling point of the CAN bus from the bus parameters;

[0019] Looking up the CAN(FD) communication basic parameters corresponding to the baud rate and the sampling point from a preset table;

[0020] According to the CAN(FD) communication basic parameters, the current acquisition signal at the current time is obtained from the CAN bus.

[0021] Optionally, in the time compensation method of the interference test equipment, after the interference signal is applied to the CAN bus based on the picosecond advance compensation time, the method further comprises:

[0022] When the interference signal is high, it is determined that the delay compensation time of the CAN bus is the opening time of the transistor switch;

[0023] When the interference signal is low, the delay compensation time of the CAN bus is determined as a total delay time; wherein the total delay time refers to the sum of the delay time from the CAN PHY bus to the CAN RX signal line and the delay time from the CAN TX signal line to the CAN PHY bus.

[0024] Optionally, in the time compensation method of the interference test device, the method further includes:

[0025] Obtaining the picosecond-level delay compensation time;

[0026] According to a preset threshold, the picosecond-level delay compensation time is equally divided to obtain a plurality of divided delay times, and the plurality of divided delay times are sent to the plurality of timing controllers.

[0027] Optionally, in the time compensation method of the interference test device, the method further includes:

[0028] Obtaining the temperature voltage and the tap number corresponding to the picosecond-level delay compensation time;

[0029] Calibrating the temperature voltage by using the IDelayCtrl unit in the delay compensation module;

[0030] Based on the calibrated temperature voltage, the tap number corresponding to the picosecond-level delay compensation time is adjusted so that the delay times of all timing controller units in the delay compensation module are the same.

[0031] Optionally, in the time compensation method of the interference test device, the leading compensation of the nanosecond-level delay time by the configurable leading compensation and output module to obtain the nanosecond-level leading compensation time includes:

[0032] Obtaining the frequency of the system clock and the position on the CAN bus at the current time;

[0033] The nanosecond-level leading compensation time is obtained by the configurable leading compensation and output module according to the frequency and the position.

[0034] Optionally, in the time compensation method of the interference test device, the lag compensation of the picosecond-level delay time by the delay compensation module to obtain the picosecond-level delay compensation time includes:

[0035] Obtaining the system clock, the nanosecond-level leading compensation time, and the user-configurable delay parameter;

[0036] The picosecond-level delay value is calculated by the delay tap number distribution module in the delay compensation module using the user-configurable delay parameter.

[0037] The picosecond-level delay time is adjusted by each timing controller in the delay compensation module according to the system clock, the nanosecond-level advance compensation time and the picosecond-level delay value, to obtain a picosecond-level delay compensation time.

[0038] The second aspect of the present application provides a time compensation system of an interference test device, the time compensation system comprising: a user configuration parameter analysis module, a configurable advance compensation and output module and a delay compensation module;

[0039] The user configuration parameter analysis module is configured to obtain a first delay time and a second delay time, and to decompose the first delay time and the second delay time to obtain a nanosecond-level delay time corresponding to the first delay time and a picosecond-level delay time corresponding to the second delay time.

[0040] The configurable advance compensation and output module is configured to advance compensate the nanosecond-level delay time to obtain a nanosecond-level advance compensation time; wherein the configurable advance compensation and output module is composed of a preset logic code.

[0041] The delay compensation module is configured to lag compensate the picosecond-level delay time to obtain a picosecond-level delay compensation time, to calculate a sum of the nanosecond-level advance compensation time and the picosecond-level delay compensation time to obtain a picosecond-level advance compensation time, and to impose the interference signal on the CAN bus based on the picosecond-level advance compensation time; wherein the delay compensation module is composed of a plurality of timing controllers connected in cascade, and the picosecond-level delay time is adjusted by the plurality of timing controllers.

[0042] Optionally, in the time compensation system of the interference test device, the user configuration parameter analysis module is further configured to:

[0043] The user configuration parameter analysis module is configured to obtain a bus parameter on the CAN bus, and to obtain a current acquisition signal on the CAN bus at a current time based on the bus parameter.

[0044] The analysis module is configured to analyze the current acquisition signal to obtain an interference position of the current acquisition signal on a CAN RX signal line.

[0045] The delay compensation module is configured to impose a target interference signal on the CAN bus according to the interference position.

[0046] Optionally, in the time compensation system of the interference test device, the user configuration parameter analysis module performs the operation of obtaining the current acquisition signal on the CAN bus at the current time based on the bus parameter, specifically by:

[0047] Extract the baud rate and sampling points of the CAN bus from the bus parameters;

[0048] Find the CAN(FD) communication basic parameters corresponding to the baud rate and the sampling point from the preset table;

[0049] Based on the CAN(FD) communication basic parameters, the current acquisition signal at the current moment is obtained from the CAN bus.

[0050] Optionally, in the time compensation system of the aforementioned interference testing equipment, it is also used for:

[0051] The delay compensation module is used to determine the delay compensation time of the CAN bus as the turn-on time of the transistor switch when the interference signal is high.

[0052] The delay compensation module is used to determine the delay compensation time of the CAN bus as the total delay time when the interference signal is low; wherein, the total delay time refers to the sum of the delay time from the CAN PHY bus to the CAN RX signal line and the delay time from the CAN TX signal line to the CAN PHY bus.

[0053] Optionally, in the time compensation system of the aforementioned interference testing equipment, it is also used for:

[0054] The delay compensation module is used to acquire the picosecond-level delay compensation time, and to divide the picosecond-level delay compensation time into multiple segments according to a preset threshold to obtain multiple segmented delay times, and to send the multiple segmented delay times to multiple timing controllers.

[0055] Optionally, in the time compensation system of the aforementioned interference testing equipment, it is also used for:

[0056] The delay compensation module is used to acquire the temperature voltage and the number of taps corresponding to the picosecond-level delay compensation time, and to calibrate the temperature voltage using the IDELAYCTRL unit in the delay compensation module, and to adjust the number of taps corresponding to the picosecond-level delay compensation time based on the calibrated temperature voltage, so that the delay time of all timing controller units in the delay compensation module is the same.

[0057] Optionally, in the time compensation system of the aforementioned interference testing equipment, the step of performing advance compensation on the nanosecond-level delay time through the configurable advance compensation and output module to obtain a nanosecond-level advance compensation time is specifically used for:

[0058] Obtain the system clock frequency and the current position on the CAN bus;

[0059] The configurable lead compensation and output module performs nanosecond-level timing on the nanosecond-level delay time based on the frequency and the position to obtain the nanosecond-level lead compensation time.

[0060] Optionally, in the time compensation system of the aforementioned interference testing equipment, the step of performing hysteresis compensation on the picosecond-level delay time through the delay compensation module to obtain the picosecond-level delay compensation time is specifically used for:

[0061] Acquire the system clock, the nanosecond-level lead compensation time, and the user-configurable delay parameters;

[0062] The delay tap allocation module in the delay compensation module uses the user-configurable delay parameters to calculate picosecond-level delay values.

[0063] Each timing controller in the delay compensation module adjusts the picosecond-level delay time at the picosecond level based on the system clock, the nanosecond-level lead compensation time, and the picosecond-level delay value to obtain the picosecond-level delay compensation time.

[0064] This application provides a time compensation method for interference testing equipment. The method involves acquiring a first delay time and a second delay time, then decomposing these delay times to obtain a nanosecond-level delay time corresponding to the first delay time and a picosecond-level delay time corresponding to the second delay time. Next, a configurable lead compensation and output module performs lead compensation on the nanosecond-level delay time to obtain a nanosecond-level lead compensation time. Then, a delay compensation module performs lag compensation on the picosecond-level delay time to obtain a picosecond-level delay compensation time. Finally, the sum of the nanosecond-level lead compensation time and the picosecond-level delay compensation time is calculated to obtain the picosecond-level lead compensation time. The delay compensation module consists of multiple cascaded timing controllers. Finally, based on the picosecond-level lead compensation time, an interference signal is applied to the CAN bus. Thus, by cascading multiple timing controllers in the delay compensation module, picosecond-level delay compensation is achieved, enabling the interference signal applied to the CAN bus to achieve picosecond-level resolution accuracy. Attached Figure Description

[0065] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0066] Figure 1 This is a schematic diagram of the structure of a time compensation system provided in an embodiment of this application;

[0067] Figure 2 A time-compensated waveform diagram of a CAN(FD) interference signal provided in an embodiment of this application;

[0068] Figure 3 A flowchart illustrating a time compensation method for an interference testing device provided in an embodiment of this application;

[0069] Figure 4 A flowchart illustrating a method for obtaining nanosecond-level lead compensation time, provided for another embodiment of this application;

[0070] Figure 5 This is a schematic diagram of the structure of a delay compensation module provided in an embodiment of this application;

[0071] Figure 6 A flowchart illustrating a method for obtaining picosecond-level delay compensation time, provided for another embodiment of this application;

[0072] Figure 7 A flowchart illustrating a method for calibrating delay compensation time according to another embodiment of this application;

[0073] Figure 8 A schematic flowchart illustrating a temperature and voltage processing method according to another embodiment of this application;

[0074] Figure 9 A flowchart illustrating a method for applying an interference signal, provided in another embodiment of this application;

[0075] Figure 10 A flowchart illustrating a method for acquiring a currently collected signal, provided as another embodiment of this application;

[0076] Figure 11 This is a schematic diagram of the structure of a time compensation system for an interference testing device provided in another embodiment of this application. Detailed Implementation

[0077] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0078] In this application, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0079] This application provides a time compensation method for interference testing equipment, applied to a time compensation system, to solve the problem that existing technologies cannot achieve high-precision time compensation with resolutions below the nanosecond level.

[0080] It should be noted that the time compensation system achieves high-precision time compensation with picosecond-level resolution by combining and cascading internal custom logic in a programmable gate array (FPGA) and multiple timing controller units. This ensures the accuracy of the applied interference signal and reduces the test error at the sampling point.

[0081] Optionally, such as Figure 1 As shown in the figure, this application provides a time compensation system, including: a host computer, a ZYNQ chip, and a CAN PHY chip.

[0082] The host computer is used to speed up data transmission. During the CAN bus signal transmission process, it transmits and compresses the control parameters required by multiple boards and the signals themselves, according to the communication protocol between itself and the ZYNQ chip.

[0083] The ZYNQ chip is based on FPGA and ARM processors, integrating the FPGA and ARM processor cores onto a single chip, providing powerful hardware acceleration and flexible software processing capabilities. The ZYNQ chip includes a PS (Power Supply) side and a PL (Power Logic) side. Specifically, the PL side refers to the FPGA controller inside the ZYNQ chip, and the PS side refers to the ARM controller inside the ZYNQ chip.

[0084] It should be noted that the PS end includes a user configuration parameter parsing module, while the PL end includes a parsing module, a CAN(FD) interference delay and lead compensation automatic allocation module, a CAN(FD) interference signal configurable lead compensation and output module, and a delay compensation module composed of multiple cascaded ODELAYE3 and IDELAYE3 modules. Both ODELAYE3 and IDELAYE3 are timing controllers used for picosecond-level delay adjustment.

[0085] It should also be noted that the user configuration parameter parsing module may include a USB data parsing module, a CAN(FD) configurable delay parameter module, and a CAN(FD) configurable control parameter module. Specifically, the USB data parsing module is used to reverse-parse USB CDC serial port data into control parameters required by multiple boards based on the communication protocol between the host computer and ZYNQ, which is the parsed data described in the following embodiments.

[0086] The CAN(FD) configurable delay parameter module is used to send the parsed data as a delay time to the CAN(FD) interference delay and lead compensation automatic allocation module in the PL terminal via the ZYNQ internal AXI bus.

[0087] The CAN(FD) configurable control parameter module is used to send the parsed data to the high-speed parsing module in the PL terminal via the ZYNQ internal AXI bus when the parsed data is used as a parameter.

[0088] The parsing module includes a high-speed CAN(FD) data parsing module and a real-time CAN(FD) status parsing module. The high-speed CAN(FD) data parsing module parses the parameters, obtains the corresponding values, and sends them to the real-time CAN(FD) status parsing module. The real-time CAN(FD) status parsing module parses the CAN(FD) protocol position of the signal based on the corresponding parameter values.

[0089] The CAN(FD) interference delay and lead compensation automatic allocation module is used to allocate the delay time to the CAN(FD) interference signal separately. It is a configurable lead compensation and output module and a delay compensation module.

[0090] The CAN(FD) interference signal configurable lead compensation and output module is used to process the delay time, providing a lead compensation interference signal with a time in the nanosecond range and a resolution not exceeding the FPGA internal system clock frequency (160MHz≥f≥16MHz).

[0091] The delay compensation module, composed of multiple cascaded ODELAYE3 and IDELAYE3, is used to compensate for nanosecond-level advance interference signals and, in combination with its own picosecond-level lag compensation signal, ultimately apply picosecond-level resolution interference signals to the CAN (FD).

[0092] The CAN PHY chip includes the CAN TX signal line, CAN RX signal line, and the CAN bus. During the transmission of the CAN(FD) message signal, there is a signal conversion delay as it travels through the CAN bus, passes through the PHY chip, and is converted to the CAN RX signal line. Subsequently, interference signals are converted from the CAN TX signal line through the PHY chip to the CAN bus. Therefore, when the CAN(FD) message signal is converted by the PHY chip and sent to the host computer, the host computer uses the USB protocol to send the CAN(FD) message signal to the ZYNQ chip to determine a picosecond-level delay compensation time. Based on this delay time, the interference signal is transmitted to the CAN TX signal line and then applied to the CAN bus via the PHY chip. For details, please refer to [link to relevant documentation]. Figure 2 The waveform diagram shown is a time-compensated waveform of the CAN(FD) interference signal.

[0093] This application provides a time compensation method for interference testing equipment, such as... Figure 3 As shown, the specific steps include:

[0094] S301, Obtain the first delay time and the second delay time.

[0095] It should be noted that there is a signal conversion delay during the process of the CAN(FD) message signal being converted from the CAN bus to the CAN RX signal line via the PHY chip, and the interference signal being converted from the CAN TX signal line to the CAN bus via the PHY chip. Therefore, in order to compensate for the signal conversion delay when an interference signal is subsequently applied to the CAN bus, it is necessary to know the delay time. Therefore, in this embodiment, a high-precision oscilloscope is used to analyze the currently acquired signal to determine the delay time (nanosecond error) of the currently acquired signal being converted from the CAN bus to the CAN RX signal line via the PHY chip, which is the first delay time, and the delay time (picosecond error) of the CAN TX signal line being converted from the CAN bus via the PHY chip, which is the second delay time.

[0096] S302. Decompose the first delay time and the second delay time to obtain the nanosecond-level delay time corresponding to the first delay time and the picosecond-level delay time corresponding to the second delay time.

[0097] It should be noted that after obtaining the first delay time and the second delay time using a high-precision oscilloscope, the two delay times are then transmitted to the USB data parsing module in the PS terminal of the ZYNQ chip via the host computer interface program through the USB protocol for decomposition.

[0098] Specifically, by decomposing the first delay time using the FPGA basic logic inside the system, the nanosecond-level delay time corresponding to the first delay time can be obtained. Then, by decomposing the second delay time using the FPGA primitive logic inside the system, the picosecond-level delay time corresponding to the second delay time can be obtained.

[0099] S303. A nanosecond-level delay time is compensated for by a configurable advance compensation and output module to obtain a nanosecond-level advance compensation time.

[0100] The configurable advance compensation and output module consists of preset logic code.

[0101] Specifically, the custom logic inside the FPGA in the configurable advance compensation and output module is used to perform advance compensation on the nanosecond-level delay time, thereby obtaining the nanosecond-level advance compensation time, which is the nanosecond-level advance compensation time obtained by the FPGA internal system clock by pacing the nanosecond-level delay time.

[0102] Optionally, in another embodiment of this application, one specific implementation of step S303 is as follows: Figure 4 As shown, it includes the following steps:

[0103] S401: Obtain the system clock frequency and the current position on the CAN bus.

[0104] It should be noted that, in order for the configurable lead compensation and output module to accurately output nanosecond-level lead compensation time, it is necessary to obtain the system clock frequency and the current position on the CAN bus beforehand. This allows the configurable lead compensation and output module to output nanosecond-level lead compensation time based on the frequency and position. Specifically, on the Windows platform, the QueryPerformanceFrequency function can be used to obtain the system clock frequency. On the Linux platform, you can use the clock_getres function to obtain the system clock frequency, or you can use a programming language to obtain it. Optionally, the embodiments of this application are not limited to the means of obtaining the system clock frequency; the specific method can be set according to requirements. Furthermore, an appropriate CAN bus communication library or driver can be used to encapsulate the current position on the CAN bus into a CAN message and send it out through the CAN bus, thereby obtaining the current position on the CAN bus.

[0105] S402. The configurable lead compensation and output module performs nanosecond-level timing on the nanosecond-level delay time according to the frequency and position to obtain the nanosecond-level lead compensation time.

[0106] Specifically, the configurable lead compensation and output module calls the FPGA's internal system clock to perform nanosecond-level timing on the nanosecond-level delay time based on the frequency and position, thereby obtaining the nanosecond-level lead compensation time.

[0107] S304. The picosecond-level delay time is compensated for by the delay compensation module to obtain the picosecond-level delay compensation time. The nanosecond-level advance compensation time and the picosecond-level delay compensation time are calculated together to obtain the picosecond-level advance compensation time.

[0108] The delay compensation module consists of multiple timing controllers cascaded together, and uses these multiple timing controllers to adjust the picosecond-level delay time.

[0109] It should be emphasized that the structural diagram of the delay compensation module is as follows: Figure 5 As shown, the specific Figure 5 The delay compensation module shown is constructed from multiple ODLAYE3, IDELAYE3, and IDELAYCTRL units. The CASC_OUT interface of IDELAYE3 and ODLAYE3 is connected to the CASC_IN interface of the next level, and the DATAOUT interface is connected to the CASC_RETURN interface of the previous level. This connection method forms a multi-level cascade, constructing a high-speed signal link within the FPGA and forming the final delay chain. In the multi-level cascaded delay chain, the first-level ODLAYE3 unit has the attribute MASTER, used to control the final delayed signal output. The IDELAYE3 and ODLAYE3 units in the middle of the delay chain have the attribute SLAVE_MIDDLE, and the IDELAYE3 or ODLAYE3 unit at the end of the delay chain has the attribute SLAVE_END. These units together construct the high-speed delay link within the FPGA, providing a larger adjustable delay range for the first-level ODLAYE3 unit. Thus, by using the delay compensation module to compensate for picosecond-level delay times, a picosecond-level resolution delay compensation time can be obtained.

[0110] It should be noted that when applying interference signals to the CAN bus later, in order to apply the interference signals at the appropriate time to achieve specific testing, security assessment, or attack detection purposes, it is necessary to calculate the appropriate time to apply the interference signals to the CAN bus in advance. Therefore, a delay compensation module combines nanosecond-level lead compensation time and picosecond-level delay compensation time to obtain picosecond-level lead compensation time, thus ultimately realizing a picosecond-level resolution time compensation scheme on the CAN(FD) interference testing equipment.

[0111] Optionally, in another embodiment of this application, one specific implementation of step S304 is as follows: Figure 6 As shown, it includes the following steps:

[0112] S601: Obtain the system clock, nanosecond-level lead compensation time, and user-configurable delay parameters.

[0113] Understandably, users can configure delay parameters to calculate picosecond-level delay values, and then use these picosecond-level delay values ​​to determine the required delay time.

[0114] Optionally, the system clock can be obtained using API functions provided by the operating system or third-party libraries, and a configuration interface can be provided to the user for setting delay parameters. These parameters may include the delay time to be compensated, the compensation strategy (e.g., static compensation or dynamic compensation), the source of the compensation value (e.g., user input or sensor measurement), and the unit of the compensation value (e.g., nanoseconds, microseconds, etc.).

[0115] S602. The delay tap allocation module in the delay compensation module calculates the picosecond-level delay value using user-configurable delay parameters.

[0116] Understandably, the delay tap allocation module within the delay compensation module can design a delay compensation algorithm based on user-configured delay parameters to ensure delay compensation at the picosecond level. Then, the delay value is calculated based on the delay compensation algorithm.

[0117] The specific delay compensation algorithm can be:

[0118] Input parameters: User-configurable delay parameters

[0119] User-defined delay time (unit: picoseconds)

[0120] Delay compensation strategies (static or dynamic)

[0121] The source of the delay value (e.g., user input, sensor measurements, etc.)

[0122] Static delay compensation:

[0123] If the delay compensation strategy is static, the user-defined delay time will be used directly as the delay compensation value.

[0124] Dynamic delay compensation:

[0125] If the delay compensation strategy is dynamic, the delay value is obtained in real time according to the source of the delay value and converted into a picosecond-level delay value.

[0126] The dynamic delay compensation value can be calculated using the delay value measured by the sensor or other real-time data.

[0127] Picosecond-level latency calculation:

[0128] The user-defined delay time is added to the static or dynamic delay compensation value to obtain the final picosecond-level delay value.

[0129] Output: Picosecond-level latency value.

[0130] It should be noted that this is just an example of a delay compensation algorithm.

[0131] S603. Each timing controller in the delay compensation module adjusts the picosecond-level delay time according to the system clock, nanosecond-level lead compensation time, and picosecond-level delay value to obtain the picosecond-level delay compensation time.

[0132] Understandably, each timing controller is used to receive the system clock signal, the picosecond-level delay value, and the nanosecond-level lead compensation time, and adjusts the delay in each timing controller according to the received system clock signal, picosecond-level delay value, and nanosecond-level lead compensation time to achieve picosecond-level delay compensation.

[0133] Specifically, picosecond-level delay compensation is achieved through the hardware in the delay compensation module and the wiring layout of each timing controller.

[0134] S305, based on picosecond-level lead compensation time, applies an interference signal on the CAN bus.

[0135] Specifically, since an interference signal needs to be applied to the CAN bus a certain amount of time in advance to offset the subsequent delay compensation time within the CAN bus, and to ensure the accuracy of the applied interference signal to a certain extent, an interference signal with a set delay compensation time is applied to the CAN bus based on the advance time, thereby achieving picosecond-level advance compensation of the interference signal.

[0136] For example, the system wants to apply an interference signal at the ACK SLOT position on the CAN bus. However, due to the nanosecond and picosecond delays (e.g., a delay of 65.15 nanoseconds) in the CAN PHY signal conversion or transistor operation, the interference signal needs to be applied in advance to ensure accuracy. This can be achieved by adding the nanosecond-level lead compensation time to the picosecond-level delay compensation time, resulting in 65.15 nanoseconds (picosecond-level lead compensation time). The system then needs to apply the interference signal 65.15 nanoseconds in advance to the CAN TX signal line. After conversion by the CAN PHY, the interference signal will be applied precisely at the start of the ACK SLOT position on the CAN bus.

[0137] It should be noted that the interference signal applied to the CAN bus is based on the required level of the CAN bus, so the interference signal can be either high or low.

[0138] Optionally, after an interference signal is applied to the CAN bus, the CAN bus itself generates a delay compensation time based on the level value corresponding to the interference signal. Therefore, after executing step S305, in another embodiment of this application, a method for determining the delay compensation time is provided, specifically including the following steps:

[0139] When the interference signal is high, the delay compensation time of the CAN bus is determined to be the turn-on time of the transistor switch.

[0140] It should be noted that when the applied interference signal is high level, the transistor inside the CAN bus will first turn on. At this time, the turn-on time of the transistor switch is the delay compensation time of the CAN bus. The picosecond-level lead compensation time is to offset the turn-on time of the transistor switch, thereby ensuring the accuracy of the applied interference signal. Therefore, the high-level interference signal will be applied to the high-speed transistor in the CAN bus.

[0141] When the interference signal is low, the delay compensation time of the CAN bus is determined as the total delay time.

[0142] The total delay time refers to the sum of the delay time from the CAN PHY bus to the CAN RX signal line and the delay time from the CAN TX signal line to the CAN PHY bus.

[0143] It should be noted that when the interference signal is low, the delay time from the CAN PHY bus to the CAN RX signal line and the delay time from the CAN TX signal line to the CAN PHY bus need to be considered to ensure that the interference signal can interfere with the CAN(FD) waveform being transmitted on the CAN bus within an appropriate time, causing it to generate an error frame. Therefore, when the interference signal is low, the delay compensation time of the CAN bus is the sum of the delay time from the CAN PHY bus to the CAN RX signal line and the delay time from the CAN TX signal line to the CAN PHY bus. At this time, the low-level interference signal will be applied to the CAN TX signal line, and then the CAN PHY chip will convert the interference signal applied to the CAN TX signal line into an interference signal applied to the CAN bus.

[0144] Optionally, to ensure the overall system's time compensation accuracy, it is necessary to calibrate the picosecond-level delay compensation time generated by the delay compensation module. Therefore, in another embodiment of this application, a method for calibrating the delay compensation time is provided, such as... Figure 7 As shown, the specific steps include:

[0145] S701, obtain picosecond-level delay compensation time.

[0146] S702. According to the preset threshold, the picosecond-level delay compensation time is divided into multiple segments to obtain multiple segmented delay times, and the multiple segmented delay times are sent to multiple timing controllers.

[0147] Specifically, in order to achieve more precise interference delay control in the system and make the system more flexible in delay compensation, and to adjust the delay time in smaller steps, thereby more accurately controlling the arrival time of the interference signal, this application embodiment adopts a time segmentation method. According to a preset threshold n, the picosecond-level delay compensation time is divided into n equal parts, each with a fixed delay of (1000 / (nf))ps, thereby ensuring the time compensation accuracy of the overall system.

[0148] For example, assuming a nanosecond-level delay of 65.15 nanoseconds, and the FPGA uses a clock frequency of 160MHz, then 65.15 nanoseconds corresponds to a time of 6.25 nanoseconds. First, a lead compensation time multiple of 6.25 nanoseconds can be achieved using custom logic within the FPGA's configurable lead compensation and output module. In this example, a lead compensation time multiple of 6.25 nanoseconds is 68.75 nanoseconds (since the delay compensation module can only generate delay compensation, not lead compensation, the lead compensation time provided by the configurable lead compensation and output module must exceed the actual required compensation time). Then, the delay compensation module needs to generate a delay of 68.75 - 65.15 nanoseconds = 3.6 nanoseconds. This requires adjusting the number of equal parts (n parts) of the delay time divided into n parts by the IDELAYE3 and ODELAYE3 multi-level cascaded units in the delay compensation module to find the value closest to 3.6 nanoseconds, thus ultimately achieving a picosecond-level delay compensation time.

[0149] Optionally, to ensure that the delay time produced by each timing controller in the delay compensation module is the same under different environments, it is necessary to process the temperature voltage. Therefore, in another embodiment of this application, a method for processing the temperature voltage is provided, such as... Figure 8 As shown, the specific steps include:

[0150] S801, obtain the number of taps corresponding to the temperature, voltage, and picosecond-level delay compensation time.

[0151] Understandably, in order to dynamically adjust each timing controller in the delay compensation module according to the temperature and voltage changes under the current environmental conditions in order to maintain the stability and performance of the system, it is necessary to obtain the temperature, voltage, and the number of taps corresponding to the picosecond-level delay compensation time in advance.

[0152] S802. Use the IDELAYCTRL unit in the delay compensation module to calibrate the temperature and voltage.

[0153] Specifically, since changes in temperature and voltage can affect the operating speed and performance of the chip, which in turn affects the accuracy of the delay unit, it is necessary to use the IDELAYCTRL unit in the delay compensation module to calibrate the temperature and voltage to ensure that the system can maintain stable delay accuracy.

[0154] S803. Based on the calibrated temperature and voltage, adjust the number of taps corresponding to the picosecond-level delay compensation time so that the delay time of all timing controller units in the delay compensation module is the same.

[0155] Specifically, based on the calibrated temperature and voltage, the number of taps required for the picosecond-level delay compensation time is determined. Then, based on the determined number of taps, the number of taps corresponding to the picosecond-level delay compensation time generated by each timing controller is adjusted to achieve the required picosecond-level delay compensation time, thereby ensuring that the picosecond-level delay compensation time generated by each timing controller is the same.

[0156] Optionally, besides applying interference signals to the CAN bus in advance based on picosecond-level lead compensation time, it is also possible to find precise interference locations on the CAN bus and apply interference signals. Therefore, in another embodiment of this application, a method for applying interference signals is provided, such as... Figure 9 As shown, the specific steps include:

[0157] S901, Obtain bus parameters on the CAN bus.

[0158] It should be noted that in order to apply interference signals at the location of the acquired signal during the subsequent measurement of CAN(FD) sampling points, thereby reducing the measurement error of CAN(FD) sampling points, it is necessary to obtain the bus parameters on the CAN bus from the host computer via the USB protocol. Therefore, the CAN(FD) bus parameters can provide higher bandwidth, flexibility, real-time performance and reliability, thus enabling the effective acquisition of the current acquisition signal on the CAN bus at the current moment.

[0159] S902. Based on bus parameters, obtain the current acquisition signal on the CAN bus at the current moment.

[0160] Specifically, first, connect the CAN interface device to the CAN bus that needs to be monitored. The CAN interface device can be a CAN(FD) interface card, a USB to CAN adapter, or a CAN interface module on an embedded system. Then, initialize the CAN interface device using the corresponding programming library or driver. Next, set the logic for acquiring the CAN bus in the program to read the acquired signals from the CAN bus. Finally, based on the bus parameters, acquire the current acquired signal from the CAN bus at the current moment.

[0161] Optionally, in another embodiment of this application, one specific implementation of step S902 is as follows: Figure 10 As shown, it includes the following steps:

[0162] S1001. Extract the baud rate and sampling points of the CAN bus from the bus parameters.

[0163] Understandably, the bus parameters contain data from the CAN bus, but not all data can be used to acquire data from the CAN bus. Therefore, in order to acquire data from the CAN bus flexibly and quickly in the future, it is necessary to extract parameters that are beneficial to the acquisition signal from the bus parameters in advance, namely the baud rate and sampling points of the CAN bus.

[0164] S1002. Find the CAN(FD) communication basic parameters corresponding to the baud rate and sampling point from the preset table.

[0165] It should be noted that the CAN protocol uses a table to record the required parameters, namely the basic parameters of CAN(FD) communication. Because there is a specific relationship between baud rate, sampling points, and interference parameters, the corresponding basic CAN(FD) communication parameters can be looked up in the table using the baud rate and sampling points. Subsequently, based on these basic CAN(FD) communication parameters, the current acquisition signal is collected from the CAN bus. The basic CAN(FD) communication parameters can include TSEG1, TSEG2, and SJW. According to the CAN protocol, TSEG1 represents the synchronization segment time, TSEG2 represents the follow-up segment time, and SJW represents the resynchronization jump width.

[0166] S1003. Based on the basic parameters of CAN (FD) communication, obtain the current acquisition signal from the CAN bus at the current moment.

[0167] Specifically, based on TSEG1, TSEG2, and SJW, the current acquisition signal at the current moment is obtained from the CAN bus.

[0168] S903. Analyze the currently acquired signal to obtain the interference position of the currently acquired signal on the CAN RX signal line.

[0169] Specifically, since the currently acquired signal contains a lot of data from the CAN(FD) bus, such as IP address, port, and the position of the signal on the bus, it is necessary to use the CAN(FD) real-time status parsing module to extract from the currently acquired signal which bit of the CAN(FD) message the current acquired signal is in at the current time, which clock slice under the current bit, and the soft synchronization compensation width. In this way, the interference position of the current acquired signal on the CAN RX signal line at the current moment can be obtained.

[0170] S904. Apply the target interference signal to the CAN bus according to the location of the interference.

[0171] Specifically, the interference position where the target interference signal is applied is first located on the CAN bus. Then, the target interference signal with picosecond resolution is sent to the CAN bus through the delay compensation module, so that the CAN bus applies the target interference signal at the interference position. Thus, the delay time compensation with picosecond resolution can be achieved through the cascading of delay compensation modules, so that the interference signal applied at the interference position on the CAN bus can also achieve the accuracy of picosecond resolution.

[0172] It should be noted that the target interference signal can be either high or low level. For a detailed explanation, please refer to the specific implementation method in the method for determining the delay compensation time provided above, which will not be repeated here.

[0173] This application provides a time compensation method for interference testing equipment. The method involves acquiring a first delay time and a second delay time, then decomposing these delay times to obtain a nanosecond-level delay time corresponding to the first delay time and a picosecond-level delay time corresponding to the second delay time. Next, a configurable lead compensation and output module performs lead compensation on the nanosecond-level delay time to obtain a nanosecond-level lead compensation time. Then, a delay compensation module performs lag compensation on the picosecond-level delay time to obtain a picosecond-level delay compensation time. Finally, the sum of the nanosecond-level lead compensation time and the picosecond-level delay compensation time is calculated to obtain the picosecond-level lead compensation time. The delay compensation module consists of multiple cascaded timing controllers. Finally, based on the picosecond-level lead compensation time, an interference signal is applied to the CAN bus. Thus, by cascading multiple timing controllers in the delay compensation module, picosecond-level delay compensation is achieved, enabling the interference signal applied to the CAN bus to achieve picosecond-level resolution accuracy.

[0174] Another embodiment of this application provides a time compensation system for interference testing equipment, such as... Figure 11 As shown, the time compensation system includes: a user configuration parameter parsing module 1101, a configurable advance compensation and output module 1102, and a delay compensation module 1103.

[0175] The user configuration parameter parsing module 1101 is used to obtain the first delay time and the second delay time, and to decompose the first delay time and the second delay time to obtain the nanosecond-level delay time corresponding to the first delay time and the picosecond-level delay time corresponding to the second delay time.

[0176] The configurable lead compensation and output module 1102 is used to perform lead compensation on nanosecond-level delay time to obtain nanosecond-level lead compensation time. The configurable lead compensation and output module is composed of preset logic code.

[0177] The delay compensation module 1103 is used to perform lag compensation on picosecond-level delay times to obtain a picosecond-level delay compensation time, and to calculate the sum of the nanosecond-level lead compensation time and the picosecond-level delay compensation time to obtain a picosecond-level lead compensation time. It is also used to apply an interference signal to the CAN bus based on the picosecond-level lead compensation time. The delay compensation module consists of multiple timing controllers cascaded together, and utilizes these multiple timing controllers to adjust the picosecond-level delay time.

[0178] It should be noted that the specific working process of the above modules in the embodiments of this application can be referred to steps S301 to S305 in the above method embodiments, and will not be repeated here.

[0179] Optionally, in another embodiment of the time compensation system for an interference testing device provided in this application, it is further used for:

[0180] The user configuration parameter parsing module is used to obtain bus parameters on the CAN bus, and to obtain the current acquisition signal on the CAN bus at the current moment based on the bus parameters.

[0181] The analysis module is used to analyze the currently acquired signal to determine the interference location of the currently acquired signal on the CAN RX signal line.

[0182] The delay compensation module is used to apply the target interference signal on the CAN bus according to the location of the interference.

[0183] Optionally, in another embodiment of this application, a time compensation system for an interference testing device includes a user configuration parameter parsing module that performs operations based on bus parameters to obtain the currently acquired signal on the CAN bus at the current moment, specifically for:

[0184] Extract the baud rate and sampling points of the CAN bus from the bus parameters.

[0185] Find the CAN(FD) communication basic parameters corresponding to the baud rate and sampling point from the preset table.

[0186] Based on the basic parameters of CAN(FD) communication, the current acquisition signal at the current moment is obtained from the CAN bus.

[0187] Optionally, in another embodiment of the time compensation system for an interference testing device provided in this application, it is further used for:

[0188] The delay compensation module is used to determine the delay compensation time of the CAN bus as the turn-on time of the transistor switch when the interference signal is high.

[0189] The delay compensation module is used to determine the total delay time of the CAN bus when the interference signal is low. The total delay time refers to the sum of the delay time from the CAN PHY bus to the CAN RX signal line and the delay time from the CAN TX signal line to the CAN PHY bus.

[0190] Optionally, in another embodiment of the time compensation system for an interference testing device provided in this application, it is further used for:

[0191] The delay compensation module is used to obtain the picosecond-level delay compensation time, and to divide the picosecond-level delay compensation time into multiple segments according to a preset threshold, thereby obtaining multiple segmented delay times, and then sending the multiple segmented delay times to multiple timing controllers.

[0192] Optionally, in another embodiment of the time compensation system for an interference testing device provided in this application, it is further used for:

[0193] The delay compensation module is used to obtain the temperature voltage and the number of taps corresponding to the picosecond-level delay compensation time, and to calibrate the temperature voltage using the IDELAYCTRL unit in the delay compensation module. Based on the calibrated temperature voltage, it adjusts the number of taps corresponding to the picosecond-level delay compensation time so that the delay time of all timing controller units in the delay compensation module is the same.

[0194] Optionally, in another embodiment of this application, a time compensation system for an interference testing device is provided, in which a configurable lead compensation and output module is used to perform lead compensation on nanosecond-level delay time to obtain nanosecond-level lead compensation time, specifically used for:

[0195] Obtain the system clock frequency and the current position on the CAN bus.

[0196] The configurable lead compensation and output module performs nanosecond-level timing based on frequency and position to obtain nanosecond-level lead compensation time.

[0197] Optionally, in another embodiment of this application, a time compensation system for an interference testing device is provided, in which a delay compensation module performs hysteresis compensation on picosecond-level delay time to obtain a picosecond-level delay compensation time, specifically used for:

[0198] Obtain the system clock, nanosecond-level lead compensation time, and user-configurable delay parameters.

[0199] The delay tap allocation module in the delay compensation module calculates picosecond-level delay values ​​using user-configurable delay parameters.

[0200] Each timing controller in the delay compensation module adjusts the picosecond-level delay time based on the system clock, nanosecond-level lead compensation time, and picosecond-level delay value to obtain the picosecond-level delay compensation time.

[0201] It should be noted that the specific working process of each module provided in the above embodiments of this application can be referred to the corresponding steps in the above method embodiments, and will not be repeated here.

[0202] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0203] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A time compensation method for interference testing equipment, characterized in that, include: Obtain the first delay time and the second delay time; The first delay time and the second delay time are decomposed to obtain the nanosecond-level delay time corresponding to the first delay time and the picosecond-level delay time corresponding to the second delay time; The nanosecond-level delay time is compensated in advance by a configurable advance compensation and output module to obtain a nanosecond-level advance compensation time; wherein, the configurable advance compensation and output module is composed of preset logic code; The picosecond-level delay time is compensated for by a delay compensation module to obtain a picosecond-level delay compensation time. The sum of the nanosecond-level advance compensation time and the picosecond-level delay compensation time is calculated to obtain a picosecond-level advance compensation time. The delay compensation module is composed of multiple timing controllers cascaded together, and the delay of the picosecond-level delay time is adjusted by the multiple timing controllers. An interference signal is applied to the CAN bus based on the picosecond-level lead compensation time.

2. The method according to claim 1, characterized in that, Also includes: Obtain bus parameters on the CAN bus; Based on the bus parameters, obtain the current acquisition signal on the CAN bus at the current moment; The currently acquired signal is analyzed to determine the interference location of the currently acquired signal on the CAN RX signal line; Based on the location of the interference, a target interference signal is applied to the CAN bus.

3. The method according to claim 2, characterized in that, The step of obtaining the currently acquired signal on the CAN bus at the current moment based on the bus parameters includes: Extract the baud rate and sampling points of the CAN bus from the bus parameters; Find the CAN communication basic parameters corresponding to the baud rate and the sampling point from the preset table; Based on the CAN communication basic parameters, the current acquisition signal at the current moment is obtained from the CAN bus.

4. The method according to claim 1, characterized in that, Based on the picosecond-level lead compensation time, after applying an interference signal on the CAN bus, the method further includes: When the interference signal is high, the delay compensation time of the CAN bus is determined to be the turn-on time of the transistor switch; When the interference signal is low, the delay compensation time of the CAN bus is determined as the total delay time; wherein, the total delay time refers to the sum of the delay time from the CAN PHY bus to the CAN RX signal line and the delay time from the CAN TX signal line to the CAN PHY bus.

5. The method according to claim 1, characterized in that, Also includes: Obtain the picosecond-level delay compensation time; According to a preset threshold, the picosecond-level delay compensation time is divided into multiple segments to obtain multiple segmented delay times, and the multiple segmented delay times are sent to multiple timing controllers.

6. The method according to claim 1, characterized in that, Also includes: Obtain the temperature voltage and the number of taps corresponding to the picosecond-level delay compensation time; The temperature voltage is calibrated using the IDELAYCTRL unit in the delay compensation module; Based on the calibrated temperature and voltage, the number of taps corresponding to the picosecond-level delay compensation time is adjusted so that the delay time of all timing controllers in the delay compensation module is the same.

7. The method according to claim 1, characterized in that, The step of performing lead compensation on the nanosecond-level delay time through a configurable lead compensation and output module to obtain a nanosecond-level lead compensation time includes: Obtain the system clock frequency and the current position on the CAN bus; The configurable lead compensation and output module performs nanosecond-level timing on the nanosecond-level delay time based on the frequency and the position to obtain the nanosecond-level lead compensation time.

8. The method according to claim 1, characterized in that, The step of performing hysteresis compensation on the picosecond-level delay time through the delay compensation module to obtain the picosecond-level delay compensation time includes: Acquire the system clock, the nanosecond-level lead compensation time, and the user-configurable delay parameters; The delay tap allocation module in the delay compensation module uses the user-configurable delay parameters to calculate picosecond-level delay values. Each timing controller in the delay compensation module adjusts the picosecond-level delay time at the picosecond level based on the system clock, the nanosecond-level lead compensation time, and the picosecond-level delay value to obtain the picosecond-level delay compensation time.

9. A time compensation system for interference testing equipment, characterized in that, The time compensation system includes: a user configuration parameter parsing module, a configurable advance compensation and output module, and a delay compensation module; The user configuration parameter parsing module is used to obtain a first delay time and a second delay time, and to decompose the first delay time and the second delay time to obtain a nanosecond-level delay time corresponding to the first delay time and a picosecond-level delay time corresponding to the second delay time. The configurable lead compensation and output module is used to perform lead compensation on nanosecond-level delay time to obtain nanosecond-level lead compensation time; wherein, the configurable lead compensation and output module is composed of preset logic code; The delay compensation module is used to perform lag compensation on the picosecond-level delay time to obtain a picosecond-level delay compensation time, and to calculate the sum of the nanosecond-level lead compensation time and the picosecond-level delay compensation time to obtain a picosecond-level lead compensation time, and to apply an interference signal on the CAN bus based on the picosecond-level lead compensation time; wherein, the delay compensation module is composed of multiple timing controllers cascaded together, and the multiple timing controllers are used to adjust the picosecond-level delay time.

10. The system according to claim 9, characterized in that, Also used for: The user configuration parameter parsing module is used to obtain bus parameters on the CAN bus, and to obtain the current acquisition signal on the CAN bus at the current moment based on the bus parameters. The analysis module is used to analyze the currently acquired signal to obtain the interference position of the currently acquired signal on the CAN RX signal line; The delay compensation module is used to apply a target interference signal on the CAN bus according to the location of the interference.

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