Intelligent destruction method and device of storage chip, electronic equipment and storage medium

Abstract

The application relates to the technical field of semiconductor manufacturing, and provides an intelligent destruction method and device of a storage chip, an electronic device and a storage medium, the storage chip comprising a printed circuit board, the printed circuit board being provided with a flash memory, a charging module and a capacitor module; the method comprises the following steps: when a destruction instruction is received, the charging module is controlled to charge the capacitor module to a preset voltage; after the capacitor module is charged to the preset voltage, the charging module is controlled to stop charging the capacitor module, and the capacitor module discharges to the flash memory to destroy the flash memory. In the application, after the charging module charges the capacitor module, the capacitor module can apply high voltage to damage the structure of the flash memory, so that data destruction in the physical layer is realized, and the reliability is high.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor manufacturing, and in particular to an intelligent destruction method and device of a storage chip, an electronic device and a storage medium. BACKGROUND

[0002] In the related art, when a device installed with a storage chip is discarded, there is a need to clear the data stored in the flash memory. At present, the data stored in the flash memory is basically quickly erased by a master control chip. However, the erasing by the master control chip is a pure software-level destruction scheme, which may fail in some cases, resulting in a failure of data destruction. SUMMARY

[0003] In view of the deficiencies in the prior art, the present application provides an intelligent destruction method and device of a storage chip, an electronic device and a storage medium, which are beneficial to destroying data in the storage chip through a physical level.

[0004] To solve the above problems, the present application provides the following technical scheme:

[0005] In a first aspect, the present application provides an intelligent destruction method of a storage chip. The storage chip includes a printed circuit board, and the printed circuit board is provided with a flash memory, a charging module and a capacitor module. The method comprises the following steps:

[0006] When a destruction instruction is received, the charging module is controlled to charge the capacitor module to a preset voltage.

[0007] After the capacitor module is charged to the preset voltage, the charging module is controlled to stop charging the capacitor module, and the capacitor module discharges to the flash memory to destroy the flash memory.

[0008] In some embodiments, when the destruction instruction is received, the charging module is controlled to charge the capacitor module to the preset voltage, which comprises the following steps:

[0009] When the destruction instruction is received, the first switch module is controlled to be turned on to control the charging module to charge the capacitor module to the preset voltage.

[0010] In some embodiments, after the capacitor module is charged to the preset voltage, the charging module is controlled to stop charging the capacitor module, and the capacitor module discharges to the flash memory to destroy the flash memory, which comprises the following steps:

[0011] After the capacitor module is charged to the preset voltage, the first switch module is controlled to be turned off, the charging module stops charging the capacitor module, and the capacitor module discharges to the flash memory to destroy the flash memory.

[0012] In some embodiments, the method further comprises:

[0013] When the first switch module is turned on, if a stop destroying instruction is received, the first switch module and the second switch module are controlled to be turned off, and the third switch module is turned on.

[0014] In some embodiments, the control of the charging module to charge the capacitor module to a preset voltage comprises:

[0015] The power supply chip is controlled to charge the capacitor module to a preset voltage.

[0016] In some embodiments, the control of the charging module to charge the capacitor module to a preset voltage comprises:

[0017] The charging module is controlled to charge the capacitor module for a preset time, so that the voltage of the capacitor module reaches a preset voltage.

[0018] In some embodiments, the printed circuit board is provided with a plurality of flash memories and a plurality of capacitor modules; wherein,

[0019] The charging module is connected to the first end of each capacitor module;

[0020] The second end of each capacitor module is connected to the first end of the corresponding flash memory;

[0021] The second end of each flash memory is grounded.

[0022] In a second aspect, the embodiments of the present application provide an intelligent destroying device of a storage chip, the storage chip comprising a printed circuit board, the printed circuit board being provided with a flash memory, a charging module and a capacitor module; the device comprising:

[0023] A first control unit is configured to control the charging module to charge the capacitor module to a preset voltage when a destroying instruction is received;

[0024] A second control unit is configured to control the charging module to stop charging the capacitor module after the capacitor module is charged to a preset voltage, and the capacitor module discharges to the flash memory to destroy the flash memory.

[0025] In a third aspect, the embodiments of the present application provide an electronic device, the electronic device comprising:

[0026] At least one processor; and,

[0027] A memory in communication connection with the at least one processor; wherein,

[0028] The memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the intelligent destruction method of the storage chip according to the first aspect.

[0029] In a fourth aspect, an embodiment of the present application provides a computer readable storage medium storing an executable program, and the executable program is executed by a processor to implement the intelligent destruction method of the storage chip according to the first aspect.

[0030] The present application provides an intelligent destruction method and device of a storage chip, an electronic device, and a storage medium. The storage chip includes a printed circuit board, and the printed circuit board is provided with a flash memory, a charging module, and a capacitor module. The method includes: when a destruction instruction is received, controlling the charging module to charge the capacitor module to a preset voltage; after the capacitor module is charged to the preset voltage, controlling the charging module to stop charging the capacitor module, and the capacitor module discharges to the flash memory to destroy the flash memory. In the present application, after the charging module charges the capacitor module, the capacitor module can apply a high voltage to damage the structure of the flash memory, thereby realizing physical layer data destruction with high reliability. BRIEF DESCRIPTION OF DRAWINGS

[0031] Figure 1 FIG. 1 is a first structural schematic diagram of a storage chip with a destruction function provided by an embodiment of the present application.

[0032] Figure 2 FIG. 2 is a second structural schematic diagram of a storage chip with a destruction function provided by an embodiment of the present application.

[0033] Figure 3 FIG. 3 is a flow schematic diagram of an intelligent destruction method of a storage chip provided by an embodiment of the present application.

[0034] Figure 4 FIG. 4 is a structural schematic diagram of an electronic device according to an embodiment of the present application.

[0035] Figure 5 FIG. 5 is a structural block diagram of a computer readable storage medium provided by an embodiment of the present application. DETAILED DESCRIPTION

[0036] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative labor fall within the scope of protection of the present application.

[0037] In addition, the terms "first", "second", etc. are used only for descriptive purposes and should not be construed as indicating or implying relative importance or an indicated number of technical features. Therefore, the features defined as "first", "second", etc. can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise specifically limited.

[0038] Please refer to Figure 1 , Figure 1 is a first structural schematic diagram of a storage chip with a destruction function provided by the embodiments of the present application. As shown in Figure 1 , the storage chip with a destruction function 1 comprises a printed circuit board 10, wherein the printed circuit board 10 is provided with a flash memory 20, a charging module 30 and a capacitor module 40.

[0039] In some embodiments, the charging module 30 and the capacitor module 40 are circuit structures drawn in a printed circuit board (PCB).

[0040] In some embodiments, the storage chip 1 further comprises a plastic sealing layer (not shown in the figure), and the plastic sealing refers to a process of packaging and protecting part of components on the circuit board or the entire circuit board. Such packaging usually uses plastic materials such as epoxy resin or silicone resin, and the plastic sealing layer can provide mechanical protection, moisture resistance, dust resistance and insulation for the circuit, thereby prolonging the service life and reliability of the product.

[0041] In some embodiments, the flash memory 20 is a chip installed in the PCB.

[0042] Optionally, a master control chip and a double data rate synchronous dynamic random access memory 60 (DDR SRAM) are further arranged in the printed circuit board.

[0043] Specifically, Figure 1 only the connection relationship among the flash memory 20, the charging module 30 and the capacitor module 40 is shown, and the remaining connection relationship is not shown, which should not be understood as a limitation of the present application.

[0044] Exemplarily, the master control chip 50 is further connected with the flash memory 20 through a bus to read or write data, but Figure 1The bus, which is not shown, is, for example, a "Serial Peripheral Interface (SPI) bus", an "Inter-Integrated Circuit (I2C) bus", a "Quad SPI (QSPI) bus", a "Universal Serial Bus (USB)", a "Peripheral Component Interconnect express (PCIe)", and the like, and defines a physical path, a communication protocol, and an electrical specification for data transmission between the master chip 50 and the flash memory 20.

[0045] Optionally, the master chip 50 comprises a Central Processing Unit (CPU) or a Micro controller Unit (MCU).

[0046] In some embodiments, in order to ensure that the electric energy released by the capacitor module 40 can damage the flash memory, the withstand voltage value of the capacitor module 40 is greater than the working voltage of the flash memory 20; wherein the withstand voltage value of the capacitor refers to the maximum voltage value that the capacitor can withstand, and when the voltage of the capacitor is less than or equal to the withstand voltage value, the capacitor will not be broken down or damaged due to excessive voltage.

[0047] In some embodiments, the charging module 30 is connected to the first end of the capacitor module 40 for charging the capacitor module 40; the second end of the capacitor module 40 is connected to the first end of the flash memory 20; and the second end of the flash memory 20 is grounded.

[0048] Optionally, the first end of the flash memory 20 is one pin of the flash memory 20, and the second end of the flash memory 20 is a ground pin of the flash memory 20.

[0049] In some embodiments, in the circuit loop formed by the flash memory 20, the charging module 30, and the capacitor module 40, the capacitor module 40 and the flash memory 20 are connected in series.

[0050] In some embodiments, the charging current I of the charging module 30 should be greater than or equal to C * dV / dt, wherein C is the capacitance value of the capacitor module 40, and dV / dt is equal to the withstand voltage value of the capacitor module 40 divided by the charging time.

[0051] In some embodiments, the capacitor module 40 includes a plurality of tantalum capacitors in parallel, specifically, the tantalum capacitors have a volume much smaller than aluminum electrolytic capacitors at the same capacitance, are suitable for high-density installation, especially in electronic devices with limited space, and have better temperature characteristics and frequency characteristics than aluminum electrolytic capacitors, a wide operating temperature range, small leakage current, and good long-term stability.

[0052] In some embodiments, in order to achieve fast destruction of data, the distance between each tantalum capacitor and the corresponding flash memory on the printed circuit board is less than 5 mm.

[0053] Optionally, the storage chip 1 is a solid state disk, which is a wafer-level master control chip, flash memory, cache chip and other electronic components processed into a chip through system-in-package technology (SiP), with a small size, and an area generally less than 100mm*100mm.

[0054] Please refer to Figure 2 , Figure 2 is a second structural diagram of the storage chip with a destruction function provided by the embodiments of the present application. As Figure 2 shown, the printed circuit board 10 further includes a first switch module 70.

[0055] In some embodiments, the charging module 30 is connected to the capacitor module 40 through the first switch module 70, when the first switch module 70 is turned on, the charging module 30 charges the capacitor module 40; when the first switch module 70 is turned off, the charging module 30 stops charging the capacitor module 40, and the capacitor module 40 discharges to the flash memory 20 to destroy the flash memory 20.

[0056] Specifically, the master control chip 50 can control the first switch module 70 to be turned on or turned off, when the first switch module 70 is turned on, the charging module 30 charges the capacitor module 40, and when the first switch module 70 is turned off, the capacitor module 40 discharges externally.

[0057] Through the first switch module 70, whether the charging module 30 charges the capacitor module 40 can be controlled, so as to control the timing of destroying data.

[0058] In some embodiments, the printed circuit board 10 further includes a second switch module 80, a third switch module 90 and a current limiting module 100; the current limiting module 100 includes at least one current limiting resistor; the second end of the capacitor module 40 is connected to the first end of the second switch module 80 and the first end of the third switch module 90; the second end of the second switch module 80 is connected to the first end of the flash memory 20; the second end of the third switch module 90 is connected to the first end of the current limiting module 100, and the second end of the current limiting module 100 is grounded.

[0059] In some embodiments, the voltage range of the flash memory 20 is generally in the range of 1.8V to 3.6V, and since the voltage resistance value of the capacitor module 40 needs to be greater than 18V, for example, 28V, in order to prevent the current from being too large when the capacitor module 40 releases the electric energy, the value of the current limiting resistor should be greater than 500 ohms, for example, 1K ohms.

[0060] Optionally, in order to simplify the wiring, all the capacitor modules 40 release the voltage through the same pressure relief line, and at this time the value of the current limiting resistor should be greater than N*500 ohms, for example, N*1K ohms; wherein N is the number of flash memories 20 and also the number of capacitor modules 40.

[0061] In some embodiments, a plurality of flash memories 20 and a plurality of capacitor modules 40 are provided on the printed circuit board 10; wherein the charging module 30 is connected to the first end of each of the capacitor modules 40; the second end of each of the capacitor modules 40 is connected to the first end of the corresponding flash memory 20; and the second end of each of the flash memories 20 is grounded.

[0062] In some embodiments, when N flash memories 20 and N capacitor modules 40 are provided on the printed circuit board 10, N second switch modules 80 and one third switch module 90 should be provided on the printed circuit board 10, that is, each flash memory 20 corresponds to one capacitor module 40 and one second switch module 80, but all the capacitor modules 40 release the voltage through the same third switch module 90; wherein N is a positive integer.

[0063] At this time, the second end of each of the capacitor modules 40 is connected to the first end of the corresponding second switch module 80 and the first end of the third switch module 90, and the second end of each of the second switch modules 80 is connected to the first end of the corresponding flash memory.

[0064] In some embodiments, the charging module 30 includes an external interface for connecting an external device and receiving the electric energy delivered by the external device to charge the capacitor module 40 by the external device.

[0065] Specifically, the above arrangement is suitable for a storage chip with low cost, and when there is a need for destruction, the flash memory 20 is destroyed by an external voltage to destroy the data.

[0066] In some embodiments, the printed circuit board 10 further includes a master control chip 50 for controlling the switching state of the first switch module 70, the second switch module 80 and the third switch module 90; wherein the switching state includes turning on and turning off.

[0067] Optionally, the first switch module 70 comprises a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), and the master control chip 50 can control the first switch module 70 to be turned on or turned off by applying a control signal to the gate of the MOSFET.

[0068] Optionally, the second switch module 80 and the third switch module 90 each comprise a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), and the master control chip 50 can control the second switch module 80 and the third switch module 90 to be turned on or turned off by applying a control signal to the gate of the MOSFET.

[0069] In some embodiments, the master control chip 50 comprises a first pin for receiving a destruction instruction for controlling the first switch module 70 to be turned on, and a second pin for receiving a stop destruction instruction for controlling the second switch module 80 to be turned off and the third switch module 90 to be turned on.

[0070] Optionally, the master control chip 50 has an idle pin, which can be used to receive the destruction instruction and the stop destruction instruction.

[0071] In some embodiments, each of the capacitor modules 40 comprises a plurality of capacitors arranged in parallel, and the plurality of capacitors are sorted, and each of the plurality of capacitors except the first capacitor is connected to an NMOS tube, and the capacitor corresponding to the NMOS tube is defined as a current capacitor, the gate of each NMOS tube is connected to the second end of the previous capacitor of the current capacitor, the second end of the previous capacitor is connected to the first switch module 70, the source is connected to the first switch module 70, and the drain is connected to the current capacitor.

[0072] Thus, the capacitors in the capacitor module 40 are charged in a stepped manner, the charging time of the capacitor module 40 is appropriately extended, the user is given a sufficient time window to receive the notification destruction instruction, and the capacitor module 40 is prevented from being in a high voltage state for a long time, which can cause electromagnetic interference to other chips and generate excessive heat, etc.

[0073] In some embodiments, the printed circuit board 10 further comprises a power supply chip, and the processing unit can control the power supply chip to charge the capacitor module 40.

[0074] At this time, the step of controlling the charging module to charge the capacitor module to a preset voltage comprises:

[0075] The control power chip charges the capacitor module to a preset voltage.

[0076] In some embodiments, a diode is further arranged between the second switch module 80 and the flash memory 20, an anode of the diode is connected to the second switch module 80, and a cathode of the diode is connected to the flash memory 20.

[0077] In some embodiments, when the destruction instruction is received, the first switch module 70 is turned on, the second switch module 80 is turned on, and the third switch module 90 is turned off, and when the capacitor module 40 reaches a preset voltage, for example, a withstand voltage value, the first switch module 70 is turned off, so that the capacitor module 40 discharges to the flash memory 20 to destroy the flash memory.

[0078] Further, when the first switch module 70 is turned on, if a stop destruction instruction is received, the first switch module 70 is turned off after the third switch module 90 is turned on and the second switch module 80 is turned off, so that the capacitor module 40 releases electric energy through the current limiting module 100.

[0079] The intelligent destruction method of the storage chip in the embodiments of the present application can be applied to the storage chip with the above-mentioned destruction function.

[0080] Please refer to Figure 3 , Figure 3 is a flowchart of an intelligent destruction method of a storage chip provided by the embodiments of the present application. The storage chip includes a printed circuit board, and the printed circuit board is provided with a flash memory, a charging module, and a capacitor module; as shown in Figure 3 the method S100 includes steps S110 to S120.

[0081] Step S110: when a destruction instruction is received, the charging module is controlled to charge the capacitor module to a preset voltage.

[0082] In some embodiments, step S110 includes the step of: controlling the charging module to charge the capacitor module for a preset time, so that the voltage of the capacitor module reaches the preset voltage.

[0083] Specifically, the preset time can be set as needed, and the present application does not make any limitation.

[0084] Step S120: after the capacitor module is charged to the preset voltage, the charging module is controlled to stop charging the capacitor module, and the capacitor module discharges to the flash memory to destroy the flash memory.

[0085] In some embodiments, step S110 includes step 111: when a destruction instruction is received, the first switch module is turned on to control the charging module to charge the capacitor module to a preset voltage.

[0086] Optionally, when the first switch module is controlled to be turned on, the second switch module is controlled to be turned on and the third switch module is controlled to be turned off.

[0087] In some embodiments, based on step 111, step S120 comprises step 121: after the capacitor module is charged to the preset voltage, the first switch module is controlled to be turned off, the charging module stops charging the capacitor module, and the capacitor module discharges to the flash memory to destroy the flash memory.

[0088] In this way, not only can the destruction of the flash memory be controlled to start, but also remedial measures can be performed after the destruction instruction is issued by mistake, and the flash memory destruction can be terminated by issuing a stop destruction instruction.

[0089] However, tantalum capacitors are electrolytic capacitors using metal tantalum as a dielectric material, and high voltage can cause electrolyte decomposition, drying, or chemical composition change, thereby affecting the performance of the capacitor. At a higher working voltage, the ion conduction performance of the electrolyte can deteriorate, causing the effective capacitance value to decrease, and even possibly shortening the service life of the capacitor. In addition, too high a voltage can also cause the medium of the electrolytic capacitor to oxidize more severely, further reducing the capacitance value.

[0090] When destroying data, the present application needs to quickly destroy the data, so the tantalum capacitors are quickly charged to make their voltage approach the withstand voltage value. If a stop destruction instruction is received at this time, although the destruction process can be blocked, the effective capacitance value of the tantalum capacitor can decrease or even fail, causing the next destruction to fail. Therefore, in some embodiments, each tantalum capacitor of the capacitor module is connected in series with a resistor, and a switch that can short the resistor is provided, referred to as a resistor switch. The method provided in the embodiments of the present application further comprises the following steps.

[0091] (1) When the destruction instruction is received, the first switch module and all resistor switches are controlled to be turned on to limit the impact current and voltage spike at the moment when the first switch module is turned on.

[0092] (2) After charging for a first preset time, all resistor switches are turned off for fast charging.

[0093] (3) After charging for a second preset time, the first switch module is turned off to make the capacitor module discharge to the flash memory to destroy the flash memory.

[0094] Through the above setting of the resistor, the impact current and voltage spike at the moment when the first switch module is turned on can be limited to protect the tantalum capacitor from overvoltage damage. In addition, the user is given a certain time to change his mind. If the stop destruction instruction is issued within the first preset time after charging, the loss of the effective capacitance value of the tantalum capacitor can be further reduced.

[0095] The embodiment of the present application further provides an intelligent destroying device of a storage chip, the storage chip comprising a printed circuit board, the printed circuit board being provided with a flash memory, a charging module and a capacitor module; the device comprising:

[0096] a first control unit, configured to control the charging module to charge the capacitor module to a preset voltage when a destroying instruction is received;

[0097] a second control unit, configured to control the charging module to stop charging the capacitor module after the capacitor module is charged to the preset voltage, and the capacitor module discharges the flash memory to destroy the flash memory.

[0098] Please refer to Figure 4 , Figure 4 is a structural schematic diagram of an electronic device according to an embodiment of the present application. As shown in Figure 3 , the electronic device 200 comprises one or more processors 210 and a memory 220, Figure 4 , the processor 210 is taken as an example.

[0099] In some embodiments, the processor 210 and the memory 220 can be connected through a bus or other means, Figure 4 , the connection through the bus is taken as an example.

[0100] In some embodiments, the processor 210 is configured to control the charging module to charge the capacitor module to a preset voltage when a destroying instruction is received, and control the charging module to stop charging the capacitor module after the capacitor module is charged to the preset voltage, and the capacitor module discharges the flash memory to destroy the flash memory.

[0101] In some embodiments, the memory 220 serves as a non-volatile computer readable storage medium, and can be used to store non-volatile software programs, non-volatile computer executable programs and modules, such as the program instructions / modules of the intelligent destroying method of the storage chip according to the embodiment of the present application. The processor 210 executes various functional applications and data processing of the electronic device by running the non-volatile software programs, instructions and modules stored in the memory 220, that is, implements the intelligent destroying method of the storage chip according to the method embodiment.

[0102] In some embodiments, the memory 220 can include a program region and a data region, where the program region can store an operating system, at least one application required by a function, and the data region can store data created according to the use of the electronic device, etc. In addition, the memory 220 can include a high-speed random access memory, and can further include a non-volatile memory, such as at least one magnetic disk storage device, a flash memory device, or other non-volatile solid-state memory device. In some embodiments, the memory 220 can optionally include a memory disposed remotely with respect to the processor 210, and these remote memories can be connected to the controller through a network. Examples of the network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0103] In some embodiments, one or more modules are stored in the memory 220, and when executed by the one or more processors 210, perform the smart destruction method of a storage chip in any of the above method embodiments, for example, perform the method steps S110 to S120 in the above described Figure 4

[0104] Please refer to Figure 5 , Figure 5 is a structural block diagram of a computer readable storage medium provided by an embodiment of the present application. The computer readable storage medium 300 stores a program code 310 therein, and the program code 310 can be invoked by a processor to execute the smart destruction method of a storage chip described in the above method embodiments.

[0105] The computer readable storage medium 300 can be an electronic memory such as a flash memory, an EEPROM (electrically erasable programmable read-only memory), an EPROM, a hard disk, or a ROM. Alternatively, the computer readable storage medium includes a non-volatile computer readable medium (non-transitory computer-readable storage medium). The computer readable storage medium 300 has a storage space for program codes that perform any of the method steps in the above control method. These program codes can be read from or written into one or more computer program products. The program codes can be compressed in an appropriate form, for example.

[0106] ​To sum up, the application provides an intelligent destruction method and device of a storage chip, an electronic device and a storage medium, the storage chip comprising a printed circuit board, the printed circuit board being provided with a flash memory, a charging module and a capacitor module; the method comprising: when a destruction instruction is received, controlling the charging module to charge the capacitor module to a preset voltage; after the capacitor module is charged to the preset voltage, controlling the charging module to stop charging the capacitor module, and the capacitor module discharges to the flash memory to destroy the flash memory. In the application, after the charging module charges the capacitor module, the capacitor module can apply high voltage to damage the structure of the flash memory, thereby realizing data destruction at the physical level and having high reliability.

[0107] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the application, and not to limit them; although the application has been described in detail with reference to the foregoing embodiments, those skilled in the art will understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part of the technical features; and these modifications or replacements do not drive the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the application.

Claims

1. A method for intelligently destroying a memory chip, characterized in that, The memory chip includes a printed circuit board, on which a flash memory, a charging module, and a capacitor module are disposed. Each tantalum capacitor in the capacitor module is connected in series with a resistor. The printed circuit board is also provided with a resistor switch for short-circuiting the resistor. The printed circuit board also includes a first switch module, a second switch module, a third switch module, and a current limiting module; Each capacitor module includes multiple capacitors connected in parallel. The multiple capacitors are ordered, and each capacitor except the first one is connected to an NMOS transistor. The capacitor corresponding to the NMOS transistor is the current capacitor. The gate of each NMOS transistor is connected to the second terminal of the previous capacitor of the current capacitor. The second terminal of the previous capacitor is connected to the first switching module, the source is connected to the first switching module, and the drain is connected to the current capacitor. The method includes: Upon receiving a destruction command, the charging module is controlled to charge the capacitor module to a preset voltage; the step of controlling the charging module to charge the capacitor module to a preset voltage upon receiving a destruction command includes: upon receiving a destruction command, controlling the first switch module to turn on, so as to control the charging module to charge the capacitor module to a preset voltage; The step of controlling the charging module to charge the capacitor module to a preset voltage includes: controlling the charging module to charge the capacitor module for a preset time so that the voltage of the capacitor module reaches the preset voltage, wherein the first switch module and all the resistor switches are turned on to limit the inrush current and voltage spike at the moment the first switch module is turned on; after charging for a first preset time, all the resistor switches are turned off to perform fast charging; After the capacitor module is charged to a preset voltage, the charging module is controlled to stop charging the capacitor module, and the capacitor module discharges to the flash memory to destroy the flash memory. After a second preset charging time, the first switch module is turned off to allow the capacitor module to discharge to the flash memory to destroy the flash memory. When the first switch module is turned on, if a stop and destroy command is received, the first switch module and the second switch module are turned off, and the third switch module is turned on. After the third switch module is turned on and the second switch module is turned off, the first switch module is turned off, so that the capacitor module releases electrical energy through the current limiting module.

2. The method according to claim 1, characterized in that, After the capacitor module is charged to a preset voltage, the charging module is controlled to stop charging the capacitor module, and the capacitor module discharges to the flash memory to destroy the flash memory, including: After the capacitor module is charged to a preset voltage, the first switch module is turned off, the charging module stops charging the capacitor module, and the capacitor module discharges to the flash memory to destroy the flash memory.

3. The method according to claim 1, characterized in that, The step of controlling the charging module to charge the capacitor module to a preset voltage includes: The control power chip charges the capacitor module to a preset voltage.

4. The method according to claim 1, characterized in that, The printed circuit board is equipped with multiple flash memory modules and multiple capacitor modules; wherein... The charging module is connected to the first end of each of the capacitor modules; The second end of each capacitor module is connected to the first end of the corresponding flash memory; The second terminal of each flash memory is grounded.

5. A smart destruction device for a memory chip, characterized in that, The memory chip includes a printed circuit board, on which flash memory, a charging module, and a capacitor module are disposed; each tantalum capacitor in the capacitor module is connected in series with a resistor, and the printed circuit board is also provided with a resistor switch for short-circuiting the resistor; The printed circuit board also includes a first switch module, a second switch module, a third switch module, and a current limiting module; Each capacitor module includes multiple capacitors connected in parallel. The multiple capacitors are ordered, and each capacitor except the first one is connected to an NMOS transistor. The capacitor corresponding to the NMOS transistor is the current capacitor. The gate of each NMOS transistor is connected to the second terminal of the previous capacitor of the current capacitor. The second terminal of the previous capacitor is connected to the first switching module, the source is connected to the first switching module, and the drain is connected to the current capacitor. The device includes: The first control unit is used to control the charging module to charge the capacitor module to a preset voltage when a destruction command is received; The step of controlling the charging module to charge the capacitor module to a preset voltage when a destruction command is received includes: controlling the first switch module to turn on when a destruction command is received, so as to control the charging module to charge the capacitor module to a preset voltage; The step of controlling the charging module to charge the capacitor module to a preset voltage includes: controlling the charging module to charge the capacitor module for a preset time so that the voltage of the capacitor module reaches the preset voltage, wherein the first switch module and all the resistor switches are turned on to limit the inrush current and voltage spike at the moment the first switch module is turned on; after charging for a first preset time, all the resistor switches are turned off to perform fast charging; The second control unit is configured to control the charging module to stop charging the capacitor module after the capacitor module is charged to a preset voltage, and the capacitor module discharges to the flash memory to destroy the flash memory. The first switch module is turned off after a second preset charging time to allow the capacitor module to discharge to the flash memory to destroy the flash memory. When the first switch module is turned on, if a stop and destroy command is received, the first switch module and the second switch module are turned off, and the third switch module is turned on. After the third switch module is turned on and the second switch module is turned off, the first switch module is turned off, so that the capacitor module releases electrical energy through the current limiting module.

6. An electronic device, characterized in that, The electronic device includes: At least one processor; and, A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, which, when executed by the at least one processor, enables the at least one processor to perform the intelligent destruction method of the memory chip as described in any one of claims 1-4.

7. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores an executable program, which is executed by a processor to implement the intelligent destruction method of the memory chip as described in any one of claims 1-4.

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