Power semiconductor device and method for manufacturing the same

Abstract

The present disclosure relates to a power semiconductor device and a manufacturing method thereof. The power semiconductor device comprises: a wafer, a metal electrode and a thermal interface material layer. The thermal interface material layer is arranged between the metal electrode and the wafer. The metal electrode and the wafer are connected through the thermal interface material layer. The contact interface between the thermal interface material layer and the metal electrode forms a continuous phase structure. The contact interface between the thermal interface material layer and the wafer forms a continuous phase structure. The metal electrode and the wafer of the power semiconductor device disclosed in the present disclosure are connected through the thermal interface material layer, which can reduce the contact thermal resistance between the metal electrode and the wafer, thereby reducing the contact thermal resistance of the power semiconductor device, which is beneficial to improving the flow capacity of the power semiconductor device. At the same time, the connection between the metal electrode and the wafer through the thermal interface material layer can also reduce the mechanical pressure of the metal electrode and the wafer, reduce the risk of mechanical damage to the power semiconductor device, and improve the reliability of the power semiconductor device.

Description

Technical Field

[0001] The present disclosure relates to the field of power electronics technology, and in particular to a power semiconductor device and a manufacturing method thereof. Background Art

[0002] The current integrated gate-commutated thyristor (IGCT) is usually a rigid press-fit structure, and the electrical connection between all components in the IGCT device is achieved through pressure contact. However, pressure contact leads to large contact thermal resistance between components, and the heat dissipation performance of the IGCT device packaging structure is poor. The heat dissipation performance of the IGCT device packaging structure has become a key factor restricting the improvement of the device's current capacity, limiting the improvement of the IGCT device's current capacity.

[0003] Therefore, eliminating the interface contact thermal resistance between the components of the IGCT device and improving the current carrying capacity of the IGCT device have become issues that need to be urgently addressed in the field. Summary of the invention

[0004] 1. Technical issues to be resolved

[0005] The technical problems to be solved by the present disclosure include: 1. The interface contact thermal resistance between the components of the IGCT device is large; 2. The current carrying capacity of the IGCT device is poor.

[0006] (II) Technical solution

[0007] A first aspect of the present disclosure provides a power semiconductor device, comprising:

[0008] Wafer;

[0009] Metal electrodes;

[0010] A thermal interface material layer, wherein the thermal interface material layer is arranged between the metal electrode and the wafer, the metal electrode and the wafer are connected through the thermal interface material layer, the contact interface between the thermal interface material layer and the metal electrode forms a continuous phase structure, and the contact interface between the thermal interface material layer and the wafer forms a continuous phase structure.

[0011] Optionally, the continuous phase structure includes at least one connection method of sintering and welding.

[0012] Optionally, the thermal interface material layer includes one or more metal materials.

[0013] Optionally, the thermal interface material layer comprises:

[0014] a first connection layer, one side of the first connection layer being connected to the metal electrode;

[0015] a skeleton layer, wherein the skeleton layer is connected to a side of the first connection layer away from the metal electrode, and a contact interface between the skeleton layer and the first connection layer forms a continuous phase structure;

[0016] A second connecting layer, wherein the second connecting layer is connected to a side of the skeleton layer away from the first connecting layer, a contact interface between the second connecting layer and the skeleton layer forms a continuous phase structure, and a side of the second connecting layer away from the skeleton layer is connected to the wafer.

[0017] Optionally, the first connecting layer includes a first metal, the second connecting layer includes a second metal; the skeleton layer includes a third metal or a fourth metal or a mixture of the third metal and the fourth metal, and the third metal or the fourth metal or the mixture of the third metal and the fourth metal forms pores in the skeleton layer.

[0018] Optionally, the first metal is the same as or different from the second metal material, including at least one of silver or copper, or a composite metal material of silver or copper; the third metal includes at least one of palladium, copper or gold, or a composite metal material of palladium, copper or gold; the fourth metal includes at least one of palladium, copper or gold, or a composite metal material of palladium, copper or gold.

[0019] Optionally, the metal electrode includes a first electrode layer, a second electrode layer and a third electrode layer which are stacked, and at least one of the first electrode layer, the second electrode layer and the third electrode layer is a porous structure.

[0020] Optionally, the second electrode layer is a porous structure, and the porosity of the second electrode layer is less than 10%.

[0021] Optionally, the metal electrode is an anode electrode, a gate electrode or a cathode electrode.

[0022] Optionally, the metal electrode is disposed on the first surface of the wafer, and the metal electrode is connected to the first surface via a first thermal interface material layer.

[0023] Optionally, along the radial direction of the metal electrode, the side wall of the metal electrode is recessed toward the center of the metal electrode, or the side wall of the metal electrode is convex in a direction away from the center of the metal electrode.

[0024] Optionally, the metal electrode is provided on the second surface of the wafer, and the metal electrode is connected to the second surface.

[0025] A second aspect of the present disclosure is a method for manufacturing a power semiconductor device, comprising the following steps:

[0026] Providing metal electrodes;

[0027] forming a thermal interface material layer on the metal electrode;

[0028] Providing a wafer, wherein the wafer includes a region corresponding to the metal electrode;

[0029] Transferring the metal electrode to the wafer, wherein the metal electrode is arranged in a region corresponding to the metal electrode, and the thermal interface material layer is arranged between the metal electrode and the wafer;

[0030] The metal electrode and the wafer are processed under the first process conditions so that the contact interface between the thermal interface material layer and the metal electrode forms a continuous phase structure, the contact interface between the thermal interface material layer and the wafer forms a continuous phase structure, and the metal electrode and the wafer are connected through the thermal interface material layer.

[0031] Optionally, the continuous phase structure includes at least one connection method of sintering and welding.

[0032] Optionally, forming a thermal interface material layer on the metal electrode comprises:

[0033] A first connection layer, a skeleton layer, and a second connection layer are sequentially formed on the metal electrode, wherein the first connection layer includes a first metal, the second connection layer includes a second metal, the skeleton layer includes a third metal or a fourth metal, or a mixture of the third metal and the fourth metal, and the third metal or the fourth metal or the mixture of the third metal and the fourth metal forms pores in the skeleton layer;

[0034] Under the first process condition, the contact interface between the skeleton layer and the first connecting layer forms a continuous phase structure, the skeleton layer and the second connecting layer are connected, and the contact interface between the second connecting layer and the skeleton layer forms a continuous phase structure.

[0035] Optionally, the first metal is the same as or different from the second metal material, including at least one of silver or copper, or a composite metal material of silver or copper; the third metal includes at least one of palladium, copper or gold, or a composite metal material of palladium, copper or gold; the fourth metal includes at least one of palladium, copper or gold, or a composite metal material of palladium, copper or gold.

[0036] Optionally, the metal electrode is an anode electrode, a gate electrode or a cathode electrode;

[0037] The metal electrode includes a first electrode layer, a second electrode layer and a third electrode layer which are stacked, and at least one of the first electrode layer, the second electrode layer and the third electrode layer is a porous structure.

[0038] Optionally, the first process conditions include:

[0039] Pressure ≤30MPa, temperature ≤250℃.

[0040] (III) Beneficial effects

[0041] The power semiconductor device and the manufacturing method thereof disclosed in the present invention have the following beneficial effects:

[0042] The metal electrode and wafer of the power semiconductor device disclosed in the present invention are connected through a thermal interface material layer instead of a rigid crimping connection, which can reduce the contact thermal resistance between the metal electrode and the wafer, reduce the contact thermal resistance of the power semiconductor device, and help improve the current carrying capacity of the power semiconductor device; at the same time, the metal electrode and the wafer are connected through the thermal interface material layer, which can reduce the mechanical pressure on the metal electrode and the wafer, reduce the risk of mechanical damage to the power semiconductor device, and improve the reliability of the power semiconductor device.

[0043] The manufacturing method of the power semiconductor device disclosed in the present invention forms a thermal interface material layer on the metal electrode, and then processes the metal electrode and the wafer so that the metal electrode and the wafer are connected through the thermal interface material layer, thereby reducing the mechanical pressure between the metal electrode and the wafer, reducing the contact thermal resistance between the metal electrode and the wafer, and improving the current carrying capacity of the power semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0045] Figure 1 It is an exploded view of the structure of an IGCT device provided in an exemplary related solution.

[0046] Figure 2 FIG. 4 is a schematic structural diagram of a power semiconductor device provided in an exemplary embodiment.

[0047] Figure 3-1 FIG. 4 is a schematic diagram of the structure of a thermal interface material layer provided in an exemplary embodiment.

[0048] Figure 3-2 FIG. 4 is a schematic diagram of the structure of a thermal interface material layer provided in an exemplary embodiment.

[0049] Figure 4 FIG. 4 is a schematic diagram of the structure of a metal electrode provided in an exemplary embodiment.

[0050] Figure 5 FIG. 1 is a schematic diagram of the structure of a metal electrode used as an anode electrode in an exemplary embodiment.

[0051] Figure 6 FIG. 1 is a schematic structural diagram of a metal electrode used as a cathode electrode in an exemplary embodiment.

[0052] Figure 7 FIG. 1 is a schematic structural diagram of a metal electrode used as a gate electrode in an exemplary embodiment.

[0053] Figure 8 FIG. 4 is a schematic structural diagram of a power semiconductor device provided in an exemplary embodiment.

[0054] Fig. 9 FIG. 1 is a top view of one side of the second surface of a power semiconductor device provided in an exemplary embodiment.

[0055] Fig.10 The present invention is a flow chart of a method for manufacturing a power semiconductor device provided in an exemplary embodiment.

[0056] Reference numerals:

[0057] 10. Wafer; 101. First surface; 102. Second surface; 20. Metal electrode; 120. Anode electrode; 121. First anode layer; 122. Second anode layer; 123. Third anode layer; 220. Cathode electrode; 221. First cathode layer; 222. Second cathode layer; 223. Third cathode layer; 320. Gate electrode; 321. First gate layer; 322. Second gate layer; 323. Third gate layer; 30. Thermal interface material layer; 31. First connection layer; 32. Intermediate layer; 33. Second connection layer; 130. First thermal interface material layer; 230. Second thermal interface material layer; 330. Third thermal interface material layer; 150. First coating layer; 250. Second coating layer; 350. Third coating layer; 360. Insulation layer;

[0058] 901', tube base; 902', gate spoke; 903', first gasket; 904', first elastic sheet; 905', second elastic sheet; 906', second gasket; 907', ​​gate insulating base; 908', gate gasket; 909', gate electrode; 910', cathode electrode; 911', wafer; 912', anode electrode; 913', insulating sleeve; 914', tube shell cover. DETAILED DESCRIPTION

[0059] In order to facilitate understanding of the present disclosure, the present disclosure will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present disclosure more thorough and comprehensive.

[0060] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0061] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic representations of ideal embodiments (and intermediate structures) of the present disclosure, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Thus, embodiments of the present disclosure should not be limited to the particular shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the present disclosure.

[0062] The GCT device is mainly composed of a GCT element and a driving circuit board connected to the lead-out electrode. The GCT element is the core component of the IGCT device. The GCT element is composed of a semiconductor chip and a packaging tube shell. Figure 1 : is an exploded view of the GCT element in the IGCT device in the related scheme, such as Figure 1 As shown, the GCT element mainly includes a tube seat 901', a gate spoke 902', a first gasket 903', a first elastic sheet 904', a second elastic sheet 905', a second gasket 906', a gate insulating seat 907', ​​a gate gasket 908', a gate electrode 909', a cathode electrode 910', a wafer 911', an anode electrode 912', an insulating sleeve 913' and a tube shell cover 914', and all of the above components are electrically connected by rigid crimping.

[0063] In the relevant scheme, the pressure contact of the components in the GCT element leads to a large contact thermal resistance, which accounts for about 60% of the thermal resistance of the IGCT device, greatly limiting the current carrying capacity of the IGCT device, especially the contact resistance generated by the rigid pressing of the anode electrode 912', the gate electrode 909', the cathode electrode 910' and the wafer 911', which has a great impact on the contact thermal resistance of the GCT element. From the process point of view, the rigid pressing process has high requirements on the processing accuracy of the components, and the risk of mechanical damage to the device caused by rigid pressing is high. In addition, in the rigid pressing packaging method, the edge of the wafer is covered with insulating silicone and cannot directly contact the metal electrode. The heat dissipation performance is worse than other areas, which may cause uneven temperature distribution on the wafer surface and become a potential weak point of failure.

[0064] In view of this, the present disclosure provides a power semiconductor device and a manufacturing method thereof, wherein the power semiconductor device comprises a wafer, a metal electrode and a thermal interface material layer, wherein the thermal interface material layer is arranged between the metal electrode and the wafer, wherein the metal electrode and the wafer are connected via the thermal interface material layer, wherein the contact interface between the thermal interface material layer and the metal electrode forms a continuous phase structure, and wherein the contact interface between the thermal interface material layer and the wafer forms a continuous phase structure. The power semiconductor device of the present disclosure changes the connection mode between the metal electrode and the wafer, wherein the metal electrode and the wafer are connected via the thermal interface material layer instead of the rigid crimping connection, thereby reducing the contact thermal resistance between the metal electrode and the wafer, thereby reducing the contact thermal resistance of the power semiconductor device, and being beneficial to improving the flow capacity of the power semiconductor device, and at the same time, the connection between the metal electrode and the wafer via the thermal interface material layer can also reduce the mechanical pressure between the metal electrode and the wafer, thereby reducing the risk of mechanical damage to the power semiconductor device, and improving the reliability of the power semiconductor device.

[0065] Figure 2 It is a schematic diagram of the structure of a power semiconductor device. Figure 2 As shown, the power semiconductor device includes: a wafer 10, a metal electrode 20 and a thermal interface material layer 30. The thermal interface material layer 30 is disposed between the metal electrode 20 and the wafer 10, the metal electrode 20 and the wafer 10 are connected through the thermal interface material layer 30, and the contact interface between the thermal interface material layer 30 and the metal electrode 20 forms a continuous phase structure, and the contact interface between the thermal interface material layer 30 and the wafer 10 forms a continuous phase structure.

[0066] The continuous phase structure between the thermal interface material layer 30 and the metal electrode 20 is a non-interface connection structure, which may include at least one connection method of sintering, metallurgy (such as welding), etc., so that the metal electrode 20 and the wafer 10 are connected as a whole through the thermal interface material layer 30 .

[0067] The metal electrode 20 may include at least one of an anode electrode 120, a cathode electrode 220 and a gate electrode 320. The metal electrode 20 is disposed on the first surface 101 and / or the second surface 102 of the wafer 10, and is connected to the wafer 10 and the first surface 101 and / or the second surface 102 through the thermal interface material layer 30. That is, at least one of the anode electrode 120, the cathode electrode 220 and the gate electrode 320 of the power semiconductor device disclosed in the present invention is connected to the wafer 10 through the thermal interface material layer 30, and the interface-free connection structure is formed, which can reduce the contact thermal resistance of the power semiconductor device, thereby improving its current carrying capacity.

[0068] The thermal interface material layer 30 is disposed between the metal electrode 20 and the wafer 10 . The material of the thermal interface material layer 30 includes one or more metal materials.

[0069] In the power semiconductor device provided in this embodiment, the metal electrode and the wafer are connected by a thermal interface material layer instead of a rigid crimping connection, thereby reducing the contact thermal resistance between the metal electrode and the wafer, thereby reducing the contact thermal resistance of the power semiconductor device, which is beneficial to improving the current carrying capacity of the power semiconductor device. At the same time, the connection of the metal electrode and the wafer by the thermal interface material layer can also reduce the mechanical pressure on the metal electrode and the wafer, reduce the risk of mechanical damage to the power semiconductor device, and improve the reliability of the power semiconductor device.

[0070] Figure 3-1 Figure 2 is a schematic diagram of the thermal interface material layer. Figure 2 , Figure 3-1 As shown, the thermal interface material layer 30 is disposed between the metal electrode 20 and the wafer 10. One side of the thermal interface material layer 30 is connected to one side of the wafer 10, and the other side of the thermal interface material layer 30 is connected to one side of the metal electrode 20. The continuous phase structure between the thermal interface material layer 30 and the metal electrode 20 is a non-interface connection phase structure, which may include at least one connection method of sintering, metallurgy (such as welding), etc. The metal electrode 20 and the wafer 10 are connected as a whole through the thermal interface material layer 30. The material of the thermal interface material layer 30 includes one or more metal materials. The metal material may include a combination of metal materials with different densities and different particle sizes, so that the thermal interface material layer 30 has a certain porosity and density, which can make the thermal interface material layer 30 non-interface connected with the metal electrode 20 and the wafer 10, reduce the contact thermal resistance, and have the ability to disperse thermal stress, further improving the reliability of the device.

[0071] Figure 3-2 Figure 2 is a schematic diagram of the thermal interface material layer. Figure 2 , Figure 3-2 As shown, the thermal interface material layer 30 includes a first connection layer 31, a skeleton layer 32, and a second connection layer 33 which are sequentially arranged between the metal electrode 20 and the wafer 10. One side of the first connection layer 31 is connected to the metal electrode 20; the skeleton layer 32 is connected to the side of the first connection layer 31 away from the metal electrode 20, and the contact interface between the skeleton layer 32 and the first connection layer 31 forms a continuous phase structure; the second connection layer 33 is connected to the side of the skeleton layer 31 away from the first connection layer 31, and the contact interface between the second connection layer 33 and the skeleton layer 32 forms a continuous phase structure, and the side of the second connection layer 33 away from the skeleton layer 32 is connected to the wafer 10.

[0072] like Figure 3-2 As shown, the first connection layer 31 includes a first metal, and the second connection layer 33 includes a second metal; the first metal and the second metal are metal materials with high density. For example, the density of the first metal and the second metal is 8g / cm 3 -11 3 g / cm 3The first metal and the second metal may be the same or different; the first metal and the second metal may include at least one of silver or copper or a composite metal material of silver or copper. In this way, the materials of the first connection layer 31 and the second connection layer 33 have high thermal conductivity, low melting point, and high stability. In this embodiment, the materials of the first connection layer 31 and the second connection layer 33 include silver.

[0073] It can be understood that the first connection layer 31 of the thermal interface material layer 30 of the present embodiment includes a first metal. In other embodiments, the first connection layer 31 may also include an alloy formed by a first metal and a second metal. Similarly, in other embodiments, the second connection layer 33 may also include a first metal. The second connection layer 33 includes an alloy formed by a first metal and a second metal. The combination of the first metal and the second metal in the second connection layer 33 can prevent the first metal from diffusing into the wafer 10, thereby reducing the risk of short circuit or open circuit failure of the wafer 10.

[0074] like Figure 3-2 As shown, the skeleton layer 32 includes a third metal or a fourth metal or a mixture of the third metal and the fourth metal, and the third metal or the fourth metal or the mixture of the third metal and the fourth metal in the skeleton layer 32 forms pores in the skeleton layer 32; the third metal or the fourth metal includes at least one of palladium, copper or gold, or a composite metal material of palladium, copper or gold. In this embodiment, the material of the skeleton layer 32 includes palladium.

[0075] The contact interface of the thermal interface material layer 30, the skeleton layer 32 and the first connection layer 31 of this embodiment forms a non-interface connection phase structure, and the contact interface of the skeleton layer 32 and the second connection layer 33 forms a non-interface continuous phase structure. The non-interface connection phase structure can be connected into a whole by at least one connection method of sintering, metallurgy (such as welding), etc.

[0076] The skeleton layer 32 of the present embodiment is a loose porous structure. The skeleton layer 32 can eliminate part of the stress generated during the sintering process, thereby improving the structural stability and reliability of the thermal interface material layer 30 .

[0077] In some embodiments, as shown in Fig. 3, the metal content of the third metal or the fourth metal or the mixture of the third metal and the fourth metal in the thermal interface material layer 30 is 5wt%-15wt%. For example, the metal content of the third metal or the fourth metal or the mixture of the third metal and the fourth metal in the thermal interface material layer 30 may be 5wt%, 6wt%, 7wt%, 9wt%, 10wt%, 11wt%, 13wt% or 15wt%.

[0078] In some embodiments, the thickness of the thermal interface material layer 30 is 50 μm-100 μm, wherein the thickness of the first connection layer 31 is 15 μm-20 μm, the thickness of the skeleton layer 32 is 10 μm-15 μm, and the thickness of the second connection layer 33 is 15 μm-20 μm. For example, the thickness of the first connection layer 31 can be 15 μm, 16 μm, 17 μm, 18 μm, 19 μm or 20 μm; the thickness of the skeleton layer 32 can be 10 μm, 11 μm, 12 μm, 13 μm, 14 μm or 15 μm; the thickness of the second connection layer 33 can be 15 μm, 16 μm, 17 μm, 18 μm, 19 μm or 20 μm.

[0079] In some embodiments, the metal electrode 20 is an anode electrode, a gate electrode, or a cathode electrode.

[0080] Figure 4 Schematic diagram of the structure of the metal electrode 20. Figure 4 As shown, the metal electrode 20 includes a first electrode layer 21, a second electrode layer 22 and a third electrode layer 23 which are stacked, and at least one of the first electrode layer 21, the second electrode layer 22 and the third electrode layer 23 is a porous structure. The porous structure can increase the elasticity of the metal electrode 20, which is conducive to releasing some mechanical stress between the components of the power semiconductor device. At the same time, the porous structure can increase the thermal conductivity of the metal electrode 20, which can further reduce the contact thermal resistance between the components of the power semiconductor device and improve the current flow capacity of the power semiconductor device.

[0081] The material of the first electrode layer 21 and the material of the third electrode layer 23 include molybdenum, and the material of the second electrode layer 22 includes copper; the second electrode layer 22 is a porous structure, and the porosity of the second electrode layer 22 is less than 10%. In this way, it can ensure that the metal electrode 20 has good electrical conductivity and increase the thermal conductivity of the metal electrode 20. At the same time, the metal electrode 20 has elasticity, which can reduce the mechanical damage to the wafer 10 caused by the mechanical stress between the components of the power semiconductor device.

[0082] Figure 8 It is a schematic diagram of the structure of a power semiconductor device. Figure 8 As shown, the power semiconductor device includes a wafer 10, and the wafer 10 includes a first surface 101 and a second surface 102 arranged opposite to each other, and the first surface 101 of the wafer 10 is provided with an anode region. The first surface 101 of the wafer 10 is provided with a metal electrode 20, and the metal electrode 20 is connected to the first surface 101 through a first thermal interface material layer 130. The contact interface between the first thermal interface material layer 130 and the metal electrode 20 forms a continuous phase structure, and the contact interface between the first thermal interface material layer 130 and the first surface 101 of the wafer 10 forms a continuous phase structure.

[0083] In this embodiment, refer to Figure 8The entire surface of the first surface 101 serves as an anode region, and the metal electrode 20 provided on the first surface 101 serves as an anode electrode 120 .

[0084] The metal electrode 20 and the first surface 101 are connected through the first thermal interface material layer 130, which eliminates the contact thermal resistance between the metal electrode 20 and the surface of the wafer 10, reduces the mechanical pressure between the metal electrode 20 and the wafer 10, reduces the working mechanical pressure of the metal electrode 20 and the wafer 10, reduces the risk of mechanical damage to the power semiconductor device, improves the reliability of the power semiconductor device, and can improve the current flow capacity of the power semiconductor device; the metal electrode 20 and the wafer 10 are connected through the first thermal interface material layer 130, so that the size of the anode electrode of the first surface 101 can be set larger, the metal electrode 20 (anode electrode) can have the same size as the first surface 101 of the wafer 10, and the contact area between the metal electrode 20 and the wafer 10 reaches the maximum, further improving the heat dissipation capacity of the power semiconductor device, increasing the uniformity of the surface temperature of the wafer 10, which is conducive to further improving the current flow capacity of the power semiconductor device.

[0085] In some embodiments, Figure 5 , Figure 8 As shown, along the radial direction of the metal electrode 20, the side wall of the metal electrode 20 is recessed toward the center of the metal electrode 20, or the side wall of the metal electrode 20 is convex in the direction away from the center of the metal electrode 20. In this way, the heat dissipation area of ​​the metal electrode 20 is increased without affecting the contact area between the metal electrode 20 and the wafer 10, and the heat dissipation capacity of the metal electrode 20 is increased. When the power semiconductor device is packaged, the contact area between the side wall of the metal electrode 20 and the insulating glue is larger, and the heat dissipation effect of the metal electrode 20 is better.

[0086] It can be understood that the purpose of the inward recess or outward protrusion of the side wall of the metal electrode 20 in this embodiment is to increase the heat dissipation area and increase the contact area between the metal electrode 20 and the insulating glue. In this embodiment, there is no restriction on the size of the inward recess or outward protrusion of the metal electrode 20. The side wall of the metal electrode 20 can be partially recessed inward or protruded outward, or the entire side wall of the circumference of the metal electrode 20 can be recessed inward or protruded outward, so as to increase the area of ​​the side wall of the metal electrode 20.

[0087] In a preferred embodiment, the side wall of the metal electrode 20 can be provided with a plurality of inwardly recessed recesses and / or a plurality of outwardly protruding protrusions. For example, the protrusions and recesses can be alternately arranged along the circumference of the metal electrode 20 to form a serrated morphology on the side wall of the metal electrode 20. In this way, the alternating arrangement of the protrusions and recesses further increases the area of ​​the side wall of the metal electrode 20, increases the heat dissipation area of ​​the metal electrode 20, and increases the subsequent contact area between the metal electrode 20 and the insulating glue.

[0088] like Figure 8 As shown, in the power semiconductor device of this embodiment, the second surface 102 of the wafer 10 is also provided with a metal electrode 20, and the metal electrode 20 is connected to the second surface 102. The second surface 102 is also provided with a thermal interface material layer 30, and the metal electrode 20 is connected to the second surface 102 through the thermal interface material layer 30.

[0089] In this embodiment, the second surface 102 is provided with a cathode region and a gate region that are spaced apart. The cathode region and the gate region of the second surface 102 are each provided with a metal electrode 20, the metal electrode 20 provided in the cathode region is a cathode electrode 220, and the metal electrode 20 provided in the gate region is a gate electrode 320. The metal electrode 20 on the cathode region is connected to the cathode region through the second thermal interface material layer 30, and the metal electrode 20 on the gate region is connected to the gate region through the third thermal interface material layer 330.

[0090] In other embodiments, the cathode electrode 220 can be connected to the second surface 102 of the wafer 10 by rigid pressing, for example, the cathode electrode 220 can be set on the cathode region by rigid pressing. The gate electrode 320 can be connected to the second surface 102 of the wafer 10 by other methods, for example, the gate electrode 320 can be set on the gate region by rigid pressing.

[0091] Reference Fig. 9 As shown, the cathode electrode 220 and the gate electrode 320 are concentrically arranged ring structures. The power semiconductor device may include multiple cathode electrodes 220, and the gate electrode 230 may be arranged at the center of the multiple cathode electrodes 220, or the gate electrode 230 may be arranged at the outermost periphery of the center of the multiple cathode electrodes 220, or refer to Fig. 9 , the gate electrode 230 may be disposed between a plurality of cathode electrodes 220 .

[0092] In this embodiment, an insulating layer 360 is provided on the side wall of the gate electrode 320 . The insulating layer 360 is used to prevent the gate electrode 320 and the cathode electrode 220 from being short-circuited and turned on, thereby improving the safety and electrical performance of the power semiconductor device.

[0093] Compared with the solution of connecting components of power semiconductor devices through crimping in the related art, the anode electrode, cathode electrode, and gate electrode of the power semiconductor device of this embodiment are connected together through a thermal interface material layer with high thermal conductivity and a wafer, which greatly reduces the contact thermal resistance between the anode electrode, cathode electrode, gate electrode and the wafer surface. The contact thermal resistance of the power semiconductor device is reduced by 10%-15%, which greatly improves the current carrying capacity of the power semiconductor device.

[0094] At the same time, in this embodiment, a thermal interface material layer connection is used instead of a crimping connection, so that the anode electrode, cathode electrode, and gate electrode can be integrated on the entire wafer, and the front side of the first side of the wafer is used as the anode area to connect to the anode electrode, which not only increases the heat dissipation area of ​​the wafer, but also increases the contact area between the anode electrode and the wafer, thereby improving the uniformity of the wafer surface temperature, which is beneficial to further improve the working performance of the power semiconductor device.

[0095] In an exemplary embodiment of the present disclosure, a method for manufacturing a power semiconductor device is provided, such as Fig.10 As shown, Fig.10 A flow chart of a method for manufacturing a power semiconductor device provided according to an exemplary embodiment of the present disclosure is shown. This embodiment does not limit the power semiconductor device. The power semiconductor device will be described below by taking an integrated gate-commutated thyristor (IGCT) as an example, but this embodiment is not limited to this. The power semiconductor device in this embodiment may also have other structures.

[0096] like Fig.10 As shown, a method for manufacturing a power semiconductor device provided by an exemplary embodiment of the present disclosure includes the following steps:

[0097] Step S11: providing a metal electrode.

[0098] Step S12: forming a thermal interface material layer on the metal electrode.

[0099] Step S13: providing a wafer, wherein the wafer includes an area corresponding to the metal electrode.

[0100] Step S14: transferring the metal electrode to the wafer, setting the metal electrode in the area corresponding to the metal electrode, and setting the thermal interface material layer between the metal electrode and the wafer.

[0101] Step S15: Processing the metal electrode and the wafer under the first process conditions so that the contact interface between the thermal interface material layer and the metal electrode forms a continuous phase structure, the contact interface between the thermal interface material layer and the wafer forms a continuous phase structure, and the metal electrode and the wafer are connected through the thermal interface material layer.

[0102] In step S11, refer to Figure 2 As shown, the metal electrode 20 can be one of the anode electrode 120, the cathode electrode 220 or the gate electrode 320. The metal electrode 20 includes a first electrode layer 21, a second electrode layer 22 and a third electrode layer 23 which are stacked, and at least one of the first electrode layer 21, the second electrode layer 22 and the third electrode layer 23 is a porous structure.

[0103] In one example, the second electrode layer 22 is a porous structure.

[0104] In this embodiment, the metal electrode 20 can be manufactured by using 3D printing technology.

[0105] In step S12, in this embodiment, refer to Figure 2 As shown, a thermal interface material layer 30 is formed on the metal electrode 20, using the following implementation method:

[0106] Reference Figure 2 As shown in Figure 3, a first connection layer 31, a skeleton layer 32 and a second connection layer 33 are sequentially formed on the metal electrode 20, the first connection layer 31 includes a first metal, the second connection layer 33 includes a second metal, the skeleton layer 32 includes a third metal or a fourth metal or a mixture of the third metal and the fourth metal, and the third metal or the fourth metal or the mixture of the third metal and the fourth metal forms pores in the skeleton layer 32.

[0107] In this embodiment, the first metal is the same as or different from the second metal material, including at least one of silver or copper, or a composite metal material of silver or copper; the third metal is different from the fourth metal, and the third metal includes at least one of palladium, copper or gold, or a composite metal material of palladium, copper or gold; the fourth metal includes at least one of palladium, copper or gold, or a composite metal material of palladium, copper or gold.

[0108] Specifically, in this embodiment, refer to Figure 2 As shown in FIG3 , silver particles are deposited on the metal electrode 20 to form a first connection layer 31, the diameter of the silver particles is 50nm-1μm, and the thickness of the first connection layer 31 is 15-20μm. Then, palladium particles are deposited on the first connection layer 31 to form a skeleton layer 32, the diameter of the palladium particles is 100nm-10μm, and the thickness of the skeleton layer 32 is 10μm-15μm. This embodiment utilizes the large diameter of palladium particles, and the palladium particles are accumulated in the skeleton layer 32 to form gaps, so that the skeleton layer 32 formed is a mesh structure.

[0109] Next, silver particles are deposited on the skeleton layer 32 to form the second connection layer 33 . The diameter of the silver particles is 50 nm-1 μm, and the thickness of the second connection layer 33 is 15-20 μm.

[0110] In this embodiment, the content of the second metal in the thermal interface material layer 30 is 5wt%-15wt%. For example, the content of the second metal in the thermal interface material layer 30 may be 5wt%, 6wt%, 7wt%, 9wt%, 10wt%, 11wt%, 13wt% or 15wt%.

[0111] In this embodiment, the thermal interface material layer 30 includes a stacked three-layer structure, the bottom first connection layer 31 includes a first metal, the material of the top second connection layer 33 includes a second metal, and the middle skeleton layer 32 includes a loose third metal or a fourth metal or a mixture of the third metal and the fourth metal (at least one of palladium, copper or gold). In this way, after the thermal interface material layer 30 is sintered (detailed description will be given in subsequent steps), part of the skeleton layer 32, the third metal or the fourth metal or the mixture of the third metal and the fourth metal and part of the first metal in the first connection layer 31 are combined into an alloy, and the third metal or the fourth metal or the mixture of the third metal and the fourth metal and part of the second metal in the second connection layer 32 are combined into an alloy, which can prevent the first metal and / or the second metal from migrating into the metal electrode 20 or the wafer 10 and affecting the performance of the power semiconductor device.

[0112] In step S13, refer to Figure 2 As shown, the wafer 10 provided in this embodiment is a semiconductor wafer, for example, the wafer 10 may be a silicon wafer. The first surface 101 and / or the second surface 102 of the wafer 10 is provided with an area corresponding to the metal electrode 20 .

[0113] In step S14, refer to Figure 2 As shown, the thermal interface material layer 30 faces the wafer 10 , the metal electrode 20 is disposed on the wafer 10 , and the thermal interface material layer 30 is disposed between the metal electrode 20 and the wafer 10 .

[0114] In step S15, refer to Figure 2 As shown, under the first process condition, the metal electrode 20 and the wafer 30 are sintered and metallurgically treated (such as welding). Under the first process condition, the first continuous phase structure includes at least one connection method of sintering and welding.

[0115] The connecting layer 31 is connected to the metal electrode 20, and the contact interface between the first connecting layer 31 and the metal electrode 20 forms a continuous phase structure. The second connecting layer 33 is connected to the wafer 10, and the contact interface between the second connecting layer 33 and the wafer 10 forms a continuous phase structure. The skeleton layer 32 is connected to the first connecting layer 31, and the contact interface between the skeleton layer 32 and the first connecting layer 31 forms a continuous phase structure. The skeleton layer 32 is connected to the second connecting layer 33, and the contact interface between the second connecting layer 33 and the skeleton layer 32 forms a continuous phase structure.

[0116] The first process condition has a pressure of ≤30 MPa and a temperature of ≤250°C.

[0117] Specifically, when the pressure of the first process condition is ≤30 MPa, the gas in the sintering environment can be diffused into the thermal interface material layer 30 more quickly, which is beneficial to shorten the processing time and prevents the pressure from being too high to damage the wafer 10 or the metal electrode 20. When the temperature of the first process condition is ≤250°C, the temperature stress can be reduced to avoid thermal damage to the wafer 10 caused by the processing temperature of the metal electrode 20 and the wafer 10 being too high.

[0118] The manufacturing method of the power semiconductor device of this embodiment forms a thermal interface material layer on the metal electrode and then uses a sintering process to process the metal electrode and the wafer so that the metal electrode and the wafer are connected through the thermal interface material layer, thereby reducing the mechanical pressure between the metal electrode and the wafer, reducing the contact thermal resistance between the metal electrode and the wafer, and improving the current carrying capacity of the power semiconductor device.

[0119] In some embodiments, after step S15, the following steps are further performed: chamfering the wafer 10, and then injecting insulating glue into the surface of the wafer 10, so that the insulating glue covers the wafer 10 and the metal electrode 20 on the wafer 10. Then, the wafer 10 and the metal electrode 20 covered with the insulating glue are packaged together with other components to form a power semiconductor device.

[0120] According to an exemplary embodiment, a method for manufacturing a power semiconductor device comprises the following steps:

[0121] First, a metal electrode 20 is provided as an anode electrode 120. Figure 5 As shown, the anode electrode 120 includes a first anode layer 121, a second anode layer 122 and a third anode layer 123 which are stacked, and at least one of the first anode layer 121, the second anode layer 122 and the third anode layer 123 is a porous structure.

[0122] Reference Figure 5 , a first anode layer 121 is formed by 3D printing technology, and the material of the first anode layer 121 includes molybdenum. Then, a second anode layer 122 is formed on the first anode layer 121 by 3D printing technology, and the material of the second anode layer 122 includes loose metal copper, and the porosity of the second anode layer 122 is less than 10%. Next, a third anode layer 123 is formed on the second anode layer 122 by 3D printing technology, and the material of the third anode layer 123 includes molybdenum. The first anode layer 121, the second anode layer 122 and the third anode layer 123 together form the anode electrode 120. The anode electrode 120 formed in this embodiment has good conductivity, and the porous structure of the second anode layer 122 can increase the elasticity of the anode electrode 120, and the second anode layer 122 can release part of the mechanical stress in the power semiconductor device.

[0123] In some embodiments, after the anode electrode 120 is formed, the side wall of the anode electrode 120 is processed so that along the radial direction of the anode electrode 120, the side wall of the anode electrode 120 is recessed toward the center of the anode electrode 120, or the side wall of the anode electrode 120 is convex in a direction away from the center of the anode electrode 120, so as to ensure that the anode electrode 120 and the wafer 10 have a maximum contact area, while increasing the area of ​​the side wall of the anode electrode 120 and the heat dissipation area of ​​the anode electrode 120, which can improve the heat dissipation capacity of the anode electrode 120, thereby further improving the heat dissipation capacity of the formed power semiconductor device and enhancing the current carrying capacity of the power semiconductor device.

[0124] Then, a first thermal interface material layer 130 is formed on the surface of the anode electrode 120 .

[0125] Refer to Figure 3. Figure 8 , silver particles are deposited on the anode electrode 120 using 3D printing technology to form a first connection layer, the diameter of the silver particles is 50nm-1μm, and the thickness of the first connection layer is 15μm-20μm. Palladium particles are deposited on the first connection layer using 3D printing technology to form an intermediate layer, the diameter of the palladium particles is 100nm-10μm, and the thickness of the intermediate layer is 10μm-15μm. Silver particles are deposited on the intermediate layer using 3D printing technology to form a second connection layer, the diameter of the silver particles is 50nm-1μm, and the thickness of the second connection layer is 15μm-20μm. The first connection layer, the intermediate layer, and the second connection layer form a first thermal interface material layer 130 on the anode electrode 120.

[0126] The content of palladium particles in the first thermal interface material layer 130 is 5wt%-15wt%. For example, the content of palladium particles in the first thermal interface material layer 130 may be 5wt%, 6wt%, 7wt%, 9wt%, 10wt%, 11wt%, 13wt% or 15wt%.

[0127] The diameter of the palladium particles in the middle layer is larger than the diameter of the silver particles in the first connection layer and the second connection layer. The palladium particles are accumulated between the first connection layer and the second connection layer to form a structural gap in the middle layer, that is, the middle layer has a porous structure. In this way, the stress in the sintering process can be released and the reliability of the first thermal interface material layer 130 is improved.

[0128] In this embodiment, after the anode electrode is formed, the following steps are further performed:

[0129] Reference Figure 8, a first plating layer 150 is formed on the anode electrode 120 by using 3D printing technology, the thickness of the first plating layer 150 is 1μm-5μm, and the material of the first plating layer 150 includes silver. The first plating layer 150 is arranged on the side of the anode electrode 120 away from the first thermal interface material layer 130, that is, the first plating layer 150 and the first thermal interface material layer 130 are arranged on both sides of the anode electrode 120 relatively. In order to save process steps, the first plating layer 150 can be formed simultaneously with the first connection layer of the first thermal interface material layer 130, or the first plating layer 150 can be formed simultaneously with the second connection layer of the first thermal interface material layer 130.

[0130] Then, the anode electrode 120 is disposed on the anode region of the wafer 10 , where the anode region is located on the first surface 101 of the wafer 10 , and the first thermal interface material layer 130 is disposed between the anode electrode 120 and the first surface 101 .

[0131] In this embodiment, refer to Figure 8 The entire first surface 101 of the wafer 10 is used as the anode area, and the anode electrode 120 and the first surface 101 of the wafer 10 have the same shape and size. In this way, the anode electrode 120 is arranged on the first surface 101 of the wafer 10 and the contact area with the wafer 10 is maximized, thereby improving the uniformity of the surface temperature of the wafer 10 to a greater extent and improving the heat dissipation efficiency of the power semiconductor device to a greater extent.

[0132] Next, the anode electrode 120 and the wafer 10 are processed under the first process conditions so that the contact interface between the first thermal interface material layer 130 and the anode electrode 120 forms a continuous phase structure, the contact interface between the first thermal interface material layer 130 and the first surface 101 forms a continuous phase structure, and the anode electrode 120 and the first surface 101 are connected through the first thermal interface material layer 130.

[0133] Reference Figure 8 , the anode electrode 120 and the wafer 10 are sintered under the first process conditions, the sintering pressure of the first process conditions is ≤30MPa, and the sintering temperature is ≤250°C, so that the anode electrode 120 is connected to the first surface 101 of the wafer 10 through the first thermal interface material layer 130. The sintering process can be performed once or multiple times according to the sintering conditions.

[0134] In the power semiconductor device formed in this embodiment, the anode electrode and the wafer are connected by a first thermal interface material layer, which reduces the contact thermal resistance between the anode electrode and the wafer, reduces the mechanical pressure between components in the power semiconductor device, avoids rigid pressing to damage the anode electrode and / or wafer, and improves the reliability of the power semiconductor device.

[0135] In the power semiconductor device formed in this embodiment, a first plating layer is formed on the surface of the anode electrode away from the wafer, and the first plating layer has good conductivity, so that the contact resistance / thermal resistance between the anode electrode and other components (such as the copper electrode of the tube shell) can be reduced by the first plating layer. For example, the material of the first plating layer includes silver.

[0136] In the power semiconductor device formed in this embodiment, the anode electrode is recessed inward or protruded outward. After the power semiconductor device is injected with insulating glue for packaging, the contact area between the side wall of the anode electrode and the insulating glue at the edge of the wafer is larger, thereby increasing the heat dissipation area of ​​the anode electrode, further improving the heat dissipation efficiency of the anode electrode, and ensuring that the anode electrode and the insulating glue are more tightly connected, thereby improving the structural stability of the packaging structure.

[0137] According to an exemplary embodiment, the method for manufacturing a power semiconductor device of this embodiment further performs the following steps:

[0138] Provide a metal electrode 20 as a cathode electrode 220, referring to Figure 6 In this embodiment, the cathode electrode 220 includes a first cathode layer 221, a second cathode layer 222 and a third cathode layer 223 stacked in sequence. The materials of the first cathode layer 221 and the third cathode layer 223 include molybdenum, the material of the second cathode layer 222 exposes loose metal copper, and the porosity of the second cathode layer 222 is less than 10%.

[0139] A second thermal interface material layer 230 is formed on the surface of the cathode electrode 220. The second thermal interface material layer 230 is formed on the cathode electrode 220 using 3D printing technology. The second thermal interface material layer 230 includes a first connection layer, an intermediate layer, and a second connection layer sequentially disposed on the cathode electrode 220.

[0140] Reference Figure 8 , a second plating layer 250 is formed on the cathode electrode 220 by using 3D printing technology, the thickness of the second plating layer 250 is 1μm-5μm, and the material of the second plating layer 250 includes silver. The second plating layer 250 is arranged on the side of the cathode electrode 220 away from the second thermal interface material layer 230, and the second plating layer 250 can be formed at the same time as the first connection layer of the second thermal interface material layer 230, or the second plating layer 250 can be formed at the same time as the second connection layer of the second thermal interface material layer 230.

[0141] Reference Figure 8 The cathode electrode 220 is disposed on the cathode region of the wafer 10 , wherein the cathode region is disposed on the second surface 102 of the wafer 10 opposite to the first surface 101 of the wafer 10 . The second thermal interface material layer 230 is disposed between the cathode electrode 220 and the second surface 102 .

[0142] Continue to refer to Figure 8 The cathode electrode 220 and the wafer 10 are sintered under the first process condition, and the sintering pressure of the first process condition is ≤30MPa and the sintering temperature is ≤250°C, so that the cathode electrode 220 is connected to the second surface 102 of the wafer 10 through the second thermal interface material layer 230. The sintering process can be performed once or multiple times according to the sintering conditions.

[0143] In the power semiconductor device formed in this embodiment, the cathode electrode and the wafer are connected through the second thermal interface material layer, which reduces the contact thermal resistance between the cathode electrode and the wafer, reduces the mechanical pressure between the components in the power semiconductor device, avoids rigid pressing to damage the cathode electrode and / or wafer, and improves the reliability of the power semiconductor device.

[0144] According to an exemplary embodiment, the method for manufacturing a power semiconductor device of this embodiment further performs the following steps:

[0145] Reference Figure 7 A metal electrode 20 is provided as a gate electrode 320. The gate electrode 320 includes a first gate electrode layer 321, a second gate electrode layer 322 and a third gate electrode layer 323 stacked in sequence, the materials of the first gate electrode layer 321 and the third gate electrode layer 323 include molybdenum, the material of the second gate electrode layer 322 exposes loose metal copper, and the porosity of the second gate electrode layer 322 is less than 10%.

[0146] Refer to Figure 3. Figure 7 , Figure 8 A third thermal interface material layer 330 is formed on the gate electrode 320 using 3D printing technology. The implementation method for forming the third thermal interface material layer 330 is the same as the implementation method for forming the first thermal interface material layer 130, and will not be repeated here.

[0147] The third plating layer 350 is formed on the gate electrode 320 by 3D printing technology. The thickness of the third plating layer 350 is 1 μm-5 μm. The material of the third plating layer 350 includes silver. The third plating layer 350 is disposed on a side of the gate electrode 320 away from the third thermal interface material layer 330 .

[0148] Reference Figure 7 , Figure 8 , an insulating material is coated on the side wall of the gate electrode 320 to form an insulating layer 360, and the material of the insulating layer 360 may include polyimide, etc. In this way, the gate electrode 320 and the cathode electrode 220 are both connected to the second surface 102 of the wafer 10, and the insulating layer 360 covers the side wall of the gate electrode 320, which can prevent the gate electrode 320 and the cathode electrode 22 from being short-circuited and turned on, thereby improving the safety and electrical performance of the power semiconductor device.

[0149] Reference Figure 8The gate electrode 320 is disposed on the gate region of the wafer 10, and the third thermal interface material layer 330 is disposed between the gate electrode 320 and the second surface 102. The gate region is disposed on the second surface 102 of the wafer 10, and the gate region and the cathode region are disposed at intervals on the second surface 102 of the wafer 10.

[0150] Reference Figure 8 The gate electrode 320 and the wafer 10 are sintered under the first process conditions, wherein the sintering pressure of the first process conditions is ≤30 MPa and the sintering temperature is ≤250° C., so that the gate electrode 320 is connected to the second surface 102 of the wafer 10 through the third thermal interface material layer 330. The sintering process can be performed once or multiple times according to the sintering conditions.

[0151] In the power semiconductor device formed in this embodiment, the gate electrode and the wafer are connected through the second thermal interface material layer, which reduces the contact thermal resistance between the gate electrode and the wafer, reduces the mechanical pressure between the components in the power semiconductor device, avoids rigid pressing to damage the gate electrode and / or wafer, and improves the reliability of the power semiconductor device.

[0152] According to an exemplary embodiment, this embodiment does not constitute a limitation on the above embodiment. This embodiment is a further description of the method for manufacturing a power semiconductor device in the above embodiment. In some embodiments, referring to Figure 8 After the cathode electrode 220 and the gate electrode 320 are respectively arranged on the cathode region and the gate region of the second surface 102 of the wafer 10, the cathode electrode 220, the gate electrode 320 and the wafer 10 are sintered under the first process condition, so that the cathode electrode 220 is connected to the second surface 102 of the wafer 10 through the second thermal interface material layer 230, and the gate electrode 320 is connected to the second surface 102 of the wafer 10 through the third thermal interface material layer 330. In this way, a sintering step is saved, the manufacturing process is simplified, and it is beneficial to improve the product yield and reduce the production cost.

[0153] In some embodiments, after the gate electrode 320 and the wafer 10 are connected, the following steps are performed: the wafer 10 is chamfered, and then an insulating glue (not shown in the figure) is injected into the surface of the wafer 10, and the insulating glue covers the wafer 10 and the anode electrode 120, the cathode electrode 220 and the gate electrode 320 on the wafer 10. Then, the structure covered with the insulating glue is combined with other structures and packaged to form a power semiconductor device.

[0154] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0155] The above-described embodiments only express several implementation methods of the present disclosure, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present disclosure, and these all belong to the protection scope of the present disclosure. Therefore, the protection scope of the patent of the present disclosure shall be subject to the attached claims.

Claims

1. A power semiconductor device, characterized in that: include: Wafer; Metal electrodes; A thermal interface material layer, wherein the thermal interface material layer is disposed between the metal electrode and the wafer, the metal electrode and the wafer are connected via the thermal interface material layer, a contact interface between the thermal interface material layer and the metal electrode forms a continuous phase structure, and a contact interface between the thermal interface material layer and the wafer forms a continuous phase structure; The thermal interface material layer comprises: a first connection layer, one side of the first connection layer being connected to the metal electrode; a skeleton layer, wherein the skeleton layer is connected to a side of the first connection layer away from the metal electrode, and a contact interface between the skeleton layer and the first connection layer forms a continuous phase structure; a second connection layer, wherein the second connection layer is connected to a side of the skeleton layer away from the first connection layer, a contact interface between the second connection layer and the skeleton layer forms a continuous phase structure, and a side of the second connection layer away from the skeleton layer is connected to the wafer; The first connecting layer includes a first metal, and the second connecting layer includes a second metal; the skeleton layer includes a third metal or a fourth metal or a mixture of the third metal and the fourth metal, and the third metal or the fourth metal or the mixture of the third metal and the fourth metal forms pores in the skeleton layer; The first metal is the same as or different from the second metal material, and includes at least one of silver or copper, or a composite metal material of silver or copper; the third metal includes at least one of palladium, copper or gold, or a composite metal material of palladium, copper or gold; the fourth metal includes at least one of palladium, copper or gold, or a composite metal material of palladium, copper or gold.

2. The power semiconductor device according to claim 1, characterized in that: The continuous phase structure includes at least one connection method of sintering and welding.

3. The power semiconductor device according to claim 1, characterized in that: The thermal interface material layer includes one or more metal materials.

4. The power semiconductor device according to claim 1, characterized in that: The metal electrode includes a first electrode layer, a second electrode layer and a third electrode layer which are stacked, and at least one of the first electrode layer, the second electrode layer and the third electrode layer is a porous structure.

5. The power semiconductor device according to claim 4, characterized in that: The second electrode layer is a porous structure, and the porosity of the second electrode layer is less than 10%.

6. The power semiconductor device according to claim 4, characterized in that: The metal electrode is an anode electrode, a gate electrode or a cathode electrode.

7. The power semiconductor device according to claim 6, characterized in that: The metal electrode is disposed on the first surface of the wafer, and the metal electrode is connected to the first surface through a first thermal interface material layer.

8. The power semiconductor device according to claim 7, characterized in that: Along the radial direction of the metal electrode, the side wall of the metal electrode is recessed toward the center of the metal electrode, or the side wall of the metal electrode is convex toward a direction away from the center of the metal electrode.

9. The power semiconductor device according to claim 8, characterized in that: The metal electrode is disposed on the second surface of the wafer, and the metal electrode is connected to the second surface.

10. A method for manufacturing a power semiconductor device, characterized in that: The following steps are involved: Providing metal electrodes; forming a thermal interface material layer on the metal electrode; Providing a wafer, wherein the wafer includes a region corresponding to the metal electrode; Transferring the metal electrode to the wafer, wherein the metal electrode is arranged in a region corresponding to the metal electrode, and the thermal interface material layer is arranged between the metal electrode and the wafer; Processing the metal electrode and the wafer under a first process condition so that a contact interface between the thermal interface material layer and the metal electrode forms a continuous phase structure, a contact interface between the thermal interface material layer and the wafer forms a continuous phase structure, and the metal electrode and the wafer are connected via the thermal interface material layer; The step of forming a thermal interface material layer on the metal electrode comprises: A first connection layer, a skeleton layer, and a second connection layer are sequentially formed on the metal electrode, wherein the first connection layer includes a first metal, the second connection layer includes a second metal, the skeleton layer includes a third metal or a fourth metal, or a mixture of the third metal and the fourth metal, and the third metal or the fourth metal or the mixture of the third metal and the fourth metal forms pores in the skeleton layer; Under the first process condition, the contact interface between the skeleton layer and the first connecting layer forms a continuous phase structure, the skeleton layer and the second connecting layer are connected, and the contact interface between the second connecting layer and the skeleton layer forms a continuous phase structure; The first metal is the same as or different from the second metal material, and includes at least one of silver or copper, or a composite metal material of silver or copper; the third metal includes at least one of palladium, copper or gold, or a composite metal material of palladium, copper or gold; the fourth metal includes at least one of palladium, copper or gold, or a composite metal material of palladium, copper or gold.

11. The method for manufacturing a power semiconductor device according to claim 10, characterized in that: The continuous phase structure includes at least one connection method of sintering and welding.

12. The method for manufacturing a power semiconductor device according to claim 10, characterized in that: The metal electrode is an anode electrode, a gate electrode or a cathode electrode; The metal electrode includes a first electrode layer, a second electrode layer and a third electrode layer which are stacked, and at least one of the first electrode layer, the second electrode layer and the third electrode layer is a porous structure.

13. The method for manufacturing a power semiconductor device according to claim 10, characterized in that: The first process conditions include: Pressure ≤30MPa, temperature ≤250℃.

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