A planar gate MOSFET with reduced on-resistance and a method for manufacturing the same

Abstract

A planar gate MOSFET with reduced on-resistance and a preparation method thereof relate to the field of semiconductor technology. A thin N+ layer is formed between the P body region and the P+ channel region of the device. In the off state, no voltage is applied to the G pole electrode. The N+ layer is completely depleted and non-conductive under the clamping of the P body region and the P+ channel region. In the on state, a positive voltage is applied to the G pole electrode, and an inversion layer conductive channel is formed in the P+ channel region on one side of the gate oxide. At the same time, due to the positive voltage applied to the G pole electrode, the N+ layer clamped by the P body region and the P+ channel region changes from a completely depleted state to a normal conductive state. The N+ layer and the inversion layer conductive channel are connected in parallel to jointly bear the on-current of the device, thereby reducing the on-resistance of the planar gate vertical conductive MOSFET.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a planar gate MOSFET with reduced on-resistance and a preparation method thereof. Background Art

[0002] In the field of power electronic device technology, MOSFET, as a commonly used power semiconductor, has replaced triode and become one of the most commonly used switching devices in the power semiconductor field.

[0003] During the decades of iteration of MOSFET, improving power density has always been one of its main development directions. Reducing the on-resistance per unit area is the most effective way to increase the power density of the device, and it is also one of the most important research and development directions of MOSFET.

[0004] At present, the conventional planar gate MOSFET structure is as follows Fig.11 As shown in the figure, the industry's measures to reduce its on-resistance are mainly to reduce the cell pitch and adopt a super junction structure. With the improvement of process accuracy, the cell pitch of planar gate MOSFET has been reduced to the theoretical limit in recent years. After 20 years of development, the super junction structure has also reached its theoretical limit. Therefore, in order to reduce the on-resistance of planar gate MOSFET, new technologies and new structures must be adopted to achieve the purpose of further reducing its on-resistance. Summary of the invention

[0005] Aiming at the research and development direction of reducing the on-resistance value per unit area of ​​MOSFET, the present invention provides a planar gate MOSFET with reduced on-resistance and a preparation method thereof.

[0006] The technical solution of the present invention is:

[0007] A method for preparing a planar gate MOSFET with reduced on-resistance comprises the following steps:

[0008] Step S100, preparing a plurality of spaced P body regions in the epitaxial wafer;

[0009] Step S200, preparing a plurality of N+ regions spaced apart in a P body region;

[0010] Step S300, preparing a P+ channel region in the N+ region;

[0011] Step S400, preparing a gate dielectric on the epitaxial wafer, and preparing polysilicon on the gate dielectric above the P+ channel region;

[0012] Step S500, depositing an isolation layer on the epitaxial wafer, and opening windows in the N+ region and the polysilicon to prepare an S-pole electrode and a G-pole electrode respectively;

[0013] Step S600, preparing a D-pole electrode at the bottom of the epitaxial wafer, and the entire device is prepared.

[0014] Specifically, step S100 includes:

[0015] Step S110 , using a photolithography process and a mask to protect the outer area of ​​the P body region; and forming a plurality of spaced P body regions through a diffusion process or an ion implantation process.

[0016] Specifically, the thickness of the P body region is 1-20 um, and the spacing distance is 1-10 um.

[0017] Specifically, step S200 includes:

[0018] Step S210, using a photolithography process and a mask to protect the area outside the N+ region; and forming a plurality of N+ regions spaced apart by a diffusion process or an ion implantation process.

[0019] Specifically, the thickness of the N+ region is 0.5-10 um.

[0020] Specifically, step S300 includes:

[0021] Step S310: using a photolithography process and a mask to protect the outer area of ​​the P+ channel region; and forming the P+ channel region through a diffusion process or an ion implantation process.

[0022] Specifically, step S400 includes:

[0023] Step S410, preparing a gate dielectric on the epitaxial wafer using a thermal oxidation technique;

[0024] Step S420 , using a mask to protect the outer area of ​​the P+ channel region through a photolithography process, and preparing polysilicon on the gate dielectric above the P+ channel region through chemical vapor deposition.

[0025] Specifically, step S500 includes:

[0026] Step S510, preparing an isolation layer by chemical vapor deposition, protecting the N+ region and the outer region of the polysilicon by a mask through a photolithography process, and opening windows in the N+ region and the polysilicon by an etching process;

[0027] Step S520, preparing corresponding S-pole electrodes and G-pole electrodes at the N+ region and the polysilicon window by a stripping process or an etching process.

[0028] A planar gate MOSFET with reduced on-resistance includes a D-pole electrode, an epitaxial wafer, polysilicon and an isolation layer arranged in sequence from bottom to top;

[0029] The top of the epitaxial wafer is provided with:

[0030] P body regions are provided in plurality and are spaced apart from each other, and extend downward from the top surface of the epitaxial wafer respectively;

[0031] There are several N+ regions, each located in the P body region and extending downward from the top surface of the epitaxial wafer, and the bottom surface of each N+ region is higher than the bottom surface of the P body region;

[0032] There are several P+ channel regions, each extending downward from the top surface of the corresponding N+ region, and the bottom surface of each P+ channel region is higher than the bottom surface of the N+ region; a side surface of each N+ region and the P+ channel region overlaps with one side of the P body region;

[0033] A gate dielectric, located on the top surface of the epitaxial wafer;

[0034] The polysilicon is provided with a plurality of layers spaced apart from each other and respectively located above the P+ channel region and on the top surface of the gate dielectric;

[0035] The isolation layer is provided with:

[0036] An S-pole electrode extends downward from the top surface of the isolation layer into the P-body region and is connected to the N+ region and the P-body region to form an ohmic contact;

[0037] A G-pole electrode extending downward from the top surface of the isolation layer into the polysilicon and forming an ohmic contact with the polysilicon;

[0038] Specifically, the epitaxial wafer includes an N+ substrate layer and an N-voltage-resistant layer connected from bottom to top;

[0039] The D-pole electrode is connected to the N+ substrate layer to form an ohmic contact.

[0040] Beneficial effects of the present invention:

[0041] Compared with the traditional planar gate vertical conductive MOSFET, the present invention forms a thin N+ layer between the P body region and the P+ channel region of the device. In the off state, no voltage is applied to the G pole electrode, and the N+ layer is completely depleted and non-conductive under the clamping of the P body region and the P+ channel region. In the on state, a positive voltage is applied to the G pole electrode, and an inversion layer conductive channel is formed in the P+ channel region on one side of the gate oxide. At the same time, due to the positive voltage applied to the G pole electrode, the N+ layer clamped by the P body region and the P+ channel region changes from a completely depleted state to a normal conductive state. The N+ layer and the inversion layer conductive channel are connected in parallel to jointly bear the through-current of the device, thereby reducing the on-resistance of the planar gate vertical conductive MOSFET. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 It is a process flow chart of the present invention;

[0043] Figure 2 is a schematic diagram of the cross-sectional structure of the device in step S100;

[0044] Figure 3 is a schematic diagram of the cross-sectional structure of the device in step S200;

[0045] Figure 4 is a schematic diagram of the cross-sectional structure of the device in step S300;

[0046] Figure 5 is a schematic diagram of the gate dielectric structure prepared in step S400;

[0047] Figure 6 is a schematic diagram of the polysilicon structure prepared in step S400;

[0048] Figure 7 is a schematic diagram of the structure of the deposited isolation layer in step S500;

[0049] Figure 8 is a schematic diagram of the window structure at the N+ region and the polysilicon in step S500;

[0050] Fig. 9 is a schematic diagram of the structure of the S-pole electrode and the G-pole electrode prepared in step S500;

[0051] Fig.10 It is a schematic diagram of the structure after preparation;

[0052] Fig.11 This is a schematic diagram of the conventional structure MOSFET structure;

[0053] In the figure, 1 is the epitaxial wafer, 2 is the P body region, 3 is the N+ region, 4 is the P+ channel region, 5 is the gate dielectric, 6 is the polysilicon, 7 is the isolation layer, 8 is the S pole electrode, 9 is the G pole electrode, 10 is the D electrode, 11 is the N+ substrate layer, and 12 is the N- voltage-resistant layer. DETAILED DESCRIPTION

[0054] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.

[0055] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0056] The present invention is described below with reference to Figures 1-9;

[0057] A method for preparing a planar gate MOSFET with reduced on-resistance comprises the following steps:

[0058] Step S100, preparing a plurality of spaced P body regions 2 in the epitaxial wafer 1; Figure 2 As shown;

[0059] Step S110, using a photolithography process and a mask to protect the outer area of ​​the P body region 2; forming a plurality of spaced P body regions 2 by a diffusion process or an ion implantation process;

[0060] Correspondingly, the epitaxial wafer 1 is an N-type epitaxial wafer, which is composed of an N+ substrate layer 11 and an N-voltage-resistant layer 12 from bottom to top. The thickness of the epitaxial wafer 1 is 100-2000um, the thickness of the N+ substrate layer 11 is 90-1500um, the thickness of the N-voltage-resistant layer 12 is 10-500um, the thickness of the P body region 2 is 1-20um, and the spacing distance is 1-10um; the doping concentration range of the N-type doping is 1e 14 .cm -3 -1e 20 .cm -3 , the doping concentration range of P-type doping is 1e 15 .cm -3 -1e 20 .cm -3 , the relevant parameter settings are related to the electrical design of the device;

[0061] In this embodiment, the thickness of the epitaxial wafer 1 is 350um, the thickness of the N+ substrate layer 13 is 300um, and the doping concentration is 2e 19 .cm -3 , the thickness of N-voltage-resistant layer 14 is 50um, and the doping concentration is 1e 16 .cm -3 , the thickness of P body region 2 is 5um, the spacing is 2um, and the doping concentration is 1e 17 .cm -3 , the P body region 2 is prepared using an ion implantation process.

[0062] Step S200, preparing a plurality of N+ regions 3 spaced apart in the P body region 2; Figure 3 As shown;

[0063] Step S210, using a photolithography process and a mask to protect the outer area of ​​the N+ region 3; forming a plurality of N+ regions 3 arranged at intervals by a diffusion process or an ion implantation process;

[0064] Accordingly, the N+ region 3 extends downward from the top surface of the epitaxial wafer 1, and its bottom surface is higher than the bottom surface of the P body region 2, with a thickness of 0.5-10um and a doping concentration range of 1e 18 .cm-3 -1e 20 .cm -3 , the relevant parameter settings are related to the electrical design of the device;

[0065] In this embodiment, the thickness of N+ region 3 is 3um and the doping concentration is 2e 19. cm -3 , an N+ region 3 is prepared using an ion implantation process.

[0066] Step S300, preparing a P+ channel region 4 in the N+ region 3; Figure 4 As shown;

[0067] Step S310, using a photolithography process and a mask to protect the outer area of ​​the P+ channel region 4; forming the P+ channel region 4 by a diffusion process or an ion implantation process;

[0068] Accordingly, the P+ channel region 4 extends downward from the top surface of the epitaxial wafer 1, and its bottom surface is higher than the bottom surface of the N+ region 3, and its thickness is set to 0.25-5um, and the doping concentration range is 1e 18 .cm -3 -1e 20 .cm -3 , the relevant parameter settings are related to the electrical design of the device;

[0069] In this embodiment, the thickness of the P+ channel region 4 is 2.95 um and the doping concentration is 3e 18. cm -3 , an N+ region 3 is prepared using an ion implantation process.

[0070] Step S400, preparing a gate dielectric 5 on the epitaxial wafer 1, such as Figure 5 As shown, polysilicon 6 is prepared on the gate dielectric 5 above the P+ channel region 4. Figure 6 As shown;

[0071] Step S410, preparing a gate dielectric 5 on the epitaxial wafer 1 using a thermal oxidation technique;

[0072] Step S420, using a mask to protect the outer area of ​​the P+ channel region 4 through a photolithography process, and preparing polysilicon 6 on the gate dielectric 5 above the P+ channel region 4 through chemical vapor deposition;

[0073] Accordingly, the gate dielectric 5 is made of SiO2, with a thickness of 40-500nm, and the thickness of the polysilicon 6 is set to 100nm-5um;

[0074] In this embodiment, 80 nm SiO2 is prepared as the gate dielectric 5 by using thermal oxidation technology, and 500 nm polysilicon 6 is prepared by using chemical vapor deposition.

[0075] Step S500, depositing an isolation layer 7 on the epitaxial wafer, such as Figure 7 As shown, windows are opened at the N+ region 3 and the polysilicon 6, as shown Figure 8 As shown, the S-pole electrode 8 and the G-pole electrode 9 are prepared respectively. Fig. 9 As shown;

[0076] Step S510, preparing the isolation layer 7 by chemical vapor deposition, protecting the N+ region 3 and the outer area of ​​the polysilicon 6 by using a mask through a photolithography process, and opening windows in the N+ region 3 and the polysilicon 6 by an etching process;

[0077] Step S520, preparing corresponding S-pole electrode 8 and G-pole electrode 9 at the N+ region and the polysilicon 6 window by stripping or etching;

[0078] Accordingly, the isolation layer 7 plays a protective role, and is made of SiO2 or Si3N4, with a thickness set to 10-5000nm. ICP dry etching is used to open windows, and the window opening depth is greater than the sum of the thicknesses of the isolation layer 7 and the gate dielectric 5. The S-pole electrode 8 extends downward from the top surface of the isolation layer 7, and is connected to the N+ region 3 and the P-body region 2 to form an ohmic contact. The G-pole electrode 9 extends downward from the top surface of the isolation layer 7, and is connected to the polysilicon 6 to form an ohmic contact.

[0079] In this embodiment, Si3N4 is used as the isolation layer 7, the thickness is set to 200nm, ICP dry etching is used for window opening, the window opening depth is 300nm, and Al / Ti two-layer metal is used to prepare the S-pole electrode 8 and the G-pole electrode 9.

[0080] Step S600, prepare the D-pole electrode 10 at the bottom of the epitaxial wafer, and the entire device is prepared; Fig.10 As shown;

[0081] Step S610, preparing a D-pole electrode 10 at the bottom of the epitaxial wafer 1 through a thinning process and a back-gold process, and the entire device is prepared;

[0082] Accordingly, the epitaxial wafer 1 is thinned using a thinning process, and a D-pole electrode 10 is prepared using a back-gold process. The D-pole electrode 10 is connected to the N+ substrate layer 11 to form an ohmic contact.

[0083] In this embodiment, a 350 um thick epitaxial wafer 1 is thinned to 180 um using a thinning process, and a D-pole electrode 10 is prepared using two layers of Al / Ti metal, and the entire device is prepared.

[0084] A planar gate MOSFET with reduced on-resistance comprises a D-pole electrode 10, an epitaxial wafer 1, polysilicon 6 and an isolation layer 7 arranged in sequence from bottom to top;

[0085] The top of the epitaxial wafer 1 is provided with:

[0086] P body regions 2 are provided in plurality and spaced apart from each other, are located in the N-voltage-resistant layer 12, extend downward from the top surface of the epitaxial wafer 1, and have bottom surfaces higher than the bottom surface of the N-voltage-resistant layer 12;

[0087] There are several N+ regions 3, each located in the P body region 2, extending downward from the top surface of the epitaxial wafer 1, and having a bottom surface higher than the bottom surface of the P body region 2;

[0088] There are several P+ channel regions 4, each extending downward from the top surface of the corresponding N+ region 3, and the bottom surface thereof is higher than the bottom surface of the N+ region 3; one side surface of the N+ region 3 and the P+ channel region 4 respectively overlaps with one side of the P body region 2;

[0089] In the P body region 2, along the vertical direction of the region where the P+ channel region 4 is located, a structure of a P+ channel region 4, an N+ region 3 and a P body region 2 is formed from top to bottom; in this structure, the N+ region 3 is completely depleted by the P+ channel region 4 and the P body region 2 along the vertical direction.

[0090] A gate dielectric 5, located on the top surface of the epitaxial wafer 1;

[0091] The polysilicon 6 is provided with a plurality of layers spaced apart from each other and respectively located above the P+ channel region 4 and on the top surface of the gate dielectric 5;

[0092] The isolation layer 7 is provided with:

[0093] An S-pole electrode 8 extends downward from the top surface of the isolation layer 7 into the P-body region 2 and is connected to the N+ region 3 and the P-body region 2 to form an ohmic contact;

[0094] A G-pole electrode 9 extends downward from the top surface of the isolation layer 7 into the polysilicon 6 and forms an ohmic contact with the polysilicon 6;

[0095] It is further defined that the epitaxial wafer 1 includes an N+ substrate layer 11 and an N-voltage-resistant layer 12 connected from bottom to top; a D-pole electrode 10 is connected to the N+ substrate layer 11 to form an ohmic contact.

[0096] The present invention has the following advantages:

[0097] The on-resistance of the planar gate vertical conductive MOSFET is mainly composed of two parts, one part is provided by the N-voltage-resistant layer resistance, and the other part is provided by the inversion layer channel resistance. Compared with the planar gate vertical conductive MOSFET with a traditional structure, the present invention innovatively forms a thin N+ layer between the P body region and the P+ channel region of the device. In the off state, no voltage is applied to the G pole electrode, and the N+ layer is completely depleted and non-conductive under the clamping of the P body region and the P+ channel region. In the on state, a positive voltage is applied to the G pole electrode, and an inversion layer conductive channel is formed in the P+ channel region on the gate oxide side. At the same time, due to the positive voltage applied to the G pole electrode, the N+ layer clamped by the P body region and the P+ channel region changes from a completely depleted state to a normal conductive state. The N+ layer and the inversion layer conductive channel are connected in parallel to jointly bear the on-current of the device, thereby reducing the on-resistance of the planar gate vertical conductive MOSFET.

[0098] Compared with the traditional planar gate vertical conduction MOSFET ( Fig.10 ), under the same process conditions, a planar gate MOSFET with reduced on-resistance prepared by the present invention ( Fig. 9 ), the on-resistance is reduced by 10%-20%.

[0099] Regarding the contents disclosed in this case, there are a few points that need to be explained:

[0100] The drawings of the embodiments disclosed in this case only involve the structures involved in the embodiments disclosed in this case, and other structures can refer to the usual designs;

[0101] In the absence of conflict, the embodiments and features of the embodiments disclosed in this case can be combined with each other to obtain new embodiments;

[0102] The above are only specific implementation methods disclosed in this case, but the protection scope of the present disclosure is not limited thereto. The protection scope disclosed in this case should be based on the protection scope of the claims.

Claims

1. A method for preparing a planar gate MOSFET with reduced on-resistance, characterized in that: The following steps are involved: Step S100, preparing a plurality of spaced P body regions (2) in the epitaxial wafer (1); Step S200, preparing a plurality of N+ regions (3) arranged at intervals in the P body region (2); Step S300, preparing a P+ channel region (4) in the N+ region (3); Step S310, using a photolithography process and a mask to protect the outer area of ​​the P+ channel region (4); forming the P+ channel region (4) by a diffusion process or an ion implantation process; Step S400, preparing a gate dielectric (5) on the epitaxial wafer (1), and preparing polysilicon (6) on the gate dielectric (5) above the P+ channel region (4); Step S410, preparing a gate dielectric (5) on the epitaxial wafer (1) using a thermal oxidation technique; Step S420, using a mask to protect the outer area of ​​the P+ channel region (4) through a photolithography process, and preparing polysilicon (6) on the gate dielectric (5) above the P+ channel region (4) through chemical vapor deposition; Step S500, depositing an isolation layer (7) on the epitaxial wafer, and opening windows at the N+ region (3) and the polysilicon (6), and preparing an S-pole electrode (8) and a G-pole electrode (9) respectively; Step S510, using chemical vapor deposition to prepare an isolation layer (7), using a photolithography process to protect the N+ region (3) and the outer region of the polysilicon (6) using a mask, and using an etching process to open windows in the N+ region (3) and the polysilicon (6); Step S520, preparing corresponding S-pole electrodes (8) and G-pole electrodes (9) at the N+ region and the polysilicon (6) window openings by means of a stripping process or an etching process; Step S600, preparing a D-pole electrode (10) at the bottom of the epitaxial wafer, and the entire device is prepared.

2. The method for preparing a planar gate MOSFET with reduced on-resistance according to claim 1, characterized in that: Step S100 includes: Step S110, using a photolithography process and a mask to protect the outer area of ​​the P body region (2); and forming a plurality of spaced P body regions (2) through a diffusion process or an ion implantation process.

3. A method for preparing a planar gate MOSFET with reduced on-resistance according to claim 1 or 2, characterized in that: The thickness of the P body region (2) is 1-20 microns, and the spacing distance is 1-10 microns.

4. The method for preparing a planar gate MOSFET with reduced on-resistance according to claim 1, characterized in that: Step S200 includes: Step S210: using a photolithography process and a mask to protect the outer area of ​​the N+ region (3); and forming a plurality of N+ regions (3) arranged at intervals by a diffusion process or an ion implantation process.

5. A method for preparing a planar gate MOSFET with reduced on-resistance according to claim 1 or 4, characterized in that: The thickness of the N+ region (3) is 0.5-10 microns.

6. A planar gate MOSFET with reduced on-resistance, prepared by the method for preparing a planar gate MOSFET with reduced on-resistance according to claim 1, characterized in that: It comprises a D-pole electrode (10), an epitaxial wafer (1), polysilicon (6) and an isolation layer (7) which are arranged in sequence from bottom to top; The epitaxial wafer (1) is provided with: P body regions (2), provided with a plurality of mutually spaced P body regions (2), extending downward from the top surface of the epitaxial wafer (1); A plurality of N+ regions (3) are provided, each of which is located in the P body region (2) and extends downward from the top surface of the epitaxial wafer (1), and has a bottom surface higher than the bottom surface of the P body region (2); A plurality of P+ channel regions (4) are provided, each extending downward from the top surface of the corresponding N+ region (3), and having a bottom surface higher than the bottom surface of the N+ region (3); a side surface of the N+ region (3) and the P+ channel region (4) respectively overlaps with a side surface of the P body region (2); A gate dielectric (5) located on the top surface of the epitaxial wafer (1); The polysilicon (6) is provided with a plurality of layers which are spaced apart from each other and are respectively located above the P+ channel region (4) and on the top surface of the gate dielectric (5); The isolation layer (7) is provided with: An S-pole electrode (8) extending downward from the top surface of the isolation layer (7) into the P-body region (2) and connected to the N+ region (3) and the P-body region (2) to form an ohmic contact; A G-pole electrode (9) extends downward from the top surface of the isolation layer (7) into the polysilicon (6) and forms an ohmic contact with the polysilicon (6).

7. A planar gate MOSFET with reduced on-resistance according to claim 6, characterized in that: The epitaxial wafer (1) comprises an N+ substrate layer (11) and an N-voltage-resistant layer (12) connected from bottom to top; The D-pole electrode (10) is connected to the N+ substrate layer (11) to form an ohmic contact.

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